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authorDave Gerlach <d-gerlach@ti.com>2017-03-06 10:23:38 -0500
committerTony Lindgren <tony@atomide.com>2017-03-23 16:43:12 -0400
commit72ac40fcb164a3d8fbd1ff13647abe67df26ced5 (patch)
tree47afa740bd58629eec142fc4af3eca92bf99c62e
parent9f6b5728baffb32c4be480684b0149e791832f07 (diff)
ARM: dts: am33xx: Add updated operating-points-v2 table for cpu
After the ti-cpufreq driver has been added, we can now drop the operating-points table present in am33xx.dtsi for the cpu and add an operating-points-v2 table with all OPPs available for all silicon revisions. Also add necessary data for use by ti-cpufreq to selectively enable the appropriate OPPs at runtime as part of the operating-points table. Information from AM335x Data Manual, SPRS717i, Revised December 2015, Table 5-7. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> eviewed-by: Lukasz Majewski <lukma@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi87
1 files changed, 74 insertions, 13 deletions
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 9e96d60976b7..9e242943dcec 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -46,19 +46,7 @@
46 device_type = "cpu"; 46 device_type = "cpu";
47 reg = <0>; 47 reg = <0>;
48 48
49 /* 49 operating-points-v2 = <&cpu0_opp_table>;
50 * To consider voltage drop between PMIC and SoC,
51 * tolerance value is reduced to 2% from 4% and
52 * voltage value is increased as a precaution.
53 */
54 operating-points = <
55 /* kHz uV */
56 720000 1285000
57 600000 1225000
58 500000 1125000
59 275000 1125000
60 >;
61 voltage-tolerance = <2>; /* 2 percentage */
62 50
63 clocks = <&dpll_mpu_ck>; 51 clocks = <&dpll_mpu_ck>;
64 clock-names = "cpu"; 52 clock-names = "cpu";
@@ -67,6 +55,79 @@
67 }; 55 };
68 }; 56 };
69 57
58 cpu0_opp_table: opp-table {
59 compatible = "operating-points-v2-ti-cpu";
60 syscon = <&scm_conf>;
61
62 /*
63 * The three following nodes are marked with opp-suspend
64 * because the can not be enabled simultaneously on a
65 * single SoC.
66 */
67 opp50@300000000 {
68 opp-hz = /bits/ 64 <300000000>;
69 opp-microvolt = <950000 931000 969000>;
70 opp-supported-hw = <0x06 0x0010>;
71 opp-suspend;
72 };
73
74 opp100@275000000 {
75 opp-hz = /bits/ 64 <275000000>;
76 opp-microvolt = <1100000 1078000 1122000>;
77 opp-supported-hw = <0x01 0x00FF>;
78 opp-suspend;
79 };
80
81 opp100@300000000 {
82 opp-hz = /bits/ 64 <300000000>;
83 opp-microvolt = <1100000 1078000 1122000>;
84 opp-supported-hw = <0x06 0x0020>;
85 opp-suspend;
86 };
87
88 opp100@500000000 {
89 opp-hz = /bits/ 64 <500000000>;
90 opp-microvolt = <1100000 1078000 1122000>;
91 opp-supported-hw = <0x01 0xFFFF>;
92 };
93
94 opp100@600000000 {
95 opp-hz = /bits/ 64 <600000000>;
96 opp-microvolt = <1100000 1078000 1122000>;
97 opp-supported-hw = <0x06 0x0040>;
98 };
99
100 opp120@600000000 {
101 opp-hz = /bits/ 64 <600000000>;
102 opp-microvolt = <1200000 1176000 1224000>;
103 opp-supported-hw = <0x01 0xFFFF>;
104 };
105
106 opp120@720000000 {
107 opp-hz = /bits/ 64 <720000000>;
108 opp-microvolt = <1200000 1176000 1224000>;
109 opp-supported-hw = <0x06 0x0080>;
110 };
111
112 oppturbo@720000000 {
113 opp-hz = /bits/ 64 <720000000>;
114 opp-microvolt = <1260000 1234800 1285200>;
115 opp-supported-hw = <0x01 0xFFFF>;
116 };
117
118 oppturbo@800000000 {
119 opp-hz = /bits/ 64 <800000000>;
120 opp-microvolt = <1260000 1234800 1285200>;
121 opp-supported-hw = <0x06 0x0100>;
122 };
123
124 oppnitro@1000000000 {
125 opp-hz = /bits/ 64 <1000000000>;
126 opp-microvolt = <1325000 1298500 1351500>;
127 opp-supported-hw = <0x04 0x0200>;
128 };
129 };
130
70 pmu { 131 pmu {
71 compatible = "arm,cortex-a8-pmu"; 132 compatible = "arm,cortex-a8-pmu";
72 interrupts = <3>; 133 interrupts = <3>;