aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorAristeu Rozanski <aris@redhat.com>2015-06-12 09:44:52 -0400
committerMauro Carvalho Chehab <mchehab@osg.samsung.com>2015-09-08 19:32:13 -0400
commit7179385afef252cd3f52c0a06cc0c405ae6d66bc (patch)
treee8453acce4d4b139af0d11d1bc02e4cffd9ecec8
parent64291f7db5bd8150a74ad2036f1037e6a0428df2 (diff)
sb_edac: look harder for DDRIO on Haswell systems
In case the memory banks are populated so the first channel isn't used, the DDRIO PCI device won't be visible and it won't be possible to determine the memory type. Acked-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Aristeu Rozanski <aris@redhat.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
-rw-r--r--drivers/edac/sb_edac.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index ca7831168298..84b740d64b50 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -471,6 +471,9 @@ static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
471#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c 471#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
472#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d 472#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
473#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd 473#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
474#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
475#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
476#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
474static const struct pci_id_descr pci_dev_descr_haswell[] = { 477static const struct pci_id_descr pci_dev_descr_haswell[] = {
475 /* first item must be the HA */ 478 /* first item must be the HA */
476 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) }, 479 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) },
@@ -488,6 +491,9 @@ static const struct pci_id_descr pci_dev_descr_haswell[] = {
488 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) }, 491 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) },
489 492
490 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) }, 493 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) },
494 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1) },
495 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1) },
496 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1) },
491 497
492 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) }, 498 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) },
493 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) }, 499 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) },
@@ -1869,7 +1875,11 @@ static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
1869 } 1875 }
1870 break; 1876 break;
1871 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0: 1877 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
1872 pvt->pci_ddrio = pdev; 1878 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
1879 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
1880 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
1881 if (!pvt->pci_ddrio)
1882 pvt->pci_ddrio = pdev;
1873 break; 1883 break;
1874 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1: 1884 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
1875 pvt->pci_ha1 = pdev; 1885 pvt->pci_ha1 = pdev;