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authorVignesh R <vigneshr@ti.com>2016-08-17 08:13:01 -0400
committerJonathan Cameron <jic23@kernel.org>2016-08-21 14:48:31 -0400
commit7175cce1c3f1d8c8840d2004f78f96a3904249b5 (patch)
tree1943c8cf16ab4075753629fe273aba2ee51bba96
parent90c43ec6997a892448f1f86180a515f59cafd8a3 (diff)
iio: adc: ti_am335x_adc: Increase timeout value waiting for ADC sample
Now that open delay and sample delay for each channel is configurable via DT, the default IDLE_TIMEOUT value is not enough as this is calculated based on hardcoded macros. This results in driver returning EBUSY sometimes. Fix this by increasing the timeout value based on maximum value possible to open delay and sample delays for each channel. Fixes: 5dc11e810676e ("iio: adc: ti_am335x_adc: make sample delay, open delay, averaging DT parameters") Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Lee Jones <lee.jones@linaro.org> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
-rw-r--r--drivers/iio/adc/ti_am335x_adc.c2
-rw-r--r--include/linux/mfd/ti_am335x_tscadc.h8
2 files changed, 5 insertions, 5 deletions
diff --git a/drivers/iio/adc/ti_am335x_adc.c b/drivers/iio/adc/ti_am335x_adc.c
index bed9977a1863..c3cfacca2541 100644
--- a/drivers/iio/adc/ti_am335x_adc.c
+++ b/drivers/iio/adc/ti_am335x_adc.c
@@ -381,7 +381,7 @@ static int tiadc_read_raw(struct iio_dev *indio_dev,
381 381
382 am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en); 382 am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en);
383 383
384 timeout = jiffies + usecs_to_jiffies 384 timeout = jiffies + msecs_to_jiffies
385 (IDLE_TIMEOUT * adc_dev->channels); 385 (IDLE_TIMEOUT * adc_dev->channels);
386 /* Wait for Fifo threshold interrupt */ 386 /* Wait for Fifo threshold interrupt */
387 while (1) { 387 while (1) {
diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
index 2567a87872b0..7f55b8b41032 100644
--- a/include/linux/mfd/ti_am335x_tscadc.h
+++ b/include/linux/mfd/ti_am335x_tscadc.h
@@ -138,16 +138,16 @@
138/* 138/*
139 * time in us for processing a single channel, calculated as follows: 139 * time in us for processing a single channel, calculated as follows:
140 * 140 *
141 * num cycles = open delay + (sample delay + conv time) * averaging 141 * max num cycles = open delay + (sample delay + conv time) * averaging
142 * 142 *
143 * num cycles: 152 + (1 + 13) * 16 = 376 143 * max num cycles: 262143 + (255 + 13) * 16 = 266431
144 * 144 *
145 * clock frequency: 26MHz / 8 = 3.25MHz 145 * clock frequency: 26MHz / 8 = 3.25MHz
146 * clock period: 1 / 3.25MHz = 308ns 146 * clock period: 1 / 3.25MHz = 308ns
147 * 147 *
148 * processing time: 376 * 308ns = 116us 148 * max processing time: 266431 * 308ns = 83ms(approx)
149 */ 149 */
150#define IDLE_TIMEOUT 116 /* microsec */ 150#define IDLE_TIMEOUT 83 /* milliseconds */
151 151
152#define TSCADC_CELLS 2 152#define TSCADC_CELLS 2
153 153