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authorDavid S. Miller <davem@davemloft.net>2017-01-24 15:03:42 -0500
committerDavid S. Miller <davem@davemloft.net>2017-01-24 15:03:42 -0500
commit7110fe471efb0160f89dbcb58251bd69842ceba1 (patch)
tree75b4a0ca0bbc05975364b7b78e8072c6cb4bfdbb
parent82272db84d874ebe8b4ae24d4e64d770882dbdd1 (diff)
parentaa13f7cedd9f2813acb83db98bbd3041dfa1e8fa (diff)
Merge branch 'aquantia'
David VomLehn says: ==================== net: ethernet: aquantia: Add AQtion 2.5/5 GB NIC driver This series introduces the AQtion NIC driver for the aQuantia AQC107/AQC108 network devices. v1: Initial version v2: o Make necessary drivers/net/ethernet changes to integrate software o Drop intermediate atlantic directory o Remove Makefile things only appropriate to out of tree module building v3: o Move changes to drivers/net/ethernet/{Kconfig,Makefile} to the last patch to ensure clean bisection. o Removed inline attribute aq_hw_write_req() as it was defined in only one .c file. o #included pci.h in aq_common.h to get struct pci definition. o Modified code to unlock based execution flow rather than using a flag. o Made a number of functions that were only used in a single file static. o Cleaned up error and return code handling in various places. o Remove AQ_CFG_IP_ALIGN definition. o Other minor code clean up. v4: o Using do_div for 64 bit division. o Modified NIC statistics code. o Using build_skb instead netdev_alloc_skb for single fragment packets. o Removed extra aq_nic.o from Makefile v5: o Removed extra newline at the end of the files. v6: o Removed unnecessary cast from void*. o Reworked strings array for ethtool statistics. o Added stringset == ETH_SS_STATS checking. o AQ_OBJ_HEADER replaced to aq_obj_header_s struct. o AQ_OBJ_SET/TST/CLR macroses replaced to inline functions. o Driver sources placed in to atlantic directory. o Fixed compilation warnings (Make W=1) o Added firmware version checking. o Code cleaning. v7 o Removed unnecessary cast from memory allocation function (aq_ring.c). v8 o Switched to using kcalloc instead kzalloc. o Now provide bus_info for ethtool o Used div() to avoid __bad_udelay build error. Signed-off-by: Alexander Loktionov <Alexander.Loktionov@aquantia.com> Signed-off-by: Dmitrii Tarakanov <Dmitrii.Tarakanov@aquantia.com> Signed-off-by: Pavel Belous <Pavel.Belous@aquantia.com> Signed-off-by: David M. VomLehn <vomlehn@texas.net> ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/Kconfig1
-rw-r--r--drivers/net/ethernet/Makefile1
-rw-r--r--drivers/net/ethernet/aquantia/Kconfig24
-rw-r--r--drivers/net/ethernet/aquantia/Makefile5
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/Makefile42
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_cfg.h77
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_common.h23
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c261
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_ethtool.h19
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_hw.h177
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c68
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h47
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_main.c273
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_main.h17
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_nic.c937
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_nic.h108
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_nic_internal.h46
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c345
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h34
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_ring.c376
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_ring.h157
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_rss.h26
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_utils.h50
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_vec.c392
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_vec.h42
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c905
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.h34
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h155
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c958
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h34
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h207
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c1394
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h677
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h2375
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c570
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h210
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/ver.h18
37 files changed, 11085 insertions, 0 deletions
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index afc07d4434bb..8c08f9deef92 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -29,6 +29,7 @@ source "drivers/net/ethernet/amazon/Kconfig"
29source "drivers/net/ethernet/amd/Kconfig" 29source "drivers/net/ethernet/amd/Kconfig"
30source "drivers/net/ethernet/apm/Kconfig" 30source "drivers/net/ethernet/apm/Kconfig"
31source "drivers/net/ethernet/apple/Kconfig" 31source "drivers/net/ethernet/apple/Kconfig"
32source "drivers/net/ethernet/aquantia/Kconfig"
32source "drivers/net/ethernet/arc/Kconfig" 33source "drivers/net/ethernet/arc/Kconfig"
33source "drivers/net/ethernet/atheros/Kconfig" 34source "drivers/net/ethernet/atheros/Kconfig"
34source "drivers/net/ethernet/aurora/Kconfig" 35source "drivers/net/ethernet/aurora/Kconfig"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index e7861a8aa817..26dce5bf2c18 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_NET_VENDOR_AMAZON) += amazon/
15obj-$(CONFIG_NET_VENDOR_AMD) += amd/ 15obj-$(CONFIG_NET_VENDOR_AMD) += amd/
16obj-$(CONFIG_NET_XGENE) += apm/ 16obj-$(CONFIG_NET_XGENE) += apm/
17obj-$(CONFIG_NET_VENDOR_APPLE) += apple/ 17obj-$(CONFIG_NET_VENDOR_APPLE) += apple/
18obj-$(CONFIG_NET_VENDOR_AQUANTIA) += aquantia/
18obj-$(CONFIG_NET_VENDOR_ARC) += arc/ 19obj-$(CONFIG_NET_VENDOR_ARC) += arc/
19obj-$(CONFIG_NET_VENDOR_ATHEROS) += atheros/ 20obj-$(CONFIG_NET_VENDOR_ATHEROS) += atheros/
20obj-$(CONFIG_NET_VENDOR_AURORA) += aurora/ 21obj-$(CONFIG_NET_VENDOR_AURORA) += aurora/
diff --git a/drivers/net/ethernet/aquantia/Kconfig b/drivers/net/ethernet/aquantia/Kconfig
new file mode 100644
index 000000000000..cdf78e069a39
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/Kconfig
@@ -0,0 +1,24 @@
1#
2# aQuantia device configuration
3#
4
5config NET_VENDOR_AQUANTIA
6 bool "aQuantia devices"
7 default y
8 ---help---
9 Set this to y if you have an Ethernet network cards that uses the aQuantia
10 AQC107/AQC108 chipset.
11
12 This option does not build any drivers; it casues the aQuantia
13 drivers that can be built to appear in the list of Ethernet drivers.
14
15
16if NET_VENDOR_AQUANTIA
17
18config AQTION
19 tristate "aQuantia AQtion(tm) Support"
20 depends on PCI && X86_64
21 ---help---
22 This enables the support for the aQuantia AQtion(tm) Ethernet card.
23
24endif # NET_VENDOR_AQUANTIA
diff --git a/drivers/net/ethernet/aquantia/Makefile b/drivers/net/ethernet/aquantia/Makefile
new file mode 100644
index 000000000000..4f4897b689b2
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the aQuantia device drivers.
3#
4
5obj-$(CONFIG_AQTION) += atlantic/
diff --git a/drivers/net/ethernet/aquantia/atlantic/Makefile b/drivers/net/ethernet/aquantia/atlantic/Makefile
new file mode 100644
index 000000000000..e4ae696920ef
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/Makefile
@@ -0,0 +1,42 @@
1################################################################################
2#
3# aQuantia Ethernet Controller AQtion Linux Driver
4# Copyright(c) 2014-2017 aQuantia Corporation.
5#
6# This program is free software; you can redistribute it and/or modify it
7# under the terms and conditions of the GNU General Public License,
8# version 2, as published by the Free Software Foundation.
9#
10# This program is distributed in the hope it will be useful, but WITHOUT
11# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13# more details.
14#
15# You should have received a copy of the GNU General Public License along
16# with this program. If not, see <http://www.gnu.org/licenses/>.
17#
18# The full GNU General Public License is included in this distribution in
19# the file called "COPYING".
20#
21# Contact Information: <rdc-drv@aquantia.com>
22# aQuantia Corporation, 105 E. Tasman Dr. San Jose, CA 95134, USA
23#
24################################################################################
25
26#
27# Makefile for the AQtion(tm) Ethernet driver
28#
29
30obj-$(CONFIG_AQTION) += atlantic.o
31
32atlantic-objs := aq_main.o \
33 aq_nic.o \
34 aq_pci_func.o \
35 aq_vec.o \
36 aq_ring.o \
37 aq_hw_utils.o \
38 aq_ethtool.o \
39 hw_atl/hw_atl_a0.o \
40 hw_atl/hw_atl_b0.o \
41 hw_atl/hw_atl_utils.o \
42 hw_atl/hw_atl_llh.o
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h b/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h
new file mode 100644
index 000000000000..5f99237a9d52
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h
@@ -0,0 +1,77 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_cfg.h: Definition of configuration parameters and constants. */
11
12#ifndef AQ_CFG_H
13#define AQ_CFG_H
14
15#define AQ_CFG_VECS_DEF 4U
16#define AQ_CFG_TCS_DEF 1U
17
18#define AQ_CFG_TXDS_DEF 4096U
19#define AQ_CFG_RXDS_DEF 1024U
20
21#define AQ_CFG_IS_POLLING_DEF 0U
22
23#define AQ_CFG_FORCE_LEGACY_INT 0U
24
25#define AQ_CFG_IS_INTERRUPT_MODERATION_DEF 1U
26#define AQ_CFG_INTERRUPT_MODERATION_RATE_DEF 0xFFFFU
27#define AQ_CFG_IRQ_MASK 0x1FFU
28
29#define AQ_CFG_VECS_MAX 8U
30#define AQ_CFG_TCS_MAX 8U
31
32#define AQ_CFG_TX_FRAME_MAX (16U * 1024U)
33#define AQ_CFG_RX_FRAME_MAX (4U * 1024U)
34
35/* LRO */
36#define AQ_CFG_IS_LRO_DEF 1U
37
38/* RSS */
39#define AQ_CFG_RSS_INDIRECTION_TABLE_MAX 128U
40#define AQ_CFG_RSS_HASHKEY_SIZE 320U
41
42#define AQ_CFG_IS_RSS_DEF 1U
43#define AQ_CFG_NUM_RSS_QUEUES_DEF AQ_CFG_VECS_DEF
44#define AQ_CFG_RSS_BASE_CPU_NUM_DEF 0U
45
46#define AQ_CFG_PCI_FUNC_MSIX_IRQS 9U
47#define AQ_CFG_PCI_FUNC_PORTS 2U
48
49#define AQ_CFG_SERVICE_TIMER_INTERVAL (2 * HZ)
50#define AQ_CFG_POLLING_TIMER_INTERVAL ((unsigned int)(2 * HZ))
51
52#define AQ_CFG_SKB_FRAGS_MAX 32U
53
54#define AQ_CFG_NAPI_WEIGHT 64U
55
56#define AQ_CFG_MULTICAST_ADDRESS_MAX 32U
57
58/*#define AQ_CFG_MAC_ADDR_PERMANENT {0x30, 0x0E, 0xE3, 0x12, 0x34, 0x56}*/
59
60#define AQ_CFG_FC_MODE 3U
61
62#define AQ_CFG_SPEED_MSK 0xFFFFU /* 0xFFFFU==auto_neg */
63
64#define AQ_CFG_IS_AUTONEG_DEF 1U
65#define AQ_CFG_MTU_DEF 1514U
66
67#define AQ_CFG_LOCK_TRYS 100U
68
69#define AQ_CFG_DRV_AUTHOR "aQuantia"
70#define AQ_CFG_DRV_DESC "aQuantia Corporation(R) Network Driver"
71#define AQ_CFG_DRV_NAME "aquantia"
72#define AQ_CFG_DRV_VERSION __stringify(NIC_MAJOR_DRIVER_VERSION)"."\
73 __stringify(NIC_MINOR_DRIVER_VERSION)"."\
74 __stringify(NIC_BUILD_DRIVER_VERSION)"."\
75 __stringify(NIC_REVISION_DRIVER_VERSION)
76
77#endif /* AQ_CFG_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_common.h b/drivers/net/ethernet/aquantia/atlantic/aq_common.h
new file mode 100644
index 000000000000..9eb5e222a234
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_common.h
@@ -0,0 +1,23 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_common.h: Basic includes for all files in project. */
11
12#ifndef AQ_COMMON_H
13#define AQ_COMMON_H
14
15#include <linux/etherdevice.h>
16#include <linux/pci.h>
17
18#include "ver.h"
19#include "aq_nic.h"
20#include "aq_cfg.h"
21#include "aq_utils.h"
22
23#endif /* AQ_COMMON_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c b/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c
new file mode 100644
index 000000000000..c5b025e0dc10
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c
@@ -0,0 +1,261 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_ethtool.c: Definition of ethertool related functions. */
11
12#include "aq_ethtool.h"
13#include "aq_nic.h"
14
15static void aq_ethtool_get_regs(struct net_device *ndev,
16 struct ethtool_regs *regs, void *p)
17{
18 struct aq_nic_s *aq_nic = netdev_priv(ndev);
19 u32 regs_count = aq_nic_get_regs_count(aq_nic);
20
21 memset(p, 0, regs_count * sizeof(u32));
22 aq_nic_get_regs(aq_nic, regs, p);
23}
24
25static int aq_ethtool_get_regs_len(struct net_device *ndev)
26{
27 struct aq_nic_s *aq_nic = netdev_priv(ndev);
28 u32 regs_count = aq_nic_get_regs_count(aq_nic);
29
30 return regs_count * sizeof(u32);
31}
32
33static u32 aq_ethtool_get_link(struct net_device *ndev)
34{
35 return ethtool_op_get_link(ndev);
36}
37
38static int aq_ethtool_get_settings(struct net_device *ndev,
39 struct ethtool_cmd *cmd)
40{
41 struct aq_nic_s *aq_nic = netdev_priv(ndev);
42
43 aq_nic_get_link_settings(aq_nic, cmd);
44 ethtool_cmd_speed_set(cmd, netif_carrier_ok(ndev) ?
45 aq_nic_get_link_speed(aq_nic) : 0U);
46
47 return 0;
48}
49
50static int aq_ethtool_set_settings(struct net_device *ndev,
51 struct ethtool_cmd *cmd)
52{
53 struct aq_nic_s *aq_nic = netdev_priv(ndev);
54
55 return aq_nic_set_link_settings(aq_nic, cmd);
56}
57
58/* there "5U" is number of queue[#] stats lines (InPackets+...+InErrors) */
59static const unsigned int aq_ethtool_stat_queue_lines = 5U;
60static const unsigned int aq_ethtool_stat_queue_chars =
61 5U * ETH_GSTRING_LEN;
62static const char aq_ethtool_stat_names[][ETH_GSTRING_LEN] = {
63 "InPackets",
64 "InUCast",
65 "InMCast",
66 "InBCast",
67 "InErrors",
68 "OutPackets",
69 "OutUCast",
70 "OutMCast",
71 "OutBCast",
72 "InUCastOctects",
73 "OutUCastOctects",
74 "InMCastOctects",
75 "OutMCastOctects",
76 "InBCastOctects",
77 "OutBCastOctects",
78 "InOctects",
79 "OutOctects",
80 "InPacketsDma",
81 "OutPacketsDma",
82 "InOctetsDma",
83 "OutOctetsDma",
84 "InDroppedDma",
85 "Queue[0] InPackets",
86 "Queue[0] OutPackets",
87 "Queue[0] InJumboPackets",
88 "Queue[0] InLroPackets",
89 "Queue[0] InErrors",
90 "Queue[1] InPackets",
91 "Queue[1] OutPackets",
92 "Queue[1] InJumboPackets",
93 "Queue[1] InLroPackets",
94 "Queue[1] InErrors",
95 "Queue[2] InPackets",
96 "Queue[2] OutPackets",
97 "Queue[2] InJumboPackets",
98 "Queue[2] InLroPackets",
99 "Queue[2] InErrors",
100 "Queue[3] InPackets",
101 "Queue[3] OutPackets",
102 "Queue[3] InJumboPackets",
103 "Queue[3] InLroPackets",
104 "Queue[3] InErrors",
105 "Queue[4] InPackets",
106 "Queue[4] OutPackets",
107 "Queue[4] InJumboPackets",
108 "Queue[4] InLroPackets",
109 "Queue[4] InErrors",
110 "Queue[5] InPackets",
111 "Queue[5] OutPackets",
112 "Queue[5] InJumboPackets",
113 "Queue[5] InLroPackets",
114 "Queue[5] InErrors",
115 "Queue[6] InPackets",
116 "Queue[6] OutPackets",
117 "Queue[6] InJumboPackets",
118 "Queue[6] InLroPackets",
119 "Queue[6] InErrors",
120 "Queue[7] InPackets",
121 "Queue[7] OutPackets",
122 "Queue[7] InJumboPackets",
123 "Queue[7] InLroPackets",
124 "Queue[7] InErrors",
125};
126
127static void aq_ethtool_stats(struct net_device *ndev,
128 struct ethtool_stats *stats, u64 *data)
129{
130 struct aq_nic_s *aq_nic = netdev_priv(ndev);
131
132/* ASSERT: Need add lines to aq_ethtool_stat_names if AQ_CFG_VECS_MAX > 8 */
133 BUILD_BUG_ON(AQ_CFG_VECS_MAX > 8);
134 memset(data, 0, ARRAY_SIZE(aq_ethtool_stat_names) * sizeof(u64));
135 aq_nic_get_stats(aq_nic, data);
136}
137
138static void aq_ethtool_get_drvinfo(struct net_device *ndev,
139 struct ethtool_drvinfo *drvinfo)
140{
141 struct aq_nic_s *aq_nic = netdev_priv(ndev);
142 struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
143 struct pci_dev *pdev = to_pci_dev(ndev->dev.parent);
144 u32 firmware_version = aq_nic_get_fw_version(aq_nic);
145 u32 regs_count = aq_nic_get_regs_count(aq_nic);
146
147 strlcat(drvinfo->driver, AQ_CFG_DRV_NAME, sizeof(drvinfo->driver));
148 strlcat(drvinfo->version, AQ_CFG_DRV_VERSION, sizeof(drvinfo->version));
149
150 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
151 "%u.%u.%u", firmware_version >> 24,
152 (firmware_version >> 16) & 0xFFU, firmware_version & 0xFFFFU);
153
154 strlcpy(drvinfo->bus_info, pdev ? pci_name(pdev) : "",
155 sizeof(drvinfo->bus_info));
156 drvinfo->n_stats = ARRAY_SIZE(aq_ethtool_stat_names) -
157 (AQ_CFG_VECS_MAX - cfg->vecs) * aq_ethtool_stat_queue_lines;
158 drvinfo->testinfo_len = 0;
159 drvinfo->regdump_len = regs_count;
160 drvinfo->eedump_len = 0;
161}
162
163static void aq_ethtool_get_strings(struct net_device *ndev,
164 u32 stringset, u8 *data)
165{
166 struct aq_nic_s *aq_nic = netdev_priv(ndev);
167 struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
168
169 if (stringset == ETH_SS_STATS)
170 memcpy(data, *aq_ethtool_stat_names,
171 sizeof(aq_ethtool_stat_names) -
172 (AQ_CFG_VECS_MAX - cfg->vecs) *
173 aq_ethtool_stat_queue_chars);
174}
175
176static int aq_ethtool_get_sset_count(struct net_device *ndev, int stringset)
177{
178 int ret = 0;
179 struct aq_nic_s *aq_nic = netdev_priv(ndev);
180 struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
181
182 switch (stringset) {
183 case ETH_SS_STATS:
184 ret = ARRAY_SIZE(aq_ethtool_stat_names) -
185 (AQ_CFG_VECS_MAX - cfg->vecs) *
186 aq_ethtool_stat_queue_lines;
187 break;
188 default:
189 ret = -EOPNOTSUPP;
190 }
191 return ret;
192}
193
194static u32 aq_ethtool_get_rss_indir_size(struct net_device *ndev)
195{
196 return AQ_CFG_RSS_INDIRECTION_TABLE_MAX;
197}
198
199static u32 aq_ethtool_get_rss_key_size(struct net_device *ndev)
200{
201 struct aq_nic_s *aq_nic = netdev_priv(ndev);
202 struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
203
204 return sizeof(cfg->aq_rss.hash_secret_key);
205}
206
207static int aq_ethtool_get_rss(struct net_device *ndev, u32 *indir, u8 *key,
208 u8 *hfunc)
209{
210 struct aq_nic_s *aq_nic = netdev_priv(ndev);
211 struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
212 unsigned int i = 0U;
213
214 if (hfunc)
215 *hfunc = ETH_RSS_HASH_TOP; /* Toeplitz */
216 if (indir) {
217 for (i = 0; i < AQ_CFG_RSS_INDIRECTION_TABLE_MAX; i++)
218 indir[i] = cfg->aq_rss.indirection_table[i];
219 }
220 if (key)
221 memcpy(key, cfg->aq_rss.hash_secret_key,
222 sizeof(cfg->aq_rss.hash_secret_key));
223 return 0;
224}
225
226static int aq_ethtool_get_rxnfc(struct net_device *ndev,
227 struct ethtool_rxnfc *cmd,
228 u32 *rule_locs)
229{
230 struct aq_nic_s *aq_nic = netdev_priv(ndev);
231 struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(aq_nic);
232 int err = 0;
233
234 switch (cmd->cmd) {
235 case ETHTOOL_GRXRINGS:
236 cmd->data = cfg->vecs;
237 break;
238
239 default:
240 err = -EOPNOTSUPP;
241 break;
242 }
243
244 return err;
245}
246
247const struct ethtool_ops aq_ethtool_ops = {
248 .get_link = aq_ethtool_get_link,
249 .get_regs_len = aq_ethtool_get_regs_len,
250 .get_regs = aq_ethtool_get_regs,
251 .get_settings = aq_ethtool_get_settings,
252 .set_settings = aq_ethtool_set_settings,
253 .get_drvinfo = aq_ethtool_get_drvinfo,
254 .get_strings = aq_ethtool_get_strings,
255 .get_rxfh_indir_size = aq_ethtool_get_rss_indir_size,
256 .get_rxfh_key_size = aq_ethtool_get_rss_key_size,
257 .get_rxfh = aq_ethtool_get_rss,
258 .get_rxnfc = aq_ethtool_get_rxnfc,
259 .get_sset_count = aq_ethtool_get_sset_count,
260 .get_ethtool_stats = aq_ethtool_stats
261};
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.h b/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.h
new file mode 100644
index 000000000000..21c126eeb5eb
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.h
@@ -0,0 +1,19 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_ethtool.h: Declaration of ethertool related functions. */
11
12#ifndef AQ_ETHTOOL_H
13#define AQ_ETHTOOL_H
14
15#include "aq_common.h"
16
17extern const struct ethtool_ops aq_ethtool_ops;
18
19#endif /* AQ_ETHTOOL_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h
new file mode 100644
index 000000000000..fce0fd3f23ff
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h
@@ -0,0 +1,177 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_hw.h: Declaraion of abstract interface for NIC hardware specific
11 * functions.
12 */
13
14#ifndef AQ_HW_H
15#define AQ_HW_H
16
17#include "aq_common.h"
18
19/* NIC H/W capabilities */
20struct aq_hw_caps_s {
21 u64 hw_features;
22 u64 link_speed_msk;
23 unsigned int hw_priv_flags;
24 u32 rxds;
25 u32 txds;
26 u32 txhwb_alignment;
27 u32 irq_mask;
28 u32 vecs;
29 u32 mtu;
30 u32 mac_regs_count;
31 u8 ports;
32 u8 msix_irqs;
33 u8 tcs;
34 u8 rxd_alignment;
35 u8 rxd_size;
36 u8 txd_alignment;
37 u8 txd_size;
38 u8 tx_rings;
39 u8 rx_rings;
40 bool flow_control;
41 bool is_64_dma;
42 u32 fw_ver_expected;
43};
44
45struct aq_hw_link_status_s {
46 unsigned int mbps;
47};
48
49#define AQ_HW_IRQ_INVALID 0U
50#define AQ_HW_IRQ_LEGACY 1U
51#define AQ_HW_IRQ_MSI 2U
52#define AQ_HW_IRQ_MSIX 3U
53
54#define AQ_HW_POWER_STATE_D0 0U
55#define AQ_HW_POWER_STATE_D3 3U
56
57#define AQ_HW_FLAG_STARTED 0x00000004U
58#define AQ_HW_FLAG_STOPPING 0x00000008U
59#define AQ_HW_FLAG_RESETTING 0x00000010U
60#define AQ_HW_FLAG_CLOSING 0x00000020U
61#define AQ_HW_LINK_DOWN 0x04000000U
62#define AQ_HW_FLAG_ERR_UNPLUG 0x40000000U
63#define AQ_HW_FLAG_ERR_HW 0x80000000U
64
65#define AQ_HW_FLAG_ERRORS (AQ_HW_FLAG_ERR_HW | AQ_HW_FLAG_ERR_UNPLUG)
66
67struct aq_hw_s {
68 struct aq_obj_s header;
69 struct aq_nic_cfg_s *aq_nic_cfg;
70 struct aq_pci_func_s *aq_pci_func;
71 void __iomem *mmio;
72 unsigned int not_ff_addr;
73 struct aq_hw_link_status_s aq_link_status;
74};
75
76struct aq_ring_s;
77struct aq_ring_param_s;
78struct aq_nic_cfg_s;
79struct sk_buff;
80
81struct aq_hw_ops {
82 struct aq_hw_s *(*create)(struct aq_pci_func_s *aq_pci_func,
83 unsigned int port, struct aq_hw_ops *ops);
84
85 void (*destroy)(struct aq_hw_s *self);
86
87 int (*get_hw_caps)(struct aq_hw_s *self,
88 struct aq_hw_caps_s *aq_hw_caps);
89
90 int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
91 unsigned int frags);
92
93 int (*hw_ring_rx_receive)(struct aq_hw_s *self,
94 struct aq_ring_s *aq_ring);
95
96 int (*hw_ring_rx_fill)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
97 unsigned int sw_tail_old);
98
99 int (*hw_ring_tx_head_update)(struct aq_hw_s *self,
100 struct aq_ring_s *aq_ring);
101
102 int (*hw_get_mac_permanent)(struct aq_hw_s *self,
103 struct aq_hw_caps_s *aq_hw_caps,
104 u8 *mac);
105
106 int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr);
107
108 int (*hw_get_link_status)(struct aq_hw_s *self,
109 struct aq_hw_link_status_s *link_status);
110
111 int (*hw_set_link_speed)(struct aq_hw_s *self, u32 speed);
112
113 int (*hw_reset)(struct aq_hw_s *self);
114
115 int (*hw_init)(struct aq_hw_s *self, struct aq_nic_cfg_s *aq_nic_cfg,
116 u8 *mac_addr);
117
118 int (*hw_start)(struct aq_hw_s *self);
119
120 int (*hw_stop)(struct aq_hw_s *self);
121
122 int (*hw_ring_tx_init)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
123 struct aq_ring_param_s *aq_ring_param);
124
125 int (*hw_ring_tx_start)(struct aq_hw_s *self,
126 struct aq_ring_s *aq_ring);
127
128 int (*hw_ring_tx_stop)(struct aq_hw_s *self,
129 struct aq_ring_s *aq_ring);
130
131 int (*hw_ring_rx_init)(struct aq_hw_s *self,
132 struct aq_ring_s *aq_ring,
133 struct aq_ring_param_s *aq_ring_param);
134
135 int (*hw_ring_rx_start)(struct aq_hw_s *self,
136 struct aq_ring_s *aq_ring);
137
138 int (*hw_ring_rx_stop)(struct aq_hw_s *self,
139 struct aq_ring_s *aq_ring);
140
141 int (*hw_irq_enable)(struct aq_hw_s *self, u64 mask);
142
143 int (*hw_irq_disable)(struct aq_hw_s *self, u64 mask);
144
145 int (*hw_irq_read)(struct aq_hw_s *self, u64 *mask);
146
147 int (*hw_packet_filter_set)(struct aq_hw_s *self,
148 unsigned int packet_filter);
149
150 int (*hw_multicast_list_set)(struct aq_hw_s *self,
151 u8 ar_mac[AQ_CFG_MULTICAST_ADDRESS_MAX]
152 [ETH_ALEN],
153 u32 count);
154
155 int (*hw_interrupt_moderation_set)(struct aq_hw_s *self,
156 bool itr_enabled);
157
158 int (*hw_rss_set)(struct aq_hw_s *self,
159 struct aq_rss_parameters *rss_params);
160
161 int (*hw_rss_hash_set)(struct aq_hw_s *self,
162 struct aq_rss_parameters *rss_params);
163
164 int (*hw_get_regs)(struct aq_hw_s *self,
165 struct aq_hw_caps_s *aq_hw_caps, u32 *regs_buff);
166
167 int (*hw_get_hw_stats)(struct aq_hw_s *self, u64 *data,
168 unsigned int *p_count);
169
170 int (*hw_get_fw_version)(struct aq_hw_s *self, u32 *fw_version);
171
172 int (*hw_deinit)(struct aq_hw_s *self);
173
174 int (*hw_set_power)(struct aq_hw_s *self, unsigned int power_state);
175};
176
177#endif /* AQ_HW_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c
new file mode 100644
index 000000000000..5f13465995f6
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c
@@ -0,0 +1,68 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_hw_utils.c: Definitions of helper functions used across
11 * hardware layer.
12 */
13
14#include "aq_hw_utils.h"
15#include "aq_hw.h"
16
17void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk,
18 u32 shift, u32 val)
19{
20 if (msk ^ ~0) {
21 u32 reg_old, reg_new;
22
23 reg_old = aq_hw_read_reg(aq_hw, addr);
24 reg_new = (reg_old & (~msk)) | (val << shift);
25
26 if (reg_old != reg_new)
27 aq_hw_write_reg(aq_hw, addr, reg_new);
28 } else {
29 aq_hw_write_reg(aq_hw, addr, val);
30 }
31}
32
33u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift)
34{
35 return ((aq_hw_read_reg(aq_hw, addr) & msk) >> shift);
36}
37
38u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg)
39{
40 u32 value = readl(hw->mmio + reg);
41
42 if ((~0U) == value && (~0U) == readl(hw->mmio + hw->not_ff_addr))
43 aq_utils_obj_set(&hw->header.flags, AQ_HW_FLAG_ERR_UNPLUG);
44
45 return value;
46}
47
48void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value)
49{
50 writel(value, hw->mmio + reg);
51}
52
53int aq_hw_err_from_flags(struct aq_hw_s *hw)
54{
55 int err = 0;
56
57 if (aq_utils_obj_test(&hw->header.flags, AQ_HW_FLAG_ERR_UNPLUG)) {
58 err = -ENXIO;
59 goto err_exit;
60 }
61 if (aq_utils_obj_test(&hw->header.flags, AQ_HW_FLAG_ERR_HW)) {
62 err = -EIO;
63 goto err_exit;
64 }
65
66err_exit:
67 return err;
68}
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h
new file mode 100644
index 000000000000..78fcc0c3ab4d
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h
@@ -0,0 +1,47 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_hw_utils.h: Declaration of helper functions used across hardware
11 * layer.
12 */
13
14#ifndef AQ_HW_UTILS_H
15#define AQ_HW_UTILS_H
16
17#include "aq_common.h"
18
19#ifndef HIDWORD
20#define LODWORD(_qw) ((u32)(_qw))
21#define HIDWORD(_qw) ((u32)(((_qw) >> 32) & 0xffffffff))
22#endif
23
24#define AQ_HW_SLEEP(_US_) mdelay(_US_)
25
26#define AQ_HW_WAIT_FOR(_B_, _US_, _N_) \
27do { \
28 unsigned int AQ_HW_WAIT_FOR_i; \
29 for (AQ_HW_WAIT_FOR_i = _N_; (!(_B_)) && (AQ_HW_WAIT_FOR_i);\
30 --AQ_HW_WAIT_FOR_i) {\
31 udelay(_US_); \
32 } \
33 if (!AQ_HW_WAIT_FOR_i) {\
34 err = ETIME; \
35 } \
36} while (0)
37
38struct aq_hw_s;
39
40void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk,
41 u32 shift, u32 val);
42u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift);
43u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg);
44void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value);
45int aq_hw_err_from_flags(struct aq_hw_s *hw);
46
47#endif /* AQ_HW_UTILS_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_main.c b/drivers/net/ethernet/aquantia/atlantic/aq_main.c
new file mode 100644
index 000000000000..c17c70adef0d
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_main.c
@@ -0,0 +1,273 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_main.c: Main file for aQuantia Linux driver. */
11
12#include "aq_main.h"
13#include "aq_nic.h"
14#include "aq_pci_func.h"
15#include "aq_ethtool.h"
16#include "hw_atl/hw_atl_a0.h"
17#include "hw_atl/hw_atl_b0.h"
18
19#include <linux/netdevice.h>
20#include <linux/module.h>
21
22static const struct pci_device_id aq_pci_tbl[] = {
23 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_0001), },
24 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D100), },
25 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D107), },
26 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D108), },
27 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D109), },
28 {}
29};
30
31MODULE_DEVICE_TABLE(pci, aq_pci_tbl);
32
33MODULE_LICENSE("GPL v2");
34MODULE_VERSION(AQ_CFG_DRV_VERSION);
35MODULE_AUTHOR(AQ_CFG_DRV_AUTHOR);
36MODULE_DESCRIPTION(AQ_CFG_DRV_DESC);
37
38static struct aq_hw_ops *aq_pci_probe_get_hw_ops_by_id(struct pci_dev *pdev)
39{
40 struct aq_hw_ops *ops = NULL;
41
42 ops = hw_atl_a0_get_ops_by_id(pdev);
43 if (!ops)
44 ops = hw_atl_b0_get_ops_by_id(pdev);
45
46 return ops;
47}
48
49static int aq_ndev_open(struct net_device *ndev)
50{
51 struct aq_nic_s *aq_nic = NULL;
52 int err = 0;
53
54 aq_nic = aq_nic_alloc_hot(ndev);
55 if (!aq_nic) {
56 err = -ENOMEM;
57 goto err_exit;
58 }
59 err = aq_nic_init(aq_nic);
60 if (err < 0)
61 goto err_exit;
62 err = aq_nic_start(aq_nic);
63 if (err < 0)
64 goto err_exit;
65
66err_exit:
67 if (err < 0)
68 aq_nic_deinit(aq_nic);
69 return err;
70}
71
72static int aq_ndev_close(struct net_device *ndev)
73{
74 int err = 0;
75 struct aq_nic_s *aq_nic = netdev_priv(ndev);
76
77 err = aq_nic_stop(aq_nic);
78 if (err < 0)
79 goto err_exit;
80 aq_nic_deinit(aq_nic);
81 aq_nic_free_hot_resources(aq_nic);
82
83err_exit:
84 return err;
85}
86
87static int aq_ndev_start_xmit(struct sk_buff *skb, struct net_device *ndev)
88{
89 struct aq_nic_s *aq_nic = netdev_priv(ndev);
90 int err = 0;
91
92 err = aq_nic_xmit(aq_nic, skb);
93 if (err < 0)
94 goto err_exit;
95
96err_exit:
97 return err;
98}
99
100static int aq_ndev_change_mtu(struct net_device *ndev, int new_mtu)
101{
102 struct aq_nic_s *aq_nic = netdev_priv(ndev);
103 int err = 0;
104
105 if (new_mtu == ndev->mtu) {
106 err = 0;
107 goto err_exit;
108 }
109 if (new_mtu < 68) {
110 err = -EINVAL;
111 goto err_exit;
112 }
113 err = aq_nic_set_mtu(aq_nic, new_mtu + ETH_HLEN);
114 if (err < 0)
115 goto err_exit;
116 ndev->mtu = new_mtu;
117
118 if (netif_running(ndev)) {
119 aq_ndev_close(ndev);
120 aq_ndev_open(ndev);
121 }
122
123err_exit:
124 return err;
125}
126
127static int aq_ndev_set_features(struct net_device *ndev,
128 netdev_features_t features)
129{
130 struct aq_nic_s *aq_nic = netdev_priv(ndev);
131 struct aq_nic_cfg_s *aq_cfg = aq_nic_get_cfg(aq_nic);
132 bool is_lro = false;
133
134 if (aq_cfg->hw_features & NETIF_F_LRO) {
135 is_lro = features & NETIF_F_LRO;
136
137 if (aq_cfg->is_lro != is_lro) {
138 aq_cfg->is_lro = is_lro;
139
140 if (netif_running(ndev)) {
141 aq_ndev_close(ndev);
142 aq_ndev_open(ndev);
143 }
144 }
145 }
146
147 return 0;
148}
149
150static int aq_ndev_set_mac_address(struct net_device *ndev, void *addr)
151{
152 struct aq_nic_s *aq_nic = netdev_priv(ndev);
153 int err = 0;
154
155 err = eth_mac_addr(ndev, addr);
156 if (err < 0)
157 goto err_exit;
158 err = aq_nic_set_mac(aq_nic, ndev);
159 if (err < 0)
160 goto err_exit;
161
162err_exit:
163 return err;
164}
165
166static void aq_ndev_set_multicast_settings(struct net_device *ndev)
167{
168 struct aq_nic_s *aq_nic = netdev_priv(ndev);
169 int err = 0;
170
171 err = aq_nic_set_packet_filter(aq_nic, ndev->flags);
172 if (err < 0)
173 goto err_exit;
174
175 if (netdev_mc_count(ndev)) {
176 err = aq_nic_set_multicast_list(aq_nic, ndev);
177 if (err < 0)
178 goto err_exit;
179 }
180
181err_exit:;
182}
183
184static const struct net_device_ops aq_ndev_ops = {
185 .ndo_open = aq_ndev_open,
186 .ndo_stop = aq_ndev_close,
187 .ndo_start_xmit = aq_ndev_start_xmit,
188 .ndo_set_rx_mode = aq_ndev_set_multicast_settings,
189 .ndo_change_mtu = aq_ndev_change_mtu,
190 .ndo_set_mac_address = aq_ndev_set_mac_address,
191 .ndo_set_features = aq_ndev_set_features
192};
193
194static int aq_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *pci_id)
196{
197 struct aq_hw_ops *aq_hw_ops = NULL;
198 struct aq_pci_func_s *aq_pci_func = NULL;
199 int err = 0;
200
201 err = pci_enable_device(pdev);
202 if (err < 0)
203 goto err_exit;
204 aq_hw_ops = aq_pci_probe_get_hw_ops_by_id(pdev);
205 aq_pci_func = aq_pci_func_alloc(aq_hw_ops, pdev,
206 &aq_ndev_ops, &aq_ethtool_ops);
207 if (!aq_pci_func) {
208 err = -ENOMEM;
209 goto err_exit;
210 }
211 err = aq_pci_func_init(aq_pci_func);
212 if (err < 0)
213 goto err_exit;
214
215err_exit:
216 if (err < 0) {
217 if (aq_pci_func)
218 aq_pci_func_free(aq_pci_func);
219 }
220 return err;
221}
222
223static void aq_pci_remove(struct pci_dev *pdev)
224{
225 struct aq_pci_func_s *aq_pci_func = pci_get_drvdata(pdev);
226
227 aq_pci_func_deinit(aq_pci_func);
228 aq_pci_func_free(aq_pci_func);
229}
230
231static int aq_pci_suspend(struct pci_dev *pdev, pm_message_t pm_msg)
232{
233 struct aq_pci_func_s *aq_pci_func = pci_get_drvdata(pdev);
234
235 return aq_pci_func_change_pm_state(aq_pci_func, &pm_msg);
236}
237
238static int aq_pci_resume(struct pci_dev *pdev)
239{
240 struct aq_pci_func_s *aq_pci_func = pci_get_drvdata(pdev);
241 pm_message_t pm_msg = PMSG_RESTORE;
242
243 return aq_pci_func_change_pm_state(aq_pci_func, &pm_msg);
244}
245
246static struct pci_driver aq_pci_ops = {
247 .name = AQ_CFG_DRV_NAME,
248 .id_table = aq_pci_tbl,
249 .probe = aq_pci_probe,
250 .remove = aq_pci_remove,
251 .suspend = aq_pci_suspend,
252 .resume = aq_pci_resume,
253};
254
255static int __init aq_module_init(void)
256{
257 int err = 0;
258
259 err = pci_register_driver(&aq_pci_ops);
260 if (err < 0)
261 goto err_exit;
262
263err_exit:
264 return err;
265}
266
267static void __exit aq_module_exit(void)
268{
269 pci_unregister_driver(&aq_pci_ops);
270}
271
272module_init(aq_module_init);
273module_exit(aq_module_exit);
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_main.h b/drivers/net/ethernet/aquantia/atlantic/aq_main.h
new file mode 100644
index 000000000000..9748e7e575e0
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_main.h
@@ -0,0 +1,17 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_main.h: Main file for aQuantia Linux driver. */
11
12#ifndef AQ_MAIN_H
13#define AQ_MAIN_H
14
15#include "aq_common.h"
16
17#endif /* AQ_MAIN_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c
new file mode 100644
index 000000000000..84bb44186750
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c
@@ -0,0 +1,937 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_nic.c: Definition of common code for NIC. */
11
12#include "aq_nic.h"
13#include "aq_ring.h"
14#include "aq_vec.h"
15#include "aq_hw.h"
16#include "aq_pci_func.h"
17#include "aq_nic_internal.h"
18
19#include <linux/netdevice.h>
20#include <linux/etherdevice.h>
21#include <linux/timer.h>
22#include <linux/cpu.h>
23#include <linux/ip.h>
24#include <linux/tcp.h>
25#include <net/ip.h>
26
27static void aq_nic_rss_init(struct aq_nic_s *self, unsigned int num_rss_queues)
28{
29 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
30 struct aq_rss_parameters *rss_params = &cfg->aq_rss;
31 int i = 0;
32
33 static u8 rss_key[40] = {
34 0x1e, 0xad, 0x71, 0x87, 0x65, 0xfc, 0x26, 0x7d,
35 0x0d, 0x45, 0x67, 0x74, 0xcd, 0x06, 0x1a, 0x18,
36 0xb6, 0xc1, 0xf0, 0xc7, 0xbb, 0x18, 0xbe, 0xf8,
37 0x19, 0x13, 0x4b, 0xa9, 0xd0, 0x3e, 0xfe, 0x70,
38 0x25, 0x03, 0xab, 0x50, 0x6a, 0x8b, 0x82, 0x0c
39 };
40
41 rss_params->hash_secret_key_size = sizeof(rss_key);
42 memcpy(rss_params->hash_secret_key, rss_key, sizeof(rss_key));
43 rss_params->indirection_table_size = AQ_CFG_RSS_INDIRECTION_TABLE_MAX;
44
45 for (i = rss_params->indirection_table_size; i--;)
46 rss_params->indirection_table[i] = i & (num_rss_queues - 1);
47}
48
49/* Fills aq_nic_cfg with valid defaults */
50static void aq_nic_cfg_init_defaults(struct aq_nic_s *self)
51{
52 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
53
54 cfg->aq_hw_caps = &self->aq_hw_caps;
55
56 cfg->vecs = AQ_CFG_VECS_DEF;
57 cfg->tcs = AQ_CFG_TCS_DEF;
58
59 cfg->rxds = AQ_CFG_RXDS_DEF;
60 cfg->txds = AQ_CFG_TXDS_DEF;
61
62 cfg->is_polling = AQ_CFG_IS_POLLING_DEF;
63
64 cfg->is_interrupt_moderation = AQ_CFG_IS_INTERRUPT_MODERATION_DEF;
65 cfg->itr = cfg->is_interrupt_moderation ?
66 AQ_CFG_INTERRUPT_MODERATION_RATE_DEF : 0U;
67
68 cfg->is_rss = AQ_CFG_IS_RSS_DEF;
69 cfg->num_rss_queues = AQ_CFG_NUM_RSS_QUEUES_DEF;
70 cfg->aq_rss.base_cpu_number = AQ_CFG_RSS_BASE_CPU_NUM_DEF;
71 cfg->flow_control = AQ_CFG_FC_MODE;
72
73 cfg->mtu = AQ_CFG_MTU_DEF;
74 cfg->link_speed_msk = AQ_CFG_SPEED_MSK;
75 cfg->is_autoneg = AQ_CFG_IS_AUTONEG_DEF;
76
77 cfg->is_lro = AQ_CFG_IS_LRO_DEF;
78
79 cfg->vlan_id = 0U;
80
81 aq_nic_rss_init(self, cfg->num_rss_queues);
82}
83
84/* Checks hw_caps and 'corrects' aq_nic_cfg in runtime */
85int aq_nic_cfg_start(struct aq_nic_s *self)
86{
87 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
88
89 /*descriptors */
90 cfg->rxds = min(cfg->rxds, cfg->aq_hw_caps->rxds);
91 cfg->txds = min(cfg->txds, cfg->aq_hw_caps->txds);
92
93 /*rss rings */
94 cfg->vecs = min(cfg->vecs, cfg->aq_hw_caps->vecs);
95 cfg->vecs = min(cfg->vecs, num_online_cpus());
96 /* cfg->vecs should be power of 2 for RSS */
97 if (cfg->vecs >= 8U)
98 cfg->vecs = 8U;
99 else if (cfg->vecs >= 4U)
100 cfg->vecs = 4U;
101 else if (cfg->vecs >= 2U)
102 cfg->vecs = 2U;
103 else
104 cfg->vecs = 1U;
105
106 cfg->irq_type = aq_pci_func_get_irq_type(self->aq_pci_func);
107
108 if ((cfg->irq_type == AQ_HW_IRQ_LEGACY) ||
109 (self->aq_hw_caps.vecs == 1U) ||
110 (cfg->vecs == 1U)) {
111 cfg->is_rss = 0U;
112 cfg->vecs = 1U;
113 }
114
115 cfg->link_speed_msk &= self->aq_hw_caps.link_speed_msk;
116 cfg->hw_features = self->aq_hw_caps.hw_features;
117 return 0;
118}
119
120static void aq_nic_service_timer_cb(unsigned long param)
121{
122 struct aq_nic_s *self = (struct aq_nic_s *)param;
123 struct net_device *ndev = aq_nic_get_ndev(self);
124 int err = 0;
125 bool is_busy = false;
126 unsigned int i = 0U;
127 struct aq_hw_link_status_s link_status;
128 struct aq_ring_stats_rx_s stats_rx;
129 struct aq_ring_stats_tx_s stats_tx;
130
131 atomic_inc(&self->header.busy_count);
132 is_busy = true;
133 if (aq_utils_obj_test(&self->header.flags, AQ_NIC_FLAGS_IS_NOT_READY))
134 goto err_exit;
135
136 err = self->aq_hw_ops.hw_get_link_status(self->aq_hw, &link_status);
137 if (err < 0)
138 goto err_exit;
139
140 self->aq_hw_ops.hw_interrupt_moderation_set(self->aq_hw,
141 self->aq_nic_cfg.is_interrupt_moderation);
142
143 if (memcmp(&link_status, &self->link_status, sizeof(link_status))) {
144 if (link_status.mbps) {
145 aq_utils_obj_set(&self->header.flags,
146 AQ_NIC_FLAG_STARTED);
147 aq_utils_obj_clear(&self->header.flags,
148 AQ_NIC_LINK_DOWN);
149 netif_carrier_on(self->ndev);
150 } else {
151 netif_carrier_off(self->ndev);
152 aq_utils_obj_set(&self->header.flags, AQ_NIC_LINK_DOWN);
153 }
154
155 self->link_status = link_status;
156 }
157
158 memset(&stats_rx, 0U, sizeof(struct aq_ring_stats_rx_s));
159 memset(&stats_tx, 0U, sizeof(struct aq_ring_stats_tx_s));
160 for (i = AQ_DIMOF(self->aq_vec); i--;) {
161 if (self->aq_vec[i])
162 aq_vec_add_stats(self->aq_vec[i], &stats_rx, &stats_tx);
163 }
164
165 ndev->stats.rx_packets = stats_rx.packets;
166 ndev->stats.rx_bytes = stats_rx.bytes;
167 ndev->stats.rx_errors = stats_rx.errors;
168 ndev->stats.tx_packets = stats_tx.packets;
169 ndev->stats.tx_bytes = stats_tx.bytes;
170 ndev->stats.tx_errors = stats_tx.errors;
171
172err_exit:
173 if (is_busy)
174 atomic_dec(&self->header.busy_count);
175 mod_timer(&self->service_timer,
176 jiffies + AQ_CFG_SERVICE_TIMER_INTERVAL);
177}
178
179static void aq_nic_polling_timer_cb(unsigned long param)
180{
181 struct aq_nic_s *self = (struct aq_nic_s *)param;
182 struct aq_vec_s *aq_vec = NULL;
183 unsigned int i = 0U;
184
185 for (i = 0U, aq_vec = self->aq_vec[0];
186 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i])
187 aq_vec_isr(i, (void *)aq_vec);
188
189 mod_timer(&self->polling_timer, jiffies +
190 AQ_CFG_POLLING_TIMER_INTERVAL);
191}
192
193static struct net_device *aq_nic_ndev_alloc(void)
194{
195 return alloc_etherdev_mq(sizeof(struct aq_nic_s), AQ_CFG_VECS_MAX);
196}
197
198struct aq_nic_s *aq_nic_alloc_cold(const struct net_device_ops *ndev_ops,
199 const struct ethtool_ops *et_ops,
200 struct device *dev,
201 struct aq_pci_func_s *aq_pci_func,
202 unsigned int port,
203 const struct aq_hw_ops *aq_hw_ops)
204{
205 struct net_device *ndev = NULL;
206 struct aq_nic_s *self = NULL;
207 int err = 0;
208
209 ndev = aq_nic_ndev_alloc();
210 self = netdev_priv(ndev);
211 if (!self) {
212 err = -EINVAL;
213 goto err_exit;
214 }
215
216 ndev->netdev_ops = ndev_ops;
217 ndev->ethtool_ops = et_ops;
218
219 SET_NETDEV_DEV(ndev, dev);
220
221 ndev->if_port = port;
222 self->ndev = ndev;
223
224 self->aq_pci_func = aq_pci_func;
225
226 self->aq_hw_ops = *aq_hw_ops;
227 self->port = (u8)port;
228
229 self->aq_hw = self->aq_hw_ops.create(aq_pci_func, self->port,
230 &self->aq_hw_ops);
231 err = self->aq_hw_ops.get_hw_caps(self->aq_hw, &self->aq_hw_caps);
232 if (err < 0)
233 goto err_exit;
234
235 aq_nic_cfg_init_defaults(self);
236
237err_exit:
238 if (err < 0) {
239 aq_nic_free_hot_resources(self);
240 self = NULL;
241 }
242 return self;
243}
244
245int aq_nic_ndev_register(struct aq_nic_s *self)
246{
247 int err = 0;
248 unsigned int i = 0U;
249
250 if (!self->ndev) {
251 err = -EINVAL;
252 goto err_exit;
253 }
254 err = self->aq_hw_ops.hw_get_mac_permanent(self->aq_hw,
255 self->aq_nic_cfg.aq_hw_caps,
256 self->ndev->dev_addr);
257 if (err < 0)
258 goto err_exit;
259
260#if defined(AQ_CFG_MAC_ADDR_PERMANENT)
261 {
262 static u8 mac_addr_permanent[] = AQ_CFG_MAC_ADDR_PERMANENT;
263
264 ether_addr_copy(self->ndev->dev_addr, mac_addr_permanent);
265 }
266#endif
267 err = register_netdev(self->ndev);
268 if (err < 0)
269 goto err_exit;
270
271 self->is_ndev_registered = true;
272 netif_carrier_off(self->ndev);
273
274 for (i = AQ_CFG_VECS_MAX; i--;)
275 aq_nic_ndev_queue_stop(self, i);
276
277err_exit:
278 return err;
279}
280
281int aq_nic_ndev_init(struct aq_nic_s *self)
282{
283 struct aq_hw_caps_s *aq_hw_caps = self->aq_nic_cfg.aq_hw_caps;
284 struct aq_nic_cfg_s *aq_nic_cfg = &self->aq_nic_cfg;
285
286 self->ndev->hw_features |= aq_hw_caps->hw_features;
287 self->ndev->features = aq_hw_caps->hw_features;
288 self->ndev->priv_flags = aq_hw_caps->hw_priv_flags;
289 self->ndev->mtu = aq_nic_cfg->mtu - ETH_HLEN;
290
291 return 0;
292}
293
294void aq_nic_ndev_free(struct aq_nic_s *self)
295{
296 if (!self->ndev)
297 goto err_exit;
298
299 if (self->is_ndev_registered)
300 unregister_netdev(self->ndev);
301
302 if (self->aq_hw)
303 self->aq_hw_ops.destroy(self->aq_hw);
304
305 free_netdev(self->ndev);
306
307err_exit:;
308}
309
310struct aq_nic_s *aq_nic_alloc_hot(struct net_device *ndev)
311{
312 struct aq_nic_s *self = NULL;
313 int err = 0;
314
315 if (!ndev) {
316 err = -EINVAL;
317 goto err_exit;
318 }
319 self = netdev_priv(ndev);
320
321 if (!self) {
322 err = -EINVAL;
323 goto err_exit;
324 }
325 if (netif_running(ndev)) {
326 unsigned int i;
327
328 for (i = AQ_CFG_VECS_MAX; i--;)
329 netif_stop_subqueue(ndev, i);
330 }
331
332 for (self->aq_vecs = 0; self->aq_vecs < self->aq_nic_cfg.vecs;
333 self->aq_vecs++) {
334 self->aq_vec[self->aq_vecs] =
335 aq_vec_alloc(self, self->aq_vecs, &self->aq_nic_cfg);
336 if (!self->aq_vec[self->aq_vecs]) {
337 err = -ENOMEM;
338 goto err_exit;
339 }
340 }
341
342err_exit:
343 if (err < 0) {
344 aq_nic_free_hot_resources(self);
345 self = NULL;
346 }
347 return self;
348}
349
350void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx,
351 struct aq_ring_s *ring)
352{
353 self->aq_ring_tx[idx] = ring;
354}
355
356struct device *aq_nic_get_dev(struct aq_nic_s *self)
357{
358 return self->ndev->dev.parent;
359}
360
361struct net_device *aq_nic_get_ndev(struct aq_nic_s *self)
362{
363 return self->ndev;
364}
365
366int aq_nic_init(struct aq_nic_s *self)
367{
368 struct aq_vec_s *aq_vec = NULL;
369 int err = 0;
370 unsigned int i = 0U;
371
372 self->power_state = AQ_HW_POWER_STATE_D0;
373 err = self->aq_hw_ops.hw_reset(self->aq_hw);
374 if (err < 0)
375 goto err_exit;
376
377 err = self->aq_hw_ops.hw_init(self->aq_hw, &self->aq_nic_cfg,
378 aq_nic_get_ndev(self)->dev_addr);
379 if (err < 0)
380 goto err_exit;
381
382 for (i = 0U, aq_vec = self->aq_vec[0];
383 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i])
384 aq_vec_init(aq_vec, &self->aq_hw_ops, self->aq_hw);
385
386err_exit:
387 return err;
388}
389
390void aq_nic_ndev_queue_start(struct aq_nic_s *self, unsigned int idx)
391{
392 netif_start_subqueue(self->ndev, idx);
393}
394
395void aq_nic_ndev_queue_stop(struct aq_nic_s *self, unsigned int idx)
396{
397 netif_stop_subqueue(self->ndev, idx);
398}
399
400int aq_nic_start(struct aq_nic_s *self)
401{
402 struct aq_vec_s *aq_vec = NULL;
403 int err = 0;
404 unsigned int i = 0U;
405
406 err = self->aq_hw_ops.hw_multicast_list_set(self->aq_hw,
407 self->mc_list.ar,
408 self->mc_list.count);
409 if (err < 0)
410 goto err_exit;
411
412 err = self->aq_hw_ops.hw_packet_filter_set(self->aq_hw,
413 self->packet_filter);
414 if (err < 0)
415 goto err_exit;
416
417 for (i = 0U, aq_vec = self->aq_vec[0];
418 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) {
419 err = aq_vec_start(aq_vec);
420 if (err < 0)
421 goto err_exit;
422 }
423
424 err = self->aq_hw_ops.hw_start(self->aq_hw);
425 if (err < 0)
426 goto err_exit;
427
428 err = self->aq_hw_ops.hw_interrupt_moderation_set(self->aq_hw,
429 self->aq_nic_cfg.is_interrupt_moderation);
430 if (err < 0)
431 goto err_exit;
432 setup_timer(&self->service_timer, &aq_nic_service_timer_cb,
433 (unsigned long)self);
434 mod_timer(&self->service_timer, jiffies +
435 AQ_CFG_SERVICE_TIMER_INTERVAL);
436
437 if (self->aq_nic_cfg.is_polling) {
438 setup_timer(&self->polling_timer, &aq_nic_polling_timer_cb,
439 (unsigned long)self);
440 mod_timer(&self->polling_timer, jiffies +
441 AQ_CFG_POLLING_TIMER_INTERVAL);
442 } else {
443 for (i = 0U, aq_vec = self->aq_vec[0];
444 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) {
445 err = aq_pci_func_alloc_irq(self->aq_pci_func, i,
446 self->ndev->name, aq_vec,
447 aq_vec_get_affinity_mask(aq_vec));
448 if (err < 0)
449 goto err_exit;
450 }
451
452 err = self->aq_hw_ops.hw_irq_enable(self->aq_hw,
453 AQ_CFG_IRQ_MASK);
454 if (err < 0)
455 goto err_exit;
456 }
457
458 for (i = 0U, aq_vec = self->aq_vec[0];
459 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i])
460 aq_nic_ndev_queue_start(self, i);
461
462 err = netif_set_real_num_tx_queues(self->ndev, self->aq_vecs);
463 if (err < 0)
464 goto err_exit;
465
466 err = netif_set_real_num_rx_queues(self->ndev, self->aq_vecs);
467 if (err < 0)
468 goto err_exit;
469
470err_exit:
471 return err;
472}
473
474static unsigned int aq_nic_map_skb_frag(struct aq_nic_s *self,
475 struct sk_buff *skb,
476 struct aq_ring_buff_s *dx)
477{
478 unsigned int ret = 0U;
479 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
480 unsigned int frag_count = 0U;
481
482 dx->flags = 0U;
483 dx->len = skb_headlen(skb);
484 dx->pa = dma_map_single(aq_nic_get_dev(self), skb->data, dx->len,
485 DMA_TO_DEVICE);
486 dx->len_pkt = skb->len;
487 dx->is_sop = 1U;
488 dx->is_mapped = 1U;
489
490 ++ret;
491
492 if (skb->ip_summed == CHECKSUM_PARTIAL) {
493 dx->is_ip_cso = (htons(ETH_P_IP) == skb->protocol) ? 1U : 0U;
494 dx->is_tcp_cso =
495 (ip_hdr(skb)->protocol == IPPROTO_TCP) ? 1U : 0U;
496 dx->is_udp_cso =
497 (ip_hdr(skb)->protocol == IPPROTO_UDP) ? 1U : 0U;
498 }
499
500 for (; nr_frags--; ++frag_count) {
501 unsigned int frag_len;
502 dma_addr_t frag_pa;
503 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_count];
504
505 frag_len = skb_frag_size(frag);
506
507 frag_pa = skb_frag_dma_map(aq_nic_get_dev(self), frag, 0,
508 frag_len, DMA_TO_DEVICE);
509
510 while (frag_len > AQ_CFG_TX_FRAME_MAX) {
511 ++dx;
512 ++ret;
513 dx->flags = 0U;
514 dx->len = AQ_CFG_TX_FRAME_MAX;
515 dx->pa = frag_pa;
516 dx->is_mapped = 1U;
517
518 frag_len -= AQ_CFG_TX_FRAME_MAX;
519 frag_pa += AQ_CFG_TX_FRAME_MAX;
520 }
521
522 ++dx;
523 ++ret;
524
525 dx->flags = 0U;
526 dx->len = frag_len;
527 dx->pa = frag_pa;
528 dx->is_mapped = 1U;
529 }
530
531 dx->is_eop = 1U;
532 dx->skb = skb;
533
534 return ret;
535}
536
537static unsigned int aq_nic_map_skb_lso(struct aq_nic_s *self,
538 struct sk_buff *skb,
539 struct aq_ring_buff_s *dx)
540{
541 dx->flags = 0U;
542 dx->len_pkt = skb->len;
543 dx->len_l2 = ETH_HLEN;
544 dx->len_l3 = ip_hdrlen(skb);
545 dx->len_l4 = tcp_hdrlen(skb);
546 dx->mss = skb_shinfo(skb)->gso_size;
547 dx->is_txc = 1U;
548 return 1U;
549}
550
551static unsigned int aq_nic_map_skb(struct aq_nic_s *self, struct sk_buff *skb,
552 struct aq_ring_buff_s *dx)
553{
554 unsigned int ret = 0U;
555
556 if (unlikely(skb_is_gso(skb))) {
557 ret = aq_nic_map_skb_lso(self, skb, dx);
558 ++dx;
559 }
560
561 ret += aq_nic_map_skb_frag(self, skb, dx);
562
563 return ret;
564}
565
566int aq_nic_xmit(struct aq_nic_s *self, struct sk_buff *skb)
567__releases(&ring->lock)
568__acquires(&ring->lock)
569{
570 struct aq_ring_s *ring = NULL;
571 unsigned int frags = 0U;
572 unsigned int vec = skb->queue_mapping % self->aq_nic_cfg.vecs;
573 unsigned int tc = 0U;
574 unsigned int trys = AQ_CFG_LOCK_TRYS;
575 int err = 0;
576 bool is_nic_in_bad_state;
577 bool is_busy = false;
578 struct aq_ring_buff_s buffers[AQ_CFG_SKB_FRAGS_MAX];
579
580 frags = skb_shinfo(skb)->nr_frags + 1;
581
582 ring = self->aq_ring_tx[AQ_NIC_TCVEC2RING(self, tc, vec)];
583
584 atomic_inc(&self->header.busy_count);
585 is_busy = true;
586
587 if (frags > AQ_CFG_SKB_FRAGS_MAX) {
588 dev_kfree_skb_any(skb);
589 goto err_exit;
590 }
591
592 is_nic_in_bad_state = aq_utils_obj_test(&self->header.flags,
593 AQ_NIC_FLAGS_IS_NOT_TX_READY) ||
594 (aq_ring_avail_dx(ring) <
595 AQ_CFG_SKB_FRAGS_MAX);
596
597 if (is_nic_in_bad_state) {
598 aq_nic_ndev_queue_stop(self, ring->idx);
599 err = NETDEV_TX_BUSY;
600 goto err_exit;
601 }
602
603 do {
604 if (spin_trylock(&ring->header.lock)) {
605 frags = aq_nic_map_skb(self, skb, &buffers[0]);
606
607 aq_ring_tx_append_buffs(ring, &buffers[0], frags);
608
609 err = self->aq_hw_ops.hw_ring_tx_xmit(self->aq_hw,
610 ring, frags);
611 if (err >= 0) {
612 if (aq_ring_avail_dx(ring) <
613 AQ_CFG_SKB_FRAGS_MAX + 1)
614 aq_nic_ndev_queue_stop(self, ring->idx);
615 }
616 spin_unlock(&ring->header.lock);
617
618 if (err >= 0) {
619 ++ring->stats.tx.packets;
620 ring->stats.tx.bytes += skb->len;
621 }
622 break;
623 }
624 } while (--trys);
625
626 if (!trys) {
627 err = NETDEV_TX_BUSY;
628 goto err_exit;
629 }
630
631err_exit:
632 if (is_busy)
633 atomic_dec(&self->header.busy_count);
634 return err;
635}
636
637int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags)
638{
639 int err = 0;
640
641 err = self->aq_hw_ops.hw_packet_filter_set(self->aq_hw, flags);
642 if (err < 0)
643 goto err_exit;
644
645 self->packet_filter = flags;
646
647err_exit:
648 return err;
649}
650
651int aq_nic_set_multicast_list(struct aq_nic_s *self, struct net_device *ndev)
652{
653 struct netdev_hw_addr *ha = NULL;
654 unsigned int i = 0U;
655
656 self->mc_list.count = 0U;
657
658 netdev_for_each_mc_addr(ha, ndev) {
659 ether_addr_copy(self->mc_list.ar[i++], ha->addr);
660 ++self->mc_list.count;
661 }
662
663 return self->aq_hw_ops.hw_multicast_list_set(self->aq_hw,
664 self->mc_list.ar,
665 self->mc_list.count);
666}
667
668int aq_nic_set_mtu(struct aq_nic_s *self, int new_mtu)
669{
670 int err = 0;
671
672 if (new_mtu > self->aq_hw_caps.mtu) {
673 err = -EINVAL;
674 goto err_exit;
675 }
676 self->aq_nic_cfg.mtu = new_mtu;
677
678err_exit:
679 return err;
680}
681
682int aq_nic_set_mac(struct aq_nic_s *self, struct net_device *ndev)
683{
684 return self->aq_hw_ops.hw_set_mac_address(self->aq_hw, ndev->dev_addr);
685}
686
687unsigned int aq_nic_get_link_speed(struct aq_nic_s *self)
688{
689 return self->link_status.mbps;
690}
691
692int aq_nic_get_regs(struct aq_nic_s *self, struct ethtool_regs *regs, void *p)
693{
694 u32 *regs_buff = p;
695 int err = 0;
696
697 regs->version = 1;
698
699 err = self->aq_hw_ops.hw_get_regs(self->aq_hw,
700 &self->aq_hw_caps, regs_buff);
701 if (err < 0)
702 goto err_exit;
703
704err_exit:
705 return err;
706}
707
708int aq_nic_get_regs_count(struct aq_nic_s *self)
709{
710 return self->aq_hw_caps.mac_regs_count;
711}
712
713void aq_nic_get_stats(struct aq_nic_s *self, u64 *data)
714{
715 struct aq_vec_s *aq_vec = NULL;
716 unsigned int i = 0U;
717 unsigned int count = 0U;
718 int err = 0;
719
720 err = self->aq_hw_ops.hw_get_hw_stats(self->aq_hw, data, &count);
721 if (err < 0)
722 goto err_exit;
723
724 data += count;
725 count = 0U;
726
727 for (i = 0U, aq_vec = self->aq_vec[0];
728 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) {
729 data += count;
730 aq_vec_get_sw_stats(aq_vec, data, &count);
731 }
732
733err_exit:;
734 (void)err;
735}
736
737void aq_nic_get_link_settings(struct aq_nic_s *self, struct ethtool_cmd *cmd)
738{
739 cmd->port = PORT_TP;
740 cmd->transceiver = XCVR_EXTERNAL;
741 /* This driver supports only 10G capable adapters, so DUPLEX_FULL */
742 cmd->duplex = DUPLEX_FULL;
743 cmd->autoneg = self->aq_nic_cfg.is_autoneg;
744
745 cmd->supported |= (self->aq_hw_caps.link_speed_msk & AQ_NIC_RATE_10G) ?
746 ADVERTISED_10000baseT_Full : 0U;
747 cmd->supported |= (self->aq_hw_caps.link_speed_msk & AQ_NIC_RATE_1G) ?
748 ADVERTISED_1000baseT_Full : 0U;
749 cmd->supported |= (self->aq_hw_caps.link_speed_msk & AQ_NIC_RATE_100M) ?
750 ADVERTISED_100baseT_Full : 0U;
751 cmd->supported |= self->aq_hw_caps.flow_control ? SUPPORTED_Pause : 0;
752 cmd->supported |= SUPPORTED_Autoneg;
753
754 cmd->advertising = (self->aq_nic_cfg.is_autoneg) ?
755 ADVERTISED_Autoneg : 0U;
756 cmd->advertising |=
757 (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_10G) ?
758 ADVERTISED_10000baseT_Full : 0U;
759 cmd->advertising |=
760 (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_1G) ?
761 ADVERTISED_1000baseT_Full : 0U;
762
763 cmd->advertising |=
764 (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_100M) ?
765 ADVERTISED_100baseT_Full : 0U;
766 cmd->advertising |= (self->aq_nic_cfg.flow_control) ?
767 ADVERTISED_Pause : 0U;
768}
769
770int aq_nic_set_link_settings(struct aq_nic_s *self, struct ethtool_cmd *cmd)
771{
772 u32 speed = 0U;
773 u32 rate = 0U;
774 int err = 0;
775
776 if (cmd->autoneg == AUTONEG_ENABLE) {
777 rate = self->aq_hw_caps.link_speed_msk;
778 self->aq_nic_cfg.is_autoneg = true;
779 } else {
780 speed = ethtool_cmd_speed(cmd);
781
782 switch (speed) {
783 case SPEED_100:
784 rate = AQ_NIC_RATE_100M;
785 break;
786
787 case SPEED_1000:
788 rate = AQ_NIC_RATE_1G;
789 break;
790
791 case SPEED_2500:
792 rate = AQ_NIC_RATE_2GS;
793 break;
794
795 case SPEED_5000:
796 rate = AQ_NIC_RATE_5G;
797 break;
798
799 case SPEED_10000:
800 rate = AQ_NIC_RATE_10G;
801 break;
802
803 default:
804 err = -1;
805 goto err_exit;
806 break;
807 }
808 if (!(self->aq_hw_caps.link_speed_msk & rate)) {
809 err = -1;
810 goto err_exit;
811 }
812
813 self->aq_nic_cfg.is_autoneg = false;
814 }
815
816 err = self->aq_hw_ops.hw_set_link_speed(self->aq_hw, rate);
817 if (err < 0)
818 goto err_exit;
819
820 self->aq_nic_cfg.link_speed_msk = rate;
821
822err_exit:
823 return err;
824}
825
826struct aq_nic_cfg_s *aq_nic_get_cfg(struct aq_nic_s *self)
827{
828 return &self->aq_nic_cfg;
829}
830
831u32 aq_nic_get_fw_version(struct aq_nic_s *self)
832{
833 u32 fw_version = 0U;
834
835 self->aq_hw_ops.hw_get_fw_version(self->aq_hw, &fw_version);
836
837 return fw_version;
838}
839
840int aq_nic_stop(struct aq_nic_s *self)
841{
842 struct aq_vec_s *aq_vec = NULL;
843 unsigned int i = 0U;
844
845 for (i = 0U, aq_vec = self->aq_vec[0];
846 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i])
847 aq_nic_ndev_queue_stop(self, i);
848
849 del_timer_sync(&self->service_timer);
850
851 self->aq_hw_ops.hw_irq_disable(self->aq_hw, AQ_CFG_IRQ_MASK);
852
853 if (self->aq_nic_cfg.is_polling)
854 del_timer_sync(&self->polling_timer);
855 else
856 aq_pci_func_free_irqs(self->aq_pci_func);
857
858 for (i = 0U, aq_vec = self->aq_vec[0];
859 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i])
860 aq_vec_stop(aq_vec);
861
862 return self->aq_hw_ops.hw_stop(self->aq_hw);
863}
864
865void aq_nic_deinit(struct aq_nic_s *self)
866{
867 struct aq_vec_s *aq_vec = NULL;
868 unsigned int i = 0U;
869
870 if (!self)
871 goto err_exit;
872
873 for (i = 0U, aq_vec = self->aq_vec[0];
874 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i])
875 aq_vec_deinit(aq_vec);
876
877 if (self->power_state == AQ_HW_POWER_STATE_D0) {
878 (void)self->aq_hw_ops.hw_deinit(self->aq_hw);
879 } else {
880 (void)self->aq_hw_ops.hw_set_power(self->aq_hw,
881 self->power_state);
882 }
883
884err_exit:;
885}
886
887void aq_nic_free_hot_resources(struct aq_nic_s *self)
888{
889 unsigned int i = 0U;
890
891 if (!self)
892 goto err_exit;
893
894 for (i = AQ_DIMOF(self->aq_vec); i--;) {
895 if (self->aq_vec[i])
896 aq_vec_free(self->aq_vec[i]);
897 }
898
899err_exit:;
900}
901
902int aq_nic_change_pm_state(struct aq_nic_s *self, pm_message_t *pm_msg)
903{
904 int err = 0;
905
906 if (!netif_running(self->ndev)) {
907 err = 0;
908 goto err_exit;
909 }
910 rtnl_lock();
911 if (pm_msg->event & PM_EVENT_SLEEP || pm_msg->event & PM_EVENT_FREEZE) {
912 self->power_state = AQ_HW_POWER_STATE_D3;
913 netif_device_detach(self->ndev);
914 netif_tx_stop_all_queues(self->ndev);
915
916 err = aq_nic_stop(self);
917 if (err < 0)
918 goto err_exit;
919
920 aq_nic_deinit(self);
921 } else {
922 err = aq_nic_init(self);
923 if (err < 0)
924 goto err_exit;
925
926 err = aq_nic_start(self);
927 if (err < 0)
928 goto err_exit;
929
930 netif_device_attach(self->ndev);
931 netif_tx_start_all_queues(self->ndev);
932 }
933 rtnl_unlock();
934
935err_exit:
936 return err;
937}
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.h b/drivers/net/ethernet/aquantia/atlantic/aq_nic.h
new file mode 100644
index 000000000000..055e2cdb0f6f
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.h
@@ -0,0 +1,108 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_nic.h: Declaration of common code for NIC. */
11
12#ifndef AQ_NIC_H
13#define AQ_NIC_H
14
15#include "aq_common.h"
16#include "aq_rss.h"
17
18struct aq_ring_s;
19struct aq_pci_func_s;
20struct aq_hw_ops;
21
22#define AQ_NIC_FC_OFF 0U
23#define AQ_NIC_FC_TX 1U
24#define AQ_NIC_FC_RX 2U
25#define AQ_NIC_FC_FULL 3U
26#define AQ_NIC_FC_AUTO 4U
27
28#define AQ_NIC_RATE_10G BIT(0)
29#define AQ_NIC_RATE_5G BIT(1)
30#define AQ_NIC_RATE_5GSR BIT(2)
31#define AQ_NIC_RATE_2GS BIT(3)
32#define AQ_NIC_RATE_1G BIT(4)
33#define AQ_NIC_RATE_100M BIT(5)
34
35struct aq_nic_cfg_s {
36 struct aq_hw_caps_s *aq_hw_caps;
37 u64 hw_features;
38 u32 rxds; /* rx ring size, descriptors # */
39 u32 txds; /* tx ring size, descriptors # */
40 u32 vecs; /* vecs==allocated irqs */
41 u32 irq_type;
42 u32 itr;
43 u32 num_rss_queues;
44 u32 mtu;
45 u32 ucp_0x364;
46 u32 flow_control;
47 u32 link_speed_msk;
48 u32 vlan_id;
49 u16 is_mc_list_enabled;
50 u16 mc_list_count;
51 bool is_autoneg;
52 bool is_interrupt_moderation;
53 bool is_polling;
54 bool is_rss;
55 bool is_lro;
56 u8 tcs;
57 struct aq_rss_parameters aq_rss;
58};
59
60#define AQ_NIC_FLAG_STARTED 0x00000004U
61#define AQ_NIC_FLAG_STOPPING 0x00000008U
62#define AQ_NIC_FLAG_RESETTING 0x00000010U
63#define AQ_NIC_FLAG_CLOSING 0x00000020U
64#define AQ_NIC_LINK_DOWN 0x04000000U
65#define AQ_NIC_FLAG_ERR_UNPLUG 0x40000000U
66#define AQ_NIC_FLAG_ERR_HW 0x80000000U
67
68#define AQ_NIC_TCVEC2RING(_NIC_, _TC_, _VEC_) \
69 ((_TC_) * AQ_CFG_TCS_MAX + (_VEC_))
70
71struct aq_nic_s *aq_nic_alloc_cold(const struct net_device_ops *ndev_ops,
72 const struct ethtool_ops *et_ops,
73 struct device *dev,
74 struct aq_pci_func_s *aq_pci_func,
75 unsigned int port,
76 const struct aq_hw_ops *aq_hw_ops);
77int aq_nic_ndev_init(struct aq_nic_s *self);
78struct aq_nic_s *aq_nic_alloc_hot(struct net_device *ndev);
79void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx,
80 struct aq_ring_s *ring);
81struct device *aq_nic_get_dev(struct aq_nic_s *self);
82struct net_device *aq_nic_get_ndev(struct aq_nic_s *self);
83int aq_nic_init(struct aq_nic_s *self);
84int aq_nic_cfg_start(struct aq_nic_s *self);
85int aq_nic_ndev_register(struct aq_nic_s *self);
86void aq_nic_ndev_queue_start(struct aq_nic_s *self, unsigned int idx);
87void aq_nic_ndev_queue_stop(struct aq_nic_s *self, unsigned int idx);
88void aq_nic_ndev_free(struct aq_nic_s *self);
89int aq_nic_start(struct aq_nic_s *self);
90int aq_nic_xmit(struct aq_nic_s *self, struct sk_buff *skb);
91int aq_nic_get_regs(struct aq_nic_s *self, struct ethtool_regs *regs, void *p);
92int aq_nic_get_regs_count(struct aq_nic_s *self);
93void aq_nic_get_stats(struct aq_nic_s *self, u64 *data);
94int aq_nic_stop(struct aq_nic_s *self);
95void aq_nic_deinit(struct aq_nic_s *self);
96void aq_nic_free_hot_resources(struct aq_nic_s *self);
97int aq_nic_set_mtu(struct aq_nic_s *self, int new_mtu);
98int aq_nic_set_mac(struct aq_nic_s *self, struct net_device *ndev);
99int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags);
100int aq_nic_set_multicast_list(struct aq_nic_s *self, struct net_device *ndev);
101unsigned int aq_nic_get_link_speed(struct aq_nic_s *self);
102void aq_nic_get_link_settings(struct aq_nic_s *self, struct ethtool_cmd *cmd);
103int aq_nic_set_link_settings(struct aq_nic_s *self, struct ethtool_cmd *cmd);
104struct aq_nic_cfg_s *aq_nic_get_cfg(struct aq_nic_s *self);
105u32 aq_nic_get_fw_version(struct aq_nic_s *self);
106int aq_nic_change_pm_state(struct aq_nic_s *self, pm_message_t *pm_msg);
107
108#endif /* AQ_NIC_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic_internal.h b/drivers/net/ethernet/aquantia/atlantic/aq_nic_internal.h
new file mode 100644
index 000000000000..f81738a71c42
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic_internal.h
@@ -0,0 +1,46 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_nic_internal.h: Definition of private object structure. */
11
12#ifndef AQ_NIC_INTERNAL_H
13#define AQ_NIC_INTERNAL_H
14
15struct aq_nic_s {
16 struct aq_obj_s header;
17 struct aq_vec_s *aq_vec[AQ_CFG_VECS_MAX];
18 struct aq_ring_s *aq_ring_tx[AQ_CFG_VECS_MAX * AQ_CFG_TCS_MAX];
19 struct aq_hw_s *aq_hw;
20 struct net_device *ndev;
21 struct aq_pci_func_s *aq_pci_func;
22 unsigned int aq_vecs;
23 unsigned int packet_filter;
24 unsigned int power_state;
25 bool is_ndev_registered;
26 u8 port;
27 struct aq_hw_ops aq_hw_ops;
28 struct aq_hw_caps_s aq_hw_caps;
29 struct aq_nic_cfg_s aq_nic_cfg;
30 struct timer_list service_timer;
31 struct timer_list polling_timer;
32 struct aq_hw_link_status_s link_status;
33 struct {
34 u32 count;
35 u8 ar[AQ_CFG_MULTICAST_ADDRESS_MAX][ETH_ALEN];
36 } mc_list;
37};
38
39#define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING | \
40 AQ_NIC_FLAG_RESETTING | AQ_NIC_FLAG_CLOSING | \
41 AQ_NIC_FLAG_ERR_UNPLUG | AQ_NIC_FLAG_ERR_HW)
42
43#define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \
44 AQ_NIC_LINK_DOWN)
45
46#endif /* AQ_NIC_INTERNAL_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c
new file mode 100644
index 000000000000..afcecdbf124c
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c
@@ -0,0 +1,345 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_pci_func.c: Definition of PCI functions. */
11
12#include "aq_pci_func.h"
13#include "aq_nic.h"
14#include "aq_vec.h"
15#include "aq_hw.h"
16#include <linux/interrupt.h>
17
18struct aq_pci_func_s {
19 struct pci_dev *pdev;
20 struct aq_nic_s *port[AQ_CFG_PCI_FUNC_PORTS];
21 void __iomem *mmio;
22 void *aq_vec[AQ_CFG_PCI_FUNC_MSIX_IRQS];
23 resource_size_t mmio_pa;
24 unsigned int msix_entry_mask;
25 unsigned int irq_type;
26 unsigned int ports;
27 bool is_pci_enabled;
28 bool is_regions;
29 bool is_pci_using_dac;
30 struct aq_hw_caps_s aq_hw_caps;
31 struct msix_entry msix_entry[AQ_CFG_PCI_FUNC_MSIX_IRQS];
32};
33
34struct aq_pci_func_s *aq_pci_func_alloc(struct aq_hw_ops *aq_hw_ops,
35 struct pci_dev *pdev,
36 const struct net_device_ops *ndev_ops,
37 const struct ethtool_ops *eth_ops)
38{
39 struct aq_pci_func_s *self = NULL;
40 int err = 0;
41 unsigned int port = 0U;
42
43 if (!aq_hw_ops) {
44 err = -EFAULT;
45 goto err_exit;
46 }
47 self = kzalloc(sizeof(*self), GFP_KERNEL);
48 if (!self) {
49 err = -ENOMEM;
50 goto err_exit;
51 }
52
53 pci_set_drvdata(pdev, self);
54 self->pdev = pdev;
55
56 err = aq_hw_ops->get_hw_caps(NULL, &self->aq_hw_caps);
57 if (err < 0)
58 goto err_exit;
59
60 self->ports = self->aq_hw_caps.ports;
61
62 for (port = 0; port < self->ports; ++port) {
63 struct aq_nic_s *aq_nic = aq_nic_alloc_cold(ndev_ops, eth_ops,
64 &pdev->dev, self,
65 port, aq_hw_ops);
66
67 if (!aq_nic) {
68 err = -ENOMEM;
69 goto err_exit;
70 }
71 self->port[port] = aq_nic;
72 }
73
74err_exit:
75 if (err < 0) {
76 if (self)
77 aq_pci_func_free(self);
78 self = NULL;
79 }
80
81 (void)err;
82 return self;
83}
84
85int aq_pci_func_init(struct aq_pci_func_s *self)
86{
87 int err = 0;
88 unsigned int bar = 0U;
89 unsigned int port = 0U;
90 unsigned int i = 0U;
91
92 err = pci_enable_device(self->pdev);
93 if (err < 0)
94 goto err_exit;
95
96 self->is_pci_enabled = true;
97
98 err = pci_set_dma_mask(self->pdev, DMA_BIT_MASK(64));
99 if (!err) {
100 err = pci_set_consistent_dma_mask(self->pdev, DMA_BIT_MASK(64));
101 self->is_pci_using_dac = 1;
102 }
103 if (err) {
104 err = pci_set_dma_mask(self->pdev, DMA_BIT_MASK(32));
105 if (!err)
106 err = pci_set_consistent_dma_mask(self->pdev,
107 DMA_BIT_MASK(32));
108 self->is_pci_using_dac = 0;
109 }
110 if (err != 0) {
111 err = -ENOSR;
112 goto err_exit;
113 }
114
115 err = pci_request_regions(self->pdev, AQ_CFG_DRV_NAME "_mmio");
116 if (err < 0)
117 goto err_exit;
118
119 self->is_regions = true;
120
121 pci_set_master(self->pdev);
122
123 for (bar = 0; bar < 4; ++bar) {
124 if (IORESOURCE_MEM & pci_resource_flags(self->pdev, bar)) {
125 resource_size_t reg_sz;
126
127 self->mmio_pa = pci_resource_start(self->pdev, bar);
128 if (self->mmio_pa == 0U) {
129 err = -EIO;
130 goto err_exit;
131 }
132
133 reg_sz = pci_resource_len(self->pdev, bar);
134 if ((reg_sz <= 24 /*ATL_REGS_SIZE*/)) {
135 err = -EIO;
136 goto err_exit;
137 }
138
139 self->mmio = ioremap_nocache(self->mmio_pa, reg_sz);
140 if (!self->mmio) {
141 err = -EIO;
142 goto err_exit;
143 }
144 break;
145 }
146 }
147
148 if (err < 0)
149 goto err_exit;
150 for (i = 0; i < self->aq_hw_caps.msix_irqs; i++)
151 self->msix_entry[i].entry = i;
152
153 /*enable interrupts */
154#if AQ_CFG_FORCE_LEGACY_INT
155 self->irq_type = AQ_HW_IRQ_LEGACY;
156#else
157 err = pci_enable_msix(self->pdev, self->msix_entry,
158 self->aq_hw_caps.msix_irqs);
159
160 if (err >= 0) {
161 self->irq_type = AQ_HW_IRQ_MSIX;
162 } else {
163 err = pci_enable_msi(self->pdev);
164
165 if (err >= 0) {
166 self->irq_type = AQ_HW_IRQ_MSI;
167 } else {
168 self->irq_type = AQ_HW_IRQ_LEGACY;
169 err = 0;
170 }
171 }
172#endif
173
174 /* net device init */
175 for (port = 0; port < self->ports; ++port) {
176 if (!self->port[port])
177 continue;
178
179 err = aq_nic_cfg_start(self->port[port]);
180 if (err < 0)
181 goto err_exit;
182
183 err = aq_nic_ndev_init(self->port[port]);
184 if (err < 0)
185 goto err_exit;
186
187 err = aq_nic_ndev_register(self->port[port]);
188 if (err < 0)
189 goto err_exit;
190 }
191
192err_exit:
193 if (err < 0)
194 aq_pci_func_deinit(self);
195 return err;
196}
197
198int aq_pci_func_alloc_irq(struct aq_pci_func_s *self, unsigned int i,
199 char *name, void *aq_vec, cpumask_t *affinity_mask)
200{
201 int err = 0;
202
203 switch (self->irq_type) {
204 case AQ_HW_IRQ_MSIX:
205 err = request_irq(self->msix_entry[i].vector, aq_vec_isr, 0,
206 name, aq_vec);
207 break;
208
209 case AQ_HW_IRQ_MSI:
210 err = request_irq(self->pdev->irq, aq_vec_isr, 0, name, aq_vec);
211 break;
212
213 case AQ_HW_IRQ_LEGACY:
214 err = request_irq(self->pdev->irq, aq_vec_isr_legacy,
215 IRQF_SHARED, name, aq_vec);
216 break;
217
218 default:
219 err = -EFAULT;
220 break;
221 }
222
223 if (err >= 0) {
224 self->msix_entry_mask |= (1 << i);
225 self->aq_vec[i] = aq_vec;
226
227 if (self->irq_type == AQ_HW_IRQ_MSIX)
228 irq_set_affinity_hint(self->msix_entry[i].vector,
229 affinity_mask);
230 }
231
232 return err;
233}
234
235void aq_pci_func_free_irqs(struct aq_pci_func_s *self)
236{
237 unsigned int i = 0U;
238
239 for (i = 32U; i--;) {
240 if (!((1U << i) & self->msix_entry_mask))
241 continue;
242
243 switch (self->irq_type) {
244 case AQ_HW_IRQ_MSIX:
245 irq_set_affinity_hint(self->msix_entry[i].vector, NULL);
246 free_irq(self->msix_entry[i].vector, self->aq_vec[i]);
247 break;
248
249 case AQ_HW_IRQ_MSI:
250 free_irq(self->pdev->irq, self->aq_vec[i]);
251 break;
252
253 case AQ_HW_IRQ_LEGACY:
254 free_irq(self->pdev->irq, self->aq_vec[i]);
255 break;
256
257 default:
258 break;
259 }
260
261 self->msix_entry_mask &= ~(1U << i);
262 }
263}
264
265void __iomem *aq_pci_func_get_mmio(struct aq_pci_func_s *self)
266{
267 return self->mmio;
268}
269
270unsigned int aq_pci_func_get_irq_type(struct aq_pci_func_s *self)
271{
272 return self->irq_type;
273}
274
275void aq_pci_func_deinit(struct aq_pci_func_s *self)
276{
277 if (!self)
278 goto err_exit;
279
280 aq_pci_func_free_irqs(self);
281
282 switch (self->irq_type) {
283 case AQ_HW_IRQ_MSI:
284 pci_disable_msi(self->pdev);
285 break;
286
287 case AQ_HW_IRQ_MSIX:
288 pci_disable_msix(self->pdev);
289 break;
290
291 case AQ_HW_IRQ_LEGACY:
292 break;
293
294 default:
295 break;
296 }
297
298 if (self->is_regions)
299 pci_release_regions(self->pdev);
300
301 if (self->is_pci_enabled)
302 pci_disable_device(self->pdev);
303
304err_exit:;
305}
306
307void aq_pci_func_free(struct aq_pci_func_s *self)
308{
309 unsigned int port = 0U;
310
311 if (!self)
312 goto err_exit;
313
314 for (port = 0; port < self->ports; ++port) {
315 if (!self->port[port])
316 continue;
317
318 aq_nic_ndev_free(self->port[port]);
319 }
320
321 kfree(self);
322
323err_exit:;
324}
325
326int aq_pci_func_change_pm_state(struct aq_pci_func_s *self,
327 pm_message_t *pm_msg)
328{
329 int err = 0;
330 unsigned int port = 0U;
331
332 if (!self) {
333 err = -EFAULT;
334 goto err_exit;
335 }
336 for (port = 0; port < self->ports; ++port) {
337 if (!self->port[port])
338 continue;
339
340 (void)aq_nic_change_pm_state(self->port[port], pm_msg);
341 }
342
343err_exit:
344 return err;
345}
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h
new file mode 100644
index 000000000000..ecb033791203
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h
@@ -0,0 +1,34 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_pci_func.h: Declaration of PCI functions. */
11
12#ifndef AQ_PCI_FUNC_H
13#define AQ_PCI_FUNC_H
14
15#include "aq_common.h"
16
17struct aq_pci_func_s *aq_pci_func_alloc(struct aq_hw_ops *hw_ops,
18 struct pci_dev *pdev,
19 const struct net_device_ops *ndev_ops,
20 const struct ethtool_ops *eth_ops);
21int aq_pci_func_init(struct aq_pci_func_s *self);
22int aq_pci_func_alloc_irq(struct aq_pci_func_s *self, unsigned int i,
23 char *name, void *aq_vec,
24 cpumask_t *affinity_mask);
25void aq_pci_func_free_irqs(struct aq_pci_func_s *self);
26int aq_pci_func_start(struct aq_pci_func_s *self);
27void __iomem *aq_pci_func_get_mmio(struct aq_pci_func_s *self);
28unsigned int aq_pci_func_get_irq_type(struct aq_pci_func_s *self);
29void aq_pci_func_deinit(struct aq_pci_func_s *self);
30void aq_pci_func_free(struct aq_pci_func_s *self);
31int aq_pci_func_change_pm_state(struct aq_pci_func_s *self,
32 pm_message_t *pm_msg);
33
34#endif /* AQ_PCI_FUNC_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ring.c b/drivers/net/ethernet/aquantia/atlantic/aq_ring.c
new file mode 100644
index 000000000000..b517b2670a71
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_ring.c
@@ -0,0 +1,376 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_ring.c: Definition of functions for Rx/Tx rings. */
11
12#include "aq_ring.h"
13#include "aq_nic.h"
14#include "aq_hw.h"
15
16#include <linux/netdevice.h>
17#include <linux/etherdevice.h>
18
19static struct aq_ring_s *aq_ring_alloc(struct aq_ring_s *self,
20 struct aq_nic_s *aq_nic)
21{
22 int err = 0;
23
24 self->buff_ring =
25 kcalloc(self->size, sizeof(struct aq_ring_buff_s), GFP_KERNEL);
26
27 if (!self->buff_ring) {
28 err = -ENOMEM;
29 goto err_exit;
30 }
31 self->dx_ring = dma_alloc_coherent(aq_nic_get_dev(aq_nic),
32 self->size * self->dx_size,
33 &self->dx_ring_pa, GFP_KERNEL);
34 if (!self->dx_ring) {
35 err = -ENOMEM;
36 goto err_exit;
37 }
38
39err_exit:
40 if (err < 0) {
41 aq_ring_free(self);
42 self = NULL;
43 }
44 return self;
45}
46
47struct aq_ring_s *aq_ring_tx_alloc(struct aq_ring_s *self,
48 struct aq_nic_s *aq_nic,
49 unsigned int idx,
50 struct aq_nic_cfg_s *aq_nic_cfg)
51{
52 int err = 0;
53
54 self->aq_nic = aq_nic;
55 self->idx = idx;
56 self->size = aq_nic_cfg->txds;
57 self->dx_size = aq_nic_cfg->aq_hw_caps->txd_size;
58
59 self = aq_ring_alloc(self, aq_nic);
60 if (!self) {
61 err = -ENOMEM;
62 goto err_exit;
63 }
64
65err_exit:
66 if (err < 0) {
67 aq_ring_free(self);
68 self = NULL;
69 }
70 return self;
71}
72
73struct aq_ring_s *aq_ring_rx_alloc(struct aq_ring_s *self,
74 struct aq_nic_s *aq_nic,
75 unsigned int idx,
76 struct aq_nic_cfg_s *aq_nic_cfg)
77{
78 int err = 0;
79
80 self->aq_nic = aq_nic;
81 self->idx = idx;
82 self->size = aq_nic_cfg->rxds;
83 self->dx_size = aq_nic_cfg->aq_hw_caps->rxd_size;
84
85 self = aq_ring_alloc(self, aq_nic);
86 if (!self) {
87 err = -ENOMEM;
88 goto err_exit;
89 }
90
91err_exit:
92 if (err < 0) {
93 aq_ring_free(self);
94 self = NULL;
95 }
96 return self;
97}
98
99int aq_ring_init(struct aq_ring_s *self)
100{
101 self->hw_head = 0;
102 self->sw_head = 0;
103 self->sw_tail = 0;
104 return 0;
105}
106
107void aq_ring_tx_append_buffs(struct aq_ring_s *self,
108 struct aq_ring_buff_s *buffer,
109 unsigned int buffers)
110{
111 if (likely(self->sw_tail + buffers < self->size)) {
112 memcpy(&self->buff_ring[self->sw_tail], buffer,
113 sizeof(buffer[0]) * buffers);
114 } else {
115 unsigned int first_part = self->size - self->sw_tail;
116 unsigned int second_part = buffers - first_part;
117
118 memcpy(&self->buff_ring[self->sw_tail], buffer,
119 sizeof(buffer[0]) * first_part);
120
121 memcpy(&self->buff_ring[0], &buffer[first_part],
122 sizeof(buffer[0]) * second_part);
123 }
124}
125
126int aq_ring_tx_clean(struct aq_ring_s *self)
127{
128 struct device *dev = aq_nic_get_dev(self->aq_nic);
129
130 for (; self->sw_head != self->hw_head;
131 self->sw_head = aq_ring_next_dx(self, self->sw_head)) {
132 struct aq_ring_buff_s *buff = &self->buff_ring[self->sw_head];
133
134 if (likely(buff->is_mapped)) {
135 if (unlikely(buff->is_sop))
136 dma_unmap_single(dev, buff->pa, buff->len,
137 DMA_TO_DEVICE);
138 else
139 dma_unmap_page(dev, buff->pa, buff->len,
140 DMA_TO_DEVICE);
141 }
142
143 if (unlikely(buff->is_eop))
144 dev_kfree_skb_any(buff->skb);
145 }
146
147 if (aq_ring_avail_dx(self) > AQ_CFG_SKB_FRAGS_MAX)
148 aq_nic_ndev_queue_start(self->aq_nic, self->idx);
149
150 return 0;
151}
152
153static inline unsigned int aq_ring_dx_in_range(unsigned int h, unsigned int i,
154 unsigned int t)
155{
156 return (h < t) ? ((h < i) && (i < t)) : ((h < i) || (i < t));
157}
158
159#define AQ_SKB_ALIGN SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
160int aq_ring_rx_clean(struct aq_ring_s *self, int *work_done, int budget)
161{
162 struct net_device *ndev = aq_nic_get_ndev(self->aq_nic);
163 int err = 0;
164 bool is_rsc_completed = true;
165
166 for (; (self->sw_head != self->hw_head) && budget;
167 self->sw_head = aq_ring_next_dx(self, self->sw_head),
168 --budget, ++(*work_done)) {
169 struct aq_ring_buff_s *buff = &self->buff_ring[self->sw_head];
170 struct sk_buff *skb = NULL;
171 unsigned int next_ = 0U;
172 unsigned int i = 0U;
173 struct aq_ring_buff_s *buff_ = NULL;
174
175 if (buff->is_error) {
176 __free_pages(buff->page, 0);
177 continue;
178 }
179
180 if (buff->is_cleaned)
181 continue;
182
183 if (!buff->is_eop) {
184 for (next_ = buff->next,
185 buff_ = &self->buff_ring[next_]; true;
186 next_ = buff_->next,
187 buff_ = &self->buff_ring[next_]) {
188 is_rsc_completed =
189 aq_ring_dx_in_range(self->sw_head,
190 next_,
191 self->hw_head);
192
193 if (unlikely(!is_rsc_completed)) {
194 is_rsc_completed = false;
195 break;
196 }
197
198 if (buff_->is_eop)
199 break;
200 }
201
202 if (!is_rsc_completed) {
203 err = 0;
204 goto err_exit;
205 }
206 }
207
208 /* for single fragment packets use build_skb() */
209 if (buff->is_eop) {
210 skb = build_skb(page_address(buff->page),
211 buff->len + AQ_SKB_ALIGN);
212 if (unlikely(!skb)) {
213 err = -ENOMEM;
214 goto err_exit;
215 }
216
217 skb->dev = ndev;
218 skb_put(skb, buff->len);
219 } else {
220 skb = netdev_alloc_skb(ndev, ETH_HLEN);
221 if (unlikely(!skb)) {
222 err = -ENOMEM;
223 goto err_exit;
224 }
225 skb_put(skb, ETH_HLEN);
226 memcpy(skb->data, page_address(buff->page), ETH_HLEN);
227
228 skb_add_rx_frag(skb, 0, buff->page, ETH_HLEN,
229 buff->len - ETH_HLEN,
230 SKB_TRUESIZE(buff->len - ETH_HLEN));
231
232 for (i = 1U, next_ = buff->next,
233 buff_ = &self->buff_ring[next_]; true;
234 next_ = buff_->next,
235 buff_ = &self->buff_ring[next_], ++i) {
236 skb_add_rx_frag(skb, i, buff_->page, 0,
237 buff_->len,
238 SKB_TRUESIZE(buff->len -
239 ETH_HLEN));
240 buff_->is_cleaned = 1;
241
242 if (buff_->is_eop)
243 break;
244 }
245 }
246
247 skb->protocol = eth_type_trans(skb, ndev);
248 if (unlikely(buff->is_cso_err)) {
249 ++self->stats.rx.errors;
250 __skb_mark_checksum_bad(skb);
251 } else {
252 if (buff->is_ip_cso) {
253 __skb_incr_checksum_unnecessary(skb);
254 if (buff->is_udp_cso || buff->is_tcp_cso)
255 __skb_incr_checksum_unnecessary(skb);
256 } else {
257 skb->ip_summed = CHECKSUM_NONE;
258 }
259 }
260
261 skb_set_hash(skb, buff->rss_hash,
262 buff->is_hash_l4 ? PKT_HASH_TYPE_L4 :
263 PKT_HASH_TYPE_NONE);
264
265 skb_record_rx_queue(skb, self->idx);
266
267 netif_receive_skb(skb);
268
269 ++self->stats.rx.packets;
270 self->stats.rx.bytes += skb->len;
271 }
272
273err_exit:
274 return err;
275}
276
277int aq_ring_rx_fill(struct aq_ring_s *self)
278{
279 struct aq_ring_buff_s *buff = NULL;
280 int err = 0;
281 int i = 0;
282
283 for (i = aq_ring_avail_dx(self); i--;
284 self->sw_tail = aq_ring_next_dx(self, self->sw_tail)) {
285 buff = &self->buff_ring[self->sw_tail];
286
287 buff->flags = 0U;
288 buff->len = AQ_CFG_RX_FRAME_MAX;
289
290 buff->page = alloc_pages(GFP_ATOMIC | __GFP_COLD |
291 __GFP_COMP, 0);
292 if (!buff->page) {
293 err = -ENOMEM;
294 goto err_exit;
295 }
296
297 buff->pa = dma_map_page(aq_nic_get_dev(self->aq_nic),
298 buff->page, 0,
299 AQ_CFG_RX_FRAME_MAX, DMA_FROM_DEVICE);
300
301 err = dma_mapping_error(aq_nic_get_dev(self->aq_nic), buff->pa);
302 if (err < 0)
303 goto err_exit;
304
305 buff = NULL;
306 }
307 if (err < 0)
308 goto err_exit;
309
310err_exit:
311 if (err < 0) {
312 if (buff && buff->page)
313 __free_pages(buff->page, 0);
314 }
315
316 return err;
317}
318
319void aq_ring_rx_deinit(struct aq_ring_s *self)
320{
321 if (!self)
322 goto err_exit;
323
324 for (; self->sw_head != self->sw_tail;
325 self->sw_head = aq_ring_next_dx(self, self->sw_head)) {
326 struct aq_ring_buff_s *buff = &self->buff_ring[self->sw_head];
327
328 dma_unmap_page(aq_nic_get_dev(self->aq_nic), buff->pa,
329 AQ_CFG_RX_FRAME_MAX, DMA_FROM_DEVICE);
330
331 __free_pages(buff->page, 0);
332 }
333
334err_exit:;
335}
336
337void aq_ring_tx_deinit(struct aq_ring_s *self)
338{
339 if (!self)
340 goto err_exit;
341
342 for (; self->sw_head != self->sw_tail;
343 self->sw_head = aq_ring_next_dx(self, self->sw_head)) {
344 struct aq_ring_buff_s *buff = &self->buff_ring[self->sw_head];
345 struct device *ndev = aq_nic_get_dev(self->aq_nic);
346
347 if (likely(buff->is_mapped)) {
348 if (unlikely(buff->is_sop)) {
349 dma_unmap_single(ndev, buff->pa, buff->len,
350 DMA_TO_DEVICE);
351 } else {
352 dma_unmap_page(ndev, buff->pa, buff->len,
353 DMA_TO_DEVICE);
354 }
355 }
356
357 if (unlikely(buff->is_eop))
358 dev_kfree_skb_any(buff->skb);
359 }
360err_exit:;
361}
362
363void aq_ring_free(struct aq_ring_s *self)
364{
365 if (!self)
366 goto err_exit;
367
368 kfree(self->buff_ring);
369
370 if (self->dx_ring)
371 dma_free_coherent(aq_nic_get_dev(self->aq_nic),
372 self->size * self->dx_size, self->dx_ring,
373 self->dx_ring_pa);
374
375err_exit:;
376}
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ring.h b/drivers/net/ethernet/aquantia/atlantic/aq_ring.h
new file mode 100644
index 000000000000..0ac3f9e7bee6
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_ring.h
@@ -0,0 +1,157 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_ring.h: Declaration of functions for Rx/Tx rings. */
11
12#ifndef AQ_RING_H
13#define AQ_RING_H
14
15#include "aq_common.h"
16
17struct page;
18
19/* TxC SOP DX EOP
20 * +----------+----------+----------+-----------
21 * 8bytes|len l3,l4 | pa | pa | pa
22 * +----------+----------+----------+-----------
23 * 4/8bytes|len pkt |len pkt | | skb
24 * +----------+----------+----------+-----------
25 * 4/8bytes|is_txc |len,flags |len |len,is_eop
26 * +----------+----------+----------+-----------
27 *
28 * This aq_ring_buff_s doesn't have endianness dependency.
29 * It is __packed for cache line optimizations.
30 */
31struct __packed aq_ring_buff_s {
32 union {
33 /* RX */
34 struct {
35 u32 rss_hash;
36 u16 next;
37 u8 is_hash_l4;
38 u8 rsvd1;
39 struct page *page;
40 };
41 /* EOP */
42 struct {
43 dma_addr_t pa_eop;
44 struct sk_buff *skb;
45 };
46 /* DX */
47 struct {
48 dma_addr_t pa;
49 };
50 /* SOP */
51 struct {
52 dma_addr_t pa_sop;
53 u32 len_pkt_sop;
54 };
55 /* TxC */
56 struct {
57 u32 mss;
58 u8 len_l2;
59 u8 len_l3;
60 u8 len_l4;
61 u8 rsvd2;
62 u32 len_pkt;
63 };
64 };
65 union {
66 struct {
67 u32 len:16;
68 u32 is_ip_cso:1;
69 u32 is_udp_cso:1;
70 u32 is_tcp_cso:1;
71 u32 is_cso_err:1;
72 u32 is_sop:1;
73 u32 is_eop:1;
74 u32 is_txc:1;
75 u32 is_mapped:1;
76 u32 is_cleaned:1;
77 u32 is_error:1;
78 u32 rsvd3:6;
79 };
80 u32 flags;
81 };
82};
83
84struct aq_ring_stats_rx_s {
85 u64 errors;
86 u64 packets;
87 u64 bytes;
88 u64 lro_packets;
89 u64 jumbo_packets;
90};
91
92struct aq_ring_stats_tx_s {
93 u64 errors;
94 u64 packets;
95 u64 bytes;
96};
97
98union aq_ring_stats_s {
99 struct aq_ring_stats_rx_s rx;
100 struct aq_ring_stats_tx_s tx;
101};
102
103struct aq_ring_s {
104 struct aq_obj_s header;
105 struct aq_ring_buff_s *buff_ring;
106 u8 *dx_ring; /* descriptors ring, dma shared mem */
107 struct aq_nic_s *aq_nic;
108 unsigned int idx; /* for HW layer registers operations */
109 unsigned int hw_head;
110 unsigned int sw_head;
111 unsigned int sw_tail;
112 unsigned int size; /* descriptors number */
113 unsigned int dx_size; /* TX or RX descriptor size, */
114 /* stored here for fater math */
115 union aq_ring_stats_s stats;
116 dma_addr_t dx_ring_pa;
117};
118
119struct aq_ring_param_s {
120 unsigned int vec_idx;
121 unsigned int cpu;
122 cpumask_t affinity_mask;
123};
124
125static inline unsigned int aq_ring_next_dx(struct aq_ring_s *self,
126 unsigned int dx)
127{
128 return (++dx >= self->size) ? 0U : dx;
129}
130
131static inline unsigned int aq_ring_avail_dx(struct aq_ring_s *self)
132{
133 return (((self->sw_tail >= self->sw_head)) ?
134 (self->size - 1) - self->sw_tail + self->sw_head :
135 self->sw_head - self->sw_tail - 1);
136}
137
138struct aq_ring_s *aq_ring_tx_alloc(struct aq_ring_s *self,
139 struct aq_nic_s *aq_nic,
140 unsigned int idx,
141 struct aq_nic_cfg_s *aq_nic_cfg);
142struct aq_ring_s *aq_ring_rx_alloc(struct aq_ring_s *self,
143 struct aq_nic_s *aq_nic,
144 unsigned int idx,
145 struct aq_nic_cfg_s *aq_nic_cfg);
146int aq_ring_init(struct aq_ring_s *self);
147void aq_ring_tx_deinit(struct aq_ring_s *self);
148void aq_ring_rx_deinit(struct aq_ring_s *self);
149void aq_ring_free(struct aq_ring_s *self);
150void aq_ring_tx_append_buffs(struct aq_ring_s *ring,
151 struct aq_ring_buff_s *buffer,
152 unsigned int buffers);
153int aq_ring_tx_clean(struct aq_ring_s *self);
154int aq_ring_rx_clean(struct aq_ring_s *self, int *work_done, int budget);
155int aq_ring_rx_fill(struct aq_ring_s *self);
156
157#endif /* AQ_RING_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_rss.h b/drivers/net/ethernet/aquantia/atlantic/aq_rss.h
new file mode 100644
index 000000000000..1db6eb20a8f2
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_rss.h
@@ -0,0 +1,26 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_rss.h: Receive Side Scaling definitions. */
11
12#ifndef AQ_RSS_H
13#define AQ_RSS_H
14
15#include "aq_common.h"
16#include "aq_cfg.h"
17
18struct aq_rss_parameters {
19 u16 base_cpu_number;
20 u16 indirection_table_size;
21 u16 hash_secret_key_size;
22 u32 hash_secret_key[AQ_CFG_RSS_HASHKEY_SIZE / sizeof(u32)];
23 u8 indirection_table[AQ_CFG_RSS_INDIRECTION_TABLE_MAX];
24};
25
26#endif /* AQ_RSS_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_utils.h b/drivers/net/ethernet/aquantia/atlantic/aq_utils.h
new file mode 100644
index 000000000000..4446bd90fd86
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_utils.h
@@ -0,0 +1,50 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_utils.h: Useful macro and structures used in all layers of driver. */
11
12#ifndef AQ_UTILS_H
13#define AQ_UTILS_H
14
15#include "aq_common.h"
16
17#define AQ_DIMOF(_ARY_) ARRAY_SIZE(_ARY_)
18
19struct aq_obj_s {
20 spinlock_t lock; /* spinlock for nic/rings processing */
21 atomic_t flags;
22 atomic_t busy_count;
23};
24
25static inline void aq_utils_obj_set(atomic_t *flags, u32 mask)
26{
27 unsigned long flags_old, flags_new;
28
29 do {
30 flags_old = atomic_read(flags);
31 flags_new = flags_old | (mask);
32 } while (atomic_cmpxchg(flags, flags_old, flags_new) != flags_old);
33}
34
35static inline void aq_utils_obj_clear(atomic_t *flags, u32 mask)
36{
37 unsigned long flags_old, flags_new;
38
39 do {
40 flags_old = atomic_read(flags);
41 flags_new = flags_old & ~(mask);
42 } while (atomic_cmpxchg(flags, flags_old, flags_new) != flags_old);
43}
44
45static inline bool aq_utils_obj_test(atomic_t *flags, u32 mask)
46{
47 return atomic_read(flags) & mask;
48}
49
50#endif /* AQ_UTILS_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_vec.c b/drivers/net/ethernet/aquantia/atlantic/aq_vec.c
new file mode 100644
index 000000000000..140962f23e61
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_vec.c
@@ -0,0 +1,392 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_vec.c: Definition of common structure for vector of Rx and Tx rings.
11 * Definition of functions for Rx and Tx rings. Friendly module for aq_nic.
12 */
13
14#include "aq_vec.h"
15#include "aq_nic.h"
16#include "aq_ring.h"
17#include "aq_hw.h"
18
19#include <linux/netdevice.h>
20
21struct aq_vec_s {
22 struct aq_obj_s header;
23 struct aq_hw_ops *aq_hw_ops;
24 struct aq_hw_s *aq_hw;
25 struct aq_nic_s *aq_nic;
26 unsigned int tx_rings;
27 unsigned int rx_rings;
28 struct aq_ring_param_s aq_ring_param;
29 struct napi_struct napi;
30 struct aq_ring_s ring[AQ_CFG_TCS_MAX][2];
31};
32
33#define AQ_VEC_TX_ID 0
34#define AQ_VEC_RX_ID 1
35
36static int aq_vec_poll(struct napi_struct *napi, int budget)
37__releases(&self->lock)
38__acquires(&self->lock)
39{
40 struct aq_vec_s *self = container_of(napi, struct aq_vec_s, napi);
41 struct aq_ring_s *ring = NULL;
42 int work_done = 0;
43 int err = 0;
44 unsigned int i = 0U;
45 unsigned int sw_tail_old = 0U;
46 bool was_tx_cleaned = false;
47
48 if (!self) {
49 err = -EINVAL;
50 } else if (spin_trylock(&self->header.lock)) {
51 for (i = 0U, ring = self->ring[0];
52 self->tx_rings > i; ++i, ring = self->ring[i]) {
53 if (self->aq_hw_ops->hw_ring_tx_head_update) {
54 err = self->aq_hw_ops->hw_ring_tx_head_update(
55 self->aq_hw,
56 &ring[AQ_VEC_TX_ID]);
57 if (err < 0)
58 goto err_exit;
59 }
60
61 if (ring[AQ_VEC_TX_ID].sw_head !=
62 ring[AQ_VEC_TX_ID].hw_head) {
63 err = aq_ring_tx_clean(&ring[AQ_VEC_TX_ID]);
64 if (err < 0)
65 goto err_exit;
66 was_tx_cleaned = true;
67 }
68
69 err = self->aq_hw_ops->hw_ring_rx_receive(self->aq_hw,
70 &ring[AQ_VEC_RX_ID]);
71 if (err < 0)
72 goto err_exit;
73
74 if (ring[AQ_VEC_RX_ID].sw_head !=
75 ring[AQ_VEC_RX_ID].hw_head) {
76 err = aq_ring_rx_clean(&ring[AQ_VEC_RX_ID],
77 &work_done,
78 budget - work_done);
79 if (err < 0)
80 goto err_exit;
81
82 sw_tail_old = ring[AQ_VEC_RX_ID].sw_tail;
83
84 err = aq_ring_rx_fill(&ring[AQ_VEC_RX_ID]);
85 if (err < 0)
86 goto err_exit;
87
88 err = self->aq_hw_ops->hw_ring_rx_fill(
89 self->aq_hw,
90 &ring[AQ_VEC_RX_ID], sw_tail_old);
91 if (err < 0)
92 goto err_exit;
93 }
94 }
95
96 if (was_tx_cleaned)
97 work_done = budget;
98
99 if (work_done < budget) {
100 napi_complete(napi);
101 self->aq_hw_ops->hw_irq_enable(self->aq_hw,
102 1U << self->aq_ring_param.vec_idx);
103 }
104
105err_exit:
106 spin_unlock(&self->header.lock);
107 }
108
109 return work_done;
110}
111
112struct aq_vec_s *aq_vec_alloc(struct aq_nic_s *aq_nic, unsigned int idx,
113 struct aq_nic_cfg_s *aq_nic_cfg)
114{
115 struct aq_vec_s *self = NULL;
116 struct aq_ring_s *ring = NULL;
117 unsigned int i = 0U;
118 int err = 0;
119
120 self = kzalloc(sizeof(*self), GFP_KERNEL);
121 if (!self) {
122 err = -ENOMEM;
123 goto err_exit;
124 }
125
126 self->aq_nic = aq_nic;
127 self->aq_ring_param.vec_idx = idx;
128 self->aq_ring_param.cpu =
129 idx + aq_nic_cfg->aq_rss.base_cpu_number;
130
131 cpumask_set_cpu(self->aq_ring_param.cpu,
132 &self->aq_ring_param.affinity_mask);
133
134 self->tx_rings = 0;
135 self->rx_rings = 0;
136
137 netif_napi_add(aq_nic_get_ndev(aq_nic), &self->napi,
138 aq_vec_poll, AQ_CFG_NAPI_WEIGHT);
139
140 for (i = 0; i < aq_nic_cfg->tcs; ++i) {
141 unsigned int idx_ring = AQ_NIC_TCVEC2RING(self->nic,
142 self->tx_rings,
143 self->aq_ring_param.vec_idx);
144
145 ring = aq_ring_tx_alloc(&self->ring[i][AQ_VEC_TX_ID], aq_nic,
146 idx_ring, aq_nic_cfg);
147 if (!ring) {
148 err = -ENOMEM;
149 goto err_exit;
150 }
151
152 ++self->tx_rings;
153
154 aq_nic_set_tx_ring(aq_nic, idx_ring, ring);
155
156 ring = aq_ring_rx_alloc(&self->ring[i][AQ_VEC_RX_ID], aq_nic,
157 idx_ring, aq_nic_cfg);
158 if (!ring) {
159 err = -ENOMEM;
160 goto err_exit;
161 }
162
163 ++self->rx_rings;
164 }
165
166err_exit:
167 if (err < 0) {
168 aq_vec_free(self);
169 self = NULL;
170 }
171 return self;
172}
173
174int aq_vec_init(struct aq_vec_s *self, struct aq_hw_ops *aq_hw_ops,
175 struct aq_hw_s *aq_hw)
176{
177 struct aq_ring_s *ring = NULL;
178 unsigned int i = 0U;
179 int err = 0;
180
181 self->aq_hw_ops = aq_hw_ops;
182 self->aq_hw = aq_hw;
183
184 spin_lock_init(&self->header.lock);
185
186 for (i = 0U, ring = self->ring[0];
187 self->tx_rings > i; ++i, ring = self->ring[i]) {
188 err = aq_ring_init(&ring[AQ_VEC_TX_ID]);
189 if (err < 0)
190 goto err_exit;
191
192 err = self->aq_hw_ops->hw_ring_tx_init(self->aq_hw,
193 &ring[AQ_VEC_TX_ID],
194 &self->aq_ring_param);
195 if (err < 0)
196 goto err_exit;
197
198 err = aq_ring_init(&ring[AQ_VEC_RX_ID]);
199 if (err < 0)
200 goto err_exit;
201
202 err = self->aq_hw_ops->hw_ring_rx_init(self->aq_hw,
203 &ring[AQ_VEC_RX_ID],
204 &self->aq_ring_param);
205 if (err < 0)
206 goto err_exit;
207
208 err = aq_ring_rx_fill(&ring[AQ_VEC_RX_ID]);
209 if (err < 0)
210 goto err_exit;
211
212 err = self->aq_hw_ops->hw_ring_rx_fill(self->aq_hw,
213 &ring[AQ_VEC_RX_ID], 0U);
214 if (err < 0)
215 goto err_exit;
216 }
217
218err_exit:
219 return err;
220}
221
222int aq_vec_start(struct aq_vec_s *self)
223{
224 struct aq_ring_s *ring = NULL;
225 unsigned int i = 0U;
226 int err = 0;
227
228 for (i = 0U, ring = self->ring[0];
229 self->tx_rings > i; ++i, ring = self->ring[i]) {
230 err = self->aq_hw_ops->hw_ring_tx_start(self->aq_hw,
231 &ring[AQ_VEC_TX_ID]);
232 if (err < 0)
233 goto err_exit;
234
235 err = self->aq_hw_ops->hw_ring_rx_start(self->aq_hw,
236 &ring[AQ_VEC_RX_ID]);
237 if (err < 0)
238 goto err_exit;
239 }
240
241 napi_enable(&self->napi);
242
243err_exit:
244 return err;
245}
246
247void aq_vec_stop(struct aq_vec_s *self)
248{
249 struct aq_ring_s *ring = NULL;
250 unsigned int i = 0U;
251
252 for (i = 0U, ring = self->ring[0];
253 self->tx_rings > i; ++i, ring = self->ring[i]) {
254 self->aq_hw_ops->hw_ring_tx_stop(self->aq_hw,
255 &ring[AQ_VEC_TX_ID]);
256
257 self->aq_hw_ops->hw_ring_rx_stop(self->aq_hw,
258 &ring[AQ_VEC_RX_ID]);
259 }
260
261 napi_disable(&self->napi);
262}
263
264void aq_vec_deinit(struct aq_vec_s *self)
265{
266 struct aq_ring_s *ring = NULL;
267 unsigned int i = 0U;
268
269 if (!self)
270 goto err_exit;
271
272 for (i = 0U, ring = self->ring[0];
273 self->tx_rings > i; ++i, ring = self->ring[i]) {
274 aq_ring_tx_deinit(&ring[AQ_VEC_TX_ID]);
275 aq_ring_rx_deinit(&ring[AQ_VEC_RX_ID]);
276 }
277err_exit:;
278}
279
280void aq_vec_free(struct aq_vec_s *self)
281{
282 struct aq_ring_s *ring = NULL;
283 unsigned int i = 0U;
284
285 if (!self)
286 goto err_exit;
287
288 for (i = 0U, ring = self->ring[0];
289 self->tx_rings > i; ++i, ring = self->ring[i]) {
290 aq_ring_free(&ring[AQ_VEC_TX_ID]);
291 aq_ring_free(&ring[AQ_VEC_RX_ID]);
292 }
293
294 netif_napi_del(&self->napi);
295
296 kfree(self);
297
298err_exit:;
299}
300
301irqreturn_t aq_vec_isr(int irq, void *private)
302{
303 struct aq_vec_s *self = private;
304 int err = 0;
305
306 if (!self) {
307 err = -EINVAL;
308 goto err_exit;
309 }
310 napi_schedule(&self->napi);
311
312err_exit:
313 return err >= 0 ? IRQ_HANDLED : IRQ_NONE;
314}
315
316irqreturn_t aq_vec_isr_legacy(int irq, void *private)
317{
318 struct aq_vec_s *self = private;
319 u64 irq_mask = 0U;
320 irqreturn_t err = 0;
321
322 if (!self) {
323 err = -EINVAL;
324 goto err_exit;
325 }
326 err = self->aq_hw_ops->hw_irq_read(self->aq_hw, &irq_mask);
327 if (err < 0)
328 goto err_exit;
329
330 if (irq_mask) {
331 self->aq_hw_ops->hw_irq_disable(self->aq_hw,
332 1U << self->aq_ring_param.vec_idx);
333 napi_schedule(&self->napi);
334 } else {
335 self->aq_hw_ops->hw_irq_enable(self->aq_hw, 1U);
336 err = IRQ_NONE;
337 }
338
339err_exit:
340 return err >= 0 ? IRQ_HANDLED : IRQ_NONE;
341}
342
343cpumask_t *aq_vec_get_affinity_mask(struct aq_vec_s *self)
344{
345 return &self->aq_ring_param.affinity_mask;
346}
347
348void aq_vec_add_stats(struct aq_vec_s *self,
349 struct aq_ring_stats_rx_s *stats_rx,
350 struct aq_ring_stats_tx_s *stats_tx)
351{
352 struct aq_ring_s *ring = NULL;
353 unsigned int r = 0U;
354
355 for (r = 0U, ring = self->ring[0];
356 self->tx_rings > r; ++r, ring = self->ring[r]) {
357 struct aq_ring_stats_tx_s *tx = &ring[AQ_VEC_TX_ID].stats.tx;
358 struct aq_ring_stats_rx_s *rx = &ring[AQ_VEC_RX_ID].stats.rx;
359
360 stats_rx->packets += rx->packets;
361 stats_rx->bytes += rx->bytes;
362 stats_rx->errors += rx->errors;
363 stats_rx->jumbo_packets += rx->jumbo_packets;
364 stats_rx->lro_packets += rx->lro_packets;
365
366 stats_tx->packets += tx->packets;
367 stats_tx->bytes += tx->bytes;
368 stats_tx->errors += tx->errors;
369 }
370}
371
372int aq_vec_get_sw_stats(struct aq_vec_s *self, u64 *data, unsigned int *p_count)
373{
374 unsigned int count = 0U;
375 struct aq_ring_stats_rx_s stats_rx;
376 struct aq_ring_stats_tx_s stats_tx;
377
378 memset(&stats_rx, 0U, sizeof(struct aq_ring_stats_rx_s));
379 memset(&stats_tx, 0U, sizeof(struct aq_ring_stats_tx_s));
380 aq_vec_add_stats(self, &stats_rx, &stats_tx);
381
382 data[count] += stats_rx.packets;
383 data[++count] += stats_tx.packets;
384 data[++count] += stats_rx.jumbo_packets;
385 data[++count] += stats_rx.lro_packets;
386 data[++count] += stats_rx.errors;
387
388 if (p_count)
389 *p_count = ++count;
390
391 return 0;
392}
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_vec.h b/drivers/net/ethernet/aquantia/atlantic/aq_vec.h
new file mode 100644
index 000000000000..6c68b184236c
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_vec.h
@@ -0,0 +1,42 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File aq_vec.h: Definition of common structures for vector of Rx and Tx rings.
11 * Declaration of functions for Rx and Tx rings.
12 */
13
14#ifndef AQ_VEC_H
15#define AQ_VEC_H
16
17#include "aq_common.h"
18#include <linux/irqreturn.h>
19
20struct aq_hw_s;
21struct aq_hw_ops;
22struct aq_ring_stats_rx_s;
23struct aq_ring_stats_tx_s;
24
25irqreturn_t aq_vec_isr(int irq, void *private);
26irqreturn_t aq_vec_isr_legacy(int irq, void *private);
27struct aq_vec_s *aq_vec_alloc(struct aq_nic_s *aq_nic, unsigned int idx,
28 struct aq_nic_cfg_s *aq_nic_cfg);
29int aq_vec_init(struct aq_vec_s *self, struct aq_hw_ops *aq_hw_ops,
30 struct aq_hw_s *aq_hw);
31void aq_vec_deinit(struct aq_vec_s *self);
32void aq_vec_free(struct aq_vec_s *self);
33int aq_vec_start(struct aq_vec_s *self);
34void aq_vec_stop(struct aq_vec_s *self);
35cpumask_t *aq_vec_get_affinity_mask(struct aq_vec_s *self);
36int aq_vec_get_sw_stats(struct aq_vec_s *self, u64 *data,
37 unsigned int *p_count);
38void aq_vec_add_stats(struct aq_vec_s *self,
39 struct aq_ring_stats_rx_s *stats_rx,
40 struct aq_ring_stats_tx_s *stats_tx);
41
42#endif /* AQ_VEC_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c
new file mode 100644
index 000000000000..1f388054a6c7
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c
@@ -0,0 +1,905 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File hw_atl_a0.c: Definition of Atlantic hardware specific functions. */
11
12#include "../aq_hw.h"
13#include "../aq_hw_utils.h"
14#include "../aq_ring.h"
15#include "hw_atl_a0.h"
16#include "hw_atl_utils.h"
17#include "hw_atl_llh.h"
18#include "hw_atl_a0_internal.h"
19
20static int hw_atl_a0_get_hw_caps(struct aq_hw_s *self,
21 struct aq_hw_caps_s *aq_hw_caps)
22{
23 memcpy(aq_hw_caps, &hw_atl_a0_hw_caps_, sizeof(*aq_hw_caps));
24 return 0;
25}
26
27static struct aq_hw_s *hw_atl_a0_create(struct aq_pci_func_s *aq_pci_func,
28 unsigned int port,
29 struct aq_hw_ops *ops)
30{
31 struct hw_atl_s *self = NULL;
32
33 self = kzalloc(sizeof(*self), GFP_KERNEL);
34 if (!self)
35 goto err_exit;
36
37 self->base.aq_pci_func = aq_pci_func;
38
39 self->base.not_ff_addr = 0x10U;
40
41err_exit:
42 return (struct aq_hw_s *)self;
43}
44
45static void hw_atl_a0_destroy(struct aq_hw_s *self)
46{
47 kfree(self);
48}
49
50static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
51{
52 int err = 0;
53
54 glb_glb_reg_res_dis_set(self, 1U);
55 pci_pci_reg_res_dis_set(self, 0U);
56 rx_rx_reg_res_dis_set(self, 0U);
57 tx_tx_reg_res_dis_set(self, 0U);
58
59 HW_ATL_FLUSH();
60 glb_soft_res_set(self, 1);
61
62 /* check 10 times by 1ms */
63 AQ_HW_WAIT_FOR(glb_soft_res_get(self) == 0, 1000U, 10U);
64 if (err < 0)
65 goto err_exit;
66
67 itr_irq_reg_res_dis_set(self, 0U);
68 itr_res_irq_set(self, 1U);
69
70 /* check 10 times by 1ms */
71 AQ_HW_WAIT_FOR(itr_res_irq_get(self) == 0, 1000U, 10U);
72 if (err < 0)
73 goto err_exit;
74
75 hw_atl_utils_mpi_set(self, MPI_RESET, 0x0U);
76
77 err = aq_hw_err_from_flags(self);
78
79err_exit:
80 return err;
81}
82
83static int hw_atl_a0_hw_qos_set(struct aq_hw_s *self)
84{
85 u32 tc = 0U;
86 u32 buff_size = 0U;
87 unsigned int i_priority = 0U;
88 bool is_rx_flow_control = false;
89
90 /* TPS Descriptor rate init */
91 tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
92 tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
93
94 /* TPS VM init */
95 tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
96
97 /* TPS TC credits init */
98 tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
99 tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
100
101 tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
102 tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
103 tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
104 tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
105
106 /* Tx buf size */
107 buff_size = HW_ATL_A0_TXBUF_MAX;
108
109 tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
110 tpb_tx_buff_hi_threshold_per_tc_set(self,
111 (buff_size * (1024 / 32U) * 66U) /
112 100U, tc);
113 tpb_tx_buff_lo_threshold_per_tc_set(self,
114 (buff_size * (1024 / 32U) * 50U) /
115 100U, tc);
116
117 /* QoS Rx buf size per TC */
118 tc = 0;
119 is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
120 buff_size = HW_ATL_A0_RXBUF_MAX;
121
122 rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
123 rpb_rx_buff_hi_threshold_per_tc_set(self,
124 (buff_size *
125 (1024U / 32U) * 66U) /
126 100U, tc);
127 rpb_rx_buff_lo_threshold_per_tc_set(self,
128 (buff_size *
129 (1024U / 32U) * 50U) /
130 100U, tc);
131 rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
132
133 /* QoS 802.1p priority -> TC mapping */
134 for (i_priority = 8U; i_priority--;)
135 rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
136
137 return aq_hw_err_from_flags(self);
138}
139
140static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *self,
141 struct aq_rss_parameters *rss_params)
142{
143 struct aq_nic_cfg_s *cfg = NULL;
144 int err = 0;
145 unsigned int i = 0U;
146 unsigned int addr = 0U;
147
148 cfg = self->aq_nic_cfg;
149
150 for (i = 10, addr = 0U; i--; ++addr) {
151 u32 key_data = cfg->is_rss ?
152 __swab32(rss_params->hash_secret_key[i]) : 0U;
153 rpf_rss_key_wr_data_set(self, key_data);
154 rpf_rss_key_addr_set(self, addr);
155 rpf_rss_key_wr_en_set(self, 1U);
156 AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self) == 0, 1000U, 10U);
157 if (err < 0)
158 goto err_exit;
159 }
160
161 err = aq_hw_err_from_flags(self);
162
163err_exit:
164 return err;
165}
166
167static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self,
168 struct aq_rss_parameters *rss_params)
169{
170 u8 *indirection_table = rss_params->indirection_table;
171 u32 i = 0U;
172 u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
173 int err = 0;
174 u16 bitary[(HW_ATL_A0_RSS_REDIRECTION_MAX *
175 HW_ATL_A0_RSS_REDIRECTION_BITS / 16U)];
176
177 memset(bitary, 0, sizeof(bitary));
178
179 for (i = HW_ATL_A0_RSS_REDIRECTION_MAX; i--; ) {
180 (*(u32 *)(bitary + ((i * 3U) / 16U))) |=
181 ((indirection_table[i] % num_rss_queues) <<
182 ((i * 3U) & 0xFU));
183 }
184
185 for (i = AQ_DIMOF(bitary); i--;) {
186 rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
187 rpf_rss_redir_tbl_addr_set(self, i);
188 rpf_rss_redir_wr_en_set(self, 1U);
189 AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self) == 0, 1000U, 10U);
190 if (err < 0)
191 goto err_exit;
192 }
193
194 err = aq_hw_err_from_flags(self);
195
196err_exit:
197 return err;
198}
199
200static int hw_atl_a0_hw_offload_set(struct aq_hw_s *self,
201 struct aq_nic_cfg_s *aq_nic_cfg)
202{
203 int err = 0;
204
205 /* TX checksums offloads*/
206 tpo_ipv4header_crc_offload_en_set(self, 1);
207 tpo_tcp_udp_crc_offload_en_set(self, 1);
208 if (err < 0)
209 goto err_exit;
210
211 /* RX checksums offloads*/
212 rpo_ipv4header_crc_offload_en_set(self, 1);
213 rpo_tcp_udp_crc_offload_en_set(self, 1);
214 if (err < 0)
215 goto err_exit;
216
217 /* LSO offloads*/
218 tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
219 if (err < 0)
220 goto err_exit;
221
222 err = aq_hw_err_from_flags(self);
223
224err_exit:
225 return err;
226}
227
228static int hw_atl_a0_hw_init_tx_path(struct aq_hw_s *self)
229{
230 thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
231 thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
232 thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
233
234 /* Tx interrupts */
235 tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
236
237 /* misc */
238 aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
239 0x00010000U : 0x00000000U);
240 tdm_tx_dca_en_set(self, 0U);
241 tdm_tx_dca_mode_set(self, 0U);
242
243 tpb_tx_path_scp_ins_en_set(self, 1U);
244
245 return aq_hw_err_from_flags(self);
246}
247
248static int hw_atl_a0_hw_init_rx_path(struct aq_hw_s *self)
249{
250 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
251 int i;
252
253 /* Rx TC/RSS number config */
254 rpb_rpf_rx_traf_class_mode_set(self, 1U);
255
256 /* Rx flow control */
257 rpb_rx_flow_ctl_mode_set(self, 1U);
258
259 /* RSS Ring selection */
260 reg_rx_flr_rss_control1set(self, cfg->is_rss ?
261 0xB3333333U : 0x00000000U);
262
263 /* Multicast filters */
264 for (i = HW_ATL_A0_MAC_MAX; i--;) {
265 rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
266 rpfl2unicast_flr_act_set(self, 1U, i);
267 }
268
269 reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
270 reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
271
272 /* Vlan filters */
273 rpf_vlan_outer_etht_set(self, 0x88A8U);
274 rpf_vlan_inner_etht_set(self, 0x8100U);
275 rpf_vlan_prom_mode_en_set(self, 1);
276
277 /* Rx Interrupts */
278 rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
279
280 /* misc */
281 rpfl2broadcast_flr_act_set(self, 1U);
282 rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
283
284 rdm_rx_dca_en_set(self, 0U);
285 rdm_rx_dca_mode_set(self, 0U);
286
287 return aq_hw_err_from_flags(self);
288}
289
290static int hw_atl_a0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
291{
292 int err = 0;
293 unsigned int h = 0U;
294 unsigned int l = 0U;
295
296 if (!mac_addr) {
297 err = -EINVAL;
298 goto err_exit;
299 }
300 h = (mac_addr[0] << 8) | (mac_addr[1]);
301 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
302 (mac_addr[4] << 8) | mac_addr[5];
303
304 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC);
305 rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_A0_MAC);
306 rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_A0_MAC);
307 rpfl2_uc_flr_en_set(self, 1U, HW_ATL_A0_MAC);
308
309 err = aq_hw_err_from_flags(self);
310
311err_exit:
312 return err;
313}
314
315static int hw_atl_a0_hw_init(struct aq_hw_s *self,
316 struct aq_nic_cfg_s *aq_nic_cfg,
317 u8 *mac_addr)
318{
319 static u32 aq_hw_atl_igcr_table_[4][2] = {
320 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
321 { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */
322 { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */
323 { 0x20000022U, 0x20000026U } /* AQ_IRQ_MSIX */
324 };
325
326 int err = 0;
327
328 self->aq_nic_cfg = aq_nic_cfg;
329
330 hw_atl_utils_hw_chip_features_init(self,
331 &PHAL_ATLANTIC_A0->chip_features);
332
333 hw_atl_a0_hw_init_tx_path(self);
334 hw_atl_a0_hw_init_rx_path(self);
335
336 hw_atl_a0_hw_mac_addr_set(self, mac_addr);
337
338 hw_atl_utils_mpi_set(self, MPI_INIT, aq_nic_cfg->link_speed_msk);
339
340 reg_tx_dma_debug_ctl_set(self, 0x800000b8U);
341 reg_tx_dma_debug_ctl_set(self, 0x000000b8U);
342
343 hw_atl_a0_hw_qos_set(self);
344 hw_atl_a0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
345 hw_atl_a0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
346
347 err = aq_hw_err_from_flags(self);
348 if (err < 0)
349 goto err_exit;
350
351 /* Interrupts */
352 reg_irq_glb_ctl_set(self,
353 aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
354 [(aq_nic_cfg->vecs > 1U) ?
355 1 : 0]);
356
357 itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
358
359 /* Interrupts */
360 reg_gen_irq_map_set(self,
361 ((HW_ATL_A0_ERR_INT << 0x18) | (1U << 0x1F)) |
362 ((HW_ATL_A0_ERR_INT << 0x10) | (1U << 0x17)) |
363 ((HW_ATL_A0_ERR_INT << 8) | (1U << 0xF)) |
364 ((HW_ATL_A0_ERR_INT) | (1U << 0x7)), 0U);
365
366 hw_atl_a0_hw_offload_set(self, aq_nic_cfg);
367
368err_exit:
369 return err;
370}
371
372static int hw_atl_a0_hw_ring_tx_start(struct aq_hw_s *self,
373 struct aq_ring_s *ring)
374{
375 tdm_tx_desc_en_set(self, 1, ring->idx);
376 return aq_hw_err_from_flags(self);
377}
378
379static int hw_atl_a0_hw_ring_rx_start(struct aq_hw_s *self,
380 struct aq_ring_s *ring)
381{
382 rdm_rx_desc_en_set(self, 1, ring->idx);
383 return aq_hw_err_from_flags(self);
384}
385
386static int hw_atl_a0_hw_start(struct aq_hw_s *self)
387{
388 tpb_tx_buff_en_set(self, 1);
389 rpb_rx_buff_en_set(self, 1);
390 return aq_hw_err_from_flags(self);
391}
392
393static int hw_atl_a0_hw_tx_ring_tail_update(struct aq_hw_s *self,
394 struct aq_ring_s *ring)
395{
396 reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
397 return 0;
398}
399
400static int hw_atl_a0_hw_ring_tx_xmit(struct aq_hw_s *self,
401 struct aq_ring_s *ring,
402 unsigned int frags)
403{
404 struct aq_ring_buff_s *buff = NULL;
405 struct hw_atl_txd_s *txd = NULL;
406 unsigned int buff_pa_len = 0U;
407 unsigned int pkt_len = 0U;
408 unsigned int frag_count = 0U;
409 bool is_gso = false;
410
411 buff = &ring->buff_ring[ring->sw_tail];
412 pkt_len = (buff->is_eop && buff->is_sop) ? buff->len : buff->len_pkt;
413
414 for (frag_count = 0; frag_count < frags; frag_count++) {
415 txd = (struct hw_atl_txd_s *)&ring->dx_ring[ring->sw_tail *
416 HW_ATL_A0_TXD_SIZE];
417 txd->ctl = 0;
418 txd->ctl2 = 0;
419 txd->buf_addr = 0;
420
421 buff = &ring->buff_ring[ring->sw_tail];
422
423 if (buff->is_txc) {
424 txd->ctl |= (buff->len_l3 << 31) |
425 (buff->len_l2 << 24) |
426 HW_ATL_A0_TXD_CTL_CMD_TCP |
427 HW_ATL_A0_TXD_CTL_DESC_TYPE_TXC;
428 txd->ctl2 |= (buff->mss << 16) |
429 (buff->len_l4 << 8) |
430 (buff->len_l3 >> 1);
431
432 pkt_len -= (buff->len_l4 +
433 buff->len_l3 +
434 buff->len_l2);
435 is_gso = true;
436 } else {
437 buff_pa_len = buff->len;
438
439 txd->buf_addr = buff->pa;
440 txd->ctl |= (HW_ATL_A0_TXD_CTL_BLEN &
441 ((u32)buff_pa_len << 4));
442 txd->ctl |= HW_ATL_A0_TXD_CTL_DESC_TYPE_TXD;
443 /* PAY_LEN */
444 txd->ctl2 |= HW_ATL_A0_TXD_CTL2_LEN & (pkt_len << 14);
445
446 if (is_gso) {
447 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_LSO;
448 txd->ctl2 |= HW_ATL_A0_TXD_CTL2_CTX_EN;
449 }
450
451 /* Tx checksum offloads */
452 if (buff->is_ip_cso)
453 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_IPCSO;
454
455 if (buff->is_udp_cso || buff->is_tcp_cso)
456 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_TUCSO;
457
458 if (unlikely(buff->is_eop)) {
459 txd->ctl |= HW_ATL_A0_TXD_CTL_EOP;
460 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_WB;
461 }
462 }
463
464 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail);
465 }
466
467 hw_atl_a0_hw_tx_ring_tail_update(self, ring);
468 return aq_hw_err_from_flags(self);
469}
470
471static int hw_atl_a0_hw_ring_rx_init(struct aq_hw_s *self,
472 struct aq_ring_s *aq_ring,
473 struct aq_ring_param_s *aq_ring_param)
474{
475 u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
476 u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
477
478 rdm_rx_desc_en_set(self, false, aq_ring->idx);
479
480 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
481
482 reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
483 aq_ring->idx);
484
485 reg_rx_dma_desc_base_addressmswset(self,
486 dma_desc_addr_msw, aq_ring->idx);
487
488 rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
489
490 rdm_rx_desc_data_buff_size_set(self,
491 AQ_CFG_RX_FRAME_MAX / 1024U,
492 aq_ring->idx);
493
494 rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
495 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
496 rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
497
498 /* Rx ring set mode */
499
500 /* Mapping interrupt vector */
501 itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
502 itr_irq_map_en_rx_set(self, true, aq_ring->idx);
503
504 rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
505 rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
506 rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
507 rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
508
509 return aq_hw_err_from_flags(self);
510}
511
512static int hw_atl_a0_hw_ring_tx_init(struct aq_hw_s *self,
513 struct aq_ring_s *aq_ring,
514 struct aq_ring_param_s *aq_ring_param)
515{
516 u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
517 u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
518
519 reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
520 aq_ring->idx);
521
522 reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
523 aq_ring->idx);
524
525 tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
526
527 hw_atl_a0_hw_tx_ring_tail_update(self, aq_ring);
528
529 /* Set Tx threshold */
530 tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
531
532 /* Mapping interrupt vector */
533 itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
534 itr_irq_map_en_tx_set(self, true, aq_ring->idx);
535
536 tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
537 tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
538
539 return aq_hw_err_from_flags(self);
540}
541
542static int hw_atl_a0_hw_ring_rx_fill(struct aq_hw_s *self,
543 struct aq_ring_s *ring,
544 unsigned int sw_tail_old)
545{
546 for (; sw_tail_old != ring->sw_tail;
547 sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) {
548 struct hw_atl_rxd_s *rxd =
549 (struct hw_atl_rxd_s *)&ring->dx_ring[sw_tail_old *
550 HW_ATL_A0_RXD_SIZE];
551
552 struct aq_ring_buff_s *buff = &ring->buff_ring[sw_tail_old];
553
554 rxd->buf_addr = buff->pa;
555 rxd->hdr_addr = 0U;
556 }
557
558 reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
559
560 return aq_hw_err_from_flags(self);
561}
562
563static int hw_atl_a0_hw_ring_tx_head_update(struct aq_hw_s *self,
564 struct aq_ring_s *ring)
565{
566 int err = 0;
567 unsigned int hw_head_ = tdm_tx_desc_head_ptr_get(self, ring->idx);
568
569 if (aq_utils_obj_test(&self->header.flags, AQ_HW_FLAG_ERR_UNPLUG)) {
570 err = -ENXIO;
571 goto err_exit;
572 }
573 ring->hw_head = hw_head_;
574 err = aq_hw_err_from_flags(self);
575
576err_exit:
577 return err;
578}
579
580static int hw_atl_a0_hw_ring_rx_receive(struct aq_hw_s *self,
581 struct aq_ring_s *ring)
582{
583 struct device *ndev = aq_nic_get_dev(ring->aq_nic);
584
585 for (; ring->hw_head != ring->sw_tail;
586 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
587 struct aq_ring_buff_s *buff = NULL;
588 struct hw_atl_rxd_wb_s *rxd_wb = (struct hw_atl_rxd_wb_s *)
589 &ring->dx_ring[ring->hw_head * HW_ATL_A0_RXD_SIZE];
590
591 unsigned int is_err = 1U;
592 unsigned int is_rx_check_sum_enabled = 0U;
593 unsigned int pkt_type = 0U;
594
595 if (!(rxd_wb->status & 0x5U)) { /* RxD is not done */
596 if ((1U << 4) &
597 reg_rx_dma_desc_status_get(self, ring->idx)) {
598 rdm_rx_desc_en_set(self, false, ring->idx);
599 rdm_rx_desc_res_set(self, true, ring->idx);
600 rdm_rx_desc_res_set(self, false, ring->idx);
601 rdm_rx_desc_en_set(self, true, ring->idx);
602 }
603
604 if (ring->hw_head ||
605 (rdm_rx_desc_head_ptr_get(self, ring->idx) < 2U)) {
606 break;
607 } else if (!(rxd_wb->status & 0x1U)) {
608 struct hw_atl_rxd_wb_s *rxd_wb1 =
609 (struct hw_atl_rxd_wb_s *)
610 (&ring->dx_ring[(1U) *
611 HW_ATL_A0_RXD_SIZE]);
612
613 if ((rxd_wb1->status & 0x1U)) {
614 rxd_wb->pkt_len = 1514U;
615 rxd_wb->status = 3U;
616 } else {
617 break;
618 }
619 }
620 }
621
622 buff = &ring->buff_ring[ring->hw_head];
623
624 if (0x3U != (rxd_wb->status & 0x3U))
625 rxd_wb->status |= 4;
626
627 is_err = (0x0000001CU & rxd_wb->status);
628 is_rx_check_sum_enabled = (rxd_wb->type) & (0x3U << 19);
629 pkt_type = 0xFFU & (rxd_wb->type >> 4);
630
631 if (is_rx_check_sum_enabled) {
632 if (0x0U == (pkt_type & 0x3U))
633 buff->is_ip_cso = (is_err & 0x08U) ? 0 : 1;
634
635 if (0x4U == (pkt_type & 0x1CU))
636 buff->is_udp_cso = (is_err & 0x10U) ? 0 : 1;
637 else if (0x0U == (pkt_type & 0x1CU))
638 buff->is_tcp_cso = (is_err & 0x10U) ? 0 : 1;
639 }
640
641 is_err &= ~0x18U;
642 is_err &= ~0x04U;
643
644 dma_unmap_page(ndev, buff->pa, buff->len, DMA_FROM_DEVICE);
645
646 if (is_err || rxd_wb->type & 0x1000U) {
647 /* status error or DMA error */
648 buff->is_error = 1U;
649 } else {
650 if (self->aq_nic_cfg->is_rss) {
651 /* last 4 byte */
652 u16 rss_type = rxd_wb->type & 0xFU;
653
654 if (rss_type && rss_type < 0x8U) {
655 buff->is_hash_l4 = (rss_type == 0x4 ||
656 rss_type == 0x5);
657 buff->rss_hash = rxd_wb->rss_hash;
658 }
659 }
660
661 if (HW_ATL_A0_RXD_WB_STAT2_EOP & rxd_wb->status) {
662 buff->len = (rxd_wb->pkt_len &
663 (AQ_CFG_RX_FRAME_MAX - 1U));
664 buff->len = buff->len ?
665 buff->len : AQ_CFG_RX_FRAME_MAX;
666 buff->next = 0U;
667 buff->is_eop = 1U;
668 } else {
669 /* jumbo */
670 buff->next = aq_ring_next_dx(ring,
671 ring->hw_head);
672 ++ring->stats.rx.jumbo_packets;
673 }
674 }
675 }
676
677 return aq_hw_err_from_flags(self);
678}
679
680static int hw_atl_a0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
681{
682 itr_irq_msk_setlsw_set(self, LODWORD(mask) |
683 (1U << HW_ATL_A0_ERR_INT));
684 return aq_hw_err_from_flags(self);
685}
686
687static int hw_atl_a0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
688{
689 itr_irq_msk_clearlsw_set(self, LODWORD(mask));
690 itr_irq_status_clearlsw_set(self, LODWORD(mask));
691
692 if ((1U << 16) & reg_gen_irq_status_get(self))
693
694 atomic_inc(&PHAL_ATLANTIC_A0->dpc);
695
696 return aq_hw_err_from_flags(self);
697}
698
699static int hw_atl_a0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
700{
701 *mask = itr_irq_statuslsw_get(self);
702 return aq_hw_err_from_flags(self);
703}
704
705#define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
706
707static int hw_atl_a0_hw_packet_filter_set(struct aq_hw_s *self,
708 unsigned int packet_filter)
709{
710 unsigned int i = 0U;
711
712 rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
713 rpfl2multicast_flr_en_set(self, IS_FILTER_ENABLED(IFF_MULTICAST), 0);
714 rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
715
716 self->aq_nic_cfg->is_mc_list_enabled =
717 IS_FILTER_ENABLED(IFF_MULTICAST);
718
719 for (i = HW_ATL_A0_MAC_MIN; i < HW_ATL_A0_MAC_MAX; ++i)
720 rpfl2_uc_flr_en_set(self,
721 (self->aq_nic_cfg->is_mc_list_enabled &&
722 (i <= self->aq_nic_cfg->mc_list_count)) ?
723 1U : 0U, i);
724
725 return aq_hw_err_from_flags(self);
726}
727
728#undef IS_FILTER_ENABLED
729
730static int hw_atl_a0_hw_multicast_list_set(struct aq_hw_s *self,
731 u8 ar_mac
732 [AQ_CFG_MULTICAST_ADDRESS_MAX]
733 [ETH_ALEN],
734 u32 count)
735{
736 int err = 0;
737
738 if (count > (HW_ATL_A0_MAC_MAX - HW_ATL_A0_MAC_MIN)) {
739 err = EBADRQC;
740 goto err_exit;
741 }
742 for (self->aq_nic_cfg->mc_list_count = 0U;
743 self->aq_nic_cfg->mc_list_count < count;
744 ++self->aq_nic_cfg->mc_list_count) {
745 u32 i = self->aq_nic_cfg->mc_list_count;
746 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
747 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
748 (ar_mac[i][4] << 8) | ar_mac[i][5];
749
750 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC_MIN + i);
751
752 rpfl2unicast_dest_addresslsw_set(self,
753 l, HW_ATL_A0_MAC_MIN + i);
754
755 rpfl2unicast_dest_addressmsw_set(self,
756 h, HW_ATL_A0_MAC_MIN + i);
757
758 rpfl2_uc_flr_en_set(self,
759 (self->aq_nic_cfg->is_mc_list_enabled),
760 HW_ATL_A0_MAC_MIN + i);
761 }
762
763 err = aq_hw_err_from_flags(self);
764
765err_exit:
766 return err;
767}
768
769static int hw_atl_a0_hw_interrupt_moderation_set(struct aq_hw_s *self,
770 bool itr_enabled)
771{
772 unsigned int i = 0U;
773
774 if (itr_enabled && self->aq_nic_cfg->itr) {
775 if (self->aq_nic_cfg->itr != 0xFFFFU) {
776 u32 itr_ = (self->aq_nic_cfg->itr >> 1);
777
778 itr_ = min(AQ_CFG_IRQ_MASK, itr_);
779
780 PHAL_ATLANTIC_A0->itr_rx = 0x80000000U |
781 (itr_ << 0x10);
782 } else {
783 u32 n = 0xFFFFU & aq_hw_read_reg(self, 0x00002A00U);
784
785 if (n < self->aq_link_status.mbps) {
786 PHAL_ATLANTIC_A0->itr_rx = 0U;
787 } else {
788 static unsigned int hw_timers_tbl_[] = {
789 0x01CU, /* 10Gbit */
790 0x039U, /* 5Gbit */
791 0x039U, /* 5Gbit 5GS */
792 0x073U, /* 2.5Gbit */
793 0x120U, /* 1Gbit */
794 0x1FFU, /* 100Mbit */
795 };
796
797 unsigned int speed_index =
798 hw_atl_utils_mbps_2_speed_index(
799 self->aq_link_status.mbps);
800
801 PHAL_ATLANTIC_A0->itr_rx =
802 0x80000000U |
803 (hw_timers_tbl_[speed_index] << 0x10U);
804 }
805
806 aq_hw_write_reg(self, 0x00002A00U, 0x40000000U);
807 aq_hw_write_reg(self, 0x00002A00U, 0x8D000000U);
808 }
809 } else {
810 PHAL_ATLANTIC_A0->itr_rx = 0U;
811 }
812
813 for (i = HW_ATL_A0_RINGS_MAX; i--;)
814 reg_irq_thr_set(self, PHAL_ATLANTIC_A0->itr_rx, i);
815
816 return aq_hw_err_from_flags(self);
817}
818
819static int hw_atl_a0_hw_stop(struct aq_hw_s *self)
820{
821 hw_atl_a0_hw_irq_disable(self, HW_ATL_A0_INT_MASK);
822 return aq_hw_err_from_flags(self);
823}
824
825static int hw_atl_a0_hw_ring_tx_stop(struct aq_hw_s *self,
826 struct aq_ring_s *ring)
827{
828 tdm_tx_desc_en_set(self, 0U, ring->idx);
829 return aq_hw_err_from_flags(self);
830}
831
832static int hw_atl_a0_hw_ring_rx_stop(struct aq_hw_s *self,
833 struct aq_ring_s *ring)
834{
835 rdm_rx_desc_en_set(self, 0U, ring->idx);
836 return aq_hw_err_from_flags(self);
837}
838
839static int hw_atl_a0_hw_set_speed(struct aq_hw_s *self, u32 speed)
840{
841 int err = 0;
842
843 err = hw_atl_utils_mpi_set_speed(self, speed, MPI_INIT);
844 if (err < 0)
845 goto err_exit;
846
847err_exit:
848 return err;
849}
850
851static struct aq_hw_ops hw_atl_ops_ = {
852 .create = hw_atl_a0_create,
853 .destroy = hw_atl_a0_destroy,
854 .get_hw_caps = hw_atl_a0_get_hw_caps,
855
856 .hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
857 .hw_set_mac_address = hw_atl_a0_hw_mac_addr_set,
858 .hw_get_link_status = hw_atl_utils_mpi_get_link_status,
859 .hw_set_link_speed = hw_atl_a0_hw_set_speed,
860 .hw_init = hw_atl_a0_hw_init,
861 .hw_deinit = hw_atl_utils_hw_deinit,
862 .hw_set_power = hw_atl_utils_hw_set_power,
863 .hw_reset = hw_atl_a0_hw_reset,
864 .hw_start = hw_atl_a0_hw_start,
865 .hw_ring_tx_start = hw_atl_a0_hw_ring_tx_start,
866 .hw_ring_tx_stop = hw_atl_a0_hw_ring_tx_stop,
867 .hw_ring_rx_start = hw_atl_a0_hw_ring_rx_start,
868 .hw_ring_rx_stop = hw_atl_a0_hw_ring_rx_stop,
869 .hw_stop = hw_atl_a0_hw_stop,
870
871 .hw_ring_tx_xmit = hw_atl_a0_hw_ring_tx_xmit,
872 .hw_ring_tx_head_update = hw_atl_a0_hw_ring_tx_head_update,
873
874 .hw_ring_rx_receive = hw_atl_a0_hw_ring_rx_receive,
875 .hw_ring_rx_fill = hw_atl_a0_hw_ring_rx_fill,
876
877 .hw_irq_enable = hw_atl_a0_hw_irq_enable,
878 .hw_irq_disable = hw_atl_a0_hw_irq_disable,
879 .hw_irq_read = hw_atl_a0_hw_irq_read,
880
881 .hw_ring_rx_init = hw_atl_a0_hw_ring_rx_init,
882 .hw_ring_tx_init = hw_atl_a0_hw_ring_tx_init,
883 .hw_packet_filter_set = hw_atl_a0_hw_packet_filter_set,
884 .hw_multicast_list_set = hw_atl_a0_hw_multicast_list_set,
885 .hw_interrupt_moderation_set = hw_atl_a0_hw_interrupt_moderation_set,
886 .hw_rss_set = hw_atl_a0_hw_rss_set,
887 .hw_rss_hash_set = hw_atl_a0_hw_rss_hash_set,
888 .hw_get_regs = hw_atl_utils_hw_get_regs,
889 .hw_get_hw_stats = hw_atl_utils_get_hw_stats,
890 .hw_get_fw_version = hw_atl_utils_get_fw_version,
891};
892
893struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev)
894{
895 bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
896 bool is_did_ok = ((pdev->device == HW_ATL_DEVICE_ID_0001) ||
897 (pdev->device == HW_ATL_DEVICE_ID_D100) ||
898 (pdev->device == HW_ATL_DEVICE_ID_D107) ||
899 (pdev->device == HW_ATL_DEVICE_ID_D108) ||
900 (pdev->device == HW_ATL_DEVICE_ID_D109));
901
902 bool is_rev_ok = (pdev->revision == 1U);
903
904 return (is_vid_ok && is_did_ok && is_rev_ok) ? &hw_atl_ops_ : NULL;
905}
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.h
new file mode 100644
index 000000000000..6e1d527954c9
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.h
@@ -0,0 +1,34 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File hw_atl_a0.h: Declaration of abstract interface for Atlantic hardware
11 * specific functions.
12 */
13
14#ifndef HW_ATL_A0_H
15#define HW_ATL_A0_H
16
17#include "../aq_common.h"
18
19#ifndef PCI_VENDOR_ID_AQUANTIA
20
21#define PCI_VENDOR_ID_AQUANTIA 0x1D6A
22#define HW_ATL_DEVICE_ID_0001 0x0001
23#define HW_ATL_DEVICE_ID_D100 0xD100
24#define HW_ATL_DEVICE_ID_D107 0xD107
25#define HW_ATL_DEVICE_ID_D108 0xD108
26#define HW_ATL_DEVICE_ID_D109 0xD109
27
28#define HW_ATL_NIC_NAME "aQuantia AQtion 5Gbit Network Adapter"
29
30#endif
31
32struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev);
33
34#endif /* HW_ATL_A0_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h
new file mode 100644
index 000000000000..1093ea18823a
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h
@@ -0,0 +1,155 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File hw_atl_a0_internal.h: Definition of Atlantic A0 chip specific
11 * constants.
12 */
13
14#ifndef HW_ATL_A0_INTERNAL_H
15#define HW_ATL_A0_INTERNAL_H
16
17#include "../aq_common.h"
18
19#define HW_ATL_A0_MTU_JUMBO 9014U
20
21#define HW_ATL_A0_TX_RINGS 4U
22#define HW_ATL_A0_RX_RINGS 4U
23
24#define HW_ATL_A0_RINGS_MAX 32U
25#define HW_ATL_A0_TXD_SIZE 16U
26#define HW_ATL_A0_RXD_SIZE 16U
27
28#define HW_ATL_A0_MAC 0U
29#define HW_ATL_A0_MAC_MIN 1U
30#define HW_ATL_A0_MAC_MAX 33U
31
32/* interrupts */
33#define HW_ATL_A0_ERR_INT 8U
34#define HW_ATL_A0_INT_MASK 0xFFFFFFFFU
35
36#define HW_ATL_A0_TXD_CTL2_LEN 0xFFFFC000U
37#define HW_ATL_A0_TXD_CTL2_CTX_EN 0x00002000U
38#define HW_ATL_A0_TXD_CTL2_CTX_IDX 0x00001000U
39
40#define HW_ATL_A0_TXD_CTL_DESC_TYPE_TXD 0x00000001U
41#define HW_ATL_A0_TXD_CTL_DESC_TYPE_TXC 0x00000002U
42#define HW_ATL_A0_TXD_CTL_BLEN 0x000FFFF0U
43#define HW_ATL_A0_TXD_CTL_DD 0x00100000U
44#define HW_ATL_A0_TXD_CTL_EOP 0x00200000U
45
46#define HW_ATL_A0_TXD_CTL_CMD_X 0x3FC00000U
47
48#define HW_ATL_A0_TXD_CTL_CMD_VLAN BIT(22)
49#define HW_ATL_A0_TXD_CTL_CMD_FCS BIT(23)
50#define HW_ATL_A0_TXD_CTL_CMD_IPCSO BIT(24)
51#define HW_ATL_A0_TXD_CTL_CMD_TUCSO BIT(25)
52#define HW_ATL_A0_TXD_CTL_CMD_LSO BIT(26)
53#define HW_ATL_A0_TXD_CTL_CMD_WB BIT(27)
54#define HW_ATL_A0_TXD_CTL_CMD_VXLAN BIT(28)
55
56#define HW_ATL_A0_TXD_CTL_CMD_IPV6 BIT(21)
57#define HW_ATL_A0_TXD_CTL_CMD_TCP BIT(22)
58
59#define HW_ATL_A0_MPI_CONTROL_ADR 0x0368U
60#define HW_ATL_A0_MPI_STATE_ADR 0x036CU
61
62#define HW_ATL_A0_MPI_SPEED_MSK 0xFFFFU
63#define HW_ATL_A0_MPI_SPEED_SHIFT 16U
64
65#define HW_ATL_A0_RATE_10G BIT(0)
66#define HW_ATL_A0_RATE_5G BIT(1)
67#define HW_ATL_A0_RATE_2G5 BIT(3)
68#define HW_ATL_A0_RATE_1G BIT(4)
69#define HW_ATL_A0_RATE_100M BIT(5)
70
71#define HW_ATL_A0_TXBUF_MAX 160U
72#define HW_ATL_A0_RXBUF_MAX 320U
73
74#define HW_ATL_A0_RSS_REDIRECTION_MAX 64U
75#define HW_ATL_A0_RSS_REDIRECTION_BITS 3U
76
77#define HW_ATL_A0_TC_MAX 1U
78#define HW_ATL_A0_RSS_MAX 8U
79
80#define HW_ATL_A0_FW_SEMA_RAM 0x2U
81
82#define HW_ATL_A0_RXD_DD 0x1U
83#define HW_ATL_A0_RXD_NCEA0 0x1U
84
85#define HW_ATL_A0_RXD_WB_STAT2_EOP 0x0002U
86
87#define HW_ATL_A0_UCP_0X370_REG 0x370U
88
89#define HW_ATL_A0_FW_VER_EXPECTED 0x01050006U
90
91/* Hardware tx descriptor */
92struct __packed hw_atl_txd_s {
93 u64 buf_addr;
94 u32 ctl;
95 u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */
96};
97
98/* Hardware tx context descriptor */
99struct __packed hw_atl_txc_s {
100 u32 rsvd;
101 u32 len;
102 u32 ctl;
103 u32 len2;
104};
105
106/* Hardware rx descriptor */
107struct __packed hw_atl_rxd_s {
108 u64 buf_addr;
109 u64 hdr_addr;
110};
111
112/* Hardware rx descriptor writeback */
113struct __packed hw_atl_rxd_wb_s {
114 u32 type;
115 u32 rss_hash;
116 u16 status;
117 u16 pkt_len;
118 u16 next_desc_ptr;
119 u16 vlan;
120};
121
122/* HW layer capabilities */
123static struct aq_hw_caps_s hw_atl_a0_hw_caps_ = {
124 .ports = 1U,
125 .is_64_dma = true,
126 .msix_irqs = 4U,
127 .irq_mask = ~0U,
128 .vecs = HW_ATL_A0_RSS_MAX,
129 .tcs = HW_ATL_A0_TC_MAX,
130 .rxd_alignment = 1U,
131 .rxd_size = HW_ATL_A0_RXD_SIZE,
132 .rxds = 248U,
133 .txd_alignment = 1U,
134 .txd_size = HW_ATL_A0_TXD_SIZE,
135 .txds = 8U * 1024U,
136 .txhwb_alignment = 4096U,
137 .tx_rings = HW_ATL_A0_TX_RINGS,
138 .rx_rings = HW_ATL_A0_RX_RINGS,
139 .hw_features = NETIF_F_HW_CSUM |
140 NETIF_F_RXHASH |
141 NETIF_F_SG |
142 NETIF_F_TSO,
143 .hw_priv_flags = IFF_UNICAST_FLT,
144 .link_speed_msk = (HW_ATL_A0_RATE_10G |
145 HW_ATL_A0_RATE_5G |
146 HW_ATL_A0_RATE_2G5 |
147 HW_ATL_A0_RATE_1G |
148 HW_ATL_A0_RATE_100M),
149 .flow_control = true,
150 .mtu = HW_ATL_A0_MTU_JUMBO,
151 .mac_regs_count = 88,
152 .fw_ver_expected = HW_ATL_A0_FW_VER_EXPECTED,
153};
154
155#endif /* HW_ATL_A0_INTERNAL_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
new file mode 100644
index 000000000000..e7e694f693bd
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
@@ -0,0 +1,958 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */
11
12#include "../aq_hw.h"
13#include "../aq_hw_utils.h"
14#include "../aq_ring.h"
15#include "hw_atl_b0.h"
16#include "hw_atl_utils.h"
17#include "hw_atl_llh.h"
18#include "hw_atl_b0_internal.h"
19
20static int hw_atl_b0_get_hw_caps(struct aq_hw_s *self,
21 struct aq_hw_caps_s *aq_hw_caps)
22{
23 memcpy(aq_hw_caps, &hw_atl_b0_hw_caps_, sizeof(*aq_hw_caps));
24 return 0;
25}
26
27static struct aq_hw_s *hw_atl_b0_create(struct aq_pci_func_s *aq_pci_func,
28 unsigned int port,
29 struct aq_hw_ops *ops)
30{
31 struct hw_atl_s *self = NULL;
32
33 self = kzalloc(sizeof(*self), GFP_KERNEL);
34 if (!self)
35 goto err_exit;
36
37 self->base.aq_pci_func = aq_pci_func;
38
39 self->base.not_ff_addr = 0x10U;
40
41err_exit:
42 return (struct aq_hw_s *)self;
43}
44
45static void hw_atl_b0_destroy(struct aq_hw_s *self)
46{
47 kfree(self);
48}
49
50static int hw_atl_b0_hw_reset(struct aq_hw_s *self)
51{
52 int err = 0;
53
54 glb_glb_reg_res_dis_set(self, 1U);
55 pci_pci_reg_res_dis_set(self, 0U);
56 rx_rx_reg_res_dis_set(self, 0U);
57 tx_tx_reg_res_dis_set(self, 0U);
58
59 HW_ATL_FLUSH();
60 glb_soft_res_set(self, 1);
61
62 /* check 10 times by 1ms */
63 AQ_HW_WAIT_FOR(glb_soft_res_get(self) == 0, 1000U, 10U);
64 if (err < 0)
65 goto err_exit;
66
67 itr_irq_reg_res_dis_set(self, 0U);
68 itr_res_irq_set(self, 1U);
69
70 /* check 10 times by 1ms */
71 AQ_HW_WAIT_FOR(itr_res_irq_get(self) == 0, 1000U, 10U);
72 if (err < 0)
73 goto err_exit;
74
75 hw_atl_utils_mpi_set(self, MPI_RESET, 0x0U);
76
77 err = aq_hw_err_from_flags(self);
78
79err_exit:
80 return err;
81}
82
83static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
84{
85 u32 tc = 0U;
86 u32 buff_size = 0U;
87 unsigned int i_priority = 0U;
88 bool is_rx_flow_control = false;
89
90 /* TPS Descriptor rate init */
91 tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
92 tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
93
94 /* TPS VM init */
95 tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
96
97 /* TPS TC credits init */
98 tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
99 tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
100
101 tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
102 tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
103 tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
104 tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
105
106 /* Tx buf size */
107 buff_size = HW_ATL_B0_TXBUF_MAX;
108
109 tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
110 tpb_tx_buff_hi_threshold_per_tc_set(self,
111 (buff_size * (1024 / 32U) * 66U) /
112 100U, tc);
113 tpb_tx_buff_lo_threshold_per_tc_set(self,
114 (buff_size * (1024 / 32U) * 50U) /
115 100U, tc);
116
117 /* QoS Rx buf size per TC */
118 tc = 0;
119 is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
120 buff_size = HW_ATL_B0_RXBUF_MAX;
121
122 rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
123 rpb_rx_buff_hi_threshold_per_tc_set(self,
124 (buff_size *
125 (1024U / 32U) * 66U) /
126 100U, tc);
127 rpb_rx_buff_lo_threshold_per_tc_set(self,
128 (buff_size *
129 (1024U / 32U) * 50U) /
130 100U, tc);
131 rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
132
133 /* QoS 802.1p priority -> TC mapping */
134 for (i_priority = 8U; i_priority--;)
135 rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
136
137 return aq_hw_err_from_flags(self);
138}
139
140static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
141 struct aq_rss_parameters *rss_params)
142{
143 struct aq_nic_cfg_s *cfg = NULL;
144 int err = 0;
145 unsigned int i = 0U;
146 unsigned int addr = 0U;
147
148 cfg = self->aq_nic_cfg;
149
150 for (i = 10, addr = 0U; i--; ++addr) {
151 u32 key_data = cfg->is_rss ?
152 __swab32(rss_params->hash_secret_key[i]) : 0U;
153 rpf_rss_key_wr_data_set(self, key_data);
154 rpf_rss_key_addr_set(self, addr);
155 rpf_rss_key_wr_en_set(self, 1U);
156 AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self) == 0, 1000U, 10U);
157 if (err < 0)
158 goto err_exit;
159 }
160
161 err = aq_hw_err_from_flags(self);
162
163err_exit:
164 return err;
165}
166
167static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
168 struct aq_rss_parameters *rss_params)
169{
170 u8 *indirection_table = rss_params->indirection_table;
171 u32 i = 0U;
172 u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
173 int err = 0;
174 u16 bitary[(HW_ATL_B0_RSS_REDIRECTION_MAX *
175 HW_ATL_B0_RSS_REDIRECTION_BITS / 16U)];
176
177 memset(bitary, 0, sizeof(bitary));
178
179 for (i = HW_ATL_B0_RSS_REDIRECTION_MAX; i--;) {
180 (*(u32 *)(bitary + ((i * 3U) / 16U))) |=
181 ((indirection_table[i] % num_rss_queues) <<
182 ((i * 3U) & 0xFU));
183 }
184
185 for (i = AQ_DIMOF(bitary); i--;) {
186 rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
187 rpf_rss_redir_tbl_addr_set(self, i);
188 rpf_rss_redir_wr_en_set(self, 1U);
189 AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self) == 0, 1000U, 10U);
190 if (err < 0)
191 goto err_exit;
192 }
193
194 err = aq_hw_err_from_flags(self);
195
196err_exit:
197 return err;
198}
199
200static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
201 struct aq_nic_cfg_s *aq_nic_cfg)
202{
203 int err = 0;
204 unsigned int i;
205
206 /* TX checksums offloads*/
207 tpo_ipv4header_crc_offload_en_set(self, 1);
208 tpo_tcp_udp_crc_offload_en_set(self, 1);
209 if (err < 0)
210 goto err_exit;
211
212 /* RX checksums offloads*/
213 rpo_ipv4header_crc_offload_en_set(self, 1);
214 rpo_tcp_udp_crc_offload_en_set(self, 1);
215 if (err < 0)
216 goto err_exit;
217
218 /* LSO offloads*/
219 tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
220 if (err < 0)
221 goto err_exit;
222
223/* LRO offloads */
224 {
225 unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U :
226 ((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U :
227 ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0));
228
229 for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++)
230 rpo_lro_max_num_of_descriptors_set(self, val, i);
231
232 rpo_lro_time_base_divider_set(self, 0x61AU);
233 rpo_lro_inactive_interval_set(self, 0);
234 rpo_lro_max_coalescing_interval_set(self, 2);
235
236 rpo_lro_qsessions_lim_set(self, 1U);
237
238 rpo_lro_total_desc_lim_set(self, 2U);
239
240 rpo_lro_patch_optimization_en_set(self, 0U);
241
242 rpo_lro_min_pay_of_first_pkt_set(self, 10U);
243
244 rpo_lro_pkt_lim_set(self, 1U);
245
246 rpo_lro_en_set(self, aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);
247 }
248 err = aq_hw_err_from_flags(self);
249
250err_exit:
251 return err;
252}
253
254static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)
255{
256 thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
257 thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
258 thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
259
260 /* Tx interrupts */
261 tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
262
263 /* misc */
264 aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
265 0x00010000U : 0x00000000U);
266 tdm_tx_dca_en_set(self, 0U);
267 tdm_tx_dca_mode_set(self, 0U);
268
269 tpb_tx_path_scp_ins_en_set(self, 1U);
270
271 return aq_hw_err_from_flags(self);
272}
273
274static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self)
275{
276 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
277 int i;
278
279 /* Rx TC/RSS number config */
280 rpb_rpf_rx_traf_class_mode_set(self, 1U);
281
282 /* Rx flow control */
283 rpb_rx_flow_ctl_mode_set(self, 1U);
284
285 /* RSS Ring selection */
286 reg_rx_flr_rss_control1set(self, cfg->is_rss ?
287 0xB3333333U : 0x00000000U);
288
289 /* Multicast filters */
290 for (i = HW_ATL_B0_MAC_MAX; i--;) {
291 rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
292 rpfl2unicast_flr_act_set(self, 1U, i);
293 }
294
295 reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
296 reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
297
298 /* Vlan filters */
299 rpf_vlan_outer_etht_set(self, 0x88A8U);
300 rpf_vlan_inner_etht_set(self, 0x8100U);
301
302 if (cfg->vlan_id) {
303 rpf_vlan_flr_act_set(self, 1U, 0U);
304 rpf_vlan_id_flr_set(self, 0U, 0U);
305 rpf_vlan_flr_en_set(self, 0U, 0U);
306
307 rpf_vlan_accept_untagged_packets_set(self, 1U);
308 rpf_vlan_untagged_act_set(self, 1U);
309
310 rpf_vlan_flr_act_set(self, 1U, 1U);
311 rpf_vlan_id_flr_set(self, cfg->vlan_id, 0U);
312 rpf_vlan_flr_en_set(self, 1U, 1U);
313 } else {
314 rpf_vlan_prom_mode_en_set(self, 1);
315 }
316
317 /* Rx Interrupts */
318 rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
319
320 /* misc */
321 aq_hw_write_reg(self, 0x00005040U,
322 IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U);
323
324 rpfl2broadcast_flr_act_set(self, 1U);
325 rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
326
327 rdm_rx_dca_en_set(self, 0U);
328 rdm_rx_dca_mode_set(self, 0U);
329
330 return aq_hw_err_from_flags(self);
331}
332
333static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
334{
335 int err = 0;
336 unsigned int h = 0U;
337 unsigned int l = 0U;
338
339 if (!mac_addr) {
340 err = -EINVAL;
341 goto err_exit;
342 }
343 h = (mac_addr[0] << 8) | (mac_addr[1]);
344 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
345 (mac_addr[4] << 8) | mac_addr[5];
346
347 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC);
348 rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC);
349 rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC);
350 rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC);
351
352 err = aq_hw_err_from_flags(self);
353
354err_exit:
355 return err;
356}
357
358static int hw_atl_b0_hw_init(struct aq_hw_s *self,
359 struct aq_nic_cfg_s *aq_nic_cfg,
360 u8 *mac_addr)
361{
362 static u32 aq_hw_atl_igcr_table_[4][2] = {
363 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
364 { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */
365 { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */
366 { 0x20000022U, 0x20000026U } /* AQ_IRQ_MSIX */
367 };
368
369 int err = 0;
370
371 self->aq_nic_cfg = aq_nic_cfg;
372
373 hw_atl_utils_hw_chip_features_init(self,
374 &PHAL_ATLANTIC_B0->chip_features);
375
376 hw_atl_b0_hw_init_tx_path(self);
377 hw_atl_b0_hw_init_rx_path(self);
378
379 hw_atl_b0_hw_mac_addr_set(self, mac_addr);
380
381 hw_atl_utils_mpi_set(self, MPI_INIT, aq_nic_cfg->link_speed_msk);
382
383 hw_atl_b0_hw_qos_set(self);
384 hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
385 hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
386
387 err = aq_hw_err_from_flags(self);
388 if (err < 0)
389 goto err_exit;
390
391 /* Interrupts */
392 reg_irq_glb_ctl_set(self,
393 aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
394 [(aq_nic_cfg->vecs > 1U) ?
395 1 : 0]);
396
397 itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
398
399 /* Interrupts */
400 reg_gen_irq_map_set(self,
401 ((HW_ATL_B0_ERR_INT << 0x18) | (1U << 0x1F)) |
402 ((HW_ATL_B0_ERR_INT << 0x10) | (1U << 0x17)), 0U);
403
404 hw_atl_b0_hw_offload_set(self, aq_nic_cfg);
405
406err_exit:
407 return err;
408}
409
410static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self,
411 struct aq_ring_s *ring)
412{
413 tdm_tx_desc_en_set(self, 1, ring->idx);
414 return aq_hw_err_from_flags(self);
415}
416
417static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self,
418 struct aq_ring_s *ring)
419{
420 rdm_rx_desc_en_set(self, 1, ring->idx);
421 return aq_hw_err_from_flags(self);
422}
423
424static int hw_atl_b0_hw_start(struct aq_hw_s *self)
425{
426 tpb_tx_buff_en_set(self, 1);
427 rpb_rx_buff_en_set(self, 1);
428 return aq_hw_err_from_flags(self);
429}
430
431static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self,
432 struct aq_ring_s *ring)
433{
434 reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
435 return 0;
436}
437
438static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self,
439 struct aq_ring_s *ring,
440 unsigned int frags)
441{
442 struct aq_ring_buff_s *buff = NULL;
443 struct hw_atl_txd_s *txd = NULL;
444 unsigned int buff_pa_len = 0U;
445 unsigned int pkt_len = 0U;
446 unsigned int frag_count = 0U;
447 bool is_gso = false;
448
449 buff = &ring->buff_ring[ring->sw_tail];
450 pkt_len = (buff->is_eop && buff->is_sop) ? buff->len : buff->len_pkt;
451
452 for (frag_count = 0; frag_count < frags; frag_count++) {
453 txd = (struct hw_atl_txd_s *)&ring->dx_ring[ring->sw_tail *
454 HW_ATL_B0_TXD_SIZE];
455 txd->ctl = 0;
456 txd->ctl2 = 0;
457 txd->buf_addr = 0;
458
459 buff = &ring->buff_ring[ring->sw_tail];
460
461 if (buff->is_txc) {
462 txd->ctl |= (buff->len_l3 << 31) |
463 (buff->len_l2 << 24) |
464 HW_ATL_B0_TXD_CTL_CMD_TCP |
465 HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC;
466 txd->ctl2 |= (buff->mss << 16) |
467 (buff->len_l4 << 8) |
468 (buff->len_l3 >> 1);
469
470 pkt_len -= (buff->len_l4 +
471 buff->len_l3 +
472 buff->len_l2);
473 is_gso = true;
474 } else {
475 buff_pa_len = buff->len;
476
477 txd->buf_addr = buff->pa;
478 txd->ctl |= (HW_ATL_B0_TXD_CTL_BLEN &
479 ((u32)buff_pa_len << 4));
480 txd->ctl |= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD;
481 /* PAY_LEN */
482 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_LEN & (pkt_len << 14);
483
484 if (is_gso) {
485 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_LSO;
486 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_CTX_EN;
487 }
488
489 /* Tx checksum offloads */
490 if (buff->is_ip_cso)
491 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPCSO;
492
493 if (buff->is_udp_cso || buff->is_tcp_cso)
494 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_TUCSO;
495
496 if (unlikely(buff->is_eop)) {
497 txd->ctl |= HW_ATL_B0_TXD_CTL_EOP;
498 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_WB;
499 }
500 }
501
502 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail);
503 }
504
505 hw_atl_b0_hw_tx_ring_tail_update(self, ring);
506 return aq_hw_err_from_flags(self);
507}
508
509static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self,
510 struct aq_ring_s *aq_ring,
511 struct aq_ring_param_s *aq_ring_param)
512{
513 u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
514 u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
515
516 rdm_rx_desc_en_set(self, false, aq_ring->idx);
517
518 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
519
520 reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
521 aq_ring->idx);
522
523 reg_rx_dma_desc_base_addressmswset(self,
524 dma_desc_addr_msw, aq_ring->idx);
525
526 rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
527
528 rdm_rx_desc_data_buff_size_set(self,
529 AQ_CFG_RX_FRAME_MAX / 1024U,
530 aq_ring->idx);
531
532 rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
533 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
534 rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
535
536 /* Rx ring set mode */
537
538 /* Mapping interrupt vector */
539 itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
540 itr_irq_map_en_rx_set(self, true, aq_ring->idx);
541
542 rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
543 rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
544 rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
545 rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
546
547 return aq_hw_err_from_flags(self);
548}
549
550static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self,
551 struct aq_ring_s *aq_ring,
552 struct aq_ring_param_s *aq_ring_param)
553{
554 u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
555 u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
556
557 reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
558 aq_ring->idx);
559
560 reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
561 aq_ring->idx);
562
563 tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
564
565 hw_atl_b0_hw_tx_ring_tail_update(self, aq_ring);
566
567 /* Set Tx threshold */
568 tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
569
570 /* Mapping interrupt vector */
571 itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
572 itr_irq_map_en_tx_set(self, true, aq_ring->idx);
573
574 tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
575 tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
576
577 return aq_hw_err_from_flags(self);
578}
579
580static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self,
581 struct aq_ring_s *ring,
582 unsigned int sw_tail_old)
583{
584 for (; sw_tail_old != ring->sw_tail;
585 sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) {
586 struct hw_atl_rxd_s *rxd =
587 (struct hw_atl_rxd_s *)&ring->dx_ring[sw_tail_old *
588 HW_ATL_B0_RXD_SIZE];
589
590 struct aq_ring_buff_s *buff = &ring->buff_ring[sw_tail_old];
591
592 rxd->buf_addr = buff->pa;
593 rxd->hdr_addr = 0U;
594 }
595
596 reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
597
598 return aq_hw_err_from_flags(self);
599}
600
601static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self,
602 struct aq_ring_s *ring)
603{
604 int err = 0;
605 unsigned int hw_head_ = tdm_tx_desc_head_ptr_get(self, ring->idx);
606
607 if (aq_utils_obj_test(&self->header.flags, AQ_HW_FLAG_ERR_UNPLUG)) {
608 err = -ENXIO;
609 goto err_exit;
610 }
611 ring->hw_head = hw_head_;
612 err = aq_hw_err_from_flags(self);
613
614err_exit:
615 return err;
616}
617
618static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self,
619 struct aq_ring_s *ring)
620{
621 struct device *ndev = aq_nic_get_dev(ring->aq_nic);
622
623 for (; ring->hw_head != ring->sw_tail;
624 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
625 struct aq_ring_buff_s *buff = NULL;
626 struct hw_atl_rxd_wb_s *rxd_wb = (struct hw_atl_rxd_wb_s *)
627 &ring->dx_ring[ring->hw_head * HW_ATL_B0_RXD_SIZE];
628
629 unsigned int is_err = 1U;
630 unsigned int is_rx_check_sum_enabled = 0U;
631 unsigned int pkt_type = 0U;
632
633 if (!(rxd_wb->status & 0x1U)) { /* RxD is not done */
634 break;
635 }
636
637 buff = &ring->buff_ring[ring->hw_head];
638
639 is_err = (0x0000003CU & rxd_wb->status);
640
641 is_rx_check_sum_enabled = (rxd_wb->type) & (0x3U << 19);
642 is_err &= ~0x20U; /* exclude validity bit */
643
644 pkt_type = 0xFFU & (rxd_wb->type >> 4);
645
646 if (is_rx_check_sum_enabled) {
647 if (0x0U == (pkt_type & 0x3U))
648 buff->is_ip_cso = (is_err & 0x08U) ? 0U : 1U;
649
650 if (0x4U == (pkt_type & 0x1CU))
651 buff->is_udp_cso = buff->is_cso_err ? 0U : 1U;
652 else if (0x0U == (pkt_type & 0x1CU))
653 buff->is_tcp_cso = buff->is_cso_err ? 0U : 1U;
654 }
655
656 is_err &= ~0x18U;
657
658 dma_unmap_page(ndev, buff->pa, buff->len, DMA_FROM_DEVICE);
659
660 if (is_err || rxd_wb->type & 0x1000U) {
661 /* status error or DMA error */
662 buff->is_error = 1U;
663 } else {
664 if (self->aq_nic_cfg->is_rss) {
665 /* last 4 byte */
666 u16 rss_type = rxd_wb->type & 0xFU;
667
668 if (rss_type && rss_type < 0x8U) {
669 buff->is_hash_l4 = (rss_type == 0x4 ||
670 rss_type == 0x5);
671 buff->rss_hash = rxd_wb->rss_hash;
672 }
673 }
674
675 if (HW_ATL_B0_RXD_WB_STAT2_EOP & rxd_wb->status) {
676 buff->len = (rxd_wb->pkt_len &
677 (AQ_CFG_RX_FRAME_MAX - 1U));
678 buff->len = buff->len ?
679 buff->len : AQ_CFG_RX_FRAME_MAX;
680 buff->next = 0U;
681 buff->is_eop = 1U;
682 } else {
683 if (HW_ATL_B0_RXD_WB_STAT2_RSCCNT &
684 rxd_wb->status) {
685 /* LRO */
686 buff->next = rxd_wb->next_desc_ptr;
687 ++ring->stats.rx.lro_packets;
688 } else {
689 /* jumbo */
690 buff->next =
691 aq_ring_next_dx(ring,
692 ring->hw_head);
693 ++ring->stats.rx.jumbo_packets;
694 }
695 }
696 }
697 }
698
699 return aq_hw_err_from_flags(self);
700}
701
702static int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
703{
704 itr_irq_msk_setlsw_set(self, LODWORD(mask));
705 return aq_hw_err_from_flags(self);
706}
707
708static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
709{
710 itr_irq_msk_clearlsw_set(self, LODWORD(mask));
711 itr_irq_status_clearlsw_set(self, LODWORD(mask));
712
713 atomic_inc(&PHAL_ATLANTIC_B0->dpc);
714 return aq_hw_err_from_flags(self);
715}
716
717static int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
718{
719 *mask = itr_irq_statuslsw_get(self);
720 return aq_hw_err_from_flags(self);
721}
722
723#define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
724
725static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self,
726 unsigned int packet_filter)
727{
728 unsigned int i = 0U;
729
730 rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
731 rpfl2multicast_flr_en_set(self,
732 IS_FILTER_ENABLED(IFF_MULTICAST), 0);
733
734 rpfl2_accept_all_mc_packets_set(self,
735 IS_FILTER_ENABLED(IFF_ALLMULTI));
736
737 rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
738
739 self->aq_nic_cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST);
740
741 for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i)
742 rpfl2_uc_flr_en_set(self,
743 (self->aq_nic_cfg->is_mc_list_enabled &&
744 (i <= self->aq_nic_cfg->mc_list_count)) ?
745 1U : 0U, i);
746
747 return aq_hw_err_from_flags(self);
748}
749
750#undef IS_FILTER_ENABLED
751
752static int hw_atl_b0_hw_multicast_list_set(struct aq_hw_s *self,
753 u8 ar_mac
754 [AQ_CFG_MULTICAST_ADDRESS_MAX]
755 [ETH_ALEN],
756 u32 count)
757{
758 int err = 0;
759
760 if (count > (HW_ATL_B0_MAC_MAX - HW_ATL_B0_MAC_MIN)) {
761 err = -EBADRQC;
762 goto err_exit;
763 }
764 for (self->aq_nic_cfg->mc_list_count = 0U;
765 self->aq_nic_cfg->mc_list_count < count;
766 ++self->aq_nic_cfg->mc_list_count) {
767 u32 i = self->aq_nic_cfg->mc_list_count;
768 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
769 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
770 (ar_mac[i][4] << 8) | ar_mac[i][5];
771
772 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i);
773
774 rpfl2unicast_dest_addresslsw_set(self,
775 l, HW_ATL_B0_MAC_MIN + i);
776
777 rpfl2unicast_dest_addressmsw_set(self,
778 h, HW_ATL_B0_MAC_MIN + i);
779
780 rpfl2_uc_flr_en_set(self,
781 (self->aq_nic_cfg->is_mc_list_enabled),
782 HW_ATL_B0_MAC_MIN + i);
783 }
784
785 err = aq_hw_err_from_flags(self);
786
787err_exit:
788 return err;
789}
790
791static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self,
792 bool itr_enabled)
793{
794 unsigned int i = 0U;
795
796 if (itr_enabled && self->aq_nic_cfg->itr) {
797 tdm_tx_desc_wr_wb_irq_en_set(self, 0U);
798 tdm_tdm_intr_moder_en_set(self, 1U);
799 rdm_rx_desc_wr_wb_irq_en_set(self, 0U);
800 rdm_rdm_intr_moder_en_set(self, 1U);
801
802 PHAL_ATLANTIC_B0->itr_tx = 2U;
803 PHAL_ATLANTIC_B0->itr_rx = 2U;
804
805 if (self->aq_nic_cfg->itr != 0xFFFFU) {
806 unsigned int max_timer = self->aq_nic_cfg->itr / 2U;
807 unsigned int min_timer = self->aq_nic_cfg->itr / 32U;
808
809 max_timer = min(0x1FFU, max_timer);
810 min_timer = min(0xFFU, min_timer);
811
812 PHAL_ATLANTIC_B0->itr_tx |= min_timer << 0x8U;
813 PHAL_ATLANTIC_B0->itr_tx |= max_timer << 0x10U;
814 PHAL_ATLANTIC_B0->itr_rx |= min_timer << 0x8U;
815 PHAL_ATLANTIC_B0->itr_rx |= max_timer << 0x10U;
816 } else {
817 static unsigned int hw_atl_b0_timers_table_tx_[][2] = {
818 {0xffU, 0xffU}, /* 10Gbit */
819 {0xffU, 0x1ffU}, /* 5Gbit */
820 {0xffU, 0x1ffU}, /* 5Gbit 5GS */
821 {0xffU, 0x1ffU}, /* 2.5Gbit */
822 {0xffU, 0x1ffU}, /* 1Gbit */
823 {0xffU, 0x1ffU}, /* 100Mbit */
824 };
825
826 static unsigned int hw_atl_b0_timers_table_rx_[][2] = {
827 {0x6U, 0x38U},/* 10Gbit */
828 {0xCU, 0x70U},/* 5Gbit */
829 {0xCU, 0x70U},/* 5Gbit 5GS */
830 {0x18U, 0xE0U},/* 2.5Gbit */
831 {0x30U, 0x80U},/* 1Gbit */
832 {0x4U, 0x50U},/* 100Mbit */
833 };
834
835 unsigned int speed_index =
836 hw_atl_utils_mbps_2_speed_index(
837 self->aq_link_status.mbps);
838
839 PHAL_ATLANTIC_B0->itr_tx |=
840 hw_atl_b0_timers_table_tx_[speed_index]
841 [0] << 0x8U; /* set min timer value */
842 PHAL_ATLANTIC_B0->itr_tx |=
843 hw_atl_b0_timers_table_tx_[speed_index]
844 [1] << 0x10U; /* set max timer value */
845
846 PHAL_ATLANTIC_B0->itr_rx |=
847 hw_atl_b0_timers_table_rx_[speed_index]
848 [0] << 0x8U; /* set min timer value */
849 PHAL_ATLANTIC_B0->itr_rx |=
850 hw_atl_b0_timers_table_rx_[speed_index]
851 [1] << 0x10U; /* set max timer value */
852 }
853 } else {
854 tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
855 tdm_tdm_intr_moder_en_set(self, 0U);
856 rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
857 rdm_rdm_intr_moder_en_set(self, 0U);
858 PHAL_ATLANTIC_B0->itr_tx = 0U;
859 PHAL_ATLANTIC_B0->itr_rx = 0U;
860 }
861
862 for (i = HW_ATL_B0_RINGS_MAX; i--;) {
863 reg_tx_intr_moder_ctrl_set(self,
864 PHAL_ATLANTIC_B0->itr_tx, i);
865 reg_rx_intr_moder_ctrl_set(self,
866 PHAL_ATLANTIC_B0->itr_rx, i);
867 }
868
869 return aq_hw_err_from_flags(self);
870}
871
872static int hw_atl_b0_hw_stop(struct aq_hw_s *self)
873{
874 hw_atl_b0_hw_irq_disable(self, HW_ATL_B0_INT_MASK);
875 return aq_hw_err_from_flags(self);
876}
877
878static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self,
879 struct aq_ring_s *ring)
880{
881 tdm_tx_desc_en_set(self, 0U, ring->idx);
882 return aq_hw_err_from_flags(self);
883}
884
885static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self,
886 struct aq_ring_s *ring)
887{
888 rdm_rx_desc_en_set(self, 0U, ring->idx);
889 return aq_hw_err_from_flags(self);
890}
891
892static int hw_atl_b0_hw_set_speed(struct aq_hw_s *self, u32 speed)
893{
894 int err = 0;
895
896 err = hw_atl_utils_mpi_set_speed(self, speed, MPI_INIT);
897 if (err < 0)
898 goto err_exit;
899
900err_exit:
901 return err;
902}
903
904static struct aq_hw_ops hw_atl_ops_ = {
905 .create = hw_atl_b0_create,
906 .destroy = hw_atl_b0_destroy,
907 .get_hw_caps = hw_atl_b0_get_hw_caps,
908
909 .hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
910 .hw_set_mac_address = hw_atl_b0_hw_mac_addr_set,
911 .hw_get_link_status = hw_atl_utils_mpi_get_link_status,
912 .hw_set_link_speed = hw_atl_b0_hw_set_speed,
913 .hw_init = hw_atl_b0_hw_init,
914 .hw_deinit = hw_atl_utils_hw_deinit,
915 .hw_set_power = hw_atl_utils_hw_set_power,
916 .hw_reset = hw_atl_b0_hw_reset,
917 .hw_start = hw_atl_b0_hw_start,
918 .hw_ring_tx_start = hw_atl_b0_hw_ring_tx_start,
919 .hw_ring_tx_stop = hw_atl_b0_hw_ring_tx_stop,
920 .hw_ring_rx_start = hw_atl_b0_hw_ring_rx_start,
921 .hw_ring_rx_stop = hw_atl_b0_hw_ring_rx_stop,
922 .hw_stop = hw_atl_b0_hw_stop,
923
924 .hw_ring_tx_xmit = hw_atl_b0_hw_ring_tx_xmit,
925 .hw_ring_tx_head_update = hw_atl_b0_hw_ring_tx_head_update,
926
927 .hw_ring_rx_receive = hw_atl_b0_hw_ring_rx_receive,
928 .hw_ring_rx_fill = hw_atl_b0_hw_ring_rx_fill,
929
930 .hw_irq_enable = hw_atl_b0_hw_irq_enable,
931 .hw_irq_disable = hw_atl_b0_hw_irq_disable,
932 .hw_irq_read = hw_atl_b0_hw_irq_read,
933
934 .hw_ring_rx_init = hw_atl_b0_hw_ring_rx_init,
935 .hw_ring_tx_init = hw_atl_b0_hw_ring_tx_init,
936 .hw_packet_filter_set = hw_atl_b0_hw_packet_filter_set,
937 .hw_multicast_list_set = hw_atl_b0_hw_multicast_list_set,
938 .hw_interrupt_moderation_set = hw_atl_b0_hw_interrupt_moderation_set,
939 .hw_rss_set = hw_atl_b0_hw_rss_set,
940 .hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set,
941 .hw_get_regs = hw_atl_utils_hw_get_regs,
942 .hw_get_hw_stats = hw_atl_utils_get_hw_stats,
943 .hw_get_fw_version = hw_atl_utils_get_fw_version,
944};
945
946struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev)
947{
948 bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
949 bool is_did_ok = ((pdev->device == HW_ATL_DEVICE_ID_0001) ||
950 (pdev->device == HW_ATL_DEVICE_ID_D100) ||
951 (pdev->device == HW_ATL_DEVICE_ID_D107) ||
952 (pdev->device == HW_ATL_DEVICE_ID_D108) ||
953 (pdev->device == HW_ATL_DEVICE_ID_D109));
954
955 bool is_rev_ok = (pdev->revision == 2U);
956
957 return (is_vid_ok && is_did_ok && is_rev_ok) ? &hw_atl_ops_ : NULL;
958}
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h
new file mode 100644
index 000000000000..a1e1bce6c1f3
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h
@@ -0,0 +1,34 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File hw_atl_b0.h: Declaration of abstract interface for Atlantic hardware
11 * specific functions.
12 */
13
14#ifndef HW_ATL_B0_H
15#define HW_ATL_B0_H
16
17#include "../aq_common.h"
18
19#ifndef PCI_VENDOR_ID_AQUANTIA
20
21#define PCI_VENDOR_ID_AQUANTIA 0x1D6A
22#define HW_ATL_DEVICE_ID_0001 0x0001
23#define HW_ATL_DEVICE_ID_D100 0xD100
24#define HW_ATL_DEVICE_ID_D107 0xD107
25#define HW_ATL_DEVICE_ID_D108 0xD108
26#define HW_ATL_DEVICE_ID_D109 0xD109
27
28#define HW_ATL_NIC_NAME "aQuantia AQtion 5Gbit Network Adapter"
29
30#endif
31
32struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev);
33
34#endif /* HW_ATL_B0_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h
new file mode 100644
index 000000000000..8bdee3ddd5a0
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h
@@ -0,0 +1,207 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File hw_atl_b0_internal.h: Definition of Atlantic B0 chip specific
11 * constants.
12 */
13
14#ifndef HW_ATL_B0_INTERNAL_H
15#define HW_ATL_B0_INTERNAL_H
16
17#include "../aq_common.h"
18
19#define HW_ATL_B0_MTU_JUMBO (16000U)
20#define HW_ATL_B0_MTU 1514U
21
22#define HW_ATL_B0_TX_RINGS 4U
23#define HW_ATL_B0_RX_RINGS 4U
24
25#define HW_ATL_B0_RINGS_MAX 32U
26#define HW_ATL_B0_TXD_SIZE (16U)
27#define HW_ATL_B0_RXD_SIZE (16U)
28
29#define HW_ATL_B0_MAC 0U
30#define HW_ATL_B0_MAC_MIN 1U
31#define HW_ATL_B0_MAC_MAX 33U
32
33/* UCAST/MCAST filters */
34#define HW_ATL_B0_UCAST_FILTERS_MAX 38
35#define HW_ATL_B0_MCAST_FILTERS_MAX 8
36
37/* interrupts */
38#define HW_ATL_B0_ERR_INT 8U
39#define HW_ATL_B0_INT_MASK (0xFFFFFFFFU)
40
41#define HW_ATL_B0_TXD_CTL2_LEN (0xFFFFC000)
42#define HW_ATL_B0_TXD_CTL2_CTX_EN (0x00002000)
43#define HW_ATL_B0_TXD_CTL2_CTX_IDX (0x00001000)
44
45#define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD (0x00000001)
46#define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC (0x00000002)
47#define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0)
48#define HW_ATL_B0_TXD_CTL_DD (0x00100000)
49#define HW_ATL_B0_TXD_CTL_EOP (0x00200000)
50
51#define HW_ATL_B0_TXD_CTL_CMD_X (0x3FC00000)
52
53#define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22)
54#define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23)
55#define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24)
56#define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25)
57#define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26)
58#define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27)
59#define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28)
60
61#define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21)
62#define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22)
63
64#define HW_ATL_B0_MPI_CONTROL_ADR 0x0368U
65#define HW_ATL_B0_MPI_STATE_ADR 0x036CU
66
67#define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU
68#define HW_ATL_B0_MPI_SPEED_SHIFT 16U
69
70#define HW_ATL_B0_RATE_10G BIT(0)
71#define HW_ATL_B0_RATE_5G BIT(1)
72#define HW_ATL_B0_RATE_2G5 BIT(3)
73#define HW_ATL_B0_RATE_1G BIT(4)
74#define HW_ATL_B0_RATE_100M BIT(5)
75
76#define HW_ATL_B0_TXBUF_MAX 160U
77#define HW_ATL_B0_RXBUF_MAX 320U
78
79#define HW_ATL_B0_RSS_REDIRECTION_MAX 64U
80#define HW_ATL_B0_RSS_REDIRECTION_BITS 3U
81#define HW_ATL_B0_RSS_HASHKEY_BITS 320U
82
83#define HW_ATL_B0_TCRSS_4_8 1
84#define HW_ATL_B0_TC_MAX 1U
85#define HW_ATL_B0_RSS_MAX 8U
86
87#define HW_ATL_B0_LRO_RXD_MAX 2U
88#define HW_ATL_B0_RS_SLIP_ENABLED 0U
89
90/* (256k -1(max pay_len) - 54(header)) */
91#define HAL_ATL_B0_LSO_MAX_SEGMENT_SIZE 262089U
92
93/* (256k -1(max pay_len) - 74(header)) */
94#define HAL_ATL_B0_LSO_IPV6_MAX_SEGMENT_SIZE 262069U
95
96#define HW_ATL_B0_CHIP_REVISION_B0 0xA0U
97#define HW_ATL_B0_CHIP_REVISION_UNKNOWN 0xFFU
98
99#define HW_ATL_B0_FW_SEMA_RAM 0x2U
100
101#define HW_ATL_B0_TXC_LEN_TUNLEN (0x0000FF00)
102#define HW_ATL_B0_TXC_LEN_OUTLEN (0xFFFF0000)
103
104#define HW_ATL_B0_TXC_CTL_DESC_TYPE (0x00000007)
105#define HW_ATL_B0_TXC_CTL_CTX_ID (0x00000008)
106#define HW_ATL_B0_TXC_CTL_VLAN (0x000FFFF0)
107#define HW_ATL_B0_TXC_CTL_CMD (0x00F00000)
108#define HW_ATL_B0_TXC_CTL_L2LEN (0x7F000000)
109
110#define HW_ATL_B0_TXC_CTL_L3LEN (0x80000000) /* L3LEN lsb */
111#define HW_ATL_B0_TXC_LEN2_L3LEN (0x000000FF) /* L3LE upper bits */
112#define HW_ATL_B0_TXC_LEN2_L4LEN (0x0000FF00)
113#define HW_ATL_B0_TXC_LEN2_MSSLEN (0xFFFF0000)
114
115#define HW_ATL_B0_RXD_DD (0x1)
116#define HW_ATL_B0_RXD_NCEA0 (0x1)
117
118#define HW_ATL_B0_RXD_WB_STAT_RSSTYPE (0x0000000F)
119#define HW_ATL_B0_RXD_WB_STAT_PKTTYPE (0x00000FF0)
120#define HW_ATL_B0_RXD_WB_STAT_RXCTRL (0x00180000)
121#define HW_ATL_B0_RXD_WB_STAT_SPLHDR (0x00200000)
122#define HW_ATL_B0_RXD_WB_STAT_HDRLEN (0xFFC00000)
123
124#define HW_ATL_B0_RXD_WB_STAT2_DD (0x0001)
125#define HW_ATL_B0_RXD_WB_STAT2_EOP (0x0002)
126#define HW_ATL_B0_RXD_WB_STAT2_RXSTAT (0x003C)
127#define HW_ATL_B0_RXD_WB_STAT2_MACERR (0x0004)
128#define HW_ATL_B0_RXD_WB_STAT2_IP4ERR (0x0008)
129#define HW_ATL_B0_RXD_WB_STAT2_TCPUPDERR (0x0010)
130#define HW_ATL_B0_RXD_WB_STAT2_RXESTAT (0x0FC0)
131#define HW_ATL_B0_RXD_WB_STAT2_RSCCNT (0xF000)
132
133#define L2_FILTER_ACTION_DISCARD (0x0)
134#define L2_FILTER_ACTION_HOST (0x1)
135
136#define HW_ATL_B0_UCP_0X370_REG (0x370)
137
138#define HW_ATL_B0_FLUSH() AQ_HW_READ_REG(self, 0x10)
139
140#define HW_ATL_B0_FW_VER_EXPECTED 0x01050006U
141
142/* Hardware tx descriptor */
143struct __packed hw_atl_txd_s {
144 u64 buf_addr;
145 u32 ctl;
146 u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */
147};
148
149/* Hardware tx context descriptor */
150struct __packed hw_atl_txc_s {
151 u32 rsvd;
152 u32 len;
153 u32 ctl;
154 u32 len2;
155};
156
157/* Hardware rx descriptor */
158struct __packed hw_atl_rxd_s {
159 u64 buf_addr;
160 u64 hdr_addr;
161};
162
163/* Hardware rx descriptor writeback */
164struct __packed hw_atl_rxd_wb_s {
165 u32 type;
166 u32 rss_hash;
167 u16 status;
168 u16 pkt_len;
169 u16 next_desc_ptr;
170 u16 vlan;
171};
172
173/* HW layer capabilities */
174static struct aq_hw_caps_s hw_atl_b0_hw_caps_ = {
175 .ports = 1U,
176 .is_64_dma = true,
177 .msix_irqs = 4U,
178 .irq_mask = ~0U,
179 .vecs = HW_ATL_B0_RSS_MAX,
180 .tcs = HW_ATL_B0_TC_MAX,
181 .rxd_alignment = 1U,
182 .rxd_size = HW_ATL_B0_RXD_SIZE,
183 .rxds = 8U * 1024U,
184 .txd_alignment = 1U,
185 .txd_size = HW_ATL_B0_TXD_SIZE,
186 .txds = 8U * 1024U,
187 .txhwb_alignment = 4096U,
188 .tx_rings = HW_ATL_B0_TX_RINGS,
189 .rx_rings = HW_ATL_B0_RX_RINGS,
190 .hw_features = NETIF_F_HW_CSUM |
191 NETIF_F_RXHASH |
192 NETIF_F_SG |
193 NETIF_F_TSO |
194 NETIF_F_LRO,
195 .hw_priv_flags = IFF_UNICAST_FLT,
196 .link_speed_msk = (HW_ATL_B0_RATE_10G |
197 HW_ATL_B0_RATE_5G |
198 HW_ATL_B0_RATE_2G5 |
199 HW_ATL_B0_RATE_1G |
200 HW_ATL_B0_RATE_100M),
201 .flow_control = true,
202 .mtu = HW_ATL_B0_MTU_JUMBO,
203 .mac_regs_count = 88,
204 .fw_ver_expected = HW_ATL_B0_FW_VER_EXPECTED,
205};
206
207#endif /* HW_ATL_B0_INTERNAL_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c
new file mode 100644
index 000000000000..3de651afa8c7
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c
@@ -0,0 +1,1394 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File hw_atl_llh.c: Definitions of bitfield and register access functions for
11 * Atlantic registers.
12 */
13
14#include "hw_atl_llh.h"
15#include "hw_atl_llh_internal.h"
16#include "../aq_hw_utils.h"
17
18/* global */
19void reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem, u32 semaphore)
20{
21 aq_hw_write_reg(aq_hw, glb_cpu_sem_adr(semaphore), glb_cpu_sem);
22}
23
24u32 reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore)
25{
26 return aq_hw_read_reg(aq_hw, glb_cpu_sem_adr(semaphore));
27}
28
29void glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis)
30{
31 aq_hw_write_reg_bit(aq_hw, glb_reg_res_dis_adr,
32 glb_reg_res_dis_msk,
33 glb_reg_res_dis_shift,
34 glb_reg_res_dis);
35}
36
37void glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res)
38{
39 aq_hw_write_reg_bit(aq_hw, glb_soft_res_adr, glb_soft_res_msk,
40 glb_soft_res_shift, soft_res);
41}
42
43u32 glb_soft_res_get(struct aq_hw_s *aq_hw)
44{
45 return aq_hw_read_reg_bit(aq_hw, glb_soft_res_adr,
46 glb_soft_res_msk,
47 glb_soft_res_shift);
48}
49
50u32 reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw)
51{
52 return aq_hw_read_reg(aq_hw, rx_dma_stat_counter7_adr);
53}
54
55u32 reg_glb_mif_id_get(struct aq_hw_s *aq_hw)
56{
57 return aq_hw_read_reg(aq_hw, glb_mif_id_adr);
58}
59
60/* stats */
61u32 rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw)
62{
63 return aq_hw_read_reg(aq_hw, rpb_rx_dma_drop_pkt_cnt_adr);
64}
65
66u32 stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
67{
68 return aq_hw_read_reg(aq_hw, stats_rx_dma_good_octet_counterlsw__adr);
69}
70
71u32 stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
72{
73 return aq_hw_read_reg(aq_hw, stats_rx_dma_good_pkt_counterlsw__adr);
74}
75
76u32 stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
77{
78 return aq_hw_read_reg(aq_hw, stats_tx_dma_good_octet_counterlsw__adr);
79}
80
81u32 stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
82{
83 return aq_hw_read_reg(aq_hw, stats_tx_dma_good_pkt_counterlsw__adr);
84}
85
86u32 stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
87{
88 return aq_hw_read_reg(aq_hw, stats_rx_dma_good_octet_countermsw__adr);
89}
90
91u32 stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
92{
93 return aq_hw_read_reg(aq_hw, stats_rx_dma_good_pkt_countermsw__adr);
94}
95
96u32 stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
97{
98 return aq_hw_read_reg(aq_hw, stats_tx_dma_good_octet_countermsw__adr);
99}
100
101u32 stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
102{
103 return aq_hw_read_reg(aq_hw, stats_tx_dma_good_pkt_countermsw__adr);
104}
105
106/* interrupt */
107void itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw, u32 irq_auto_masklsw)
108{
109 aq_hw_write_reg(aq_hw, itr_iamrlsw_adr, irq_auto_masklsw);
110}
111
112void itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, u32 rx)
113{
114/* register address for bitfield imr_rx{r}_en */
115 static u32 itr_imr_rxren_adr[32] = {
116 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
117 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU,
118 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
119 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU,
120 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
121 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU,
122 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
123 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU
124 };
125
126/* bitmask for bitfield imr_rx{r}_en */
127 static u32 itr_imr_rxren_msk[32] = {
128 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
129 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
130 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
131 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
132 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
133 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
134 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
135 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U
136 };
137
138/* lower bit position of bitfield imr_rx{r}_en */
139 static u32 itr_imr_rxren_shift[32] = {
140 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
141 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
142 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
143 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U
144 };
145
146 aq_hw_write_reg_bit(aq_hw, itr_imr_rxren_adr[rx],
147 itr_imr_rxren_msk[rx],
148 itr_imr_rxren_shift[rx],
149 irq_map_en_rx);
150}
151
152void itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, u32 tx)
153{
154/* register address for bitfield imr_tx{t}_en */
155 static u32 itr_imr_txten_adr[32] = {
156 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
157 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU,
158 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
159 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU,
160 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
161 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU,
162 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
163 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU
164 };
165
166/* bitmask for bitfield imr_tx{t}_en */
167 static u32 itr_imr_txten_msk[32] = {
168 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
169 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
170 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
171 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
172 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
173 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
174 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
175 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U
176 };
177
178/* lower bit position of bitfield imr_tx{t}_en */
179 static u32 itr_imr_txten_shift[32] = {
180 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
181 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
182 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
183 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U
184 };
185
186 aq_hw_write_reg_bit(aq_hw, itr_imr_txten_adr[tx],
187 itr_imr_txten_msk[tx],
188 itr_imr_txten_shift[tx],
189 irq_map_en_tx);
190}
191
192void itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx)
193{
194/* register address for bitfield imr_rx{r}[4:0] */
195 static u32 itr_imr_rxr_adr[32] = {
196 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
197 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU,
198 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
199 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU,
200 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
201 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU,
202 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
203 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU
204 };
205
206/* bitmask for bitfield imr_rx{r}[4:0] */
207 static u32 itr_imr_rxr_msk[32] = {
208 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU,
209 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU,
210 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU,
211 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU,
212 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU,
213 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU,
214 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU,
215 0x00001f00U, 0x0000001fU, 0x00001f00U, 0x0000001fU
216 };
217
218/* lower bit position of bitfield imr_rx{r}[4:0] */
219 static u32 itr_imr_rxr_shift[32] = {
220 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
221 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
222 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
223 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U
224 };
225
226 aq_hw_write_reg_bit(aq_hw, itr_imr_rxr_adr[rx],
227 itr_imr_rxr_msk[rx],
228 itr_imr_rxr_shift[rx],
229 irq_map_rx);
230}
231
232void itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx)
233{
234/* register address for bitfield imr_tx{t}[4:0] */
235 static u32 itr_imr_txt_adr[32] = {
236 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
237 0x00002108U, 0x00002108U, 0x0000210cU, 0x0000210cU,
238 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
239 0x00002118U, 0x00002118U, 0x0000211cU, 0x0000211cU,
240 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
241 0x00002128U, 0x00002128U, 0x0000212cU, 0x0000212cU,
242 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
243 0x00002138U, 0x00002138U, 0x0000213cU, 0x0000213cU
244 };
245
246/* bitmask for bitfield imr_tx{t}[4:0] */
247 static u32 itr_imr_txt_msk[32] = {
248 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U,
249 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U,
250 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U,
251 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U,
252 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U,
253 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U,
254 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U,
255 0x1f000000U, 0x001f0000U, 0x1f000000U, 0x001f0000U
256 };
257
258/* lower bit position of bitfield imr_tx{t}[4:0] */
259 static u32 itr_imr_txt_shift[32] = {
260 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
261 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
262 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
263 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U
264 };
265
266 aq_hw_write_reg_bit(aq_hw, itr_imr_txt_adr[tx],
267 itr_imr_txt_msk[tx],
268 itr_imr_txt_shift[tx],
269 irq_map_tx);
270}
271
272void itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_clearlsw)
273{
274 aq_hw_write_reg(aq_hw, itr_imcrlsw_adr, irq_msk_clearlsw);
275}
276
277void itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw)
278{
279 aq_hw_write_reg(aq_hw, itr_imsrlsw_adr, irq_msk_setlsw);
280}
281
282void itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis)
283{
284 aq_hw_write_reg_bit(aq_hw, itr_reg_res_dsbl_adr,
285 itr_reg_res_dsbl_msk,
286 itr_reg_res_dsbl_shift, irq_reg_res_dis);
287}
288
289void itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
290 u32 irq_status_clearlsw)
291{
292 aq_hw_write_reg(aq_hw, itr_iscrlsw_adr, irq_status_clearlsw);
293}
294
295u32 itr_irq_statuslsw_get(struct aq_hw_s *aq_hw)
296{
297 return aq_hw_read_reg(aq_hw, itr_isrlsw_adr);
298}
299
300u32 itr_res_irq_get(struct aq_hw_s *aq_hw)
301{
302 return aq_hw_read_reg_bit(aq_hw, itr_res_adr, itr_res_msk,
303 itr_res_shift);
304}
305
306void itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq)
307{
308 aq_hw_write_reg_bit(aq_hw, itr_res_adr, itr_res_msk,
309 itr_res_shift, res_irq);
310}
311
312/* rdm */
313void rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
314{
315 aq_hw_write_reg_bit(aq_hw, rdm_dcadcpuid_adr(dca),
316 rdm_dcadcpuid_msk,
317 rdm_dcadcpuid_shift, cpuid);
318}
319
320void rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en)
321{
322 aq_hw_write_reg_bit(aq_hw, rdm_dca_en_adr, rdm_dca_en_msk,
323 rdm_dca_en_shift, rx_dca_en);
324}
325
326void rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode)
327{
328 aq_hw_write_reg_bit(aq_hw, rdm_dca_mode_adr, rdm_dca_mode_msk,
329 rdm_dca_mode_shift, rx_dca_mode);
330}
331
332void rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
333 u32 rx_desc_data_buff_size, u32 descriptor)
334{
335 aq_hw_write_reg_bit(aq_hw, rdm_descddata_size_adr(descriptor),
336 rdm_descddata_size_msk,
337 rdm_descddata_size_shift,
338 rx_desc_data_buff_size);
339}
340
341void rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en, u32 dca)
342{
343 aq_hw_write_reg_bit(aq_hw, rdm_dcaddesc_en_adr(dca),
344 rdm_dcaddesc_en_msk,
345 rdm_dcaddesc_en_shift,
346 rx_desc_dca_en);
347}
348
349void rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en, u32 descriptor)
350{
351 aq_hw_write_reg_bit(aq_hw, rdm_descden_adr(descriptor),
352 rdm_descden_msk,
353 rdm_descden_shift,
354 rx_desc_en);
355}
356
357void rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
358 u32 rx_desc_head_buff_size, u32 descriptor)
359{
360 aq_hw_write_reg_bit(aq_hw, rdm_descdhdr_size_adr(descriptor),
361 rdm_descdhdr_size_msk,
362 rdm_descdhdr_size_shift,
363 rx_desc_head_buff_size);
364}
365
366void rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
367 u32 rx_desc_head_splitting, u32 descriptor)
368{
369 aq_hw_write_reg_bit(aq_hw, rdm_descdhdr_split_adr(descriptor),
370 rdm_descdhdr_split_msk,
371 rdm_descdhdr_split_shift,
372 rx_desc_head_splitting);
373}
374
375u32 rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
376{
377 return aq_hw_read_reg_bit(aq_hw, rdm_descdhd_adr(descriptor),
378 rdm_descdhd_msk, rdm_descdhd_shift);
379}
380
381void rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len, u32 descriptor)
382{
383 aq_hw_write_reg_bit(aq_hw, rdm_descdlen_adr(descriptor),
384 rdm_descdlen_msk, rdm_descdlen_shift,
385 rx_desc_len);
386}
387
388void rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res, u32 descriptor)
389{
390 aq_hw_write_reg_bit(aq_hw, rdm_descdreset_adr(descriptor),
391 rdm_descdreset_msk, rdm_descdreset_shift,
392 rx_desc_res);
393}
394
395void rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
396 u32 rx_desc_wr_wb_irq_en)
397{
398 aq_hw_write_reg_bit(aq_hw, rdm_int_desc_wrb_en_adr,
399 rdm_int_desc_wrb_en_msk,
400 rdm_int_desc_wrb_en_shift,
401 rx_desc_wr_wb_irq_en);
402}
403
404void rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en, u32 dca)
405{
406 aq_hw_write_reg_bit(aq_hw, rdm_dcadhdr_en_adr(dca),
407 rdm_dcadhdr_en_msk,
408 rdm_dcadhdr_en_shift,
409 rx_head_dca_en);
410}
411
412void rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, u32 dca)
413{
414 aq_hw_write_reg_bit(aq_hw, rdm_dcadpay_en_adr(dca),
415 rdm_dcadpay_en_msk, rdm_dcadpay_en_shift,
416 rx_pld_dca_en);
417}
418
419void rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, u32 rdm_intr_moder_en)
420{
421 aq_hw_write_reg_bit(aq_hw, rdm_int_rim_en_adr,
422 rdm_int_rim_en_msk,
423 rdm_int_rim_en_shift,
424 rdm_intr_moder_en);
425}
426
427/* reg */
428void reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map, u32 regidx)
429{
430 aq_hw_write_reg(aq_hw, gen_intr_map_adr(regidx), gen_intr_map);
431}
432
433u32 reg_gen_irq_status_get(struct aq_hw_s *aq_hw)
434{
435 return aq_hw_read_reg(aq_hw, gen_intr_stat_adr);
436}
437
438void reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl)
439{
440 aq_hw_write_reg(aq_hw, intr_glb_ctl_adr, intr_glb_ctl);
441}
442
443void reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle)
444{
445 aq_hw_write_reg(aq_hw, intr_thr_adr(throttle), intr_thr);
446}
447
448void reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
449 u32 rx_dma_desc_base_addrlsw,
450 u32 descriptor)
451{
452 aq_hw_write_reg(aq_hw, rx_dma_desc_base_addrlsw_adr(descriptor),
453 rx_dma_desc_base_addrlsw);
454}
455
456void reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
457 u32 rx_dma_desc_base_addrmsw,
458 u32 descriptor)
459{
460 aq_hw_write_reg(aq_hw, rx_dma_desc_base_addrmsw_adr(descriptor),
461 rx_dma_desc_base_addrmsw);
462}
463
464u32 reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor)
465{
466 return aq_hw_read_reg(aq_hw, rx_dma_desc_stat_adr(descriptor));
467}
468
469void reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
470 u32 rx_dma_desc_tail_ptr, u32 descriptor)
471{
472 aq_hw_write_reg(aq_hw, rx_dma_desc_tail_ptr_adr(descriptor),
473 rx_dma_desc_tail_ptr);
474}
475
476void reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr_msk)
477{
478 aq_hw_write_reg(aq_hw, rx_flr_mcst_flr_msk_adr, rx_flr_mcst_flr_msk);
479}
480
481void reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
482 u32 filter)
483{
484 aq_hw_write_reg(aq_hw, rx_flr_mcst_flr_adr(filter), rx_flr_mcst_flr);
485}
486
487void reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw, u32 rx_flr_rss_control1)
488{
489 aq_hw_write_reg(aq_hw, rx_flr_rss_control1_adr, rx_flr_rss_control1);
490}
491
492void reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_filter_control2)
493{
494 aq_hw_write_reg(aq_hw, rx_flr_control2_adr, rx_filter_control2);
495}
496
497void reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
498 u32 rx_intr_moderation_ctl,
499 u32 queue)
500{
501 aq_hw_write_reg(aq_hw, rx_intr_moderation_ctl_adr(queue),
502 rx_intr_moderation_ctl);
503}
504
505void reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw, u32 tx_dma_debug_ctl)
506{
507 aq_hw_write_reg(aq_hw, tx_dma_debug_ctl_adr, tx_dma_debug_ctl);
508}
509
510void reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
511 u32 tx_dma_desc_base_addrlsw,
512 u32 descriptor)
513{
514 aq_hw_write_reg(aq_hw, tx_dma_desc_base_addrlsw_adr(descriptor),
515 tx_dma_desc_base_addrlsw);
516}
517
518void reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
519 u32 tx_dma_desc_base_addrmsw,
520 u32 descriptor)
521{
522 aq_hw_write_reg(aq_hw, tx_dma_desc_base_addrmsw_adr(descriptor),
523 tx_dma_desc_base_addrmsw);
524}
525
526void reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
527 u32 tx_dma_desc_tail_ptr, u32 descriptor)
528{
529 aq_hw_write_reg(aq_hw, tx_dma_desc_tail_ptr_adr(descriptor),
530 tx_dma_desc_tail_ptr);
531}
532
533void reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
534 u32 tx_intr_moderation_ctl,
535 u32 queue)
536{
537 aq_hw_write_reg(aq_hw, tx_intr_moderation_ctl_adr(queue),
538 tx_intr_moderation_ctl);
539}
540
541/* RPB: rx packet buffer */
542void rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk)
543{
544 aq_hw_write_reg_bit(aq_hw, rpb_dma_sys_lbk_adr,
545 rpb_dma_sys_lbk_msk,
546 rpb_dma_sys_lbk_shift, dma_sys_lbk);
547}
548
549void rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
550 u32 rx_traf_class_mode)
551{
552 aq_hw_write_reg_bit(aq_hw, rpb_rpf_rx_tc_mode_adr,
553 rpb_rpf_rx_tc_mode_msk,
554 rpb_rpf_rx_tc_mode_shift,
555 rx_traf_class_mode);
556}
557
558void rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en)
559{
560 aq_hw_write_reg_bit(aq_hw, rpb_rx_buf_en_adr, rpb_rx_buf_en_msk,
561 rpb_rx_buf_en_shift, rx_buff_en);
562}
563
564void rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
565 u32 rx_buff_hi_threshold_per_tc,
566 u32 buffer)
567{
568 aq_hw_write_reg_bit(aq_hw, rpb_rxbhi_thresh_adr(buffer),
569 rpb_rxbhi_thresh_msk, rpb_rxbhi_thresh_shift,
570 rx_buff_hi_threshold_per_tc);
571}
572
573void rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
574 u32 rx_buff_lo_threshold_per_tc,
575 u32 buffer)
576{
577 aq_hw_write_reg_bit(aq_hw, rpb_rxblo_thresh_adr(buffer),
578 rpb_rxblo_thresh_msk,
579 rpb_rxblo_thresh_shift,
580 rx_buff_lo_threshold_per_tc);
581}
582
583void rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode)
584{
585 aq_hw_write_reg_bit(aq_hw, rpb_rx_fc_mode_adr,
586 rpb_rx_fc_mode_msk,
587 rpb_rx_fc_mode_shift, rx_flow_ctl_mode);
588}
589
590void rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
591 u32 rx_pkt_buff_size_per_tc, u32 buffer)
592{
593 aq_hw_write_reg_bit(aq_hw, rpb_rxbbuf_size_adr(buffer),
594 rpb_rxbbuf_size_msk, rpb_rxbbuf_size_shift,
595 rx_pkt_buff_size_per_tc);
596}
597
598void rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
599 u32 buffer)
600{
601 aq_hw_write_reg_bit(aq_hw, rpb_rxbxoff_en_adr(buffer),
602 rpb_rxbxoff_en_msk, rpb_rxbxoff_en_shift,
603 rx_xoff_en_per_tc);
604}
605
606/* rpf */
607
608void rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
609 u32 l2broadcast_count_threshold)
610{
611 aq_hw_write_reg_bit(aq_hw, rpfl2bc_thresh_adr,
612 rpfl2bc_thresh_msk,
613 rpfl2bc_thresh_shift,
614 l2broadcast_count_threshold);
615}
616
617void rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en)
618{
619 aq_hw_write_reg_bit(aq_hw, rpfl2bc_en_adr, rpfl2bc_en_msk,
620 rpfl2bc_en_shift, l2broadcast_en);
621}
622
623void rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw, u32 l2broadcast_flr_act)
624{
625 aq_hw_write_reg_bit(aq_hw, rpfl2bc_act_adr, rpfl2bc_act_msk,
626 rpfl2bc_act_shift, l2broadcast_flr_act);
627}
628
629void rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, u32 l2multicast_flr_en,
630 u32 filter)
631{
632 aq_hw_write_reg_bit(aq_hw, rpfl2mc_enf_adr(filter),
633 rpfl2mc_enf_msk,
634 rpfl2mc_enf_shift, l2multicast_flr_en);
635}
636
637void rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
638 u32 l2promiscuous_mode_en)
639{
640 aq_hw_write_reg_bit(aq_hw, rpfl2promis_mode_adr,
641 rpfl2promis_mode_msk,
642 rpfl2promis_mode_shift,
643 l2promiscuous_mode_en);
644}
645
646void rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_act,
647 u32 filter)
648{
649 aq_hw_write_reg_bit(aq_hw, rpfl2uc_actf_adr(filter),
650 rpfl2uc_actf_msk, rpfl2uc_actf_shift,
651 l2unicast_flr_act);
652}
653
654void rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
655 u32 filter)
656{
657 aq_hw_write_reg_bit(aq_hw, rpfl2uc_enf_adr(filter),
658 rpfl2uc_enf_msk,
659 rpfl2uc_enf_shift, l2unicast_flr_en);
660}
661
662void rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
663 u32 l2unicast_dest_addresslsw,
664 u32 filter)
665{
666 aq_hw_write_reg(aq_hw, rpfl2uc_daflsw_adr(filter),
667 l2unicast_dest_addresslsw);
668}
669
670void rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
671 u32 l2unicast_dest_addressmsw,
672 u32 filter)
673{
674 aq_hw_write_reg_bit(aq_hw, rpfl2uc_dafmsw_adr(filter),
675 rpfl2uc_dafmsw_msk, rpfl2uc_dafmsw_shift,
676 l2unicast_dest_addressmsw);
677}
678
679void rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
680 u32 l2_accept_all_mc_packets)
681{
682 aq_hw_write_reg_bit(aq_hw, rpfl2mc_accept_all_adr,
683 rpfl2mc_accept_all_msk,
684 rpfl2mc_accept_all_shift,
685 l2_accept_all_mc_packets);
686}
687
688void rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
689 u32 user_priority_tc_map, u32 tc)
690{
691/* register address for bitfield rx_tc_up{t}[2:0] */
692 static u32 rpf_rpb_rx_tc_upt_adr[8] = {
693 0x000054c4U, 0x000054c4U, 0x000054c4U, 0x000054c4U,
694 0x000054c4U, 0x000054c4U, 0x000054c4U, 0x000054c4U
695 };
696
697/* bitmask for bitfield rx_tc_up{t}[2:0] */
698 static u32 rpf_rpb_rx_tc_upt_msk[8] = {
699 0x00000007U, 0x00000070U, 0x00000700U, 0x00007000U,
700 0x00070000U, 0x00700000U, 0x07000000U, 0x70000000U
701 };
702
703/* lower bit position of bitfield rx_tc_up{t}[2:0] */
704 static u32 rpf_rpb_rx_tc_upt_shft[8] = {
705 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
706 };
707
708 aq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[tc],
709 rpf_rpb_rx_tc_upt_msk[tc],
710 rpf_rpb_rx_tc_upt_shft[tc],
711 user_priority_tc_map);
712}
713
714void rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr)
715{
716 aq_hw_write_reg_bit(aq_hw, rpf_rss_key_addr_adr,
717 rpf_rss_key_addr_msk,
718 rpf_rss_key_addr_shift,
719 rss_key_addr);
720}
721
722void rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data)
723{
724 aq_hw_write_reg(aq_hw, rpf_rss_key_wr_data_adr,
725 rss_key_wr_data);
726}
727
728u32 rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw)
729{
730 return aq_hw_read_reg_bit(aq_hw, rpf_rss_key_wr_eni_adr,
731 rpf_rss_key_wr_eni_msk,
732 rpf_rss_key_wr_eni_shift);
733}
734
735void rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en)
736{
737 aq_hw_write_reg_bit(aq_hw, rpf_rss_key_wr_eni_adr,
738 rpf_rss_key_wr_eni_msk,
739 rpf_rss_key_wr_eni_shift,
740 rss_key_wr_en);
741}
742
743void rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw, u32 rss_redir_tbl_addr)
744{
745 aq_hw_write_reg_bit(aq_hw, rpf_rss_redir_addr_adr,
746 rpf_rss_redir_addr_msk,
747 rpf_rss_redir_addr_shift, rss_redir_tbl_addr);
748}
749
750void rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
751 u32 rss_redir_tbl_wr_data)
752{
753 aq_hw_write_reg_bit(aq_hw, rpf_rss_redir_wr_data_adr,
754 rpf_rss_redir_wr_data_msk,
755 rpf_rss_redir_wr_data_shift,
756 rss_redir_tbl_wr_data);
757}
758
759u32 rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw)
760{
761 return aq_hw_read_reg_bit(aq_hw, rpf_rss_redir_wr_eni_adr,
762 rpf_rss_redir_wr_eni_msk,
763 rpf_rss_redir_wr_eni_shift);
764}
765
766void rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en)
767{
768 aq_hw_write_reg_bit(aq_hw, rpf_rss_redir_wr_eni_adr,
769 rpf_rss_redir_wr_eni_msk,
770 rpf_rss_redir_wr_eni_shift, rss_redir_wr_en);
771}
772
773void rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw, u32 tpo_to_rpf_sys_lbk)
774{
775 aq_hw_write_reg_bit(aq_hw, rpf_tpo_rpf_sys_lbk_adr,
776 rpf_tpo_rpf_sys_lbk_msk,
777 rpf_tpo_rpf_sys_lbk_shift,
778 tpo_to_rpf_sys_lbk);
779}
780
781void rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht)
782{
783 aq_hw_write_reg_bit(aq_hw, rpf_vl_inner_tpid_adr,
784 rpf_vl_inner_tpid_msk,
785 rpf_vl_inner_tpid_shift,
786 vlan_inner_etht);
787}
788
789void rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht)
790{
791 aq_hw_write_reg_bit(aq_hw, rpf_vl_outer_tpid_adr,
792 rpf_vl_outer_tpid_msk,
793 rpf_vl_outer_tpid_shift,
794 vlan_outer_etht);
795}
796
797void rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, u32 vlan_prom_mode_en)
798{
799 aq_hw_write_reg_bit(aq_hw, rpf_vl_promis_mode_adr,
800 rpf_vl_promis_mode_msk,
801 rpf_vl_promis_mode_shift,
802 vlan_prom_mode_en);
803}
804
805void rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
806 u32 vlan_accept_untagged_packets)
807{
808 aq_hw_write_reg_bit(aq_hw, rpf_vl_accept_untagged_mode_adr,
809 rpf_vl_accept_untagged_mode_msk,
810 rpf_vl_accept_untagged_mode_shift,
811 vlan_accept_untagged_packets);
812}
813
814void rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, u32 vlan_untagged_act)
815{
816 aq_hw_write_reg_bit(aq_hw, rpf_vl_untagged_act_adr,
817 rpf_vl_untagged_act_msk,
818 rpf_vl_untagged_act_shift,
819 vlan_untagged_act);
820}
821
822void rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en, u32 filter)
823{
824 aq_hw_write_reg_bit(aq_hw, rpf_vl_en_f_adr(filter),
825 rpf_vl_en_f_msk,
826 rpf_vl_en_f_shift,
827 vlan_flr_en);
828}
829
830void rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act, u32 filter)
831{
832 aq_hw_write_reg_bit(aq_hw, rpf_vl_act_f_adr(filter),
833 rpf_vl_act_f_msk,
834 rpf_vl_act_f_shift,
835 vlan_flr_act);
836}
837
838void rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, u32 filter)
839{
840 aq_hw_write_reg_bit(aq_hw, rpf_vl_id_f_adr(filter),
841 rpf_vl_id_f_msk,
842 rpf_vl_id_f_shift,
843 vlan_id_flr);
844}
845
846void rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en, u32 filter)
847{
848 aq_hw_write_reg_bit(aq_hw, rpf_et_enf_adr(filter),
849 rpf_et_enf_msk,
850 rpf_et_enf_shift, etht_flr_en);
851}
852
853void rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
854 u32 etht_user_priority_en, u32 filter)
855{
856 aq_hw_write_reg_bit(aq_hw, rpf_et_upfen_adr(filter),
857 rpf_et_upfen_msk, rpf_et_upfen_shift,
858 etht_user_priority_en);
859}
860
861void rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue_en,
862 u32 filter)
863{
864 aq_hw_write_reg_bit(aq_hw, rpf_et_rxqfen_adr(filter),
865 rpf_et_rxqfen_msk, rpf_et_rxqfen_shift,
866 etht_rx_queue_en);
867}
868
869void rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, u32 etht_user_priority,
870 u32 filter)
871{
872 aq_hw_write_reg_bit(aq_hw, rpf_et_upf_adr(filter),
873 rpf_et_upf_msk,
874 rpf_et_upf_shift, etht_user_priority);
875}
876
877void rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
878 u32 filter)
879{
880 aq_hw_write_reg_bit(aq_hw, rpf_et_rxqf_adr(filter),
881 rpf_et_rxqf_msk,
882 rpf_et_rxqf_shift, etht_rx_queue);
883}
884
885void rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
886 u32 filter)
887{
888 aq_hw_write_reg_bit(aq_hw, rpf_et_mng_rxqf_adr(filter),
889 rpf_et_mng_rxqf_msk, rpf_et_mng_rxqf_shift,
890 etht_mgt_queue);
891}
892
893void rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act, u32 filter)
894{
895 aq_hw_write_reg_bit(aq_hw, rpf_et_actf_adr(filter),
896 rpf_et_actf_msk,
897 rpf_et_actf_shift, etht_flr_act);
898}
899
900void rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter)
901{
902 aq_hw_write_reg_bit(aq_hw, rpf_et_valf_adr(filter),
903 rpf_et_valf_msk,
904 rpf_et_valf_shift, etht_flr);
905}
906
907/* RPO: rx packet offload */
908void rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
909 u32 ipv4header_crc_offload_en)
910{
911 aq_hw_write_reg_bit(aq_hw, rpo_ipv4chk_en_adr,
912 rpo_ipv4chk_en_msk,
913 rpo_ipv4chk_en_shift,
914 ipv4header_crc_offload_en);
915}
916
917void rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
918 u32 rx_desc_vlan_stripping, u32 descriptor)
919{
920 aq_hw_write_reg_bit(aq_hw, rpo_descdvl_strip_adr(descriptor),
921 rpo_descdvl_strip_msk,
922 rpo_descdvl_strip_shift,
923 rx_desc_vlan_stripping);
924}
925
926void rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
927 u32 tcp_udp_crc_offload_en)
928{
929 aq_hw_write_reg_bit(aq_hw, rpol4chk_en_adr, rpol4chk_en_msk,
930 rpol4chk_en_shift, tcp_udp_crc_offload_en);
931}
932
933void rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en)
934{
935 aq_hw_write_reg(aq_hw, rpo_lro_en_adr, lro_en);
936}
937
938void rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
939 u32 lro_patch_optimization_en)
940{
941 aq_hw_write_reg_bit(aq_hw, rpo_lro_ptopt_en_adr,
942 rpo_lro_ptopt_en_msk,
943 rpo_lro_ptopt_en_shift,
944 lro_patch_optimization_en);
945}
946
947void rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
948 u32 lro_qsessions_lim)
949{
950 aq_hw_write_reg_bit(aq_hw, rpo_lro_qses_lmt_adr,
951 rpo_lro_qses_lmt_msk,
952 rpo_lro_qses_lmt_shift,
953 lro_qsessions_lim);
954}
955
956void rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw, u32 lro_total_desc_lim)
957{
958 aq_hw_write_reg_bit(aq_hw, rpo_lro_tot_dsc_lmt_adr,
959 rpo_lro_tot_dsc_lmt_msk,
960 rpo_lro_tot_dsc_lmt_shift,
961 lro_total_desc_lim);
962}
963
964void rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
965 u32 lro_min_pld_of_first_pkt)
966{
967 aq_hw_write_reg_bit(aq_hw, rpo_lro_pkt_min_adr,
968 rpo_lro_pkt_min_msk,
969 rpo_lro_pkt_min_shift,
970 lro_min_pld_of_first_pkt);
971}
972
973void rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim)
974{
975 aq_hw_write_reg(aq_hw, rpo_lro_rsc_max_adr, lro_pkt_lim);
976}
977
978void rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
979 u32 lro_max_number_of_descriptors,
980 u32 lro)
981{
982/* Register address for bitfield lro{L}_des_max[1:0] */
983 static u32 rpo_lro_ldes_max_adr[32] = {
984 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
985 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
986 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
987 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
988 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
989 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
990 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU,
991 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU
992 };
993
994/* Bitmask for bitfield lro{L}_des_max[1:0] */
995 static u32 rpo_lro_ldes_max_msk[32] = {
996 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
997 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
998 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
999 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1000 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1001 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1002 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1003 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U
1004 };
1005
1006/* Lower bit position of bitfield lro{L}_des_max[1:0] */
1007 static u32 rpo_lro_ldes_max_shift[32] = {
1008 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1009 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1010 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1011 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
1012 };
1013
1014 aq_hw_write_reg_bit(aq_hw, rpo_lro_ldes_max_adr[lro],
1015 rpo_lro_ldes_max_msk[lro],
1016 rpo_lro_ldes_max_shift[lro],
1017 lro_max_number_of_descriptors);
1018}
1019
1020void rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
1021 u32 lro_time_base_divider)
1022{
1023 aq_hw_write_reg_bit(aq_hw, rpo_lro_tb_div_adr,
1024 rpo_lro_tb_div_msk,
1025 rpo_lro_tb_div_shift,
1026 lro_time_base_divider);
1027}
1028
1029void rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
1030 u32 lro_inactive_interval)
1031{
1032 aq_hw_write_reg_bit(aq_hw, rpo_lro_ina_ival_adr,
1033 rpo_lro_ina_ival_msk,
1034 rpo_lro_ina_ival_shift,
1035 lro_inactive_interval);
1036}
1037
1038void rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
1039 u32 lro_max_coalescing_interval)
1040{
1041 aq_hw_write_reg_bit(aq_hw, rpo_lro_max_ival_adr,
1042 rpo_lro_max_ival_msk,
1043 rpo_lro_max_ival_shift,
1044 lro_max_coalescing_interval);
1045}
1046
1047/* rx */
1048void rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis)
1049{
1050 aq_hw_write_reg_bit(aq_hw, rx_reg_res_dsbl_adr,
1051 rx_reg_res_dsbl_msk,
1052 rx_reg_res_dsbl_shift,
1053 rx_reg_res_dis);
1054}
1055
1056/* tdm */
1057void tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
1058{
1059 aq_hw_write_reg_bit(aq_hw, tdm_dcadcpuid_adr(dca),
1060 tdm_dcadcpuid_msk,
1061 tdm_dcadcpuid_shift, cpuid);
1062}
1063
1064void tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
1065 u32 large_send_offload_en)
1066{
1067 aq_hw_write_reg(aq_hw, tdm_lso_en_adr, large_send_offload_en);
1068}
1069
1070void tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en)
1071{
1072 aq_hw_write_reg_bit(aq_hw, tdm_dca_en_adr, tdm_dca_en_msk,
1073 tdm_dca_en_shift, tx_dca_en);
1074}
1075
1076void tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode)
1077{
1078 aq_hw_write_reg_bit(aq_hw, tdm_dca_mode_adr, tdm_dca_mode_msk,
1079 tdm_dca_mode_shift, tx_dca_mode);
1080}
1081
1082void tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en, u32 dca)
1083{
1084 aq_hw_write_reg_bit(aq_hw, tdm_dcaddesc_en_adr(dca),
1085 tdm_dcaddesc_en_msk, tdm_dcaddesc_en_shift,
1086 tx_desc_dca_en);
1087}
1088
1089void tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en, u32 descriptor)
1090{
1091 aq_hw_write_reg_bit(aq_hw, tdm_descden_adr(descriptor),
1092 tdm_descden_msk,
1093 tdm_descden_shift,
1094 tx_desc_en);
1095}
1096
1097u32 tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
1098{
1099 return aq_hw_read_reg_bit(aq_hw, tdm_descdhd_adr(descriptor),
1100 tdm_descdhd_msk, tdm_descdhd_shift);
1101}
1102
1103void tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
1104 u32 descriptor)
1105{
1106 aq_hw_write_reg_bit(aq_hw, tdm_descdlen_adr(descriptor),
1107 tdm_descdlen_msk,
1108 tdm_descdlen_shift,
1109 tx_desc_len);
1110}
1111
1112void tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
1113 u32 tx_desc_wr_wb_irq_en)
1114{
1115 aq_hw_write_reg_bit(aq_hw, tdm_int_desc_wrb_en_adr,
1116 tdm_int_desc_wrb_en_msk,
1117 tdm_int_desc_wrb_en_shift,
1118 tx_desc_wr_wb_irq_en);
1119}
1120
1121void tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
1122 u32 tx_desc_wr_wb_threshold,
1123 u32 descriptor)
1124{
1125 aq_hw_write_reg_bit(aq_hw, tdm_descdwrb_thresh_adr(descriptor),
1126 tdm_descdwrb_thresh_msk,
1127 tdm_descdwrb_thresh_shift,
1128 tx_desc_wr_wb_threshold);
1129}
1130
1131void tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
1132 u32 tdm_irq_moderation_en)
1133{
1134 aq_hw_write_reg_bit(aq_hw, tdm_int_mod_en_adr,
1135 tdm_int_mod_en_msk,
1136 tdm_int_mod_en_shift,
1137 tdm_irq_moderation_en);
1138}
1139
1140/* thm */
1141void thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
1142 u32 lso_tcp_flag_of_first_pkt)
1143{
1144 aq_hw_write_reg_bit(aq_hw, thm_lso_tcp_flag_first_adr,
1145 thm_lso_tcp_flag_first_msk,
1146 thm_lso_tcp_flag_first_shift,
1147 lso_tcp_flag_of_first_pkt);
1148}
1149
1150void thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
1151 u32 lso_tcp_flag_of_last_pkt)
1152{
1153 aq_hw_write_reg_bit(aq_hw, thm_lso_tcp_flag_last_adr,
1154 thm_lso_tcp_flag_last_msk,
1155 thm_lso_tcp_flag_last_shift,
1156 lso_tcp_flag_of_last_pkt);
1157}
1158
1159void thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
1160 u32 lso_tcp_flag_of_middle_pkt)
1161{
1162 aq_hw_write_reg_bit(aq_hw, thm_lso_tcp_flag_mid_adr,
1163 thm_lso_tcp_flag_mid_msk,
1164 thm_lso_tcp_flag_mid_shift,
1165 lso_tcp_flag_of_middle_pkt);
1166}
1167
1168/* TPB: tx packet buffer */
1169void tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en)
1170{
1171 aq_hw_write_reg_bit(aq_hw, tpb_tx_buf_en_adr, tpb_tx_buf_en_msk,
1172 tpb_tx_buf_en_shift, tx_buff_en);
1173}
1174
1175void tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1176 u32 tx_buff_hi_threshold_per_tc,
1177 u32 buffer)
1178{
1179 aq_hw_write_reg_bit(aq_hw, tpb_txbhi_thresh_adr(buffer),
1180 tpb_txbhi_thresh_msk, tpb_txbhi_thresh_shift,
1181 tx_buff_hi_threshold_per_tc);
1182}
1183
1184void tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1185 u32 tx_buff_lo_threshold_per_tc,
1186 u32 buffer)
1187{
1188 aq_hw_write_reg_bit(aq_hw, tpb_txblo_thresh_adr(buffer),
1189 tpb_txblo_thresh_msk, tpb_txblo_thresh_shift,
1190 tx_buff_lo_threshold_per_tc);
1191}
1192
1193void tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en)
1194{
1195 aq_hw_write_reg_bit(aq_hw, tpb_dma_sys_lbk_adr,
1196 tpb_dma_sys_lbk_msk,
1197 tpb_dma_sys_lbk_shift,
1198 tx_dma_sys_lbk_en);
1199}
1200
1201void tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
1202 u32 tx_pkt_buff_size_per_tc, u32 buffer)
1203{
1204 aq_hw_write_reg_bit(aq_hw, tpb_txbbuf_size_adr(buffer),
1205 tpb_txbbuf_size_msk,
1206 tpb_txbbuf_size_shift,
1207 tx_pkt_buff_size_per_tc);
1208}
1209
1210void tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en)
1211{
1212 aq_hw_write_reg_bit(aq_hw, tpb_tx_scp_ins_en_adr,
1213 tpb_tx_scp_ins_en_msk,
1214 tpb_tx_scp_ins_en_shift,
1215 tx_path_scp_ins_en);
1216}
1217
1218/* TPO: tx packet offload */
1219void tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
1220 u32 ipv4header_crc_offload_en)
1221{
1222 aq_hw_write_reg_bit(aq_hw, tpo_ipv4chk_en_adr,
1223 tpo_ipv4chk_en_msk,
1224 tpo_ipv4chk_en_shift,
1225 ipv4header_crc_offload_en);
1226}
1227
1228void tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
1229 u32 tcp_udp_crc_offload_en)
1230{
1231 aq_hw_write_reg_bit(aq_hw, tpol4chk_en_adr,
1232 tpol4chk_en_msk,
1233 tpol4chk_en_shift,
1234 tcp_udp_crc_offload_en);
1235}
1236
1237void tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_pkt_sys_lbk_en)
1238{
1239 aq_hw_write_reg_bit(aq_hw, tpo_pkt_sys_lbk_adr,
1240 tpo_pkt_sys_lbk_msk,
1241 tpo_pkt_sys_lbk_shift,
1242 tx_pkt_sys_lbk_en);
1243}
1244
1245/* TPS: tx packet scheduler */
1246void tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
1247 u32 tx_pkt_shed_data_arb_mode)
1248{
1249 aq_hw_write_reg_bit(aq_hw, tps_data_tc_arb_mode_adr,
1250 tps_data_tc_arb_mode_msk,
1251 tps_data_tc_arb_mode_shift,
1252 tx_pkt_shed_data_arb_mode);
1253}
1254
1255void tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
1256 u32 curr_time_res)
1257{
1258 aq_hw_write_reg_bit(aq_hw, tps_desc_rate_ta_rst_adr,
1259 tps_desc_rate_ta_rst_msk,
1260 tps_desc_rate_ta_rst_shift,
1261 curr_time_res);
1262}
1263
1264void tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
1265 u32 tx_pkt_shed_desc_rate_lim)
1266{
1267 aq_hw_write_reg_bit(aq_hw, tps_desc_rate_lim_adr,
1268 tps_desc_rate_lim_msk,
1269 tps_desc_rate_lim_shift,
1270 tx_pkt_shed_desc_rate_lim);
1271}
1272
1273void tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
1274 u32 tx_pkt_shed_desc_tc_arb_mode)
1275{
1276 aq_hw_write_reg_bit(aq_hw, tps_desc_tc_arb_mode_adr,
1277 tps_desc_tc_arb_mode_msk,
1278 tps_desc_tc_arb_mode_shift,
1279 tx_pkt_shed_desc_tc_arb_mode);
1280}
1281
1282void tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
1283 u32 tx_pkt_shed_desc_tc_max_credit,
1284 u32 tc)
1285{
1286 aq_hw_write_reg_bit(aq_hw, tps_desc_tctcredit_max_adr(tc),
1287 tps_desc_tctcredit_max_msk,
1288 tps_desc_tctcredit_max_shift,
1289 tx_pkt_shed_desc_tc_max_credit);
1290}
1291
1292void tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
1293 u32 tx_pkt_shed_desc_tc_weight, u32 tc)
1294{
1295 aq_hw_write_reg_bit(aq_hw, tps_desc_tctweight_adr(tc),
1296 tps_desc_tctweight_msk,
1297 tps_desc_tctweight_shift,
1298 tx_pkt_shed_desc_tc_weight);
1299}
1300
1301void tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
1302 u32 tx_pkt_shed_desc_vm_arb_mode)
1303{
1304 aq_hw_write_reg_bit(aq_hw, tps_desc_vm_arb_mode_adr,
1305 tps_desc_vm_arb_mode_msk,
1306 tps_desc_vm_arb_mode_shift,
1307 tx_pkt_shed_desc_vm_arb_mode);
1308}
1309
1310void tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
1311 u32 tx_pkt_shed_tc_data_max_credit,
1312 u32 tc)
1313{
1314 aq_hw_write_reg_bit(aq_hw, tps_data_tctcredit_max_adr(tc),
1315 tps_data_tctcredit_max_msk,
1316 tps_data_tctcredit_max_shift,
1317 tx_pkt_shed_tc_data_max_credit);
1318}
1319
1320void tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
1321 u32 tx_pkt_shed_tc_data_weight, u32 tc)
1322{
1323 aq_hw_write_reg_bit(aq_hw, tps_data_tctweight_adr(tc),
1324 tps_data_tctweight_msk,
1325 tps_data_tctweight_shift,
1326 tx_pkt_shed_tc_data_weight);
1327}
1328
1329/* tx */
1330void tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis)
1331{
1332 aq_hw_write_reg_bit(aq_hw, tx_reg_res_dsbl_adr,
1333 tx_reg_res_dsbl_msk,
1334 tx_reg_res_dsbl_shift, tx_reg_res_dis);
1335}
1336
1337/* msm */
1338u32 msm_reg_access_status_get(struct aq_hw_s *aq_hw)
1339{
1340 return aq_hw_read_reg_bit(aq_hw, msm_reg_access_busy_adr,
1341 msm_reg_access_busy_msk,
1342 msm_reg_access_busy_shift);
1343}
1344
1345void msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
1346 u32 reg_addr_for_indirect_addr)
1347{
1348 aq_hw_write_reg_bit(aq_hw, msm_reg_addr_adr,
1349 msm_reg_addr_msk,
1350 msm_reg_addr_shift,
1351 reg_addr_for_indirect_addr);
1352}
1353
1354void msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe)
1355{
1356 aq_hw_write_reg_bit(aq_hw, msm_reg_rd_strobe_adr,
1357 msm_reg_rd_strobe_msk,
1358 msm_reg_rd_strobe_shift,
1359 reg_rd_strobe);
1360}
1361
1362u32 msm_reg_rd_data_get(struct aq_hw_s *aq_hw)
1363{
1364 return aq_hw_read_reg(aq_hw, msm_reg_rd_data_adr);
1365}
1366
1367void msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data)
1368{
1369 aq_hw_write_reg(aq_hw, msm_reg_wr_data_adr, reg_wr_data);
1370}
1371
1372void msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe)
1373{
1374 aq_hw_write_reg_bit(aq_hw, msm_reg_wr_strobe_adr,
1375 msm_reg_wr_strobe_msk,
1376 msm_reg_wr_strobe_shift,
1377 reg_wr_strobe);
1378}
1379
1380/* pci */
1381void pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis)
1382{
1383 aq_hw_write_reg_bit(aq_hw, pci_reg_res_dsbl_adr,
1384 pci_reg_res_dsbl_msk,
1385 pci_reg_res_dsbl_shift,
1386 pci_reg_res_dis);
1387}
1388
1389void reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw, u32 glb_cpu_scratch_scp,
1390 u32 scratch_scp)
1391{
1392 aq_hw_write_reg(aq_hw, glb_cpu_scratch_scp_adr(scratch_scp),
1393 glb_cpu_scratch_scp);
1394}
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h
new file mode 100644
index 000000000000..ed1085b95adb
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h
@@ -0,0 +1,677 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File hw_atl_llh.h: Declarations of bitfield and register access functions for
11 * Atlantic registers.
12 */
13
14#ifndef HW_ATL_LLH_H
15#define HW_ATL_LLH_H
16
17#include <linux/types.h>
18
19struct aq_hw_s;
20
21/* global */
22
23/* set global microprocessor semaphore */
24void reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem,
25 u32 semaphore);
26
27/* get global microprocessor semaphore */
28u32 reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore);
29
30/* set global register reset disable */
31void glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis);
32
33/* set soft reset */
34void glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res);
35
36/* get soft reset */
37u32 glb_soft_res_get(struct aq_hw_s *aq_hw);
38
39/* stats */
40
41u32 rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw);
42
43/* get rx dma good octet counter lsw */
44u32 stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
45
46/* get rx dma good packet counter lsw */
47u32 stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
48
49/* get tx dma good octet counter lsw */
50u32 stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);
51
52/* get tx dma good packet counter lsw */
53u32 stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);
54
55/* get rx dma good octet counter msw */
56u32 stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
57
58/* get rx dma good packet counter msw */
59u32 stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
60
61/* get tx dma good octet counter msw */
62u32 stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);
63
64/* get tx dma good packet counter msw */
65u32 stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);
66
67/* get msm rx errors counter register */
68u32 reg_mac_msm_rx_errs_cnt_get(struct aq_hw_s *aq_hw);
69
70/* get msm rx unicast frames counter register */
71u32 reg_mac_msm_rx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);
72
73/* get msm rx multicast frames counter register */
74u32 reg_mac_msm_rx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);
75
76/* get msm rx broadcast frames counter register */
77u32 reg_mac_msm_rx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);
78
79/* get msm rx broadcast octets counter register 1 */
80u32 reg_mac_msm_rx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);
81
82/* get msm rx unicast octets counter register 0 */
83u32 reg_mac_msm_rx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);
84
85/* get rx dma statistics counter 7 */
86u32 reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw);
87
88/* get msm tx errors counter register */
89u32 reg_mac_msm_tx_errs_cnt_get(struct aq_hw_s *aq_hw);
90
91/* get msm tx unicast frames counter register */
92u32 reg_mac_msm_tx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);
93
94/* get msm tx multicast frames counter register */
95u32 reg_mac_msm_tx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);
96
97/* get msm tx broadcast frames counter register */
98u32 reg_mac_msm_tx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);
99
100/* get msm tx multicast octets counter register 1 */
101u32 reg_mac_msm_tx_mcst_octets_counter1get(struct aq_hw_s *aq_hw);
102
103/* get msm tx broadcast octets counter register 1 */
104u32 reg_mac_msm_tx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);
105
106/* get msm tx unicast octets counter register 0 */
107u32 reg_mac_msm_tx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);
108
109/* get global mif identification */
110u32 reg_glb_mif_id_get(struct aq_hw_s *aq_hw);
111
112/* interrupt */
113
114/* set interrupt auto mask lsw */
115void itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw, u32 irq_auto_masklsw);
116
117/* set interrupt mapping enable rx */
118void itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, u32 rx);
119
120/* set interrupt mapping enable tx */
121void itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, u32 tx);
122
123/* set interrupt mapping rx */
124void itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx);
125
126/* set interrupt mapping tx */
127void itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx);
128
129/* set interrupt mask clear lsw */
130void itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_clearlsw);
131
132/* set interrupt mask set lsw */
133void itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw);
134
135/* set interrupt register reset disable */
136void itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis);
137
138/* set interrupt status clear lsw */
139void itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
140 u32 irq_status_clearlsw);
141
142/* get interrupt status lsw */
143u32 itr_irq_statuslsw_get(struct aq_hw_s *aq_hw);
144
145/* get reset interrupt */
146u32 itr_res_irq_get(struct aq_hw_s *aq_hw);
147
148/* set reset interrupt */
149void itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq);
150
151/* rdm */
152
153/* set cpu id */
154void rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca);
155
156/* set rx dca enable */
157void rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en);
158
159/* set rx dca mode */
160void rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode);
161
162/* set rx descriptor data buffer size */
163void rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
164 u32 rx_desc_data_buff_size,
165 u32 descriptor);
166
167/* set rx descriptor dca enable */
168void rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
169 u32 dca);
170
171/* set rx descriptor enable */
172void rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
173 u32 descriptor);
174
175/* set rx descriptor header splitting */
176void rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
177 u32 rx_desc_head_splitting,
178 u32 descriptor);
179
180/* get rx descriptor head pointer */
181u32 rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor);
182
183/* set rx descriptor length */
184void rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
185 u32 descriptor);
186
187/* set rx descriptor write-back interrupt enable */
188void rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
189 u32 rx_desc_wr_wb_irq_en);
190
191/* set rx header dca enable */
192void rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
193 u32 dca);
194
195/* set rx payload dca enable */
196void rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, u32 dca);
197
198/* set rx descriptor header buffer size */
199void rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
200 u32 rx_desc_head_buff_size,
201 u32 descriptor);
202
203/* set rx descriptor reset */
204void rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
205 u32 descriptor);
206
207/* Set RDM Interrupt Moderation Enable */
208void rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, u32 rdm_intr_moder_en);
209
210/* reg */
211
212/* set general interrupt mapping register */
213void reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map, u32 regidx);
214
215/* get general interrupt status register */
216u32 reg_gen_irq_status_get(struct aq_hw_s *aq_hw);
217
218/* set interrupt global control register */
219void reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl);
220
221/* set interrupt throttle register */
222void reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle);
223
224/* set rx dma descriptor base address lsw */
225void reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
226 u32 rx_dma_desc_base_addrlsw,
227 u32 descriptor);
228
229/* set rx dma descriptor base address msw */
230void reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
231 u32 rx_dma_desc_base_addrmsw,
232 u32 descriptor);
233
234/* get rx dma descriptor status register */
235u32 reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor);
236
237/* set rx dma descriptor tail pointer register */
238void reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
239 u32 rx_dma_desc_tail_ptr,
240 u32 descriptor);
241
242/* set rx filter multicast filter mask register */
243void reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
244 u32 rx_flr_mcst_flr_msk);
245
246/* set rx filter multicast filter register */
247void reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
248 u32 filter);
249
250/* set rx filter rss control register 1 */
251void reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,
252 u32 rx_flr_rss_control1);
253
254/* Set RX Filter Control Register 2 */
255void reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_flr_control2);
256
257/* Set RX Interrupt Moderation Control Register */
258void reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
259 u32 rx_intr_moderation_ctl,
260 u32 queue);
261
262/* set tx dma debug control */
263void reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw, u32 tx_dma_debug_ctl);
264
265/* set tx dma descriptor base address lsw */
266void reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
267 u32 tx_dma_desc_base_addrlsw,
268 u32 descriptor);
269
270/* set tx dma descriptor base address msw */
271void reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
272 u32 tx_dma_desc_base_addrmsw,
273 u32 descriptor);
274
275/* set tx dma descriptor tail pointer register */
276void reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
277 u32 tx_dma_desc_tail_ptr,
278 u32 descriptor);
279
280/* Set TX Interrupt Moderation Control Register */
281void reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
282 u32 tx_intr_moderation_ctl,
283 u32 queue);
284
285/* set global microprocessor scratch pad */
286void reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
287 u32 glb_cpu_scratch_scp, u32 scratch_scp);
288
289/* rpb */
290
291/* set dma system loopback */
292void rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk);
293
294/* set rx traffic class mode */
295void rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
296 u32 rx_traf_class_mode);
297
298/* set rx buffer enable */
299void rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en);
300
301/* set rx buffer high threshold (per tc) */
302void rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
303 u32 rx_buff_hi_threshold_per_tc,
304 u32 buffer);
305
306/* set rx buffer low threshold (per tc) */
307void rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
308 u32 rx_buff_lo_threshold_per_tc,
309 u32 buffer);
310
311/* set rx flow control mode */
312void rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode);
313
314/* set rx packet buffer size (per tc) */
315void rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
316 u32 rx_pkt_buff_size_per_tc,
317 u32 buffer);
318
319/* set rx xoff enable (per tc) */
320void rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
321 u32 buffer);
322
323/* rpf */
324
325/* set l2 broadcast count threshold */
326void rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
327 u32 l2broadcast_count_threshold);
328
329/* set l2 broadcast enable */
330void rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en);
331
332/* set l2 broadcast filter action */
333void rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,
334 u32 l2broadcast_flr_act);
335
336/* set l2 multicast filter enable */
337void rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, u32 l2multicast_flr_en,
338 u32 filter);
339
340/* set l2 promiscuous mode enable */
341void rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
342 u32 l2promiscuous_mode_en);
343
344/* set l2 unicast filter action */
345void rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_act,
346 u32 filter);
347
348/* set l2 unicast filter enable */
349void rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
350 u32 filter);
351
352/* set l2 unicast destination address lsw */
353void rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
354 u32 l2unicast_dest_addresslsw,
355 u32 filter);
356
357/* set l2 unicast destination address msw */
358void rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
359 u32 l2unicast_dest_addressmsw,
360 u32 filter);
361
362/* Set L2 Accept all Multicast packets */
363void rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
364 u32 l2_accept_all_mc_packets);
365
366/* set user-priority tc mapping */
367void rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
368 u32 user_priority_tc_map, u32 tc);
369
370/* set rss key address */
371void rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr);
372
373/* set rss key write data */
374void rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data);
375
376/* get rss key write enable */
377u32 rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw);
378
379/* set rss key write enable */
380void rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en);
381
382/* set rss redirection table address */
383void rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,
384 u32 rss_redir_tbl_addr);
385
386/* set rss redirection table write data */
387void rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
388 u32 rss_redir_tbl_wr_data);
389
390/* get rss redirection write enable */
391u32 rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw);
392
393/* set rss redirection write enable */
394void rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en);
395
396/* set tpo to rpf system loopback */
397void rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,
398 u32 tpo_to_rpf_sys_lbk);
399
400/* set vlan inner ethertype */
401void rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht);
402
403/* set vlan outer ethertype */
404void rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht);
405
406/* set vlan promiscuous mode enable */
407void rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, u32 vlan_prom_mode_en);
408
409/* Set VLAN untagged action */
410void rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, u32 vlan_untagged_act);
411
412/* Set VLAN accept untagged packets */
413void rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
414 u32 vlan_accept_untagged_packets);
415
416/* Set VLAN filter enable */
417void rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en, u32 filter);
418
419/* Set VLAN Filter Action */
420void rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_filter_act,
421 u32 filter);
422
423/* Set VLAN ID Filter */
424void rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, u32 filter);
425
426/* set ethertype filter enable */
427void rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en, u32 filter);
428
429/* set ethertype user-priority enable */
430void rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
431 u32 etht_user_priority_en, u32 filter);
432
433/* set ethertype rx queue enable */
434void rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue_en,
435 u32 filter);
436
437/* set ethertype rx queue */
438void rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
439 u32 filter);
440
441/* set ethertype user-priority */
442void rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, u32 etht_user_priority,
443 u32 filter);
444
445/* set ethertype management queue */
446void rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
447 u32 filter);
448
449/* set ethertype filter action */
450void rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
451 u32 filter);
452
453/* set ethertype filter */
454void rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter);
455
456/* rpo */
457
458/* set ipv4 header checksum offload enable */
459void rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
460 u32 ipv4header_crc_offload_en);
461
462/* set rx descriptor vlan stripping */
463void rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
464 u32 rx_desc_vlan_stripping,
465 u32 descriptor);
466
467/* set tcp/udp checksum offload enable */
468void rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
469 u32 tcp_udp_crc_offload_en);
470
471/* Set LRO Patch Optimization Enable. */
472void rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
473 u32 lro_patch_optimization_en);
474
475/* Set Large Receive Offload Enable */
476void rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en);
477
478/* Set LRO Q Sessions Limit */
479void rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw, u32 lro_qsessions_lim);
480
481/* Set LRO Total Descriptor Limit */
482void rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw, u32 lro_total_desc_lim);
483
484/* Set LRO Min Payload of First Packet */
485void rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
486 u32 lro_min_pld_of_first_pkt);
487
488/* Set LRO Packet Limit */
489void rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_packet_lim);
490
491/* Set LRO Max Number of Descriptors */
492void rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
493 u32 lro_max_desc_num, u32 lro);
494
495/* Set LRO Time Base Divider */
496void rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
497 u32 lro_time_base_divider);
498
499/*Set LRO Inactive Interval */
500void rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
501 u32 lro_inactive_interval);
502
503/*Set LRO Max Coalescing Interval */
504void rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
505 u32 lro_max_coalescing_interval);
506
507/* rx */
508
509/* set rx register reset disable */
510void rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis);
511
512/* tdm */
513
514/* set cpu id */
515void tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca);
516
517/* set large send offload enable */
518void tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
519 u32 large_send_offload_en);
520
521/* set tx descriptor enable */
522void tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en, u32 descriptor);
523
524/* set tx dca enable */
525void tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en);
526
527/* set tx dca mode */
528void tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode);
529
530/* set tx descriptor dca enable */
531void tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en, u32 dca);
532
533/* get tx descriptor head pointer */
534u32 tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor);
535
536/* set tx descriptor length */
537void tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
538 u32 descriptor);
539
540/* set tx descriptor write-back interrupt enable */
541void tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
542 u32 tx_desc_wr_wb_irq_en);
543
544/* set tx descriptor write-back threshold */
545void tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
546 u32 tx_desc_wr_wb_threshold,
547 u32 descriptor);
548
549/* Set TDM Interrupt Moderation Enable */
550void tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
551 u32 tdm_irq_moderation_en);
552/* thm */
553
554/* set lso tcp flag of first packet */
555void thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
556 u32 lso_tcp_flag_of_first_pkt);
557
558/* set lso tcp flag of last packet */
559void thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
560 u32 lso_tcp_flag_of_last_pkt);
561
562/* set lso tcp flag of middle packet */
563void thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
564 u32 lso_tcp_flag_of_middle_pkt);
565
566/* tpb */
567
568/* set tx buffer enable */
569void tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en);
570
571/* set tx buffer high threshold (per tc) */
572void tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
573 u32 tx_buff_hi_threshold_per_tc,
574 u32 buffer);
575
576/* set tx buffer low threshold (per tc) */
577void tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
578 u32 tx_buff_lo_threshold_per_tc,
579 u32 buffer);
580
581/* set tx dma system loopback enable */
582void tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en);
583
584/* set tx packet buffer size (per tc) */
585void tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
586 u32 tx_pkt_buff_size_per_tc, u32 buffer);
587
588/* set tx path pad insert enable */
589void tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en);
590
591/* tpo */
592
593/* set ipv4 header checksum offload enable */
594void tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
595 u32 ipv4header_crc_offload_en);
596
597/* set tcp/udp checksum offload enable */
598void tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
599 u32 tcp_udp_crc_offload_en);
600
601/* set tx pkt system loopback enable */
602void tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_pkt_sys_lbk_en);
603
604/* tps */
605
606/* set tx packet scheduler data arbitration mode */
607void tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
608 u32 tx_pkt_shed_data_arb_mode);
609
610/* set tx packet scheduler descriptor rate current time reset */
611void tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
612 u32 curr_time_res);
613
614/* set tx packet scheduler descriptor rate limit */
615void tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
616 u32 tx_pkt_shed_desc_rate_lim);
617
618/* set tx packet scheduler descriptor tc arbitration mode */
619void tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
620 u32 tx_pkt_shed_desc_tc_arb_mode);
621
622/* set tx packet scheduler descriptor tc max credit */
623void tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
624 u32 tx_pkt_shed_desc_tc_max_credit,
625 u32 tc);
626
627/* set tx packet scheduler descriptor tc weight */
628void tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
629 u32 tx_pkt_shed_desc_tc_weight,
630 u32 tc);
631
632/* set tx packet scheduler descriptor vm arbitration mode */
633void tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
634 u32 tx_pkt_shed_desc_vm_arb_mode);
635
636/* set tx packet scheduler tc data max credit */
637void tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
638 u32 tx_pkt_shed_tc_data_max_credit,
639 u32 tc);
640
641/* set tx packet scheduler tc data weight */
642void tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
643 u32 tx_pkt_shed_tc_data_weight,
644 u32 tc);
645
646/* tx */
647
648/* set tx register reset disable */
649void tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis);
650
651/* msm */
652
653/* get register access status */
654u32 msm_reg_access_status_get(struct aq_hw_s *aq_hw);
655
656/* set register address for indirect address */
657void msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
658 u32 reg_addr_for_indirect_addr);
659
660/* set register read strobe */
661void msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe);
662
663/* get register read data */
664u32 msm_reg_rd_data_get(struct aq_hw_s *aq_hw);
665
666/* set register write data */
667void msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data);
668
669/* set register write strobe */
670void msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe);
671
672/* pci */
673
674/* set pci register reset disable */
675void pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis);
676
677#endif /* HW_ATL_LLH_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h
new file mode 100644
index 000000000000..5527fc0e5942
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h
@@ -0,0 +1,2375 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File hw_atl_llh_internal.h: Preprocessor definitions
11 * for Atlantic registers.
12 */
13
14#ifndef HW_ATL_LLH_INTERNAL_H
15#define HW_ATL_LLH_INTERNAL_H
16
17/* global microprocessor semaphore definitions
18 * base address: 0x000003a0
19 * parameter: semaphore {s} | stride size 0x4 | range [0, 15]
20 */
21#define glb_cpu_sem_adr(semaphore) (0x000003a0u + (semaphore) * 0x4)
22/* register address for bitfield rx dma good octet counter lsw [1f:0] */
23#define stats_rx_dma_good_octet_counterlsw__adr 0x00006808
24/* register address for bitfield rx dma good packet counter lsw [1f:0] */
25#define stats_rx_dma_good_pkt_counterlsw__adr 0x00006800
26/* register address for bitfield tx dma good octet counter lsw [1f:0] */
27#define stats_tx_dma_good_octet_counterlsw__adr 0x00008808
28/* register address for bitfield tx dma good packet counter lsw [1f:0] */
29#define stats_tx_dma_good_pkt_counterlsw__adr 0x00008800
30
31/* register address for bitfield rx dma good octet counter msw [3f:20] */
32#define stats_rx_dma_good_octet_countermsw__adr 0x0000680c
33/* register address for bitfield rx dma good packet counter msw [3f:20] */
34#define stats_rx_dma_good_pkt_countermsw__adr 0x00006804
35/* register address for bitfield tx dma good octet counter msw [3f:20] */
36#define stats_tx_dma_good_octet_countermsw__adr 0x0000880c
37/* register address for bitfield tx dma good packet counter msw [3f:20] */
38#define stats_tx_dma_good_pkt_countermsw__adr 0x00008804
39
40/* preprocessor definitions for msm rx errors counter register */
41#define mac_msm_rx_errs_cnt_adr 0x00000120u
42
43/* preprocessor definitions for msm rx unicast frames counter register */
44#define mac_msm_rx_ucst_frm_cnt_adr 0x000000e0u
45
46/* preprocessor definitions for msm rx multicast frames counter register */
47#define mac_msm_rx_mcst_frm_cnt_adr 0x000000e8u
48
49/* preprocessor definitions for msm rx broadcast frames counter register */
50#define mac_msm_rx_bcst_frm_cnt_adr 0x000000f0u
51
52/* preprocessor definitions for msm rx broadcast octets counter register 1 */
53#define mac_msm_rx_bcst_octets_counter1_adr 0x000001b0u
54
55/* preprocessor definitions for msm rx broadcast octets counter register 2 */
56#define mac_msm_rx_bcst_octets_counter2_adr 0x000001b4u
57
58/* preprocessor definitions for msm rx unicast octets counter register 0 */
59#define mac_msm_rx_ucst_octets_counter0_adr 0x000001b8u
60
61/* preprocessor definitions for rx dma statistics counter 7 */
62#define rx_dma_stat_counter7_adr 0x00006818u
63
64/* preprocessor definitions for msm tx unicast frames counter register */
65#define mac_msm_tx_ucst_frm_cnt_adr 0x00000108u
66
67/* preprocessor definitions for msm tx multicast frames counter register */
68#define mac_msm_tx_mcst_frm_cnt_adr 0x00000110u
69
70/* preprocessor definitions for global mif identification */
71#define glb_mif_id_adr 0x0000001cu
72
73/* register address for bitfield iamr_lsw[1f:0] */
74#define itr_iamrlsw_adr 0x00002090
75/* register address for bitfield rx dma drop packet counter [1f:0] */
76#define rpb_rx_dma_drop_pkt_cnt_adr 0x00006818
77
78/* register address for bitfield imcr_lsw[1f:0] */
79#define itr_imcrlsw_adr 0x00002070
80/* register address for bitfield imsr_lsw[1f:0] */
81#define itr_imsrlsw_adr 0x00002060
82/* register address for bitfield itr_reg_res_dsbl */
83#define itr_reg_res_dsbl_adr 0x00002300
84/* bitmask for bitfield itr_reg_res_dsbl */
85#define itr_reg_res_dsbl_msk 0x20000000
86/* lower bit position of bitfield itr_reg_res_dsbl */
87#define itr_reg_res_dsbl_shift 29
88/* register address for bitfield iscr_lsw[1f:0] */
89#define itr_iscrlsw_adr 0x00002050
90/* register address for bitfield isr_lsw[1f:0] */
91#define itr_isrlsw_adr 0x00002000
92/* register address for bitfield itr_reset */
93#define itr_res_adr 0x00002300
94/* bitmask for bitfield itr_reset */
95#define itr_res_msk 0x80000000
96/* lower bit position of bitfield itr_reset */
97#define itr_res_shift 31
98/* register address for bitfield dca{d}_cpuid[7:0] */
99#define rdm_dcadcpuid_adr(dca) (0x00006100 + (dca) * 0x4)
100/* bitmask for bitfield dca{d}_cpuid[7:0] */
101#define rdm_dcadcpuid_msk 0x000000ff
102/* lower bit position of bitfield dca{d}_cpuid[7:0] */
103#define rdm_dcadcpuid_shift 0
104/* register address for bitfield dca_en */
105#define rdm_dca_en_adr 0x00006180
106
107/* rx dca_en bitfield definitions
108 * preprocessor definitions for the bitfield "dca_en".
109 * port="pif_rdm_dca_en_i"
110 */
111
112/* register address for bitfield dca_en */
113#define rdm_dca_en_adr 0x00006180
114/* bitmask for bitfield dca_en */
115#define rdm_dca_en_msk 0x80000000
116/* inverted bitmask for bitfield dca_en */
117#define rdm_dca_en_mskn 0x7fffffff
118/* lower bit position of bitfield dca_en */
119#define rdm_dca_en_shift 31
120/* width of bitfield dca_en */
121#define rdm_dca_en_width 1
122/* default value of bitfield dca_en */
123#define rdm_dca_en_default 0x1
124
125/* rx dca_mode[3:0] bitfield definitions
126 * preprocessor definitions for the bitfield "dca_mode[3:0]".
127 * port="pif_rdm_dca_mode_i[3:0]"
128 */
129
130/* register address for bitfield dca_mode[3:0] */
131#define rdm_dca_mode_adr 0x00006180
132/* bitmask for bitfield dca_mode[3:0] */
133#define rdm_dca_mode_msk 0x0000000f
134/* inverted bitmask for bitfield dca_mode[3:0] */
135#define rdm_dca_mode_mskn 0xfffffff0
136/* lower bit position of bitfield dca_mode[3:0] */
137#define rdm_dca_mode_shift 0
138/* width of bitfield dca_mode[3:0] */
139#define rdm_dca_mode_width 4
140/* default value of bitfield dca_mode[3:0] */
141#define rdm_dca_mode_default 0x0
142
143/* rx desc{d}_data_size[4:0] bitfield definitions
144 * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]".
145 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
146 * port="pif_rdm_desc0_data_size_i[4:0]"
147 */
148
149/* register address for bitfield desc{d}_data_size[4:0] */
150#define rdm_descddata_size_adr(descriptor) (0x00005b18 + (descriptor) * 0x20)
151/* bitmask for bitfield desc{d}_data_size[4:0] */
152#define rdm_descddata_size_msk 0x0000001f
153/* inverted bitmask for bitfield desc{d}_data_size[4:0] */
154#define rdm_descddata_size_mskn 0xffffffe0
155/* lower bit position of bitfield desc{d}_data_size[4:0] */
156#define rdm_descddata_size_shift 0
157/* width of bitfield desc{d}_data_size[4:0] */
158#define rdm_descddata_size_width 5
159/* default value of bitfield desc{d}_data_size[4:0] */
160#define rdm_descddata_size_default 0x0
161
162/* rx dca{d}_desc_en bitfield definitions
163 * preprocessor definitions for the bitfield "dca{d}_desc_en".
164 * parameter: dca {d} | stride size 0x4 | range [0, 31]
165 * port="pif_rdm_dca_desc_en_i[0]"
166 */
167
168/* register address for bitfield dca{d}_desc_en */
169#define rdm_dcaddesc_en_adr(dca) (0x00006100 + (dca) * 0x4)
170/* bitmask for bitfield dca{d}_desc_en */
171#define rdm_dcaddesc_en_msk 0x80000000
172/* inverted bitmask for bitfield dca{d}_desc_en */
173#define rdm_dcaddesc_en_mskn 0x7fffffff
174/* lower bit position of bitfield dca{d}_desc_en */
175#define rdm_dcaddesc_en_shift 31
176/* width of bitfield dca{d}_desc_en */
177#define rdm_dcaddesc_en_width 1
178/* default value of bitfield dca{d}_desc_en */
179#define rdm_dcaddesc_en_default 0x0
180
181/* rx desc{d}_en bitfield definitions
182 * preprocessor definitions for the bitfield "desc{d}_en".
183 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
184 * port="pif_rdm_desc_en_i[0]"
185 */
186
187/* register address for bitfield desc{d}_en */
188#define rdm_descden_adr(descriptor) (0x00005b08 + (descriptor) * 0x20)
189/* bitmask for bitfield desc{d}_en */
190#define rdm_descden_msk 0x80000000
191/* inverted bitmask for bitfield desc{d}_en */
192#define rdm_descden_mskn 0x7fffffff
193/* lower bit position of bitfield desc{d}_en */
194#define rdm_descden_shift 31
195/* width of bitfield desc{d}_en */
196#define rdm_descden_width 1
197/* default value of bitfield desc{d}_en */
198#define rdm_descden_default 0x0
199
200/* rx desc{d}_hdr_size[4:0] bitfield definitions
201 * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]".
202 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
203 * port="pif_rdm_desc0_hdr_size_i[4:0]"
204 */
205
206/* register address for bitfield desc{d}_hdr_size[4:0] */
207#define rdm_descdhdr_size_adr(descriptor) (0x00005b18 + (descriptor) * 0x20)
208/* bitmask for bitfield desc{d}_hdr_size[4:0] */
209#define rdm_descdhdr_size_msk 0x00001f00
210/* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */
211#define rdm_descdhdr_size_mskn 0xffffe0ff
212/* lower bit position of bitfield desc{d}_hdr_size[4:0] */
213#define rdm_descdhdr_size_shift 8
214/* width of bitfield desc{d}_hdr_size[4:0] */
215#define rdm_descdhdr_size_width 5
216/* default value of bitfield desc{d}_hdr_size[4:0] */
217#define rdm_descdhdr_size_default 0x0
218
219/* rx desc{d}_hdr_split bitfield definitions
220 * preprocessor definitions for the bitfield "desc{d}_hdr_split".
221 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
222 * port="pif_rdm_desc_hdr_split_i[0]"
223 */
224
225/* register address for bitfield desc{d}_hdr_split */
226#define rdm_descdhdr_split_adr(descriptor) (0x00005b08 + (descriptor) * 0x20)
227/* bitmask for bitfield desc{d}_hdr_split */
228#define rdm_descdhdr_split_msk 0x10000000
229/* inverted bitmask for bitfield desc{d}_hdr_split */
230#define rdm_descdhdr_split_mskn 0xefffffff
231/* lower bit position of bitfield desc{d}_hdr_split */
232#define rdm_descdhdr_split_shift 28
233/* width of bitfield desc{d}_hdr_split */
234#define rdm_descdhdr_split_width 1
235/* default value of bitfield desc{d}_hdr_split */
236#define rdm_descdhdr_split_default 0x0
237
238/* rx desc{d}_hd[c:0] bitfield definitions
239 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]".
240 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
241 * port="rdm_pif_desc0_hd_o[12:0]"
242 */
243
244/* register address for bitfield desc{d}_hd[c:0] */
245#define rdm_descdhd_adr(descriptor) (0x00005b0c + (descriptor) * 0x20)
246/* bitmask for bitfield desc{d}_hd[c:0] */
247#define rdm_descdhd_msk 0x00001fff
248/* inverted bitmask for bitfield desc{d}_hd[c:0] */
249#define rdm_descdhd_mskn 0xffffe000
250/* lower bit position of bitfield desc{d}_hd[c:0] */
251#define rdm_descdhd_shift 0
252/* width of bitfield desc{d}_hd[c:0] */
253#define rdm_descdhd_width 13
254
255/* rx desc{d}_len[9:0] bitfield definitions
256 * preprocessor definitions for the bitfield "desc{d}_len[9:0]".
257 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
258 * port="pif_rdm_desc0_len_i[9:0]"
259 */
260
261/* register address for bitfield desc{d}_len[9:0] */
262#define rdm_descdlen_adr(descriptor) (0x00005b08 + (descriptor) * 0x20)
263/* bitmask for bitfield desc{d}_len[9:0] */
264#define rdm_descdlen_msk 0x00001ff8
265/* inverted bitmask for bitfield desc{d}_len[9:0] */
266#define rdm_descdlen_mskn 0xffffe007
267/* lower bit position of bitfield desc{d}_len[9:0] */
268#define rdm_descdlen_shift 3
269/* width of bitfield desc{d}_len[9:0] */
270#define rdm_descdlen_width 10
271/* default value of bitfield desc{d}_len[9:0] */
272#define rdm_descdlen_default 0x0
273
274/* rx desc{d}_reset bitfield definitions
275 * preprocessor definitions for the bitfield "desc{d}_reset".
276 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
277 * port="pif_rdm_q_pf_res_i[0]"
278 */
279
280/* register address for bitfield desc{d}_reset */
281#define rdm_descdreset_adr(descriptor) (0x00005b08 + (descriptor) * 0x20)
282/* bitmask for bitfield desc{d}_reset */
283#define rdm_descdreset_msk 0x02000000
284/* inverted bitmask for bitfield desc{d}_reset */
285#define rdm_descdreset_mskn 0xfdffffff
286/* lower bit position of bitfield desc{d}_reset */
287#define rdm_descdreset_shift 25
288/* width of bitfield desc{d}_reset */
289#define rdm_descdreset_width 1
290/* default value of bitfield desc{d}_reset */
291#define rdm_descdreset_default 0x0
292
293/* rx int_desc_wrb_en bitfield definitions
294 * preprocessor definitions for the bitfield "int_desc_wrb_en".
295 * port="pif_rdm_int_desc_wrb_en_i"
296 */
297
298/* register address for bitfield int_desc_wrb_en */
299#define rdm_int_desc_wrb_en_adr 0x00005a30
300/* bitmask for bitfield int_desc_wrb_en */
301#define rdm_int_desc_wrb_en_msk 0x00000004
302/* inverted bitmask for bitfield int_desc_wrb_en */
303#define rdm_int_desc_wrb_en_mskn 0xfffffffb
304/* lower bit position of bitfield int_desc_wrb_en */
305#define rdm_int_desc_wrb_en_shift 2
306/* width of bitfield int_desc_wrb_en */
307#define rdm_int_desc_wrb_en_width 1
308/* default value of bitfield int_desc_wrb_en */
309#define rdm_int_desc_wrb_en_default 0x0
310
311/* rx dca{d}_hdr_en bitfield definitions
312 * preprocessor definitions for the bitfield "dca{d}_hdr_en".
313 * parameter: dca {d} | stride size 0x4 | range [0, 31]
314 * port="pif_rdm_dca_hdr_en_i[0]"
315 */
316
317/* register address for bitfield dca{d}_hdr_en */
318#define rdm_dcadhdr_en_adr(dca) (0x00006100 + (dca) * 0x4)
319/* bitmask for bitfield dca{d}_hdr_en */
320#define rdm_dcadhdr_en_msk 0x40000000
321/* inverted bitmask for bitfield dca{d}_hdr_en */
322#define rdm_dcadhdr_en_mskn 0xbfffffff
323/* lower bit position of bitfield dca{d}_hdr_en */
324#define rdm_dcadhdr_en_shift 30
325/* width of bitfield dca{d}_hdr_en */
326#define rdm_dcadhdr_en_width 1
327/* default value of bitfield dca{d}_hdr_en */
328#define rdm_dcadhdr_en_default 0x0
329
330/* rx dca{d}_pay_en bitfield definitions
331 * preprocessor definitions for the bitfield "dca{d}_pay_en".
332 * parameter: dca {d} | stride size 0x4 | range [0, 31]
333 * port="pif_rdm_dca_pay_en_i[0]"
334 */
335
336/* register address for bitfield dca{d}_pay_en */
337#define rdm_dcadpay_en_adr(dca) (0x00006100 + (dca) * 0x4)
338/* bitmask for bitfield dca{d}_pay_en */
339#define rdm_dcadpay_en_msk 0x20000000
340/* inverted bitmask for bitfield dca{d}_pay_en */
341#define rdm_dcadpay_en_mskn 0xdfffffff
342/* lower bit position of bitfield dca{d}_pay_en */
343#define rdm_dcadpay_en_shift 29
344/* width of bitfield dca{d}_pay_en */
345#define rdm_dcadpay_en_width 1
346/* default value of bitfield dca{d}_pay_en */
347#define rdm_dcadpay_en_default 0x0
348
349/* RX rdm_int_rim_en Bitfield Definitions
350 * Preprocessor definitions for the bitfield "rdm_int_rim_en".
351 * PORT="pif_rdm_int_rim_en_i"
352 */
353
354/* Register address for bitfield rdm_int_rim_en */
355#define rdm_int_rim_en_adr 0x00005A30
356/* Bitmask for bitfield rdm_int_rim_en */
357#define rdm_int_rim_en_msk 0x00000008
358/* Inverted bitmask for bitfield rdm_int_rim_en */
359#define rdm_int_rim_en_mskn 0xFFFFFFF7
360/* Lower bit position of bitfield rdm_int_rim_en */
361#define rdm_int_rim_en_shift 3
362/* Width of bitfield rdm_int_rim_en */
363#define rdm_int_rim_en_width 1
364/* Default value of bitfield rdm_int_rim_en */
365#define rdm_int_rim_en_default 0x0
366
367/* general interrupt mapping register definitions
368 * preprocessor definitions for general interrupt mapping register
369 * base address: 0x00002180
370 * parameter: regidx {f} | stride size 0x4 | range [0, 3]
371 */
372#define gen_intr_map_adr(regidx) (0x00002180u + (regidx) * 0x4)
373
374/* general interrupt status register definitions
375 * preprocessor definitions for general interrupt status register
376 * address: 0x000021A0
377 */
378
379#define gen_intr_stat_adr 0x000021A4U
380
381/* interrupt global control register definitions
382 * preprocessor definitions for interrupt global control register
383 * address: 0x00002300
384 */
385#define intr_glb_ctl_adr 0x00002300u
386
387/* interrupt throttle register definitions
388 * preprocessor definitions for interrupt throttle register
389 * base address: 0x00002800
390 * parameter: throttle {t} | stride size 0x4 | range [0, 31]
391 */
392#define intr_thr_adr(throttle) (0x00002800u + (throttle) * 0x4)
393
394/* rx dma descriptor base address lsw definitions
395 * preprocessor definitions for rx dma descriptor base address lsw
396 * base address: 0x00005b00
397 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
398 */
399#define rx_dma_desc_base_addrlsw_adr(descriptor) \
400(0x00005b00u + (descriptor) * 0x20)
401
402/* rx dma descriptor base address msw definitions
403 * preprocessor definitions for rx dma descriptor base address msw
404 * base address: 0x00005b04
405 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
406 */
407#define rx_dma_desc_base_addrmsw_adr(descriptor) \
408(0x00005b04u + (descriptor) * 0x20)
409
410/* rx dma descriptor status register definitions
411 * preprocessor definitions for rx dma descriptor status register
412 * base address: 0x00005b14
413 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
414 */
415#define rx_dma_desc_stat_adr(descriptor) (0x00005b14u + (descriptor) * 0x20)
416
417/* rx dma descriptor tail pointer register definitions
418 * preprocessor definitions for rx dma descriptor tail pointer register
419 * base address: 0x00005b10
420 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
421 */
422#define rx_dma_desc_tail_ptr_adr(descriptor) (0x00005b10u + (descriptor) * 0x20)
423
424/* rx interrupt moderation control register definitions
425 * Preprocessor definitions for RX Interrupt Moderation Control Register
426 * Base Address: 0x00005A40
427 * Parameter: RIM {R} | stride size 0x4 | range [0, 31]
428 */
429#define rx_intr_moderation_ctl_adr(rim) (0x00005A40u + (rim) * 0x4)
430
431/* rx filter multicast filter mask register definitions
432 * preprocessor definitions for rx filter multicast filter mask register
433 * address: 0x00005270
434 */
435#define rx_flr_mcst_flr_msk_adr 0x00005270u
436
437/* rx filter multicast filter register definitions
438 * preprocessor definitions for rx filter multicast filter register
439 * base address: 0x00005250
440 * parameter: filter {f} | stride size 0x4 | range [0, 7]
441 */
442#define rx_flr_mcst_flr_adr(filter) (0x00005250u + (filter) * 0x4)
443
444/* RX Filter RSS Control Register 1 Definitions
445 * Preprocessor definitions for RX Filter RSS Control Register 1
446 * Address: 0x000054C0
447 */
448#define rx_flr_rss_control1_adr 0x000054C0u
449
450/* RX Filter Control Register 2 Definitions
451 * Preprocessor definitions for RX Filter Control Register 2
452 * Address: 0x00005104
453 */
454#define rx_flr_control2_adr 0x00005104u
455
456/* tx tx dma debug control [1f:0] bitfield definitions
457 * preprocessor definitions for the bitfield "tx dma debug control [1f:0]".
458 * port="pif_tdm_debug_cntl_i[31:0]"
459 */
460
461/* register address for bitfield tx dma debug control [1f:0] */
462#define tdm_tx_dma_debug_ctl_adr 0x00008920
463/* bitmask for bitfield tx dma debug control [1f:0] */
464#define tdm_tx_dma_debug_ctl_msk 0xffffffff
465/* inverted bitmask for bitfield tx dma debug control [1f:0] */
466#define tdm_tx_dma_debug_ctl_mskn 0x00000000
467/* lower bit position of bitfield tx dma debug control [1f:0] */
468#define tdm_tx_dma_debug_ctl_shift 0
469/* width of bitfield tx dma debug control [1f:0] */
470#define tdm_tx_dma_debug_ctl_width 32
471/* default value of bitfield tx dma debug control [1f:0] */
472#define tdm_tx_dma_debug_ctl_default 0x0
473
474/* tx dma descriptor base address lsw definitions
475 * preprocessor definitions for tx dma descriptor base address lsw
476 * base address: 0x00007c00
477 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
478 */
479#define tx_dma_desc_base_addrlsw_adr(descriptor) \
480 (0x00007c00u + (descriptor) * 0x40)
481
482/* tx dma descriptor tail pointer register definitions
483 * preprocessor definitions for tx dma descriptor tail pointer register
484 * base address: 0x00007c10
485 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
486 */
487#define tx_dma_desc_tail_ptr_adr(descriptor) (0x00007c10u + (descriptor) * 0x40)
488
489/* rx dma_sys_loopback bitfield definitions
490 * preprocessor definitions for the bitfield "dma_sys_loopback".
491 * port="pif_rpb_dma_sys_lbk_i"
492 */
493
494/* register address for bitfield dma_sys_loopback */
495#define rpb_dma_sys_lbk_adr 0x00005000
496/* bitmask for bitfield dma_sys_loopback */
497#define rpb_dma_sys_lbk_msk 0x00000040
498/* inverted bitmask for bitfield dma_sys_loopback */
499#define rpb_dma_sys_lbk_mskn 0xffffffbf
500/* lower bit position of bitfield dma_sys_loopback */
501#define rpb_dma_sys_lbk_shift 6
502/* width of bitfield dma_sys_loopback */
503#define rpb_dma_sys_lbk_width 1
504/* default value of bitfield dma_sys_loopback */
505#define rpb_dma_sys_lbk_default 0x0
506
507/* rx rx_tc_mode bitfield definitions
508 * preprocessor definitions for the bitfield "rx_tc_mode".
509 * port="pif_rpb_rx_tc_mode_i,pif_rpf_rx_tc_mode_i"
510 */
511
512/* register address for bitfield rx_tc_mode */
513#define rpb_rpf_rx_tc_mode_adr 0x00005700
514/* bitmask for bitfield rx_tc_mode */
515#define rpb_rpf_rx_tc_mode_msk 0x00000100
516/* inverted bitmask for bitfield rx_tc_mode */
517#define rpb_rpf_rx_tc_mode_mskn 0xfffffeff
518/* lower bit position of bitfield rx_tc_mode */
519#define rpb_rpf_rx_tc_mode_shift 8
520/* width of bitfield rx_tc_mode */
521#define rpb_rpf_rx_tc_mode_width 1
522/* default value of bitfield rx_tc_mode */
523#define rpb_rpf_rx_tc_mode_default 0x0
524
525/* rx rx_buf_en bitfield definitions
526 * preprocessor definitions for the bitfield "rx_buf_en".
527 * port="pif_rpb_rx_buf_en_i"
528 */
529
530/* register address for bitfield rx_buf_en */
531#define rpb_rx_buf_en_adr 0x00005700
532/* bitmask for bitfield rx_buf_en */
533#define rpb_rx_buf_en_msk 0x00000001
534/* inverted bitmask for bitfield rx_buf_en */
535#define rpb_rx_buf_en_mskn 0xfffffffe
536/* lower bit position of bitfield rx_buf_en */
537#define rpb_rx_buf_en_shift 0
538/* width of bitfield rx_buf_en */
539#define rpb_rx_buf_en_width 1
540/* default value of bitfield rx_buf_en */
541#define rpb_rx_buf_en_default 0x0
542
543/* rx rx{b}_hi_thresh[d:0] bitfield definitions
544 * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]".
545 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
546 * port="pif_rpb_rx0_hi_thresh_i[13:0]"
547 */
548
549/* register address for bitfield rx{b}_hi_thresh[d:0] */
550#define rpb_rxbhi_thresh_adr(buffer) (0x00005714 + (buffer) * 0x10)
551/* bitmask for bitfield rx{b}_hi_thresh[d:0] */
552#define rpb_rxbhi_thresh_msk 0x3fff0000
553/* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */
554#define rpb_rxbhi_thresh_mskn 0xc000ffff
555/* lower bit position of bitfield rx{b}_hi_thresh[d:0] */
556#define rpb_rxbhi_thresh_shift 16
557/* width of bitfield rx{b}_hi_thresh[d:0] */
558#define rpb_rxbhi_thresh_width 14
559/* default value of bitfield rx{b}_hi_thresh[d:0] */
560#define rpb_rxbhi_thresh_default 0x0
561
562/* rx rx{b}_lo_thresh[d:0] bitfield definitions
563 * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]".
564 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
565 * port="pif_rpb_rx0_lo_thresh_i[13:0]"
566 */
567
568/* register address for bitfield rx{b}_lo_thresh[d:0] */
569#define rpb_rxblo_thresh_adr(buffer) (0x00005714 + (buffer) * 0x10)
570/* bitmask for bitfield rx{b}_lo_thresh[d:0] */
571#define rpb_rxblo_thresh_msk 0x00003fff
572/* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */
573#define rpb_rxblo_thresh_mskn 0xffffc000
574/* lower bit position of bitfield rx{b}_lo_thresh[d:0] */
575#define rpb_rxblo_thresh_shift 0
576/* width of bitfield rx{b}_lo_thresh[d:0] */
577#define rpb_rxblo_thresh_width 14
578/* default value of bitfield rx{b}_lo_thresh[d:0] */
579#define rpb_rxblo_thresh_default 0x0
580
581/* rx rx_fc_mode[1:0] bitfield definitions
582 * preprocessor definitions for the bitfield "rx_fc_mode[1:0]".
583 * port="pif_rpb_rx_fc_mode_i[1:0]"
584 */
585
586/* register address for bitfield rx_fc_mode[1:0] */
587#define rpb_rx_fc_mode_adr 0x00005700
588/* bitmask for bitfield rx_fc_mode[1:0] */
589#define rpb_rx_fc_mode_msk 0x00000030
590/* inverted bitmask for bitfield rx_fc_mode[1:0] */
591#define rpb_rx_fc_mode_mskn 0xffffffcf
592/* lower bit position of bitfield rx_fc_mode[1:0] */
593#define rpb_rx_fc_mode_shift 4
594/* width of bitfield rx_fc_mode[1:0] */
595#define rpb_rx_fc_mode_width 2
596/* default value of bitfield rx_fc_mode[1:0] */
597#define rpb_rx_fc_mode_default 0x0
598
599/* rx rx{b}_buf_size[8:0] bitfield definitions
600 * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]".
601 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
602 * port="pif_rpb_rx0_buf_size_i[8:0]"
603 */
604
605/* register address for bitfield rx{b}_buf_size[8:0] */
606#define rpb_rxbbuf_size_adr(buffer) (0x00005710 + (buffer) * 0x10)
607/* bitmask for bitfield rx{b}_buf_size[8:0] */
608#define rpb_rxbbuf_size_msk 0x000001ff
609/* inverted bitmask for bitfield rx{b}_buf_size[8:0] */
610#define rpb_rxbbuf_size_mskn 0xfffffe00
611/* lower bit position of bitfield rx{b}_buf_size[8:0] */
612#define rpb_rxbbuf_size_shift 0
613/* width of bitfield rx{b}_buf_size[8:0] */
614#define rpb_rxbbuf_size_width 9
615/* default value of bitfield rx{b}_buf_size[8:0] */
616#define rpb_rxbbuf_size_default 0x0
617
618/* rx rx{b}_xoff_en bitfield definitions
619 * preprocessor definitions for the bitfield "rx{b}_xoff_en".
620 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
621 * port="pif_rpb_rx_xoff_en_i[0]"
622 */
623
624/* register address for bitfield rx{b}_xoff_en */
625#define rpb_rxbxoff_en_adr(buffer) (0x00005714 + (buffer) * 0x10)
626/* bitmask for bitfield rx{b}_xoff_en */
627#define rpb_rxbxoff_en_msk 0x80000000
628/* inverted bitmask for bitfield rx{b}_xoff_en */
629#define rpb_rxbxoff_en_mskn 0x7fffffff
630/* lower bit position of bitfield rx{b}_xoff_en */
631#define rpb_rxbxoff_en_shift 31
632/* width of bitfield rx{b}_xoff_en */
633#define rpb_rxbxoff_en_width 1
634/* default value of bitfield rx{b}_xoff_en */
635#define rpb_rxbxoff_en_default 0x0
636
637/* rx l2_bc_thresh[f:0] bitfield definitions
638 * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]".
639 * port="pif_rpf_l2_bc_thresh_i[15:0]"
640 */
641
642/* register address for bitfield l2_bc_thresh[f:0] */
643#define rpfl2bc_thresh_adr 0x00005100
644/* bitmask for bitfield l2_bc_thresh[f:0] */
645#define rpfl2bc_thresh_msk 0xffff0000
646/* inverted bitmask for bitfield l2_bc_thresh[f:0] */
647#define rpfl2bc_thresh_mskn 0x0000ffff
648/* lower bit position of bitfield l2_bc_thresh[f:0] */
649#define rpfl2bc_thresh_shift 16
650/* width of bitfield l2_bc_thresh[f:0] */
651#define rpfl2bc_thresh_width 16
652/* default value of bitfield l2_bc_thresh[f:0] */
653#define rpfl2bc_thresh_default 0x0
654
655/* rx l2_bc_en bitfield definitions
656 * preprocessor definitions for the bitfield "l2_bc_en".
657 * port="pif_rpf_l2_bc_en_i"
658 */
659
660/* register address for bitfield l2_bc_en */
661#define rpfl2bc_en_adr 0x00005100
662/* bitmask for bitfield l2_bc_en */
663#define rpfl2bc_en_msk 0x00000001
664/* inverted bitmask for bitfield l2_bc_en */
665#define rpfl2bc_en_mskn 0xfffffffe
666/* lower bit position of bitfield l2_bc_en */
667#define rpfl2bc_en_shift 0
668/* width of bitfield l2_bc_en */
669#define rpfl2bc_en_width 1
670/* default value of bitfield l2_bc_en */
671#define rpfl2bc_en_default 0x0
672
673/* rx l2_bc_act[2:0] bitfield definitions
674 * preprocessor definitions for the bitfield "l2_bc_act[2:0]".
675 * port="pif_rpf_l2_bc_act_i[2:0]"
676 */
677
678/* register address for bitfield l2_bc_act[2:0] */
679#define rpfl2bc_act_adr 0x00005100
680/* bitmask for bitfield l2_bc_act[2:0] */
681#define rpfl2bc_act_msk 0x00007000
682/* inverted bitmask for bitfield l2_bc_act[2:0] */
683#define rpfl2bc_act_mskn 0xffff8fff
684/* lower bit position of bitfield l2_bc_act[2:0] */
685#define rpfl2bc_act_shift 12
686/* width of bitfield l2_bc_act[2:0] */
687#define rpfl2bc_act_width 3
688/* default value of bitfield l2_bc_act[2:0] */
689#define rpfl2bc_act_default 0x0
690
691/* rx l2_mc_en{f} bitfield definitions
692 * preprocessor definitions for the bitfield "l2_mc_en{f}".
693 * parameter: filter {f} | stride size 0x4 | range [0, 7]
694 * port="pif_rpf_l2_mc_en_i[0]"
695 */
696
697/* register address for bitfield l2_mc_en{f} */
698#define rpfl2mc_enf_adr(filter) (0x00005250 + (filter) * 0x4)
699/* bitmask for bitfield l2_mc_en{f} */
700#define rpfl2mc_enf_msk 0x80000000
701/* inverted bitmask for bitfield l2_mc_en{f} */
702#define rpfl2mc_enf_mskn 0x7fffffff
703/* lower bit position of bitfield l2_mc_en{f} */
704#define rpfl2mc_enf_shift 31
705/* width of bitfield l2_mc_en{f} */
706#define rpfl2mc_enf_width 1
707/* default value of bitfield l2_mc_en{f} */
708#define rpfl2mc_enf_default 0x0
709
710/* rx l2_promis_mode bitfield definitions
711 * preprocessor definitions for the bitfield "l2_promis_mode".
712 * port="pif_rpf_l2_promis_mode_i"
713 */
714
715/* register address for bitfield l2_promis_mode */
716#define rpfl2promis_mode_adr 0x00005100
717/* bitmask for bitfield l2_promis_mode */
718#define rpfl2promis_mode_msk 0x00000008
719/* inverted bitmask for bitfield l2_promis_mode */
720#define rpfl2promis_mode_mskn 0xfffffff7
721/* lower bit position of bitfield l2_promis_mode */
722#define rpfl2promis_mode_shift 3
723/* width of bitfield l2_promis_mode */
724#define rpfl2promis_mode_width 1
725/* default value of bitfield l2_promis_mode */
726#define rpfl2promis_mode_default 0x0
727
728/* rx l2_uc_act{f}[2:0] bitfield definitions
729 * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]".
730 * parameter: filter {f} | stride size 0x8 | range [0, 37]
731 * port="pif_rpf_l2_uc_act0_i[2:0]"
732 */
733
734/* register address for bitfield l2_uc_act{f}[2:0] */
735#define rpfl2uc_actf_adr(filter) (0x00005114 + (filter) * 0x8)
736/* bitmask for bitfield l2_uc_act{f}[2:0] */
737#define rpfl2uc_actf_msk 0x00070000
738/* inverted bitmask for bitfield l2_uc_act{f}[2:0] */
739#define rpfl2uc_actf_mskn 0xfff8ffff
740/* lower bit position of bitfield l2_uc_act{f}[2:0] */
741#define rpfl2uc_actf_shift 16
742/* width of bitfield l2_uc_act{f}[2:0] */
743#define rpfl2uc_actf_width 3
744/* default value of bitfield l2_uc_act{f}[2:0] */
745#define rpfl2uc_actf_default 0x0
746
747/* rx l2_uc_en{f} bitfield definitions
748 * preprocessor definitions for the bitfield "l2_uc_en{f}".
749 * parameter: filter {f} | stride size 0x8 | range [0, 37]
750 * port="pif_rpf_l2_uc_en_i[0]"
751 */
752
753/* register address for bitfield l2_uc_en{f} */
754#define rpfl2uc_enf_adr(filter) (0x00005114 + (filter) * 0x8)
755/* bitmask for bitfield l2_uc_en{f} */
756#define rpfl2uc_enf_msk 0x80000000
757/* inverted bitmask for bitfield l2_uc_en{f} */
758#define rpfl2uc_enf_mskn 0x7fffffff
759/* lower bit position of bitfield l2_uc_en{f} */
760#define rpfl2uc_enf_shift 31
761/* width of bitfield l2_uc_en{f} */
762#define rpfl2uc_enf_width 1
763/* default value of bitfield l2_uc_en{f} */
764#define rpfl2uc_enf_default 0x0
765
766/* register address for bitfield l2_uc_da{f}_lsw[1f:0] */
767#define rpfl2uc_daflsw_adr(filter) (0x00005110 + (filter) * 0x8)
768/* register address for bitfield l2_uc_da{f}_msw[f:0] */
769#define rpfl2uc_dafmsw_adr(filter) (0x00005114 + (filter) * 0x8)
770/* bitmask for bitfield l2_uc_da{f}_msw[f:0] */
771#define rpfl2uc_dafmsw_msk 0x0000ffff
772/* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */
773#define rpfl2uc_dafmsw_shift 0
774
775/* rx l2_mc_accept_all bitfield definitions
776 * Preprocessor definitions for the bitfield "l2_mc_accept_all".
777 * PORT="pif_rpf_l2_mc_all_accept_i"
778 */
779
780/* Register address for bitfield l2_mc_accept_all */
781#define rpfl2mc_accept_all_adr 0x00005270
782/* Bitmask for bitfield l2_mc_accept_all */
783#define rpfl2mc_accept_all_msk 0x00004000
784/* Inverted bitmask for bitfield l2_mc_accept_all */
785#define rpfl2mc_accept_all_mskn 0xFFFFBFFF
786/* Lower bit position of bitfield l2_mc_accept_all */
787#define rpfl2mc_accept_all_shift 14
788/* Width of bitfield l2_mc_accept_all */
789#define rpfl2mc_accept_all_width 1
790/* Default value of bitfield l2_mc_accept_all */
791#define rpfl2mc_accept_all_default 0x0
792
793/* width of bitfield rx_tc_up{t}[2:0] */
794#define rpf_rpb_rx_tc_upt_width 3
795/* default value of bitfield rx_tc_up{t}[2:0] */
796#define rpf_rpb_rx_tc_upt_default 0x0
797
798/* rx rss_key_addr[4:0] bitfield definitions
799 * preprocessor definitions for the bitfield "rss_key_addr[4:0]".
800 * port="pif_rpf_rss_key_addr_i[4:0]"
801 */
802
803/* register address for bitfield rss_key_addr[4:0] */
804#define rpf_rss_key_addr_adr 0x000054d0
805/* bitmask for bitfield rss_key_addr[4:0] */
806#define rpf_rss_key_addr_msk 0x0000001f
807/* inverted bitmask for bitfield rss_key_addr[4:0] */
808#define rpf_rss_key_addr_mskn 0xffffffe0
809/* lower bit position of bitfield rss_key_addr[4:0] */
810#define rpf_rss_key_addr_shift 0
811/* width of bitfield rss_key_addr[4:0] */
812#define rpf_rss_key_addr_width 5
813/* default value of bitfield rss_key_addr[4:0] */
814#define rpf_rss_key_addr_default 0x0
815
816/* rx rss_key_wr_data[1f:0] bitfield definitions
817 * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]".
818 * port="pif_rpf_rss_key_wr_data_i[31:0]"
819 */
820
821/* register address for bitfield rss_key_wr_data[1f:0] */
822#define rpf_rss_key_wr_data_adr 0x000054d4
823/* bitmask for bitfield rss_key_wr_data[1f:0] */
824#define rpf_rss_key_wr_data_msk 0xffffffff
825/* inverted bitmask for bitfield rss_key_wr_data[1f:0] */
826#define rpf_rss_key_wr_data_mskn 0x00000000
827/* lower bit position of bitfield rss_key_wr_data[1f:0] */
828#define rpf_rss_key_wr_data_shift 0
829/* width of bitfield rss_key_wr_data[1f:0] */
830#define rpf_rss_key_wr_data_width 32
831/* default value of bitfield rss_key_wr_data[1f:0] */
832#define rpf_rss_key_wr_data_default 0x0
833
834/* rx rss_key_wr_en_i bitfield definitions
835 * preprocessor definitions for the bitfield "rss_key_wr_en_i".
836 * port="pif_rpf_rss_key_wr_en_i"
837 */
838
839/* register address for bitfield rss_key_wr_en_i */
840#define rpf_rss_key_wr_eni_adr 0x000054d0
841/* bitmask for bitfield rss_key_wr_en_i */
842#define rpf_rss_key_wr_eni_msk 0x00000020
843/* inverted bitmask for bitfield rss_key_wr_en_i */
844#define rpf_rss_key_wr_eni_mskn 0xffffffdf
845/* lower bit position of bitfield rss_key_wr_en_i */
846#define rpf_rss_key_wr_eni_shift 5
847/* width of bitfield rss_key_wr_en_i */
848#define rpf_rss_key_wr_eni_width 1
849/* default value of bitfield rss_key_wr_en_i */
850#define rpf_rss_key_wr_eni_default 0x0
851
852/* rx rss_redir_addr[3:0] bitfield definitions
853 * preprocessor definitions for the bitfield "rss_redir_addr[3:0]".
854 * port="pif_rpf_rss_redir_addr_i[3:0]"
855 */
856
857/* register address for bitfield rss_redir_addr[3:0] */
858#define rpf_rss_redir_addr_adr 0x000054e0
859/* bitmask for bitfield rss_redir_addr[3:0] */
860#define rpf_rss_redir_addr_msk 0x0000000f
861/* inverted bitmask for bitfield rss_redir_addr[3:0] */
862#define rpf_rss_redir_addr_mskn 0xfffffff0
863/* lower bit position of bitfield rss_redir_addr[3:0] */
864#define rpf_rss_redir_addr_shift 0
865/* width of bitfield rss_redir_addr[3:0] */
866#define rpf_rss_redir_addr_width 4
867/* default value of bitfield rss_redir_addr[3:0] */
868#define rpf_rss_redir_addr_default 0x0
869
870/* rx rss_redir_wr_data[f:0] bitfield definitions
871 * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]".
872 * port="pif_rpf_rss_redir_wr_data_i[15:0]"
873 */
874
875/* register address for bitfield rss_redir_wr_data[f:0] */
876#define rpf_rss_redir_wr_data_adr 0x000054e4
877/* bitmask for bitfield rss_redir_wr_data[f:0] */
878#define rpf_rss_redir_wr_data_msk 0x0000ffff
879/* inverted bitmask for bitfield rss_redir_wr_data[f:0] */
880#define rpf_rss_redir_wr_data_mskn 0xffff0000
881/* lower bit position of bitfield rss_redir_wr_data[f:0] */
882#define rpf_rss_redir_wr_data_shift 0
883/* width of bitfield rss_redir_wr_data[f:0] */
884#define rpf_rss_redir_wr_data_width 16
885/* default value of bitfield rss_redir_wr_data[f:0] */
886#define rpf_rss_redir_wr_data_default 0x0
887
888/* rx rss_redir_wr_en_i bitfield definitions
889 * preprocessor definitions for the bitfield "rss_redir_wr_en_i".
890 * port="pif_rpf_rss_redir_wr_en_i"
891 */
892
893/* register address for bitfield rss_redir_wr_en_i */
894#define rpf_rss_redir_wr_eni_adr 0x000054e0
895/* bitmask for bitfield rss_redir_wr_en_i */
896#define rpf_rss_redir_wr_eni_msk 0x00000010
897/* inverted bitmask for bitfield rss_redir_wr_en_i */
898#define rpf_rss_redir_wr_eni_mskn 0xffffffef
899/* lower bit position of bitfield rss_redir_wr_en_i */
900#define rpf_rss_redir_wr_eni_shift 4
901/* width of bitfield rss_redir_wr_en_i */
902#define rpf_rss_redir_wr_eni_width 1
903/* default value of bitfield rss_redir_wr_en_i */
904#define rpf_rss_redir_wr_eni_default 0x0
905
906/* rx tpo_rpf_sys_loopback bitfield definitions
907 * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback".
908 * port="pif_rpf_tpo_pkt_sys_lbk_i"
909 */
910
911/* register address for bitfield tpo_rpf_sys_loopback */
912#define rpf_tpo_rpf_sys_lbk_adr 0x00005000
913/* bitmask for bitfield tpo_rpf_sys_loopback */
914#define rpf_tpo_rpf_sys_lbk_msk 0x00000100
915/* inverted bitmask for bitfield tpo_rpf_sys_loopback */
916#define rpf_tpo_rpf_sys_lbk_mskn 0xfffffeff
917/* lower bit position of bitfield tpo_rpf_sys_loopback */
918#define rpf_tpo_rpf_sys_lbk_shift 8
919/* width of bitfield tpo_rpf_sys_loopback */
920#define rpf_tpo_rpf_sys_lbk_width 1
921/* default value of bitfield tpo_rpf_sys_loopback */
922#define rpf_tpo_rpf_sys_lbk_default 0x0
923
924/* rx vl_inner_tpid[f:0] bitfield definitions
925 * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]".
926 * port="pif_rpf_vl_inner_tpid_i[15:0]"
927 */
928
929/* register address for bitfield vl_inner_tpid[f:0] */
930#define rpf_vl_inner_tpid_adr 0x00005284
931/* bitmask for bitfield vl_inner_tpid[f:0] */
932#define rpf_vl_inner_tpid_msk 0x0000ffff
933/* inverted bitmask for bitfield vl_inner_tpid[f:0] */
934#define rpf_vl_inner_tpid_mskn 0xffff0000
935/* lower bit position of bitfield vl_inner_tpid[f:0] */
936#define rpf_vl_inner_tpid_shift 0
937/* width of bitfield vl_inner_tpid[f:0] */
938#define rpf_vl_inner_tpid_width 16
939/* default value of bitfield vl_inner_tpid[f:0] */
940#define rpf_vl_inner_tpid_default 0x8100
941
942/* rx vl_outer_tpid[f:0] bitfield definitions
943 * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]".
944 * port="pif_rpf_vl_outer_tpid_i[15:0]"
945 */
946
947/* register address for bitfield vl_outer_tpid[f:0] */
948#define rpf_vl_outer_tpid_adr 0x00005284
949/* bitmask for bitfield vl_outer_tpid[f:0] */
950#define rpf_vl_outer_tpid_msk 0xffff0000
951/* inverted bitmask for bitfield vl_outer_tpid[f:0] */
952#define rpf_vl_outer_tpid_mskn 0x0000ffff
953/* lower bit position of bitfield vl_outer_tpid[f:0] */
954#define rpf_vl_outer_tpid_shift 16
955/* width of bitfield vl_outer_tpid[f:0] */
956#define rpf_vl_outer_tpid_width 16
957/* default value of bitfield vl_outer_tpid[f:0] */
958#define rpf_vl_outer_tpid_default 0x88a8
959
960/* rx vl_promis_mode bitfield definitions
961 * preprocessor definitions for the bitfield "vl_promis_mode".
962 * port="pif_rpf_vl_promis_mode_i"
963 */
964
965/* register address for bitfield vl_promis_mode */
966#define rpf_vl_promis_mode_adr 0x00005280
967/* bitmask for bitfield vl_promis_mode */
968#define rpf_vl_promis_mode_msk 0x00000002
969/* inverted bitmask for bitfield vl_promis_mode */
970#define rpf_vl_promis_mode_mskn 0xfffffffd
971/* lower bit position of bitfield vl_promis_mode */
972#define rpf_vl_promis_mode_shift 1
973/* width of bitfield vl_promis_mode */
974#define rpf_vl_promis_mode_width 1
975/* default value of bitfield vl_promis_mode */
976#define rpf_vl_promis_mode_default 0x0
977
978/* RX vl_accept_untagged_mode Bitfield Definitions
979 * Preprocessor definitions for the bitfield "vl_accept_untagged_mode".
980 * PORT="pif_rpf_vl_accept_untagged_i"
981 */
982
983/* Register address for bitfield vl_accept_untagged_mode */
984#define rpf_vl_accept_untagged_mode_adr 0x00005280
985/* Bitmask for bitfield vl_accept_untagged_mode */
986#define rpf_vl_accept_untagged_mode_msk 0x00000004
987/* Inverted bitmask for bitfield vl_accept_untagged_mode */
988#define rpf_vl_accept_untagged_mode_mskn 0xFFFFFFFB
989/* Lower bit position of bitfield vl_accept_untagged_mode */
990#define rpf_vl_accept_untagged_mode_shift 2
991/* Width of bitfield vl_accept_untagged_mode */
992#define rpf_vl_accept_untagged_mode_width 1
993/* Default value of bitfield vl_accept_untagged_mode */
994#define rpf_vl_accept_untagged_mode_default 0x0
995
996/* rX vl_untagged_act[2:0] Bitfield Definitions
997 * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]".
998 * PORT="pif_rpf_vl_untagged_act_i[2:0]"
999 */
1000
1001/* Register address for bitfield vl_untagged_act[2:0] */
1002#define rpf_vl_untagged_act_adr 0x00005280
1003/* Bitmask for bitfield vl_untagged_act[2:0] */
1004#define rpf_vl_untagged_act_msk 0x00000038
1005/* Inverted bitmask for bitfield vl_untagged_act[2:0] */
1006#define rpf_vl_untagged_act_mskn 0xFFFFFFC7
1007/* Lower bit position of bitfield vl_untagged_act[2:0] */
1008#define rpf_vl_untagged_act_shift 3
1009/* Width of bitfield vl_untagged_act[2:0] */
1010#define rpf_vl_untagged_act_width 3
1011/* Default value of bitfield vl_untagged_act[2:0] */
1012#define rpf_vl_untagged_act_default 0x0
1013
1014/* RX vl_en{F} Bitfield Definitions
1015 * Preprocessor definitions for the bitfield "vl_en{F}".
1016 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1017 * PORT="pif_rpf_vl_en_i[0]"
1018 */
1019
1020/* Register address for bitfield vl_en{F} */
1021#define rpf_vl_en_f_adr(filter) (0x00005290 + (filter) * 0x4)
1022/* Bitmask for bitfield vl_en{F} */
1023#define rpf_vl_en_f_msk 0x80000000
1024/* Inverted bitmask for bitfield vl_en{F} */
1025#define rpf_vl_en_f_mskn 0x7FFFFFFF
1026/* Lower bit position of bitfield vl_en{F} */
1027#define rpf_vl_en_f_shift 31
1028/* Width of bitfield vl_en{F} */
1029#define rpf_vl_en_f_width 1
1030/* Default value of bitfield vl_en{F} */
1031#define rpf_vl_en_f_default 0x0
1032
1033/* RX vl_act{F}[2:0] Bitfield Definitions
1034 * Preprocessor definitions for the bitfield "vl_act{F}[2:0]".
1035 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1036 * PORT="pif_rpf_vl_act0_i[2:0]"
1037 */
1038
1039/* Register address for bitfield vl_act{F}[2:0] */
1040#define rpf_vl_act_f_adr(filter) (0x00005290 + (filter) * 0x4)
1041/* Bitmask for bitfield vl_act{F}[2:0] */
1042#define rpf_vl_act_f_msk 0x00070000
1043/* Inverted bitmask for bitfield vl_act{F}[2:0] */
1044#define rpf_vl_act_f_mskn 0xFFF8FFFF
1045/* Lower bit position of bitfield vl_act{F}[2:0] */
1046#define rpf_vl_act_f_shift 16
1047/* Width of bitfield vl_act{F}[2:0] */
1048#define rpf_vl_act_f_width 3
1049/* Default value of bitfield vl_act{F}[2:0] */
1050#define rpf_vl_act_f_default 0x0
1051
1052/* RX vl_id{F}[B:0] Bitfield Definitions
1053 * Preprocessor definitions for the bitfield "vl_id{F}[B:0]".
1054 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1055 * PORT="pif_rpf_vl_id0_i[11:0]"
1056 */
1057
1058/* Register address for bitfield vl_id{F}[B:0] */
1059#define rpf_vl_id_f_adr(filter) (0x00005290 + (filter) * 0x4)
1060/* Bitmask for bitfield vl_id{F}[B:0] */
1061#define rpf_vl_id_f_msk 0x00000FFF
1062/* Inverted bitmask for bitfield vl_id{F}[B:0] */
1063#define rpf_vl_id_f_mskn 0xFFFFF000
1064/* Lower bit position of bitfield vl_id{F}[B:0] */
1065#define rpf_vl_id_f_shift 0
1066/* Width of bitfield vl_id{F}[B:0] */
1067#define rpf_vl_id_f_width 12
1068/* Default value of bitfield vl_id{F}[B:0] */
1069#define rpf_vl_id_f_default 0x0
1070
1071/* RX et_en{F} Bitfield Definitions
1072 * Preprocessor definitions for the bitfield "et_en{F}".
1073 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1074 * PORT="pif_rpf_et_en_i[0]"
1075 */
1076
1077/* Register address for bitfield et_en{F} */
1078#define rpf_et_en_f_adr(filter) (0x00005300 + (filter) * 0x4)
1079/* Bitmask for bitfield et_en{F} */
1080#define rpf_et_en_f_msk 0x80000000
1081/* Inverted bitmask for bitfield et_en{F} */
1082#define rpf_et_en_f_mskn 0x7FFFFFFF
1083/* Lower bit position of bitfield et_en{F} */
1084#define rpf_et_en_f_shift 31
1085/* Width of bitfield et_en{F} */
1086#define rpf_et_en_f_width 1
1087/* Default value of bitfield et_en{F} */
1088#define rpf_et_en_f_default 0x0
1089
1090/* rx et_en{f} bitfield definitions
1091 * preprocessor definitions for the bitfield "et_en{f}".
1092 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1093 * port="pif_rpf_et_en_i[0]"
1094 */
1095
1096/* register address for bitfield et_en{f} */
1097#define rpf_et_enf_adr(filter) (0x00005300 + (filter) * 0x4)
1098/* bitmask for bitfield et_en{f} */
1099#define rpf_et_enf_msk 0x80000000
1100/* inverted bitmask for bitfield et_en{f} */
1101#define rpf_et_enf_mskn 0x7fffffff
1102/* lower bit position of bitfield et_en{f} */
1103#define rpf_et_enf_shift 31
1104/* width of bitfield et_en{f} */
1105#define rpf_et_enf_width 1
1106/* default value of bitfield et_en{f} */
1107#define rpf_et_enf_default 0x0
1108
1109/* rx et_up{f}_en bitfield definitions
1110 * preprocessor definitions for the bitfield "et_up{f}_en".
1111 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1112 * port="pif_rpf_et_up_en_i[0]"
1113 */
1114
1115/* register address for bitfield et_up{f}_en */
1116#define rpf_et_upfen_adr(filter) (0x00005300 + (filter) * 0x4)
1117/* bitmask for bitfield et_up{f}_en */
1118#define rpf_et_upfen_msk 0x40000000
1119/* inverted bitmask for bitfield et_up{f}_en */
1120#define rpf_et_upfen_mskn 0xbfffffff
1121/* lower bit position of bitfield et_up{f}_en */
1122#define rpf_et_upfen_shift 30
1123/* width of bitfield et_up{f}_en */
1124#define rpf_et_upfen_width 1
1125/* default value of bitfield et_up{f}_en */
1126#define rpf_et_upfen_default 0x0
1127
1128/* rx et_rxq{f}_en bitfield definitions
1129 * preprocessor definitions for the bitfield "et_rxq{f}_en".
1130 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1131 * port="pif_rpf_et_rxq_en_i[0]"
1132 */
1133
1134/* register address for bitfield et_rxq{f}_en */
1135#define rpf_et_rxqfen_adr(filter) (0x00005300 + (filter) * 0x4)
1136/* bitmask for bitfield et_rxq{f}_en */
1137#define rpf_et_rxqfen_msk 0x20000000
1138/* inverted bitmask for bitfield et_rxq{f}_en */
1139#define rpf_et_rxqfen_mskn 0xdfffffff
1140/* lower bit position of bitfield et_rxq{f}_en */
1141#define rpf_et_rxqfen_shift 29
1142/* width of bitfield et_rxq{f}_en */
1143#define rpf_et_rxqfen_width 1
1144/* default value of bitfield et_rxq{f}_en */
1145#define rpf_et_rxqfen_default 0x0
1146
1147/* rx et_up{f}[2:0] bitfield definitions
1148 * preprocessor definitions for the bitfield "et_up{f}[2:0]".
1149 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1150 * port="pif_rpf_et_up0_i[2:0]"
1151 */
1152
1153/* register address for bitfield et_up{f}[2:0] */
1154#define rpf_et_upf_adr(filter) (0x00005300 + (filter) * 0x4)
1155/* bitmask for bitfield et_up{f}[2:0] */
1156#define rpf_et_upf_msk 0x1c000000
1157/* inverted bitmask for bitfield et_up{f}[2:0] */
1158#define rpf_et_upf_mskn 0xe3ffffff
1159/* lower bit position of bitfield et_up{f}[2:0] */
1160#define rpf_et_upf_shift 26
1161/* width of bitfield et_up{f}[2:0] */
1162#define rpf_et_upf_width 3
1163/* default value of bitfield et_up{f}[2:0] */
1164#define rpf_et_upf_default 0x0
1165
1166/* rx et_rxq{f}[4:0] bitfield definitions
1167 * preprocessor definitions for the bitfield "et_rxq{f}[4:0]".
1168 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1169 * port="pif_rpf_et_rxq0_i[4:0]"
1170 */
1171
1172/* register address for bitfield et_rxq{f}[4:0] */
1173#define rpf_et_rxqf_adr(filter) (0x00005300 + (filter) * 0x4)
1174/* bitmask for bitfield et_rxq{f}[4:0] */
1175#define rpf_et_rxqf_msk 0x01f00000
1176/* inverted bitmask for bitfield et_rxq{f}[4:0] */
1177#define rpf_et_rxqf_mskn 0xfe0fffff
1178/* lower bit position of bitfield et_rxq{f}[4:0] */
1179#define rpf_et_rxqf_shift 20
1180/* width of bitfield et_rxq{f}[4:0] */
1181#define rpf_et_rxqf_width 5
1182/* default value of bitfield et_rxq{f}[4:0] */
1183#define rpf_et_rxqf_default 0x0
1184
1185/* rx et_mng_rxq{f} bitfield definitions
1186 * preprocessor definitions for the bitfield "et_mng_rxq{f}".
1187 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1188 * port="pif_rpf_et_mng_rxq_i[0]"
1189 */
1190
1191/* register address for bitfield et_mng_rxq{f} */
1192#define rpf_et_mng_rxqf_adr(filter) (0x00005300 + (filter) * 0x4)
1193/* bitmask for bitfield et_mng_rxq{f} */
1194#define rpf_et_mng_rxqf_msk 0x00080000
1195/* inverted bitmask for bitfield et_mng_rxq{f} */
1196#define rpf_et_mng_rxqf_mskn 0xfff7ffff
1197/* lower bit position of bitfield et_mng_rxq{f} */
1198#define rpf_et_mng_rxqf_shift 19
1199/* width of bitfield et_mng_rxq{f} */
1200#define rpf_et_mng_rxqf_width 1
1201/* default value of bitfield et_mng_rxq{f} */
1202#define rpf_et_mng_rxqf_default 0x0
1203
1204/* rx et_act{f}[2:0] bitfield definitions
1205 * preprocessor definitions for the bitfield "et_act{f}[2:0]".
1206 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1207 * port="pif_rpf_et_act0_i[2:0]"
1208 */
1209
1210/* register address for bitfield et_act{f}[2:0] */
1211#define rpf_et_actf_adr(filter) (0x00005300 + (filter) * 0x4)
1212/* bitmask for bitfield et_act{f}[2:0] */
1213#define rpf_et_actf_msk 0x00070000
1214/* inverted bitmask for bitfield et_act{f}[2:0] */
1215#define rpf_et_actf_mskn 0xfff8ffff
1216/* lower bit position of bitfield et_act{f}[2:0] */
1217#define rpf_et_actf_shift 16
1218/* width of bitfield et_act{f}[2:0] */
1219#define rpf_et_actf_width 3
1220/* default value of bitfield et_act{f}[2:0] */
1221#define rpf_et_actf_default 0x0
1222
1223/* rx et_val{f}[f:0] bitfield definitions
1224 * preprocessor definitions for the bitfield "et_val{f}[f:0]".
1225 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1226 * port="pif_rpf_et_val0_i[15:0]"
1227 */
1228
1229/* register address for bitfield et_val{f}[f:0] */
1230#define rpf_et_valf_adr(filter) (0x00005300 + (filter) * 0x4)
1231/* bitmask for bitfield et_val{f}[f:0] */
1232#define rpf_et_valf_msk 0x0000ffff
1233/* inverted bitmask for bitfield et_val{f}[f:0] */
1234#define rpf_et_valf_mskn 0xffff0000
1235/* lower bit position of bitfield et_val{f}[f:0] */
1236#define rpf_et_valf_shift 0
1237/* width of bitfield et_val{f}[f:0] */
1238#define rpf_et_valf_width 16
1239/* default value of bitfield et_val{f}[f:0] */
1240#define rpf_et_valf_default 0x0
1241
1242/* rx ipv4_chk_en bitfield definitions
1243 * preprocessor definitions for the bitfield "ipv4_chk_en".
1244 * port="pif_rpo_ipv4_chk_en_i"
1245 */
1246
1247/* register address for bitfield ipv4_chk_en */
1248#define rpo_ipv4chk_en_adr 0x00005580
1249/* bitmask for bitfield ipv4_chk_en */
1250#define rpo_ipv4chk_en_msk 0x00000002
1251/* inverted bitmask for bitfield ipv4_chk_en */
1252#define rpo_ipv4chk_en_mskn 0xfffffffd
1253/* lower bit position of bitfield ipv4_chk_en */
1254#define rpo_ipv4chk_en_shift 1
1255/* width of bitfield ipv4_chk_en */
1256#define rpo_ipv4chk_en_width 1
1257/* default value of bitfield ipv4_chk_en */
1258#define rpo_ipv4chk_en_default 0x0
1259
1260/* rx desc{d}_vl_strip bitfield definitions
1261 * preprocessor definitions for the bitfield "desc{d}_vl_strip".
1262 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
1263 * port="pif_rpo_desc_vl_strip_i[0]"
1264 */
1265
1266/* register address for bitfield desc{d}_vl_strip */
1267#define rpo_descdvl_strip_adr(descriptor) (0x00005b08 + (descriptor) * 0x20)
1268/* bitmask for bitfield desc{d}_vl_strip */
1269#define rpo_descdvl_strip_msk 0x20000000
1270/* inverted bitmask for bitfield desc{d}_vl_strip */
1271#define rpo_descdvl_strip_mskn 0xdfffffff
1272/* lower bit position of bitfield desc{d}_vl_strip */
1273#define rpo_descdvl_strip_shift 29
1274/* width of bitfield desc{d}_vl_strip */
1275#define rpo_descdvl_strip_width 1
1276/* default value of bitfield desc{d}_vl_strip */
1277#define rpo_descdvl_strip_default 0x0
1278
1279/* rx l4_chk_en bitfield definitions
1280 * preprocessor definitions for the bitfield "l4_chk_en".
1281 * port="pif_rpo_l4_chk_en_i"
1282 */
1283
1284/* register address for bitfield l4_chk_en */
1285#define rpol4chk_en_adr 0x00005580
1286/* bitmask for bitfield l4_chk_en */
1287#define rpol4chk_en_msk 0x00000001
1288/* inverted bitmask for bitfield l4_chk_en */
1289#define rpol4chk_en_mskn 0xfffffffe
1290/* lower bit position of bitfield l4_chk_en */
1291#define rpol4chk_en_shift 0
1292/* width of bitfield l4_chk_en */
1293#define rpol4chk_en_width 1
1294/* default value of bitfield l4_chk_en */
1295#define rpol4chk_en_default 0x0
1296
1297/* rx reg_res_dsbl bitfield definitions
1298 * preprocessor definitions for the bitfield "reg_res_dsbl".
1299 * port="pif_rx_reg_res_dsbl_i"
1300 */
1301
1302/* register address for bitfield reg_res_dsbl */
1303#define rx_reg_res_dsbl_adr 0x00005000
1304/* bitmask for bitfield reg_res_dsbl */
1305#define rx_reg_res_dsbl_msk 0x20000000
1306/* inverted bitmask for bitfield reg_res_dsbl */
1307#define rx_reg_res_dsbl_mskn 0xdfffffff
1308/* lower bit position of bitfield reg_res_dsbl */
1309#define rx_reg_res_dsbl_shift 29
1310/* width of bitfield reg_res_dsbl */
1311#define rx_reg_res_dsbl_width 1
1312/* default value of bitfield reg_res_dsbl */
1313#define rx_reg_res_dsbl_default 0x1
1314
1315/* tx dca{d}_cpuid[7:0] bitfield definitions
1316 * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]".
1317 * parameter: dca {d} | stride size 0x4 | range [0, 31]
1318 * port="pif_tdm_dca0_cpuid_i[7:0]"
1319 */
1320
1321/* register address for bitfield dca{d}_cpuid[7:0] */
1322#define tdm_dcadcpuid_adr(dca) (0x00008400 + (dca) * 0x4)
1323/* bitmask for bitfield dca{d}_cpuid[7:0] */
1324#define tdm_dcadcpuid_msk 0x000000ff
1325/* inverted bitmask for bitfield dca{d}_cpuid[7:0] */
1326#define tdm_dcadcpuid_mskn 0xffffff00
1327/* lower bit position of bitfield dca{d}_cpuid[7:0] */
1328#define tdm_dcadcpuid_shift 0
1329/* width of bitfield dca{d}_cpuid[7:0] */
1330#define tdm_dcadcpuid_width 8
1331/* default value of bitfield dca{d}_cpuid[7:0] */
1332#define tdm_dcadcpuid_default 0x0
1333
1334/* tx lso_en[1f:0] bitfield definitions
1335 * preprocessor definitions for the bitfield "lso_en[1f:0]".
1336 * port="pif_tdm_lso_en_i[31:0]"
1337 */
1338
1339/* register address for bitfield lso_en[1f:0] */
1340#define tdm_lso_en_adr 0x00007810
1341/* bitmask for bitfield lso_en[1f:0] */
1342#define tdm_lso_en_msk 0xffffffff
1343/* inverted bitmask for bitfield lso_en[1f:0] */
1344#define tdm_lso_en_mskn 0x00000000
1345/* lower bit position of bitfield lso_en[1f:0] */
1346#define tdm_lso_en_shift 0
1347/* width of bitfield lso_en[1f:0] */
1348#define tdm_lso_en_width 32
1349/* default value of bitfield lso_en[1f:0] */
1350#define tdm_lso_en_default 0x0
1351
1352/* tx dca_en bitfield definitions
1353 * preprocessor definitions for the bitfield "dca_en".
1354 * port="pif_tdm_dca_en_i"
1355 */
1356
1357/* register address for bitfield dca_en */
1358#define tdm_dca_en_adr 0x00008480
1359/* bitmask for bitfield dca_en */
1360#define tdm_dca_en_msk 0x80000000
1361/* inverted bitmask for bitfield dca_en */
1362#define tdm_dca_en_mskn 0x7fffffff
1363/* lower bit position of bitfield dca_en */
1364#define tdm_dca_en_shift 31
1365/* width of bitfield dca_en */
1366#define tdm_dca_en_width 1
1367/* default value of bitfield dca_en */
1368#define tdm_dca_en_default 0x1
1369
1370/* tx dca_mode[3:0] bitfield definitions
1371 * preprocessor definitions for the bitfield "dca_mode[3:0]".
1372 * port="pif_tdm_dca_mode_i[3:0]"
1373 */
1374
1375/* register address for bitfield dca_mode[3:0] */
1376#define tdm_dca_mode_adr 0x00008480
1377/* bitmask for bitfield dca_mode[3:0] */
1378#define tdm_dca_mode_msk 0x0000000f
1379/* inverted bitmask for bitfield dca_mode[3:0] */
1380#define tdm_dca_mode_mskn 0xfffffff0
1381/* lower bit position of bitfield dca_mode[3:0] */
1382#define tdm_dca_mode_shift 0
1383/* width of bitfield dca_mode[3:0] */
1384#define tdm_dca_mode_width 4
1385/* default value of bitfield dca_mode[3:0] */
1386#define tdm_dca_mode_default 0x0
1387
1388/* tx dca{d}_desc_en bitfield definitions
1389 * preprocessor definitions for the bitfield "dca{d}_desc_en".
1390 * parameter: dca {d} | stride size 0x4 | range [0, 31]
1391 * port="pif_tdm_dca_desc_en_i[0]"
1392 */
1393
1394/* register address for bitfield dca{d}_desc_en */
1395#define tdm_dcaddesc_en_adr(dca) (0x00008400 + (dca) * 0x4)
1396/* bitmask for bitfield dca{d}_desc_en */
1397#define tdm_dcaddesc_en_msk 0x80000000
1398/* inverted bitmask for bitfield dca{d}_desc_en */
1399#define tdm_dcaddesc_en_mskn 0x7fffffff
1400/* lower bit position of bitfield dca{d}_desc_en */
1401#define tdm_dcaddesc_en_shift 31
1402/* width of bitfield dca{d}_desc_en */
1403#define tdm_dcaddesc_en_width 1
1404/* default value of bitfield dca{d}_desc_en */
1405#define tdm_dcaddesc_en_default 0x0
1406
1407/* tx desc{d}_en bitfield definitions
1408 * preprocessor definitions for the bitfield "desc{d}_en".
1409 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
1410 * port="pif_tdm_desc_en_i[0]"
1411 */
1412
1413/* register address for bitfield desc{d}_en */
1414#define tdm_descden_adr(descriptor) (0x00007c08 + (descriptor) * 0x40)
1415/* bitmask for bitfield desc{d}_en */
1416#define tdm_descden_msk 0x80000000
1417/* inverted bitmask for bitfield desc{d}_en */
1418#define tdm_descden_mskn 0x7fffffff
1419/* lower bit position of bitfield desc{d}_en */
1420#define tdm_descden_shift 31
1421/* width of bitfield desc{d}_en */
1422#define tdm_descden_width 1
1423/* default value of bitfield desc{d}_en */
1424#define tdm_descden_default 0x0
1425
1426/* tx desc{d}_hd[c:0] bitfield definitions
1427 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]".
1428 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
1429 * port="tdm_pif_desc0_hd_o[12:0]"
1430 */
1431
1432/* register address for bitfield desc{d}_hd[c:0] */
1433#define tdm_descdhd_adr(descriptor) (0x00007c0c + (descriptor) * 0x40)
1434/* bitmask for bitfield desc{d}_hd[c:0] */
1435#define tdm_descdhd_msk 0x00001fff
1436/* inverted bitmask for bitfield desc{d}_hd[c:0] */
1437#define tdm_descdhd_mskn 0xffffe000
1438/* lower bit position of bitfield desc{d}_hd[c:0] */
1439#define tdm_descdhd_shift 0
1440/* width of bitfield desc{d}_hd[c:0] */
1441#define tdm_descdhd_width 13
1442
1443/* tx desc{d}_len[9:0] bitfield definitions
1444 * preprocessor definitions for the bitfield "desc{d}_len[9:0]".
1445 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
1446 * port="pif_tdm_desc0_len_i[9:0]"
1447 */
1448
1449/* register address for bitfield desc{d}_len[9:0] */
1450#define tdm_descdlen_adr(descriptor) (0x00007c08 + (descriptor) * 0x40)
1451/* bitmask for bitfield desc{d}_len[9:0] */
1452#define tdm_descdlen_msk 0x00001ff8
1453/* inverted bitmask for bitfield desc{d}_len[9:0] */
1454#define tdm_descdlen_mskn 0xffffe007
1455/* lower bit position of bitfield desc{d}_len[9:0] */
1456#define tdm_descdlen_shift 3
1457/* width of bitfield desc{d}_len[9:0] */
1458#define tdm_descdlen_width 10
1459/* default value of bitfield desc{d}_len[9:0] */
1460#define tdm_descdlen_default 0x0
1461
1462/* tx int_desc_wrb_en bitfield definitions
1463 * preprocessor definitions for the bitfield "int_desc_wrb_en".
1464 * port="pif_tdm_int_desc_wrb_en_i"
1465 */
1466
1467/* register address for bitfield int_desc_wrb_en */
1468#define tdm_int_desc_wrb_en_adr 0x00007b40
1469/* bitmask for bitfield int_desc_wrb_en */
1470#define tdm_int_desc_wrb_en_msk 0x00000002
1471/* inverted bitmask for bitfield int_desc_wrb_en */
1472#define tdm_int_desc_wrb_en_mskn 0xfffffffd
1473/* lower bit position of bitfield int_desc_wrb_en */
1474#define tdm_int_desc_wrb_en_shift 1
1475/* width of bitfield int_desc_wrb_en */
1476#define tdm_int_desc_wrb_en_width 1
1477/* default value of bitfield int_desc_wrb_en */
1478#define tdm_int_desc_wrb_en_default 0x0
1479
1480/* tx desc{d}_wrb_thresh[6:0] bitfield definitions
1481 * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]".
1482 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
1483 * port="pif_tdm_desc0_wrb_thresh_i[6:0]"
1484 */
1485
1486/* register address for bitfield desc{d}_wrb_thresh[6:0] */
1487#define tdm_descdwrb_thresh_adr(descriptor) (0x00007c18 + (descriptor) * 0x40)
1488/* bitmask for bitfield desc{d}_wrb_thresh[6:0] */
1489#define tdm_descdwrb_thresh_msk 0x00007f00
1490/* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */
1491#define tdm_descdwrb_thresh_mskn 0xffff80ff
1492/* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */
1493#define tdm_descdwrb_thresh_shift 8
1494/* width of bitfield desc{d}_wrb_thresh[6:0] */
1495#define tdm_descdwrb_thresh_width 7
1496/* default value of bitfield desc{d}_wrb_thresh[6:0] */
1497#define tdm_descdwrb_thresh_default 0x0
1498
1499/* tx lso_tcp_flag_first[b:0] bitfield definitions
1500 * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]".
1501 * port="pif_thm_lso_tcp_flag_first_i[11:0]"
1502 */
1503
1504/* register address for bitfield lso_tcp_flag_first[b:0] */
1505#define thm_lso_tcp_flag_first_adr 0x00007820
1506/* bitmask for bitfield lso_tcp_flag_first[b:0] */
1507#define thm_lso_tcp_flag_first_msk 0x00000fff
1508/* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */
1509#define thm_lso_tcp_flag_first_mskn 0xfffff000
1510/* lower bit position of bitfield lso_tcp_flag_first[b:0] */
1511#define thm_lso_tcp_flag_first_shift 0
1512/* width of bitfield lso_tcp_flag_first[b:0] */
1513#define thm_lso_tcp_flag_first_width 12
1514/* default value of bitfield lso_tcp_flag_first[b:0] */
1515#define thm_lso_tcp_flag_first_default 0x0
1516
1517/* tx lso_tcp_flag_last[b:0] bitfield definitions
1518 * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]".
1519 * port="pif_thm_lso_tcp_flag_last_i[11:0]"
1520 */
1521
1522/* register address for bitfield lso_tcp_flag_last[b:0] */
1523#define thm_lso_tcp_flag_last_adr 0x00007824
1524/* bitmask for bitfield lso_tcp_flag_last[b:0] */
1525#define thm_lso_tcp_flag_last_msk 0x00000fff
1526/* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */
1527#define thm_lso_tcp_flag_last_mskn 0xfffff000
1528/* lower bit position of bitfield lso_tcp_flag_last[b:0] */
1529#define thm_lso_tcp_flag_last_shift 0
1530/* width of bitfield lso_tcp_flag_last[b:0] */
1531#define thm_lso_tcp_flag_last_width 12
1532/* default value of bitfield lso_tcp_flag_last[b:0] */
1533#define thm_lso_tcp_flag_last_default 0x0
1534
1535/* tx lso_tcp_flag_mid[b:0] bitfield definitions
1536 * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]".
1537 * port="pif_thm_lso_tcp_flag_mid_i[11:0]"
1538 */
1539
1540/* Register address for bitfield lro_rsc_max[1F:0] */
1541#define rpo_lro_rsc_max_adr 0x00005598
1542/* Bitmask for bitfield lro_rsc_max[1F:0] */
1543#define rpo_lro_rsc_max_msk 0xFFFFFFFF
1544/* Inverted bitmask for bitfield lro_rsc_max[1F:0] */
1545#define rpo_lro_rsc_max_mskn 0x00000000
1546/* Lower bit position of bitfield lro_rsc_max[1F:0] */
1547#define rpo_lro_rsc_max_shift 0
1548/* Width of bitfield lro_rsc_max[1F:0] */
1549#define rpo_lro_rsc_max_width 32
1550/* Default value of bitfield lro_rsc_max[1F:0] */
1551#define rpo_lro_rsc_max_default 0x0
1552
1553/* RX lro_en[1F:0] Bitfield Definitions
1554 * Preprocessor definitions for the bitfield "lro_en[1F:0]".
1555 * PORT="pif_rpo_lro_en_i[31:0]"
1556 */
1557
1558/* Register address for bitfield lro_en[1F:0] */
1559#define rpo_lro_en_adr 0x00005590
1560/* Bitmask for bitfield lro_en[1F:0] */
1561#define rpo_lro_en_msk 0xFFFFFFFF
1562/* Inverted bitmask for bitfield lro_en[1F:0] */
1563#define rpo_lro_en_mskn 0x00000000
1564/* Lower bit position of bitfield lro_en[1F:0] */
1565#define rpo_lro_en_shift 0
1566/* Width of bitfield lro_en[1F:0] */
1567#define rpo_lro_en_width 32
1568/* Default value of bitfield lro_en[1F:0] */
1569#define rpo_lro_en_default 0x0
1570
1571/* RX lro_ptopt_en Bitfield Definitions
1572 * Preprocessor definitions for the bitfield "lro_ptopt_en".
1573 * PORT="pif_rpo_lro_ptopt_en_i"
1574 */
1575
1576/* Register address for bitfield lro_ptopt_en */
1577#define rpo_lro_ptopt_en_adr 0x00005594
1578/* Bitmask for bitfield lro_ptopt_en */
1579#define rpo_lro_ptopt_en_msk 0x00008000
1580/* Inverted bitmask for bitfield lro_ptopt_en */
1581#define rpo_lro_ptopt_en_mskn 0xFFFF7FFF
1582/* Lower bit position of bitfield lro_ptopt_en */
1583#define rpo_lro_ptopt_en_shift 15
1584/* Width of bitfield lro_ptopt_en */
1585#define rpo_lro_ptopt_en_width 1
1586/* Default value of bitfield lro_ptopt_en */
1587#define rpo_lro_ptopt_en_defalt 0x1
1588
1589/* RX lro_q_ses_lmt Bitfield Definitions
1590 * Preprocessor definitions for the bitfield "lro_q_ses_lmt".
1591 * PORT="pif_rpo_lro_q_ses_lmt_i[1:0]"
1592 */
1593
1594/* Register address for bitfield lro_q_ses_lmt */
1595#define rpo_lro_qses_lmt_adr 0x00005594
1596/* Bitmask for bitfield lro_q_ses_lmt */
1597#define rpo_lro_qses_lmt_msk 0x00003000
1598/* Inverted bitmask for bitfield lro_q_ses_lmt */
1599#define rpo_lro_qses_lmt_mskn 0xFFFFCFFF
1600/* Lower bit position of bitfield lro_q_ses_lmt */
1601#define rpo_lro_qses_lmt_shift 12
1602/* Width of bitfield lro_q_ses_lmt */
1603#define rpo_lro_qses_lmt_width 2
1604/* Default value of bitfield lro_q_ses_lmt */
1605#define rpo_lro_qses_lmt_default 0x1
1606
1607/* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions
1608 * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]".
1609 * PORT="pif_rpo_lro_tot_dsc_lmt_i[1:0]"
1610 */
1611
1612/* Register address for bitfield lro_tot_dsc_lmt[1:0] */
1613#define rpo_lro_tot_dsc_lmt_adr 0x00005594
1614/* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */
1615#define rpo_lro_tot_dsc_lmt_msk 0x00000060
1616/* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */
1617#define rpo_lro_tot_dsc_lmt_mskn 0xFFFFFF9F
1618/* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */
1619#define rpo_lro_tot_dsc_lmt_shift 5
1620/* Width of bitfield lro_tot_dsc_lmt[1:0] */
1621#define rpo_lro_tot_dsc_lmt_width 2
1622/* Default value of bitfield lro_tot_dsc_lmt[1:0] */
1623#define rpo_lro_tot_dsc_lmt_defalt 0x1
1624
1625/* RX lro_pkt_min[4:0] Bitfield Definitions
1626 * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]".
1627 * PORT="pif_rpo_lro_pkt_min_i[4:0]"
1628 */
1629
1630/* Register address for bitfield lro_pkt_min[4:0] */
1631#define rpo_lro_pkt_min_adr 0x00005594
1632/* Bitmask for bitfield lro_pkt_min[4:0] */
1633#define rpo_lro_pkt_min_msk 0x0000001F
1634/* Inverted bitmask for bitfield lro_pkt_min[4:0] */
1635#define rpo_lro_pkt_min_mskn 0xFFFFFFE0
1636/* Lower bit position of bitfield lro_pkt_min[4:0] */
1637#define rpo_lro_pkt_min_shift 0
1638/* Width of bitfield lro_pkt_min[4:0] */
1639#define rpo_lro_pkt_min_width 5
1640/* Default value of bitfield lro_pkt_min[4:0] */
1641#define rpo_lro_pkt_min_default 0x8
1642
1643/* Width of bitfield lro{L}_des_max[1:0] */
1644#define rpo_lro_ldes_max_width 2
1645/* Default value of bitfield lro{L}_des_max[1:0] */
1646#define rpo_lro_ldes_max_default 0x0
1647
1648/* RX lro_tb_div[11:0] Bitfield Definitions
1649 * Preprocessor definitions for the bitfield "lro_tb_div[11:0]".
1650 * PORT="pif_rpo_lro_tb_div_i[11:0]"
1651 */
1652
1653/* Register address for bitfield lro_tb_div[11:0] */
1654#define rpo_lro_tb_div_adr 0x00005620
1655/* Bitmask for bitfield lro_tb_div[11:0] */
1656#define rpo_lro_tb_div_msk 0xFFF00000
1657/* Inverted bitmask for bitfield lro_tb_div[11:0] */
1658#define rpo_lro_tb_div_mskn 0x000FFFFF
1659/* Lower bit position of bitfield lro_tb_div[11:0] */
1660#define rpo_lro_tb_div_shift 20
1661/* Width of bitfield lro_tb_div[11:0] */
1662#define rpo_lro_tb_div_width 12
1663/* Default value of bitfield lro_tb_div[11:0] */
1664#define rpo_lro_tb_div_default 0xC35
1665
1666/* RX lro_ina_ival[9:0] Bitfield Definitions
1667 * Preprocessor definitions for the bitfield "lro_ina_ival[9:0]".
1668 * PORT="pif_rpo_lro_ina_ival_i[9:0]"
1669 */
1670
1671/* Register address for bitfield lro_ina_ival[9:0] */
1672#define rpo_lro_ina_ival_adr 0x00005620
1673/* Bitmask for bitfield lro_ina_ival[9:0] */
1674#define rpo_lro_ina_ival_msk 0x000FFC00
1675/* Inverted bitmask for bitfield lro_ina_ival[9:0] */
1676#define rpo_lro_ina_ival_mskn 0xFFF003FF
1677/* Lower bit position of bitfield lro_ina_ival[9:0] */
1678#define rpo_lro_ina_ival_shift 10
1679/* Width of bitfield lro_ina_ival[9:0] */
1680#define rpo_lro_ina_ival_width 10
1681/* Default value of bitfield lro_ina_ival[9:0] */
1682#define rpo_lro_ina_ival_default 0xA
1683
1684/* RX lro_max_ival[9:0] Bitfield Definitions
1685 * Preprocessor definitions for the bitfield "lro_max_ival[9:0]".
1686 * PORT="pif_rpo_lro_max_ival_i[9:0]"
1687 */
1688
1689/* Register address for bitfield lro_max_ival[9:0] */
1690#define rpo_lro_max_ival_adr 0x00005620
1691/* Bitmask for bitfield lro_max_ival[9:0] */
1692#define rpo_lro_max_ival_msk 0x000003FF
1693/* Inverted bitmask for bitfield lro_max_ival[9:0] */
1694#define rpo_lro_max_ival_mskn 0xFFFFFC00
1695/* Lower bit position of bitfield lro_max_ival[9:0] */
1696#define rpo_lro_max_ival_shift 0
1697/* Width of bitfield lro_max_ival[9:0] */
1698#define rpo_lro_max_ival_width 10
1699/* Default value of bitfield lro_max_ival[9:0] */
1700#define rpo_lro_max_ival_default 0x19
1701
1702/* TX dca{D}_cpuid[7:0] Bitfield Definitions
1703 * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]".
1704 * Parameter: DCA {D} | stride size 0x4 | range [0, 31]
1705 * PORT="pif_tdm_dca0_cpuid_i[7:0]"
1706 */
1707
1708/* Register address for bitfield dca{D}_cpuid[7:0] */
1709#define tdm_dca_dcpuid_adr(dca) (0x00008400 + (dca) * 0x4)
1710/* Bitmask for bitfield dca{D}_cpuid[7:0] */
1711#define tdm_dca_dcpuid_msk 0x000000FF
1712/* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */
1713#define tdm_dca_dcpuid_mskn 0xFFFFFF00
1714/* Lower bit position of bitfield dca{D}_cpuid[7:0] */
1715#define tdm_dca_dcpuid_shift 0
1716/* Width of bitfield dca{D}_cpuid[7:0] */
1717#define tdm_dca_dcpuid_width 8
1718/* Default value of bitfield dca{D}_cpuid[7:0] */
1719#define tdm_dca_dcpuid_default 0x0
1720
1721/* TX dca{D}_desc_en Bitfield Definitions
1722 * Preprocessor definitions for the bitfield "dca{D}_desc_en".
1723 * Parameter: DCA {D} | stride size 0x4 | range [0, 31]
1724 * PORT="pif_tdm_dca_desc_en_i[0]"
1725 */
1726
1727/* Register address for bitfield dca{D}_desc_en */
1728#define tdm_dca_ddesc_en_adr(dca) (0x00008400 + (dca) * 0x4)
1729/* Bitmask for bitfield dca{D}_desc_en */
1730#define tdm_dca_ddesc_en_msk 0x80000000
1731/* Inverted bitmask for bitfield dca{D}_desc_en */
1732#define tdm_dca_ddesc_en_mskn 0x7FFFFFFF
1733/* Lower bit position of bitfield dca{D}_desc_en */
1734#define tdm_dca_ddesc_en_shift 31
1735/* Width of bitfield dca{D}_desc_en */
1736#define tdm_dca_ddesc_en_width 1
1737/* Default value of bitfield dca{D}_desc_en */
1738#define tdm_dca_ddesc_en_default 0x0
1739
1740/* TX desc{D}_en Bitfield Definitions
1741 * Preprocessor definitions for the bitfield "desc{D}_en".
1742 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]
1743 * PORT="pif_tdm_desc_en_i[0]"
1744 */
1745
1746/* Register address for bitfield desc{D}_en */
1747#define tdm_desc_den_adr(descriptor) (0x00007C08 + (descriptor) * 0x40)
1748/* Bitmask for bitfield desc{D}_en */
1749#define tdm_desc_den_msk 0x80000000
1750/* Inverted bitmask for bitfield desc{D}_en */
1751#define tdm_desc_den_mskn 0x7FFFFFFF
1752/* Lower bit position of bitfield desc{D}_en */
1753#define tdm_desc_den_shift 31
1754/* Width of bitfield desc{D}_en */
1755#define tdm_desc_den_width 1
1756/* Default value of bitfield desc{D}_en */
1757#define tdm_desc_den_default 0x0
1758
1759/* TX desc{D}_hd[C:0] Bitfield Definitions
1760 * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]".
1761 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]
1762 * PORT="tdm_pif_desc0_hd_o[12:0]"
1763 */
1764
1765/* Register address for bitfield desc{D}_hd[C:0] */
1766#define tdm_desc_dhd_adr(descriptor) (0x00007C0C + (descriptor) * 0x40)
1767/* Bitmask for bitfield desc{D}_hd[C:0] */
1768#define tdm_desc_dhd_msk 0x00001FFF
1769/* Inverted bitmask for bitfield desc{D}_hd[C:0] */
1770#define tdm_desc_dhd_mskn 0xFFFFE000
1771/* Lower bit position of bitfield desc{D}_hd[C:0] */
1772#define tdm_desc_dhd_shift 0
1773/* Width of bitfield desc{D}_hd[C:0] */
1774#define tdm_desc_dhd_width 13
1775
1776/* TX desc{D}_len[9:0] Bitfield Definitions
1777 * Preprocessor definitions for the bitfield "desc{D}_len[9:0]".
1778 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]
1779 * PORT="pif_tdm_desc0_len_i[9:0]"
1780 */
1781
1782/* Register address for bitfield desc{D}_len[9:0] */
1783#define tdm_desc_dlen_adr(descriptor) (0x00007C08 + (descriptor) * 0x40)
1784/* Bitmask for bitfield desc{D}_len[9:0] */
1785#define tdm_desc_dlen_msk 0x00001FF8
1786/* Inverted bitmask for bitfield desc{D}_len[9:0] */
1787#define tdm_desc_dlen_mskn 0xFFFFE007
1788/* Lower bit position of bitfield desc{D}_len[9:0] */
1789#define tdm_desc_dlen_shift 3
1790/* Width of bitfield desc{D}_len[9:0] */
1791#define tdm_desc_dlen_width 10
1792/* Default value of bitfield desc{D}_len[9:0] */
1793#define tdm_desc_dlen_default 0x0
1794
1795/* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions
1796 * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]".
1797 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]
1798 * PORT="pif_tdm_desc0_wrb_thresh_i[6:0]"
1799 */
1800
1801/* Register address for bitfield desc{D}_wrb_thresh[6:0] */
1802#define tdm_desc_dwrb_thresh_adr(descriptor) \
1803 (0x00007C18 + (descriptor) * 0x40)
1804/* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */
1805#define tdm_desc_dwrb_thresh_msk 0x00007F00
1806/* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */
1807#define tdm_desc_dwrb_thresh_mskn 0xFFFF80FF
1808/* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */
1809#define tdm_desc_dwrb_thresh_shift 8
1810/* Width of bitfield desc{D}_wrb_thresh[6:0] */
1811#define tdm_desc_dwrb_thresh_width 7
1812/* Default value of bitfield desc{D}_wrb_thresh[6:0] */
1813#define tdm_desc_dwrb_thresh_default 0x0
1814
1815/* TX tdm_int_mod_en Bitfield Definitions
1816 * Preprocessor definitions for the bitfield "tdm_int_mod_en".
1817 * PORT="pif_tdm_int_mod_en_i"
1818 */
1819
1820/* Register address for bitfield tdm_int_mod_en */
1821#define tdm_int_mod_en_adr 0x00007B40
1822/* Bitmask for bitfield tdm_int_mod_en */
1823#define tdm_int_mod_en_msk 0x00000010
1824/* Inverted bitmask for bitfield tdm_int_mod_en */
1825#define tdm_int_mod_en_mskn 0xFFFFFFEF
1826/* Lower bit position of bitfield tdm_int_mod_en */
1827#define tdm_int_mod_en_shift 4
1828/* Width of bitfield tdm_int_mod_en */
1829#define tdm_int_mod_en_width 1
1830/* Default value of bitfield tdm_int_mod_en */
1831#define tdm_int_mod_en_default 0x0
1832
1833/* TX lso_tcp_flag_mid[B:0] Bitfield Definitions
1834 * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]".
1835 * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]"
1836 */
1837/* register address for bitfield lso_tcp_flag_mid[b:0] */
1838#define thm_lso_tcp_flag_mid_adr 0x00007820
1839/* bitmask for bitfield lso_tcp_flag_mid[b:0] */
1840#define thm_lso_tcp_flag_mid_msk 0x0fff0000
1841/* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */
1842#define thm_lso_tcp_flag_mid_mskn 0xf000ffff
1843/* lower bit position of bitfield lso_tcp_flag_mid[b:0] */
1844#define thm_lso_tcp_flag_mid_shift 16
1845/* width of bitfield lso_tcp_flag_mid[b:0] */
1846#define thm_lso_tcp_flag_mid_width 12
1847/* default value of bitfield lso_tcp_flag_mid[b:0] */
1848#define thm_lso_tcp_flag_mid_default 0x0
1849
1850/* tx tx_buf_en bitfield definitions
1851 * preprocessor definitions for the bitfield "tx_buf_en".
1852 * port="pif_tpb_tx_buf_en_i"
1853 */
1854
1855/* register address for bitfield tx_buf_en */
1856#define tpb_tx_buf_en_adr 0x00007900
1857/* bitmask for bitfield tx_buf_en */
1858#define tpb_tx_buf_en_msk 0x00000001
1859/* inverted bitmask for bitfield tx_buf_en */
1860#define tpb_tx_buf_en_mskn 0xfffffffe
1861/* lower bit position of bitfield tx_buf_en */
1862#define tpb_tx_buf_en_shift 0
1863/* width of bitfield tx_buf_en */
1864#define tpb_tx_buf_en_width 1
1865/* default value of bitfield tx_buf_en */
1866#define tpb_tx_buf_en_default 0x0
1867
1868/* tx tx{b}_hi_thresh[c:0] bitfield definitions
1869 * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]".
1870 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
1871 * port="pif_tpb_tx0_hi_thresh_i[12:0]"
1872 */
1873
1874/* register address for bitfield tx{b}_hi_thresh[c:0] */
1875#define tpb_txbhi_thresh_adr(buffer) (0x00007914 + (buffer) * 0x10)
1876/* bitmask for bitfield tx{b}_hi_thresh[c:0] */
1877#define tpb_txbhi_thresh_msk 0x1fff0000
1878/* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */
1879#define tpb_txbhi_thresh_mskn 0xe000ffff
1880/* lower bit position of bitfield tx{b}_hi_thresh[c:0] */
1881#define tpb_txbhi_thresh_shift 16
1882/* width of bitfield tx{b}_hi_thresh[c:0] */
1883#define tpb_txbhi_thresh_width 13
1884/* default value of bitfield tx{b}_hi_thresh[c:0] */
1885#define tpb_txbhi_thresh_default 0x0
1886
1887/* tx tx{b}_lo_thresh[c:0] bitfield definitions
1888 * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]".
1889 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
1890 * port="pif_tpb_tx0_lo_thresh_i[12:0]"
1891 */
1892
1893/* register address for bitfield tx{b}_lo_thresh[c:0] */
1894#define tpb_txblo_thresh_adr(buffer) (0x00007914 + (buffer) * 0x10)
1895/* bitmask for bitfield tx{b}_lo_thresh[c:0] */
1896#define tpb_txblo_thresh_msk 0x00001fff
1897/* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */
1898#define tpb_txblo_thresh_mskn 0xffffe000
1899/* lower bit position of bitfield tx{b}_lo_thresh[c:0] */
1900#define tpb_txblo_thresh_shift 0
1901/* width of bitfield tx{b}_lo_thresh[c:0] */
1902#define tpb_txblo_thresh_width 13
1903/* default value of bitfield tx{b}_lo_thresh[c:0] */
1904#define tpb_txblo_thresh_default 0x0
1905
1906/* tx dma_sys_loopback bitfield definitions
1907 * preprocessor definitions for the bitfield "dma_sys_loopback".
1908 * port="pif_tpb_dma_sys_lbk_i"
1909 */
1910
1911/* register address for bitfield dma_sys_loopback */
1912#define tpb_dma_sys_lbk_adr 0x00007000
1913/* bitmask for bitfield dma_sys_loopback */
1914#define tpb_dma_sys_lbk_msk 0x00000040
1915/* inverted bitmask for bitfield dma_sys_loopback */
1916#define tpb_dma_sys_lbk_mskn 0xffffffbf
1917/* lower bit position of bitfield dma_sys_loopback */
1918#define tpb_dma_sys_lbk_shift 6
1919/* width of bitfield dma_sys_loopback */
1920#define tpb_dma_sys_lbk_width 1
1921/* default value of bitfield dma_sys_loopback */
1922#define tpb_dma_sys_lbk_default 0x0
1923
1924/* tx tx{b}_buf_size[7:0] bitfield definitions
1925 * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]".
1926 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
1927 * port="pif_tpb_tx0_buf_size_i[7:0]"
1928 */
1929
1930/* register address for bitfield tx{b}_buf_size[7:0] */
1931#define tpb_txbbuf_size_adr(buffer) (0x00007910 + (buffer) * 0x10)
1932/* bitmask for bitfield tx{b}_buf_size[7:0] */
1933#define tpb_txbbuf_size_msk 0x000000ff
1934/* inverted bitmask for bitfield tx{b}_buf_size[7:0] */
1935#define tpb_txbbuf_size_mskn 0xffffff00
1936/* lower bit position of bitfield tx{b}_buf_size[7:0] */
1937#define tpb_txbbuf_size_shift 0
1938/* width of bitfield tx{b}_buf_size[7:0] */
1939#define tpb_txbbuf_size_width 8
1940/* default value of bitfield tx{b}_buf_size[7:0] */
1941#define tpb_txbbuf_size_default 0x0
1942
1943/* tx tx_scp_ins_en bitfield definitions
1944 * preprocessor definitions for the bitfield "tx_scp_ins_en".
1945 * port="pif_tpb_scp_ins_en_i"
1946 */
1947
1948/* register address for bitfield tx_scp_ins_en */
1949#define tpb_tx_scp_ins_en_adr 0x00007900
1950/* bitmask for bitfield tx_scp_ins_en */
1951#define tpb_tx_scp_ins_en_msk 0x00000004
1952/* inverted bitmask for bitfield tx_scp_ins_en */
1953#define tpb_tx_scp_ins_en_mskn 0xfffffffb
1954/* lower bit position of bitfield tx_scp_ins_en */
1955#define tpb_tx_scp_ins_en_shift 2
1956/* width of bitfield tx_scp_ins_en */
1957#define tpb_tx_scp_ins_en_width 1
1958/* default value of bitfield tx_scp_ins_en */
1959#define tpb_tx_scp_ins_en_default 0x0
1960
1961/* tx ipv4_chk_en bitfield definitions
1962 * preprocessor definitions for the bitfield "ipv4_chk_en".
1963 * port="pif_tpo_ipv4_chk_en_i"
1964 */
1965
1966/* register address for bitfield ipv4_chk_en */
1967#define tpo_ipv4chk_en_adr 0x00007800
1968/* bitmask for bitfield ipv4_chk_en */
1969#define tpo_ipv4chk_en_msk 0x00000002
1970/* inverted bitmask for bitfield ipv4_chk_en */
1971#define tpo_ipv4chk_en_mskn 0xfffffffd
1972/* lower bit position of bitfield ipv4_chk_en */
1973#define tpo_ipv4chk_en_shift 1
1974/* width of bitfield ipv4_chk_en */
1975#define tpo_ipv4chk_en_width 1
1976/* default value of bitfield ipv4_chk_en */
1977#define tpo_ipv4chk_en_default 0x0
1978
1979/* tx l4_chk_en bitfield definitions
1980 * preprocessor definitions for the bitfield "l4_chk_en".
1981 * port="pif_tpo_l4_chk_en_i"
1982 */
1983
1984/* register address for bitfield l4_chk_en */
1985#define tpol4chk_en_adr 0x00007800
1986/* bitmask for bitfield l4_chk_en */
1987#define tpol4chk_en_msk 0x00000001
1988/* inverted bitmask for bitfield l4_chk_en */
1989#define tpol4chk_en_mskn 0xfffffffe
1990/* lower bit position of bitfield l4_chk_en */
1991#define tpol4chk_en_shift 0
1992/* width of bitfield l4_chk_en */
1993#define tpol4chk_en_width 1
1994/* default value of bitfield l4_chk_en */
1995#define tpol4chk_en_default 0x0
1996
1997/* tx pkt_sys_loopback bitfield definitions
1998 * preprocessor definitions for the bitfield "pkt_sys_loopback".
1999 * port="pif_tpo_pkt_sys_lbk_i"
2000 */
2001
2002/* register address for bitfield pkt_sys_loopback */
2003#define tpo_pkt_sys_lbk_adr 0x00007000
2004/* bitmask for bitfield pkt_sys_loopback */
2005#define tpo_pkt_sys_lbk_msk 0x00000080
2006/* inverted bitmask for bitfield pkt_sys_loopback */
2007#define tpo_pkt_sys_lbk_mskn 0xffffff7f
2008/* lower bit position of bitfield pkt_sys_loopback */
2009#define tpo_pkt_sys_lbk_shift 7
2010/* width of bitfield pkt_sys_loopback */
2011#define tpo_pkt_sys_lbk_width 1
2012/* default value of bitfield pkt_sys_loopback */
2013#define tpo_pkt_sys_lbk_default 0x0
2014
2015/* tx data_tc_arb_mode bitfield definitions
2016 * preprocessor definitions for the bitfield "data_tc_arb_mode".
2017 * port="pif_tps_data_tc_arb_mode_i"
2018 */
2019
2020/* register address for bitfield data_tc_arb_mode */
2021#define tps_data_tc_arb_mode_adr 0x00007100
2022/* bitmask for bitfield data_tc_arb_mode */
2023#define tps_data_tc_arb_mode_msk 0x00000001
2024/* inverted bitmask for bitfield data_tc_arb_mode */
2025#define tps_data_tc_arb_mode_mskn 0xfffffffe
2026/* lower bit position of bitfield data_tc_arb_mode */
2027#define tps_data_tc_arb_mode_shift 0
2028/* width of bitfield data_tc_arb_mode */
2029#define tps_data_tc_arb_mode_width 1
2030/* default value of bitfield data_tc_arb_mode */
2031#define tps_data_tc_arb_mode_default 0x0
2032
2033/* tx desc_rate_ta_rst bitfield definitions
2034 * preprocessor definitions for the bitfield "desc_rate_ta_rst".
2035 * port="pif_tps_desc_rate_ta_rst_i"
2036 */
2037
2038/* register address for bitfield desc_rate_ta_rst */
2039#define tps_desc_rate_ta_rst_adr 0x00007310
2040/* bitmask for bitfield desc_rate_ta_rst */
2041#define tps_desc_rate_ta_rst_msk 0x80000000
2042/* inverted bitmask for bitfield desc_rate_ta_rst */
2043#define tps_desc_rate_ta_rst_mskn 0x7fffffff
2044/* lower bit position of bitfield desc_rate_ta_rst */
2045#define tps_desc_rate_ta_rst_shift 31
2046/* width of bitfield desc_rate_ta_rst */
2047#define tps_desc_rate_ta_rst_width 1
2048/* default value of bitfield desc_rate_ta_rst */
2049#define tps_desc_rate_ta_rst_default 0x0
2050
2051/* tx desc_rate_limit[a:0] bitfield definitions
2052 * preprocessor definitions for the bitfield "desc_rate_limit[a:0]".
2053 * port="pif_tps_desc_rate_lim_i[10:0]"
2054 */
2055
2056/* register address for bitfield desc_rate_limit[a:0] */
2057#define tps_desc_rate_lim_adr 0x00007310
2058/* bitmask for bitfield desc_rate_limit[a:0] */
2059#define tps_desc_rate_lim_msk 0x000007ff
2060/* inverted bitmask for bitfield desc_rate_limit[a:0] */
2061#define tps_desc_rate_lim_mskn 0xfffff800
2062/* lower bit position of bitfield desc_rate_limit[a:0] */
2063#define tps_desc_rate_lim_shift 0
2064/* width of bitfield desc_rate_limit[a:0] */
2065#define tps_desc_rate_lim_width 11
2066/* default value of bitfield desc_rate_limit[a:0] */
2067#define tps_desc_rate_lim_default 0x0
2068
2069/* tx desc_tc_arb_mode[1:0] bitfield definitions
2070 * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]".
2071 * port="pif_tps_desc_tc_arb_mode_i[1:0]"
2072 */
2073
2074/* register address for bitfield desc_tc_arb_mode[1:0] */
2075#define tps_desc_tc_arb_mode_adr 0x00007200
2076/* bitmask for bitfield desc_tc_arb_mode[1:0] */
2077#define tps_desc_tc_arb_mode_msk 0x00000003
2078/* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */
2079#define tps_desc_tc_arb_mode_mskn 0xfffffffc
2080/* lower bit position of bitfield desc_tc_arb_mode[1:0] */
2081#define tps_desc_tc_arb_mode_shift 0
2082/* width of bitfield desc_tc_arb_mode[1:0] */
2083#define tps_desc_tc_arb_mode_width 2
2084/* default value of bitfield desc_tc_arb_mode[1:0] */
2085#define tps_desc_tc_arb_mode_default 0x0
2086
2087/* tx desc_tc{t}_credit_max[b:0] bitfield definitions
2088 * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]".
2089 * parameter: tc {t} | stride size 0x4 | range [0, 7]
2090 * port="pif_tps_desc_tc0_credit_max_i[11:0]"
2091 */
2092
2093/* register address for bitfield desc_tc{t}_credit_max[b:0] */
2094#define tps_desc_tctcredit_max_adr(tc) (0x00007210 + (tc) * 0x4)
2095/* bitmask for bitfield desc_tc{t}_credit_max[b:0] */
2096#define tps_desc_tctcredit_max_msk 0x0fff0000
2097/* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */
2098#define tps_desc_tctcredit_max_mskn 0xf000ffff
2099/* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */
2100#define tps_desc_tctcredit_max_shift 16
2101/* width of bitfield desc_tc{t}_credit_max[b:0] */
2102#define tps_desc_tctcredit_max_width 12
2103/* default value of bitfield desc_tc{t}_credit_max[b:0] */
2104#define tps_desc_tctcredit_max_default 0x0
2105
2106/* tx desc_tc{t}_weight[8:0] bitfield definitions
2107 * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]".
2108 * parameter: tc {t} | stride size 0x4 | range [0, 7]
2109 * port="pif_tps_desc_tc0_weight_i[8:0]"
2110 */
2111
2112/* register address for bitfield desc_tc{t}_weight[8:0] */
2113#define tps_desc_tctweight_adr(tc) (0x00007210 + (tc) * 0x4)
2114/* bitmask for bitfield desc_tc{t}_weight[8:0] */
2115#define tps_desc_tctweight_msk 0x000001ff
2116/* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */
2117#define tps_desc_tctweight_mskn 0xfffffe00
2118/* lower bit position of bitfield desc_tc{t}_weight[8:0] */
2119#define tps_desc_tctweight_shift 0
2120/* width of bitfield desc_tc{t}_weight[8:0] */
2121#define tps_desc_tctweight_width 9
2122/* default value of bitfield desc_tc{t}_weight[8:0] */
2123#define tps_desc_tctweight_default 0x0
2124
2125/* tx desc_vm_arb_mode bitfield definitions
2126 * preprocessor definitions for the bitfield "desc_vm_arb_mode".
2127 * port="pif_tps_desc_vm_arb_mode_i"
2128 */
2129
2130/* register address for bitfield desc_vm_arb_mode */
2131#define tps_desc_vm_arb_mode_adr 0x00007300
2132/* bitmask for bitfield desc_vm_arb_mode */
2133#define tps_desc_vm_arb_mode_msk 0x00000001
2134/* inverted bitmask for bitfield desc_vm_arb_mode */
2135#define tps_desc_vm_arb_mode_mskn 0xfffffffe
2136/* lower bit position of bitfield desc_vm_arb_mode */
2137#define tps_desc_vm_arb_mode_shift 0
2138/* width of bitfield desc_vm_arb_mode */
2139#define tps_desc_vm_arb_mode_width 1
2140/* default value of bitfield desc_vm_arb_mode */
2141#define tps_desc_vm_arb_mode_default 0x0
2142
2143/* tx data_tc{t}_credit_max[b:0] bitfield definitions
2144 * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]".
2145 * parameter: tc {t} | stride size 0x4 | range [0, 7]
2146 * port="pif_tps_data_tc0_credit_max_i[11:0]"
2147 */
2148
2149/* register address for bitfield data_tc{t}_credit_max[b:0] */
2150#define tps_data_tctcredit_max_adr(tc) (0x00007110 + (tc) * 0x4)
2151/* bitmask for bitfield data_tc{t}_credit_max[b:0] */
2152#define tps_data_tctcredit_max_msk 0x0fff0000
2153/* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */
2154#define tps_data_tctcredit_max_mskn 0xf000ffff
2155/* lower bit position of bitfield data_tc{t}_credit_max[b:0] */
2156#define tps_data_tctcredit_max_shift 16
2157/* width of bitfield data_tc{t}_credit_max[b:0] */
2158#define tps_data_tctcredit_max_width 12
2159/* default value of bitfield data_tc{t}_credit_max[b:0] */
2160#define tps_data_tctcredit_max_default 0x0
2161
2162/* tx data_tc{t}_weight[8:0] bitfield definitions
2163 * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]".
2164 * parameter: tc {t} | stride size 0x4 | range [0, 7]
2165 * port="pif_tps_data_tc0_weight_i[8:0]"
2166 */
2167
2168/* register address for bitfield data_tc{t}_weight[8:0] */
2169#define tps_data_tctweight_adr(tc) (0x00007110 + (tc) * 0x4)
2170/* bitmask for bitfield data_tc{t}_weight[8:0] */
2171#define tps_data_tctweight_msk 0x000001ff
2172/* inverted bitmask for bitfield data_tc{t}_weight[8:0] */
2173#define tps_data_tctweight_mskn 0xfffffe00
2174/* lower bit position of bitfield data_tc{t}_weight[8:0] */
2175#define tps_data_tctweight_shift 0
2176/* width of bitfield data_tc{t}_weight[8:0] */
2177#define tps_data_tctweight_width 9
2178/* default value of bitfield data_tc{t}_weight[8:0] */
2179#define tps_data_tctweight_default 0x0
2180
2181/* tx reg_res_dsbl bitfield definitions
2182 * preprocessor definitions for the bitfield "reg_res_dsbl".
2183 * port="pif_tx_reg_res_dsbl_i"
2184 */
2185
2186/* register address for bitfield reg_res_dsbl */
2187#define tx_reg_res_dsbl_adr 0x00007000
2188/* bitmask for bitfield reg_res_dsbl */
2189#define tx_reg_res_dsbl_msk 0x20000000
2190/* inverted bitmask for bitfield reg_res_dsbl */
2191#define tx_reg_res_dsbl_mskn 0xdfffffff
2192/* lower bit position of bitfield reg_res_dsbl */
2193#define tx_reg_res_dsbl_shift 29
2194/* width of bitfield reg_res_dsbl */
2195#define tx_reg_res_dsbl_width 1
2196/* default value of bitfield reg_res_dsbl */
2197#define tx_reg_res_dsbl_default 0x1
2198
2199/* mac_phy register access busy bitfield definitions
2200 * preprocessor definitions for the bitfield "register access busy".
2201 * port="msm_pif_reg_busy_o"
2202 */
2203
2204/* register address for bitfield register access busy */
2205#define msm_reg_access_busy_adr 0x00004400
2206/* bitmask for bitfield register access busy */
2207#define msm_reg_access_busy_msk 0x00001000
2208/* inverted bitmask for bitfield register access busy */
2209#define msm_reg_access_busy_mskn 0xffffefff
2210/* lower bit position of bitfield register access busy */
2211#define msm_reg_access_busy_shift 12
2212/* width of bitfield register access busy */
2213#define msm_reg_access_busy_width 1
2214
2215/* mac_phy msm register address[7:0] bitfield definitions
2216 * preprocessor definitions for the bitfield "msm register address[7:0]".
2217 * port="pif_msm_reg_addr_i[7:0]"
2218 */
2219
2220/* register address for bitfield msm register address[7:0] */
2221#define msm_reg_addr_adr 0x00004400
2222/* bitmask for bitfield msm register address[7:0] */
2223#define msm_reg_addr_msk 0x000000ff
2224/* inverted bitmask for bitfield msm register address[7:0] */
2225#define msm_reg_addr_mskn 0xffffff00
2226/* lower bit position of bitfield msm register address[7:0] */
2227#define msm_reg_addr_shift 0
2228/* width of bitfield msm register address[7:0] */
2229#define msm_reg_addr_width 8
2230/* default value of bitfield msm register address[7:0] */
2231#define msm_reg_addr_default 0x0
2232
2233/* mac_phy register read strobe bitfield definitions
2234 * preprocessor definitions for the bitfield "register read strobe".
2235 * port="pif_msm_reg_rden_i"
2236 */
2237
2238/* register address for bitfield register read strobe */
2239#define msm_reg_rd_strobe_adr 0x00004400
2240/* bitmask for bitfield register read strobe */
2241#define msm_reg_rd_strobe_msk 0x00000200
2242/* inverted bitmask for bitfield register read strobe */
2243#define msm_reg_rd_strobe_mskn 0xfffffdff
2244/* lower bit position of bitfield register read strobe */
2245#define msm_reg_rd_strobe_shift 9
2246/* width of bitfield register read strobe */
2247#define msm_reg_rd_strobe_width 1
2248/* default value of bitfield register read strobe */
2249#define msm_reg_rd_strobe_default 0x0
2250
2251/* mac_phy msm register read data[31:0] bitfield definitions
2252 * preprocessor definitions for the bitfield "msm register read data[31:0]".
2253 * port="msm_pif_reg_rd_data_o[31:0]"
2254 */
2255
2256/* register address for bitfield msm register read data[31:0] */
2257#define msm_reg_rd_data_adr 0x00004408
2258/* bitmask for bitfield msm register read data[31:0] */
2259#define msm_reg_rd_data_msk 0xffffffff
2260/* inverted bitmask for bitfield msm register read data[31:0] */
2261#define msm_reg_rd_data_mskn 0x00000000
2262/* lower bit position of bitfield msm register read data[31:0] */
2263#define msm_reg_rd_data_shift 0
2264/* width of bitfield msm register read data[31:0] */
2265#define msm_reg_rd_data_width 32
2266
2267/* mac_phy msm register write data[31:0] bitfield definitions
2268 * preprocessor definitions for the bitfield "msm register write data[31:0]".
2269 * port="pif_msm_reg_wr_data_i[31:0]"
2270 */
2271
2272/* register address for bitfield msm register write data[31:0] */
2273#define msm_reg_wr_data_adr 0x00004404
2274/* bitmask for bitfield msm register write data[31:0] */
2275#define msm_reg_wr_data_msk 0xffffffff
2276/* inverted bitmask for bitfield msm register write data[31:0] */
2277#define msm_reg_wr_data_mskn 0x00000000
2278/* lower bit position of bitfield msm register write data[31:0] */
2279#define msm_reg_wr_data_shift 0
2280/* width of bitfield msm register write data[31:0] */
2281#define msm_reg_wr_data_width 32
2282/* default value of bitfield msm register write data[31:0] */
2283#define msm_reg_wr_data_default 0x0
2284
2285/* mac_phy register write strobe bitfield definitions
2286 * preprocessor definitions for the bitfield "register write strobe".
2287 * port="pif_msm_reg_wren_i"
2288 */
2289
2290/* register address for bitfield register write strobe */
2291#define msm_reg_wr_strobe_adr 0x00004400
2292/* bitmask for bitfield register write strobe */
2293#define msm_reg_wr_strobe_msk 0x00000100
2294/* inverted bitmask for bitfield register write strobe */
2295#define msm_reg_wr_strobe_mskn 0xfffffeff
2296/* lower bit position of bitfield register write strobe */
2297#define msm_reg_wr_strobe_shift 8
2298/* width of bitfield register write strobe */
2299#define msm_reg_wr_strobe_width 1
2300/* default value of bitfield register write strobe */
2301#define msm_reg_wr_strobe_default 0x0
2302
2303/* mif soft reset bitfield definitions
2304 * preprocessor definitions for the bitfield "soft reset".
2305 * port="pif_glb_res_i"
2306 */
2307
2308/* register address for bitfield soft reset */
2309#define glb_soft_res_adr 0x00000000
2310/* bitmask for bitfield soft reset */
2311#define glb_soft_res_msk 0x00008000
2312/* inverted bitmask for bitfield soft reset */
2313#define glb_soft_res_mskn 0xffff7fff
2314/* lower bit position of bitfield soft reset */
2315#define glb_soft_res_shift 15
2316/* width of bitfield soft reset */
2317#define glb_soft_res_width 1
2318/* default value of bitfield soft reset */
2319#define glb_soft_res_default 0x0
2320
2321/* mif register reset disable bitfield definitions
2322 * preprocessor definitions for the bitfield "register reset disable".
2323 * port="pif_glb_reg_res_dsbl_i"
2324 */
2325
2326/* register address for bitfield register reset disable */
2327#define glb_reg_res_dis_adr 0x00000000
2328/* bitmask for bitfield register reset disable */
2329#define glb_reg_res_dis_msk 0x00004000
2330/* inverted bitmask for bitfield register reset disable */
2331#define glb_reg_res_dis_mskn 0xffffbfff
2332/* lower bit position of bitfield register reset disable */
2333#define glb_reg_res_dis_shift 14
2334/* width of bitfield register reset disable */
2335#define glb_reg_res_dis_width 1
2336/* default value of bitfield register reset disable */
2337#define glb_reg_res_dis_default 0x1
2338
2339/* tx dma debug control definitions */
2340#define tx_dma_debug_ctl_adr 0x00008920u
2341
2342/* tx dma descriptor base address msw definitions */
2343#define tx_dma_desc_base_addrmsw_adr(descriptor) \
2344 (0x00007c04u + (descriptor) * 0x40)
2345
2346/* tx interrupt moderation control register definitions
2347 * Preprocessor definitions for TX Interrupt Moderation Control Register
2348 * Base Address: 0x00008980
2349 * Parameter: queue {Q} | stride size 0x4 | range [0, 31]
2350 */
2351
2352#define tx_intr_moderation_ctl_adr(queue) (0x00008980u + (queue) * 0x4)
2353
2354/* pcie reg_res_dsbl bitfield definitions
2355 * preprocessor definitions for the bitfield "reg_res_dsbl".
2356 * port="pif_pci_reg_res_dsbl_i"
2357 */
2358
2359/* register address for bitfield reg_res_dsbl */
2360#define pci_reg_res_dsbl_adr 0x00001000
2361/* bitmask for bitfield reg_res_dsbl */
2362#define pci_reg_res_dsbl_msk 0x20000000
2363/* inverted bitmask for bitfield reg_res_dsbl */
2364#define pci_reg_res_dsbl_mskn 0xdfffffff
2365/* lower bit position of bitfield reg_res_dsbl */
2366#define pci_reg_res_dsbl_shift 29
2367/* width of bitfield reg_res_dsbl */
2368#define pci_reg_res_dsbl_width 1
2369/* default value of bitfield reg_res_dsbl */
2370#define pci_reg_res_dsbl_default 0x1
2371
2372/* global microprocessor scratch pad definitions */
2373#define glb_cpu_scratch_scp_adr(scratch_scp) (0x00000300u + (scratch_scp) * 0x4)
2374
2375#endif /* HW_ATL_LLH_INTERNAL_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
new file mode 100644
index 000000000000..8d6d8f5804da
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
@@ -0,0 +1,570 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File hw_atl_utils.c: Definition of common functions for Atlantic hardware
11 * abstraction layer.
12 */
13
14#include "../aq_hw.h"
15#include "../aq_hw_utils.h"
16#include "../aq_pci_func.h"
17#include "../aq_ring.h"
18#include "../aq_vec.h"
19#include "hw_atl_utils.h"
20#include "hw_atl_llh.h"
21
22#include <linux/random.h>
23
24#define HW_ATL_UCP_0X370_REG 0x0370U
25
26#define HW_ATL_FW_SM_RAM 0x2U
27#define HW_ATL_MPI_CONTROL_ADR 0x0368U
28#define HW_ATL_MPI_STATE_ADR 0x036CU
29
30#define HW_ATL_MPI_STATE_MSK 0x00FFU
31#define HW_ATL_MPI_STATE_SHIFT 0U
32#define HW_ATL_MPI_SPEED_MSK 0xFFFFU
33#define HW_ATL_MPI_SPEED_SHIFT 16U
34
35static int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
36 u32 *p, u32 cnt)
37{
38 int err = 0;
39
40 AQ_HW_WAIT_FOR(reg_glb_cpu_sem_get(self,
41 HW_ATL_FW_SM_RAM) == 1U,
42 1U, 10000U);
43
44 if (err < 0) {
45 bool is_locked;
46
47 reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);
48 is_locked = reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
49 if (!is_locked) {
50 err = -ETIME;
51 goto err_exit;
52 }
53 }
54
55 aq_hw_write_reg(self, 0x00000208U, a);
56
57 for (++cnt; --cnt;) {
58 u32 i = 0U;
59
60 aq_hw_write_reg(self, 0x00000200U, 0x00008000U);
61
62 for (i = 1024U;
63 (0x100U & aq_hw_read_reg(self, 0x00000200U)) && --i;) {
64 }
65
66 *(p++) = aq_hw_read_reg(self, 0x0000020CU);
67 }
68
69 reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);
70
71err_exit:
72 return err;
73}
74
75static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
76 u32 cnt)
77{
78 int err = 0;
79 bool is_locked;
80
81 is_locked = reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
82 if (!is_locked) {
83 err = -ETIME;
84 goto err_exit;
85 }
86
87 aq_hw_write_reg(self, 0x00000208U, a);
88
89 for (++cnt; --cnt;) {
90 u32 i = 0U;
91
92 aq_hw_write_reg(self, 0x0000020CU, *(p++));
93 aq_hw_write_reg(self, 0x00000200U, 0xC000U);
94
95 for (i = 1024U;
96 (0x100U & aq_hw_read_reg(self, 0x00000200U)) && --i;) {
97 }
98 }
99
100 reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM);
101
102err_exit:
103 return err;
104}
105
106static int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual)
107{
108 int err = 0;
109 const u32 dw_major_mask = 0xff000000U;
110 const u32 dw_minor_mask = 0x00ffffffU;
111
112 err = (dw_major_mask & (ver_expected ^ ver_actual)) ? -EOPNOTSUPP : 0;
113 if (err < 0)
114 goto err_exit;
115 err = ((dw_minor_mask & ver_expected) > (dw_minor_mask & ver_actual)) ?
116 -EOPNOTSUPP : 0;
117err_exit:
118 return err;
119}
120
121static int hw_atl_utils_init_ucp(struct aq_hw_s *self,
122 struct aq_hw_caps_s *aq_hw_caps)
123{
124 int err = 0;
125
126 if (!aq_hw_read_reg(self, 0x370U)) {
127 unsigned int rnd = 0U;
128 unsigned int ucp_0x370 = 0U;
129
130 get_random_bytes(&rnd, sizeof(unsigned int));
131
132 ucp_0x370 = 0x02020202U | (0xFEFEFEFEU & rnd);
133 aq_hw_write_reg(self, HW_ATL_UCP_0X370_REG, ucp_0x370);
134 }
135
136 reg_glb_cpu_scratch_scp_set(self, 0x00000000U, 25U);
137
138 /* check 10 times by 1ms */
139 AQ_HW_WAIT_FOR(0U != (PHAL_ATLANTIC_A0->mbox_addr =
140 aq_hw_read_reg(self, 0x360U)), 1000U, 10U);
141
142 err = hw_atl_utils_ver_match(aq_hw_caps->fw_ver_expected,
143 aq_hw_read_reg(self, 0x18U));
144 return err;
145}
146
147#define HW_ATL_RPC_CONTROL_ADR 0x0338U
148#define HW_ATL_RPC_STATE_ADR 0x033CU
149
150struct aq_hw_atl_utils_fw_rpc_tid_s {
151 union {
152 u32 val;
153 struct {
154 u16 tid;
155 u16 len;
156 };
157 };
158};
159
160#define hw_atl_utils_fw_rpc_init(_H_) hw_atl_utils_fw_rpc_wait(_H_, NULL)
161
162static int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size)
163{
164 int err = 0;
165 struct aq_hw_atl_utils_fw_rpc_tid_s sw;
166
167 if (!IS_CHIP_FEATURE(MIPS)) {
168 err = -1;
169 goto err_exit;
170 }
171 err = hw_atl_utils_fw_upload_dwords(self, PHAL_ATLANTIC->rpc_addr,
172 (u32 *)(void *)&PHAL_ATLANTIC->rpc,
173 (rpc_size + sizeof(u32) -
174 sizeof(u8)) / sizeof(u32));
175 if (err < 0)
176 goto err_exit;
177
178 sw.tid = 0xFFFFU & (++PHAL_ATLANTIC->rpc_tid);
179 sw.len = (u16)rpc_size;
180 aq_hw_write_reg(self, HW_ATL_RPC_CONTROL_ADR, sw.val);
181
182err_exit:
183 return err;
184}
185
186static int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
187 struct hw_aq_atl_utils_fw_rpc **rpc)
188{
189 int err = 0;
190 struct aq_hw_atl_utils_fw_rpc_tid_s sw;
191 struct aq_hw_atl_utils_fw_rpc_tid_s fw;
192
193 do {
194 sw.val = aq_hw_read_reg(self, HW_ATL_RPC_CONTROL_ADR);
195
196 PHAL_ATLANTIC->rpc_tid = sw.tid;
197
198 AQ_HW_WAIT_FOR(sw.tid ==
199 (fw.val =
200 aq_hw_read_reg(self, HW_ATL_RPC_STATE_ADR),
201 fw.tid), 1000U, 100U);
202 if (err < 0)
203 goto err_exit;
204
205 if (fw.len == 0xFFFFU) {
206 err = hw_atl_utils_fw_rpc_call(self, sw.len);
207 if (err < 0)
208 goto err_exit;
209 }
210 } while (sw.tid != fw.tid || 0xFFFFU == fw.len);
211 if (err < 0)
212 goto err_exit;
213
214 if (rpc) {
215 if (fw.len) {
216 err =
217 hw_atl_utils_fw_downld_dwords(self,
218 PHAL_ATLANTIC->rpc_addr,
219 (u32 *)(void *)
220 &PHAL_ATLANTIC->rpc,
221 (fw.len + sizeof(u32) -
222 sizeof(u8)) /
223 sizeof(u32));
224 if (err < 0)
225 goto err_exit;
226 }
227
228 *rpc = &PHAL_ATLANTIC->rpc;
229 }
230
231err_exit:
232 return err;
233}
234
235static int hw_atl_utils_mpi_create(struct aq_hw_s *self,
236 struct aq_hw_caps_s *aq_hw_caps)
237{
238 int err = 0;
239
240 err = hw_atl_utils_init_ucp(self, aq_hw_caps);
241 if (err < 0)
242 goto err_exit;
243
244 err = hw_atl_utils_fw_rpc_init(self);
245 if (err < 0)
246 goto err_exit;
247
248err_exit:
249 return err;
250}
251
252void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
253 struct hw_aq_atl_utils_mbox *pmbox)
254{
255 int err = 0;
256
257 err = hw_atl_utils_fw_downld_dwords(self,
258 PHAL_ATLANTIC->mbox_addr,
259 (u32 *)(void *)pmbox,
260 sizeof(*pmbox) / sizeof(u32));
261 if (err < 0)
262 goto err_exit;
263
264 if (pmbox != &PHAL_ATLANTIC->mbox)
265 memcpy(pmbox, &PHAL_ATLANTIC->mbox, sizeof(*pmbox));
266
267 if (IS_CHIP_FEATURE(REVISION_A0)) {
268 unsigned int mtu = self->aq_nic_cfg ?
269 self->aq_nic_cfg->mtu : 1514U;
270 pmbox->stats.ubrc = pmbox->stats.uprc * mtu;
271 pmbox->stats.ubtc = pmbox->stats.uptc * mtu;
272 pmbox->stats.dpc = atomic_read(&PHAL_ATLANTIC_A0->dpc);
273 } else {
274 pmbox->stats.dpc = reg_rx_dma_stat_counter7get(self);
275 }
276
277err_exit:;
278}
279
280int hw_atl_utils_mpi_set_speed(struct aq_hw_s *self, u32 speed,
281 enum hal_atl_utils_fw_state_e state)
282{
283 u32 ucp_0x368 = 0;
284
285 ucp_0x368 = (speed << HW_ATL_MPI_SPEED_SHIFT) | state;
286 aq_hw_write_reg(self, HW_ATL_MPI_CONTROL_ADR, ucp_0x368);
287
288 return 0;
289}
290
291void hw_atl_utils_mpi_set(struct aq_hw_s *self,
292 enum hal_atl_utils_fw_state_e state, u32 speed)
293{
294 int err = 0;
295 u32 transaction_id = 0;
296
297 if (state == MPI_RESET) {
298 hw_atl_utils_mpi_read_stats(self, &PHAL_ATLANTIC->mbox);
299
300 transaction_id = PHAL_ATLANTIC->mbox.transaction_id;
301
302 AQ_HW_WAIT_FOR(transaction_id !=
303 (hw_atl_utils_mpi_read_stats
304 (self, &PHAL_ATLANTIC->mbox),
305 PHAL_ATLANTIC->mbox.transaction_id),
306 1000U, 100U);
307 if (err < 0)
308 goto err_exit;
309 }
310
311 err = hw_atl_utils_mpi_set_speed(self, speed, state);
312
313err_exit:;
314}
315
316int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self,
317 struct aq_hw_link_status_s *link_status)
318{
319 u32 cp0x036C = aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR);
320 u32 link_speed_mask = cp0x036C >> HW_ATL_MPI_SPEED_SHIFT;
321
322 if (!link_speed_mask) {
323 link_status->mbps = 0U;
324 } else {
325 switch (link_speed_mask) {
326 case HAL_ATLANTIC_RATE_10G:
327 link_status->mbps = 10000U;
328 break;
329
330 case HAL_ATLANTIC_RATE_5G:
331 case HAL_ATLANTIC_RATE_5GSR:
332 link_status->mbps = 5000U;
333 break;
334
335 case HAL_ATLANTIC_RATE_2GS:
336 link_status->mbps = 2500U;
337 break;
338
339 case HAL_ATLANTIC_RATE_1G:
340 link_status->mbps = 1000U;
341 break;
342
343 case HAL_ATLANTIC_RATE_100M:
344 link_status->mbps = 100U;
345 break;
346
347 default:
348 link_status->mbps = 0U;
349 break;
350 }
351 }
352
353 return 0;
354}
355
356int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self,
357 struct aq_hw_caps_s *aq_hw_caps,
358 u8 *mac)
359{
360 int err = 0;
361 u32 h = 0U;
362 u32 l = 0U;
363 u32 mac_addr[2];
364
365 self->mmio = aq_pci_func_get_mmio(self->aq_pci_func);
366
367 hw_atl_utils_hw_chip_features_init(self,
368 &PHAL_ATLANTIC_A0->chip_features);
369
370 err = hw_atl_utils_mpi_create(self, aq_hw_caps);
371 if (err < 0)
372 goto err_exit;
373
374 if (!aq_hw_read_reg(self, HW_ATL_UCP_0X370_REG)) {
375 unsigned int rnd = 0;
376 unsigned int ucp_0x370 = 0;
377
378 get_random_bytes(&rnd, sizeof(unsigned int));
379
380 ucp_0x370 = 0x02020202 | (0xFEFEFEFE & rnd);
381 aq_hw_write_reg(self, HW_ATL_UCP_0X370_REG, ucp_0x370);
382 }
383
384 err = hw_atl_utils_fw_downld_dwords(self,
385 aq_hw_read_reg(self, 0x00000374U) +
386 (40U * 4U),
387 mac_addr,
388 AQ_DIMOF(mac_addr));
389 if (err < 0) {
390 mac_addr[0] = 0U;
391 mac_addr[1] = 0U;
392 err = 0;
393 } else {
394 mac_addr[0] = __swab32(mac_addr[0]);
395 mac_addr[1] = __swab32(mac_addr[1]);
396 }
397
398 ether_addr_copy(mac, (u8 *)mac_addr);
399
400 if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) {
401 /* chip revision */
402 l = 0xE3000000U
403 | (0xFFFFU & aq_hw_read_reg(self, HW_ATL_UCP_0X370_REG))
404 | (0x00 << 16);
405 h = 0x8001300EU;
406
407 mac[5] = (u8)(0xFFU & l);
408 l >>= 8;
409 mac[4] = (u8)(0xFFU & l);
410 l >>= 8;
411 mac[3] = (u8)(0xFFU & l);
412 l >>= 8;
413 mac[2] = (u8)(0xFFU & l);
414 mac[1] = (u8)(0xFFU & h);
415 h >>= 8;
416 mac[0] = (u8)(0xFFU & h);
417 }
418
419err_exit:
420 return err;
421}
422
423unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps)
424{
425 unsigned int ret = 0U;
426
427 switch (mbps) {
428 case 100U:
429 ret = 5U;
430 break;
431
432 case 1000U:
433 ret = 4U;
434 break;
435
436 case 2500U:
437 ret = 3U;
438 break;
439
440 case 5000U:
441 ret = 1U;
442 break;
443
444 case 10000U:
445 ret = 0U;
446 break;
447
448 default:
449 break;
450 }
451 return ret;
452}
453
454void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p)
455{
456 u32 chip_features = 0U;
457 u32 val = reg_glb_mif_id_get(self);
458 u32 mif_rev = val & 0xFFU;
459
460 if ((3U & mif_rev) == 1U) {
461 chip_features |=
462 HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 |
463 HAL_ATLANTIC_UTILS_CHIP_MPI_AQ |
464 HAL_ATLANTIC_UTILS_CHIP_MIPS;
465 } else if ((3U & mif_rev) == 2U) {
466 chip_features |=
467 HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 |
468 HAL_ATLANTIC_UTILS_CHIP_MPI_AQ |
469 HAL_ATLANTIC_UTILS_CHIP_MIPS |
470 HAL_ATLANTIC_UTILS_CHIP_TPO2 |
471 HAL_ATLANTIC_UTILS_CHIP_RPF2;
472 }
473
474 *p = chip_features;
475}
476
477int hw_atl_utils_hw_deinit(struct aq_hw_s *self)
478{
479 hw_atl_utils_mpi_set(self, MPI_DEINIT, 0x0U);
480 return 0;
481}
482
483int hw_atl_utils_hw_set_power(struct aq_hw_s *self,
484 unsigned int power_state)
485{
486 hw_atl_utils_mpi_set(self, MPI_POWER, 0x0U);
487 return 0;
488}
489
490int hw_atl_utils_get_hw_stats(struct aq_hw_s *self,
491 u64 *data, unsigned int *p_count)
492{
493 struct hw_atl_stats_s *stats = NULL;
494 int i = 0;
495
496 hw_atl_utils_mpi_read_stats(self, &PHAL_ATLANTIC->mbox);
497
498 stats = &PHAL_ATLANTIC->mbox.stats;
499
500 data[i] = stats->uprc + stats->mprc + stats->bprc;
501 data[++i] = stats->uprc;
502 data[++i] = stats->mprc;
503 data[++i] = stats->bprc;
504 data[++i] = stats->erpt;
505 data[++i] = stats->uptc + stats->mptc + stats->bptc;
506 data[++i] = stats->uptc;
507 data[++i] = stats->mptc;
508 data[++i] = stats->bptc;
509 data[++i] = stats->ubrc;
510 data[++i] = stats->ubtc;
511 data[++i] = stats->mbrc;
512 data[++i] = stats->mbtc;
513 data[++i] = stats->bbrc;
514 data[++i] = stats->bbtc;
515 data[++i] = stats->ubrc + stats->mbrc + stats->bbrc;
516 data[++i] = stats->ubtc + stats->mbtc + stats->bbtc;
517 data[++i] = stats_rx_dma_good_pkt_counterlsw_get(self);
518 data[++i] = stats_tx_dma_good_pkt_counterlsw_get(self);
519 data[++i] = stats_rx_dma_good_octet_counterlsw_get(self);
520 data[++i] = stats_tx_dma_good_octet_counterlsw_get(self);
521 data[++i] = stats->dpc;
522
523 if (p_count)
524 *p_count = ++i;
525
526 return 0;
527}
528
529static const u32 hw_atl_utils_hw_mac_regs[] = {
530 0x00005580U, 0x00005590U, 0x000055B0U, 0x000055B4U,
531 0x000055C0U, 0x00005B00U, 0x00005B04U, 0x00005B08U,
532 0x00005B0CU, 0x00005B10U, 0x00005B14U, 0x00005B18U,
533 0x00005B1CU, 0x00005B20U, 0x00005B24U, 0x00005B28U,
534 0x00005B2CU, 0x00005B30U, 0x00005B34U, 0x00005B38U,
535 0x00005B3CU, 0x00005B40U, 0x00005B44U, 0x00005B48U,
536 0x00005B4CU, 0x00005B50U, 0x00005B54U, 0x00005B58U,
537 0x00005B5CU, 0x00005B60U, 0x00005B64U, 0x00005B68U,
538 0x00005B6CU, 0x00005B70U, 0x00005B74U, 0x00005B78U,
539 0x00005B7CU, 0x00007C00U, 0x00007C04U, 0x00007C08U,
540 0x00007C0CU, 0x00007C10U, 0x00007C14U, 0x00007C18U,
541 0x00007C1CU, 0x00007C20U, 0x00007C40U, 0x00007C44U,
542 0x00007C48U, 0x00007C4CU, 0x00007C50U, 0x00007C54U,
543 0x00007C58U, 0x00007C5CU, 0x00007C60U, 0x00007C80U,
544 0x00007C84U, 0x00007C88U, 0x00007C8CU, 0x00007C90U,
545 0x00007C94U, 0x00007C98U, 0x00007C9CU, 0x00007CA0U,
546 0x00007CC0U, 0x00007CC4U, 0x00007CC8U, 0x00007CCCU,
547 0x00007CD0U, 0x00007CD4U, 0x00007CD8U, 0x00007CDCU,
548 0x00007CE0U, 0x00000300U, 0x00000304U, 0x00000308U,
549 0x0000030cU, 0x00000310U, 0x00000314U, 0x00000318U,
550 0x0000031cU, 0x00000360U, 0x00000364U, 0x00000368U,
551 0x0000036cU, 0x00000370U, 0x00000374U, 0x00006900U,
552};
553
554int hw_atl_utils_hw_get_regs(struct aq_hw_s *self,
555 struct aq_hw_caps_s *aq_hw_caps,
556 u32 *regs_buff)
557{
558 unsigned int i = 0U;
559
560 for (i = 0; i < aq_hw_caps->mac_regs_count; i++)
561 regs_buff[i] = aq_hw_read_reg(self,
562 hw_atl_utils_hw_mac_regs[i]);
563 return 0;
564}
565
566int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version)
567{
568 *fw_version = aq_hw_read_reg(self, 0x18U);
569 return 0;
570}
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h
new file mode 100644
index 000000000000..b8e3d88f0879
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h
@@ -0,0 +1,210 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File hw_atl_utils.h: Declaration of common functions for Atlantic hardware
11 * abstraction layer.
12 */
13
14#ifndef HW_ATL_UTILS_H
15#define HW_ATL_UTILS_H
16
17#include "../aq_common.h"
18
19#define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); }
20
21struct __packed hw_atl_stats_s {
22 u32 uprc;
23 u32 mprc;
24 u32 bprc;
25 u32 erpt;
26 u32 uptc;
27 u32 mptc;
28 u32 bptc;
29 u32 erpr;
30 u32 mbtc;
31 u32 bbtc;
32 u32 mbrc;
33 u32 bbrc;
34 u32 ubrc;
35 u32 ubtc;
36 u32 dpc;
37};
38
39union __packed ip_addr {
40 struct {
41 u8 addr[16];
42 } v6;
43 struct {
44 u8 padding[12];
45 u8 addr[4];
46 } v4;
47};
48
49struct __packed hw_aq_atl_utils_fw_rpc {
50 u32 msg_id;
51
52 union {
53 struct {
54 u32 pong;
55 } msg_ping;
56
57 struct {
58 u8 mac_addr[6];
59 u32 ip_addr_cnt;
60
61 struct {
62 union ip_addr addr;
63 union ip_addr mask;
64 } ip[1];
65 } msg_arp;
66
67 struct {
68 u32 len;
69 u8 packet[1514U];
70 } msg_inject;
71
72 struct {
73 u32 priority;
74 u32 wol_packet_type;
75 u16 friendly_name_len;
76 u16 friendly_name[65];
77 u32 pattern_id;
78 u32 next_wol_pattern_offset;
79
80 union {
81 struct {
82 u32 flags;
83 u8 ipv4_source_address[4];
84 u8 ipv4_dest_address[4];
85 u16 tcp_source_port_number;
86 u16 tcp_dest_port_number;
87 } ipv4_tcp_syn_parameters;
88
89 struct {
90 u32 flags;
91 u8 ipv6_source_address[16];
92 u8 ipv6_dest_address[16];
93 u16 tcp_source_port_number;
94 u16 tcp_dest_port_number;
95 } ipv6_tcp_syn_parameters;
96
97 struct {
98 u32 flags;
99 } eapol_request_id_message_parameters;
100
101 struct {
102 u32 flags;
103 u32 mask_offset;
104 u32 mask_size;
105 u32 pattern_offset;
106 u32 pattern_size;
107 } wol_bit_map_pattern;
108 } wol_pattern;
109 } msg_wol;
110
111 struct {
112 u32 is_wake_on_link_down;
113 u32 is_wake_on_link_up;
114 } msg_wolink;
115 };
116};
117
118struct __packed hw_aq_atl_utils_mbox {
119 u32 version;
120 u32 transaction_id;
121 int error;
122 struct hw_atl_stats_s stats;
123};
124
125struct __packed hw_atl_s {
126 struct aq_hw_s base;
127 struct hw_aq_atl_utils_mbox mbox;
128 u64 speed;
129 u32 itr_tx;
130 u32 itr_rx;
131 unsigned int chip_features;
132 u32 fw_ver_actual;
133 atomic_t dpc;
134 u32 mbox_addr;
135 u32 rpc_addr;
136 u32 rpc_tid;
137 struct hw_aq_atl_utils_fw_rpc rpc;
138};
139
140#define SELF ((struct hw_atl_s *)self)
141
142#define PHAL_ATLANTIC ((struct hw_atl_s *)((void *)(self)))
143#define PHAL_ATLANTIC_A0 ((struct hw_atl_s *)((void *)(self)))
144#define PHAL_ATLANTIC_B0 ((struct hw_atl_s *)((void *)(self)))
145
146#define HAL_ATLANTIC_UTILS_CHIP_MIPS 0x00000001U
147#define HAL_ATLANTIC_UTILS_CHIP_TPO2 0x00000002U
148#define HAL_ATLANTIC_UTILS_CHIP_RPF2 0x00000004U
149#define HAL_ATLANTIC_UTILS_CHIP_MPI_AQ 0x00000010U
150#define HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 0x01000000U
151#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 0x02000000U
152
153#define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \
154 PHAL_ATLANTIC->chip_features)
155
156enum hal_atl_utils_fw_state_e {
157 MPI_DEINIT = 0,
158 MPI_RESET = 1,
159 MPI_INIT = 2,
160 MPI_POWER = 4,
161};
162
163#define HAL_ATLANTIC_RATE_10G BIT(0)
164#define HAL_ATLANTIC_RATE_5G BIT(1)
165#define HAL_ATLANTIC_RATE_5GSR BIT(2)
166#define HAL_ATLANTIC_RATE_2GS BIT(3)
167#define HAL_ATLANTIC_RATE_1G BIT(4)
168#define HAL_ATLANTIC_RATE_100M BIT(5)
169#define HAL_ATLANTIC_RATE_INVALID BIT(6)
170
171void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p);
172
173void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
174 struct hw_aq_atl_utils_mbox *pmbox);
175
176void hw_atl_utils_mpi_set(struct aq_hw_s *self,
177 enum hal_atl_utils_fw_state_e state,
178 u32 speed);
179
180int hw_atl_utils_mpi_set_speed(struct aq_hw_s *self, u32 speed,
181 enum hal_atl_utils_fw_state_e state);
182
183int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self,
184 struct aq_hw_link_status_s *link_status);
185
186int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self,
187 struct aq_hw_caps_s *aq_hw_caps,
188 u8 *mac);
189
190unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps);
191
192int hw_atl_utils_hw_get_regs(struct aq_hw_s *self,
193 struct aq_hw_caps_s *aq_hw_caps,
194 u32 *regs_buff);
195
196int hw_atl_utils_hw_get_settings(struct aq_hw_s *self,
197 struct ethtool_cmd *cmd);
198
199int hw_atl_utils_hw_set_power(struct aq_hw_s *self,
200 unsigned int power_state);
201
202int hw_atl_utils_hw_deinit(struct aq_hw_s *self);
203
204int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version);
205
206int hw_atl_utils_get_hw_stats(struct aq_hw_s *self,
207 u64 *data,
208 unsigned int *p_count);
209
210#endif /* HW_ATL_UTILS_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/ver.h b/drivers/net/ethernet/aquantia/atlantic/ver.h
new file mode 100644
index 000000000000..0de858d215c2
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/ver.h
@@ -0,0 +1,18 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10#ifndef VER_H
11#define VER_H
12
13#define NIC_MAJOR_DRIVER_VERSION 1
14#define NIC_MINOR_DRIVER_VERSION 5
15#define NIC_BUILD_DRIVER_VERSION 345
16#define NIC_REVISION_DRIVER_VERSION 0
17
18#endif /* VER_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 01:35:28 -0400