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authorAlex Deucher <alexander.deucher@amd.com>2016-11-15 17:37:41 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-07-14 11:05:49 -0400
commit71086a3e8470eee3e54a454d276e6f214be28fdc (patch)
tree77aacaebdde605d1a81a000ed3bd0fc87653e54c
parent219611db30573bab37ff46f4e36571eba0bbd6a5 (diff)
drm/amdgpu/gmc6: drop fb location programming
No need to do this as the vbios does this for us. As such we no longer need to stop the mc during init. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c15
1 files changed, 0 insertions, 15 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 224b6935c885..a652fbaa7b8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -243,8 +243,6 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
243 243
244static void gmc_v6_0_mc_program(struct amdgpu_device *adev) 244static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
245{ 245{
246 struct amdgpu_mode_mc_save save;
247 u32 tmp;
248 int i, j; 246 int i, j;
249 247
250 /* Initialize HDP */ 248 /* Initialize HDP */
@@ -257,11 +255,6 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
257 } 255 }
258 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 256 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
259 257
260 if (adev->mode_info.num_crtc)
261 amdgpu_display_set_vga_render_state(adev, false);
262
263 gmc_v6_0_mc_stop(adev, &save);
264
265 if (gmc_v6_0_wait_for_idle((void *)adev)) { 258 if (gmc_v6_0_wait_for_idle((void *)adev)) {
266 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 259 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
267 } 260 }
@@ -274,13 +267,6 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
274 adev->mc.vram_end >> 12); 267 adev->mc.vram_end >> 12);
275 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 268 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
276 adev->vram_scratch.gpu_addr >> 12); 269 adev->vram_scratch.gpu_addr >> 12);
277 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
278 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
279 WREG32(mmMC_VM_FB_LOCATION, tmp);
280 /* XXX double check these! */
281 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
282 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
283 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
284 WREG32(mmMC_VM_AGP_BASE, 0); 270 WREG32(mmMC_VM_AGP_BASE, 0);
285 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 271 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
286 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 272 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
@@ -288,7 +274,6 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
288 if (gmc_v6_0_wait_for_idle((void *)adev)) { 274 if (gmc_v6_0_wait_for_idle((void *)adev)) {
289 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 275 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
290 } 276 }
291 gmc_v6_0_mc_resume(adev, &save);
292} 277}
293 278
294static int gmc_v6_0_mc_init(struct amdgpu_device *adev) 279static int gmc_v6_0_mc_init(struct amdgpu_device *adev)