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authorMichael Turquette <mturquette@baylibre.com>2017-12-19 17:44:25 -0500
committerMichael Turquette <mturquette@baylibre.com>2017-12-19 17:44:25 -0500
commit70d7aebe63985808b604c20a17875a7f07f16900 (patch)
tree751fa6f96d4778d1eb293c115b3ee29749e906c1
parent8049d8118ac95ff4b27dab4fded45cc2c0cd71b0 (diff)
parent78b4af312f910e4f28ebf4cb0a8c1983daa16924 (diff)
Merge tag 'meson-clk-for-v4.16-2' of git://github.com/BayLibre/clk-meson into clk-meson
Second round of meson clock updates for v4.16 * Rename clock lock to help in case of lockdep issues * Initial axg support
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt7
-rw-r--r--arch/arm64/Kconfig.platforms1
-rw-r--r--drivers/clk/meson/Kconfig8
-rw-r--r--drivers/clk/meson/Makefile1
-rw-r--r--drivers/clk/meson/axg.c936
-rw-r--r--drivers/clk/meson/axg.h126
-rw-r--r--drivers/clk/meson/clkc.h2
-rw-r--r--drivers/clk/meson/gxbb.c112
-rw-r--r--drivers/clk/meson/meson8b.c24
-rw-r--r--include/dt-bindings/clock/axg-clkc.h71
10 files changed, 1217 insertions, 71 deletions
diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
index 924040769186..e2b377ed6f91 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
@@ -5,8 +5,11 @@ controllers within the SoC.
5 5
6Required Properties: 6Required Properties:
7 7
8- compatible: should be "amlogic,gxbb-clkc" for GXBB SoC, 8- compatible: should be:
9 or "amlogic,gxl-clkc" for GXL and GXM SoC. 9 "amlogic,gxbb-clkc" for GXBB SoC,
10 "amlogic,gxl-clkc" for GXL and GXM SoC,
11 "amlogic,axg-clkc" for AXG SoC.
12
10- reg: physical base address of the clock controller and length of memory 13- reg: physical base address of the clock controller and length of memory
11 mapped region. 14 mapped region.
12 15
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 2401373565ff..fbedbd8f619a 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -105,6 +105,7 @@ config ARCH_MESON
105 select PINCTRL_MESON 105 select PINCTRL_MESON
106 select COMMON_CLK_AMLOGIC 106 select COMMON_CLK_AMLOGIC
107 select COMMON_CLK_GXBB 107 select COMMON_CLK_GXBB
108 select COMMON_CLK_AXG
108 select MESON_IRQ_GPIO 109 select MESON_IRQ_GPIO
109 help 110 help
110 This enables support for the Amlogic S905 SoCs. 111 This enables support for the Amlogic S905 SoCs.
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index d2d0174a6eca..7694302c70a4 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -19,3 +19,11 @@ config COMMON_CLK_GXBB
19 help 19 help
20 Support for the clock controller on AmLogic S905 devices, aka gxbb. 20 Support for the clock controller on AmLogic S905 devices, aka gxbb.
21 Say Y if you want peripherals and CPU frequency scaling to work. 21 Say Y if you want peripherals and CPU frequency scaling to work.
22
23config COMMON_CLK_AXG
24 bool
25 depends on COMMON_CLK_AMLOGIC
26 select RESET_CONTROLLER
27 help
28 Support for the clock controller on AmLogic A113D devices, aka axg.
29 Say Y if you want peripherals and CPU frequency scaling to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index b139d41b25da..3c03ce583798 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -5,3 +5,4 @@
5obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o 5obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
6obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o 6obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
7obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o gxbb-aoclk-32k.o 7obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o gxbb-aoclk-32k.o
8obj-$(CONFIG_COMMON_CLK_AXG) += axg.o
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
new file mode 100644
index 000000000000..a66b3a5e7ec0
--- /dev/null
+++ b/drivers/clk/meson/axg.c
@@ -0,0 +1,936 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * AmLogic Meson-AXG Clock Controller Driver
4 *
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
7 *
8 * Copyright (c) 2017 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
10 */
11
12#include <linux/clk.h>
13#include <linux/clk-provider.h>
14#include <linux/of_address.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include <linux/init.h>
18
19#include "clkc.h"
20#include "axg.h"
21
22static DEFINE_SPINLOCK(meson_clk_lock);
23
24static const struct pll_rate_table sys_pll_rate_table[] = {
25 PLL_RATE(24000000, 56, 1, 2),
26 PLL_RATE(48000000, 64, 1, 2),
27 PLL_RATE(72000000, 72, 1, 2),
28 PLL_RATE(96000000, 64, 1, 2),
29 PLL_RATE(120000000, 80, 1, 2),
30 PLL_RATE(144000000, 96, 1, 2),
31 PLL_RATE(168000000, 56, 1, 1),
32 PLL_RATE(192000000, 64, 1, 1),
33 PLL_RATE(216000000, 72, 1, 1),
34 PLL_RATE(240000000, 80, 1, 1),
35 PLL_RATE(264000000, 88, 1, 1),
36 PLL_RATE(288000000, 96, 1, 1),
37 PLL_RATE(312000000, 52, 1, 2),
38 PLL_RATE(336000000, 56, 1, 2),
39 PLL_RATE(360000000, 60, 1, 2),
40 PLL_RATE(384000000, 64, 1, 2),
41 PLL_RATE(408000000, 68, 1, 2),
42 PLL_RATE(432000000, 72, 1, 2),
43 PLL_RATE(456000000, 76, 1, 2),
44 PLL_RATE(480000000, 80, 1, 2),
45 PLL_RATE(504000000, 84, 1, 2),
46 PLL_RATE(528000000, 88, 1, 2),
47 PLL_RATE(552000000, 92, 1, 2),
48 PLL_RATE(576000000, 96, 1, 2),
49 PLL_RATE(600000000, 50, 1, 1),
50 PLL_RATE(624000000, 52, 1, 1),
51 PLL_RATE(648000000, 54, 1, 1),
52 PLL_RATE(672000000, 56, 1, 1),
53 PLL_RATE(696000000, 58, 1, 1),
54 PLL_RATE(720000000, 60, 1, 1),
55 PLL_RATE(744000000, 62, 1, 1),
56 PLL_RATE(768000000, 64, 1, 1),
57 PLL_RATE(792000000, 66, 1, 1),
58 PLL_RATE(816000000, 68, 1, 1),
59 PLL_RATE(840000000, 70, 1, 1),
60 PLL_RATE(864000000, 72, 1, 1),
61 PLL_RATE(888000000, 74, 1, 1),
62 PLL_RATE(912000000, 76, 1, 1),
63 PLL_RATE(936000000, 78, 1, 1),
64 PLL_RATE(960000000, 80, 1, 1),
65 PLL_RATE(984000000, 82, 1, 1),
66 PLL_RATE(1008000000, 84, 1, 1),
67 PLL_RATE(1032000000, 86, 1, 1),
68 PLL_RATE(1056000000, 88, 1, 1),
69 PLL_RATE(1080000000, 90, 1, 1),
70 PLL_RATE(1104000000, 92, 1, 1),
71 PLL_RATE(1128000000, 94, 1, 1),
72 PLL_RATE(1152000000, 96, 1, 1),
73 PLL_RATE(1176000000, 98, 1, 1),
74 PLL_RATE(1200000000, 50, 1, 0),
75 PLL_RATE(1224000000, 51, 1, 0),
76 PLL_RATE(1248000000, 52, 1, 0),
77 PLL_RATE(1272000000, 53, 1, 0),
78 PLL_RATE(1296000000, 54, 1, 0),
79 PLL_RATE(1320000000, 55, 1, 0),
80 PLL_RATE(1344000000, 56, 1, 0),
81 PLL_RATE(1368000000, 57, 1, 0),
82 PLL_RATE(1392000000, 58, 1, 0),
83 PLL_RATE(1416000000, 59, 1, 0),
84 PLL_RATE(1440000000, 60, 1, 0),
85 PLL_RATE(1464000000, 61, 1, 0),
86 PLL_RATE(1488000000, 62, 1, 0),
87 PLL_RATE(1512000000, 63, 1, 0),
88 PLL_RATE(1536000000, 64, 1, 0),
89 PLL_RATE(1560000000, 65, 1, 0),
90 PLL_RATE(1584000000, 66, 1, 0),
91 PLL_RATE(1608000000, 67, 1, 0),
92 PLL_RATE(1632000000, 68, 1, 0),
93 PLL_RATE(1656000000, 68, 1, 0),
94 PLL_RATE(1680000000, 68, 1, 0),
95 PLL_RATE(1704000000, 68, 1, 0),
96 PLL_RATE(1728000000, 69, 1, 0),
97 PLL_RATE(1752000000, 69, 1, 0),
98 PLL_RATE(1776000000, 69, 1, 0),
99 PLL_RATE(1800000000, 69, 1, 0),
100 PLL_RATE(1824000000, 70, 1, 0),
101 PLL_RATE(1848000000, 70, 1, 0),
102 PLL_RATE(1872000000, 70, 1, 0),
103 PLL_RATE(1896000000, 70, 1, 0),
104 PLL_RATE(1920000000, 71, 1, 0),
105 PLL_RATE(1944000000, 71, 1, 0),
106 PLL_RATE(1968000000, 71, 1, 0),
107 PLL_RATE(1992000000, 71, 1, 0),
108 PLL_RATE(2016000000, 72, 1, 0),
109 PLL_RATE(2040000000, 72, 1, 0),
110 PLL_RATE(2064000000, 72, 1, 0),
111 PLL_RATE(2088000000, 72, 1, 0),
112 PLL_RATE(2112000000, 73, 1, 0),
113 { /* sentinel */ },
114};
115
116static struct meson_clk_pll axg_fixed_pll = {
117 .m = {
118 .reg_off = HHI_MPLL_CNTL,
119 .shift = 0,
120 .width = 9,
121 },
122 .n = {
123 .reg_off = HHI_MPLL_CNTL,
124 .shift = 9,
125 .width = 5,
126 },
127 .od = {
128 .reg_off = HHI_MPLL_CNTL,
129 .shift = 16,
130 .width = 2,
131 },
132 .lock = &meson_clk_lock,
133 .hw.init = &(struct clk_init_data){
134 .name = "fixed_pll",
135 .ops = &meson_clk_pll_ro_ops,
136 .parent_names = (const char *[]){ "xtal" },
137 .num_parents = 1,
138 },
139};
140
141static struct meson_clk_pll axg_sys_pll = {
142 .m = {
143 .reg_off = HHI_SYS_PLL_CNTL,
144 .shift = 0,
145 .width = 9,
146 },
147 .n = {
148 .reg_off = HHI_SYS_PLL_CNTL,
149 .shift = 9,
150 .width = 5,
151 },
152 .od = {
153 .reg_off = HHI_SYS_PLL_CNTL,
154 .shift = 10,
155 .width = 2,
156 },
157 .rate_table = sys_pll_rate_table,
158 .rate_count = ARRAY_SIZE(sys_pll_rate_table),
159 .lock = &meson_clk_lock,
160 .hw.init = &(struct clk_init_data){
161 .name = "sys_pll",
162 .ops = &meson_clk_pll_ro_ops,
163 .parent_names = (const char *[]){ "xtal" },
164 .num_parents = 1,
165 .flags = CLK_GET_RATE_NOCACHE,
166 },
167};
168
169static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
170 PLL_RATE(240000000, 40, 1, 2),
171 PLL_RATE(246000000, 41, 1, 2),
172 PLL_RATE(252000000, 42, 1, 2),
173 PLL_RATE(258000000, 43, 1, 2),
174 PLL_RATE(264000000, 44, 1, 2),
175 PLL_RATE(270000000, 45, 1, 2),
176 PLL_RATE(276000000, 46, 1, 2),
177 PLL_RATE(282000000, 47, 1, 2),
178 PLL_RATE(288000000, 48, 1, 2),
179 PLL_RATE(294000000, 49, 1, 2),
180 PLL_RATE(300000000, 50, 1, 2),
181 PLL_RATE(306000000, 51, 1, 2),
182 PLL_RATE(312000000, 52, 1, 2),
183 PLL_RATE(318000000, 53, 1, 2),
184 PLL_RATE(324000000, 54, 1, 2),
185 PLL_RATE(330000000, 55, 1, 2),
186 PLL_RATE(336000000, 56, 1, 2),
187 PLL_RATE(342000000, 57, 1, 2),
188 PLL_RATE(348000000, 58, 1, 2),
189 PLL_RATE(354000000, 59, 1, 2),
190 PLL_RATE(360000000, 60, 1, 2),
191 PLL_RATE(366000000, 61, 1, 2),
192 PLL_RATE(372000000, 62, 1, 2),
193 PLL_RATE(378000000, 63, 1, 2),
194 PLL_RATE(384000000, 64, 1, 2),
195 PLL_RATE(390000000, 65, 1, 3),
196 PLL_RATE(396000000, 66, 1, 3),
197 PLL_RATE(402000000, 67, 1, 3),
198 PLL_RATE(408000000, 68, 1, 3),
199 PLL_RATE(480000000, 40, 1, 1),
200 PLL_RATE(492000000, 41, 1, 1),
201 PLL_RATE(504000000, 42, 1, 1),
202 PLL_RATE(516000000, 43, 1, 1),
203 PLL_RATE(528000000, 44, 1, 1),
204 PLL_RATE(540000000, 45, 1, 1),
205 PLL_RATE(552000000, 46, 1, 1),
206 PLL_RATE(564000000, 47, 1, 1),
207 PLL_RATE(576000000, 48, 1, 1),
208 PLL_RATE(588000000, 49, 1, 1),
209 PLL_RATE(600000000, 50, 1, 1),
210 PLL_RATE(612000000, 51, 1, 1),
211 PLL_RATE(624000000, 52, 1, 1),
212 PLL_RATE(636000000, 53, 1, 1),
213 PLL_RATE(648000000, 54, 1, 1),
214 PLL_RATE(660000000, 55, 1, 1),
215 PLL_RATE(672000000, 56, 1, 1),
216 PLL_RATE(684000000, 57, 1, 1),
217 PLL_RATE(696000000, 58, 1, 1),
218 PLL_RATE(708000000, 59, 1, 1),
219 PLL_RATE(720000000, 60, 1, 1),
220 PLL_RATE(732000000, 61, 1, 1),
221 PLL_RATE(744000000, 62, 1, 1),
222 PLL_RATE(756000000, 63, 1, 1),
223 PLL_RATE(768000000, 64, 1, 1),
224 PLL_RATE(780000000, 65, 1, 1),
225 PLL_RATE(792000000, 66, 1, 1),
226 PLL_RATE(804000000, 67, 1, 1),
227 PLL_RATE(816000000, 68, 1, 1),
228 PLL_RATE(960000000, 40, 1, 0),
229 PLL_RATE(984000000, 41, 1, 0),
230 PLL_RATE(1008000000, 42, 1, 0),
231 PLL_RATE(1032000000, 43, 1, 0),
232 PLL_RATE(1056000000, 44, 1, 0),
233 PLL_RATE(1080000000, 45, 1, 0),
234 PLL_RATE(1104000000, 46, 1, 0),
235 PLL_RATE(1128000000, 47, 1, 0),
236 PLL_RATE(1152000000, 48, 1, 0),
237 PLL_RATE(1176000000, 49, 1, 0),
238 PLL_RATE(1200000000, 50, 1, 0),
239 PLL_RATE(1224000000, 51, 1, 0),
240 PLL_RATE(1248000000, 52, 1, 0),
241 PLL_RATE(1272000000, 53, 1, 0),
242 PLL_RATE(1296000000, 54, 1, 0),
243 PLL_RATE(1320000000, 55, 1, 0),
244 PLL_RATE(1344000000, 56, 1, 0),
245 PLL_RATE(1368000000, 57, 1, 0),
246 PLL_RATE(1392000000, 58, 1, 0),
247 PLL_RATE(1416000000, 59, 1, 0),
248 PLL_RATE(1440000000, 60, 1, 0),
249 PLL_RATE(1464000000, 61, 1, 0),
250 PLL_RATE(1488000000, 62, 1, 0),
251 PLL_RATE(1512000000, 63, 1, 0),
252 PLL_RATE(1536000000, 64, 1, 0),
253 PLL_RATE(1560000000, 65, 1, 0),
254 PLL_RATE(1584000000, 66, 1, 0),
255 PLL_RATE(1608000000, 67, 1, 0),
256 PLL_RATE(1632000000, 68, 1, 0),
257 { /* sentinel */ },
258};
259
260struct pll_params_table axg_gp0_params_table[] = {
261 PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250),
262 PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000),
263 PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be),
264 PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288),
265 PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d),
266 PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000),
267};
268
269static struct meson_clk_pll axg_gp0_pll = {
270 .m = {
271 .reg_off = HHI_GP0_PLL_CNTL,
272 .shift = 0,
273 .width = 9,
274 },
275 .n = {
276 .reg_off = HHI_GP0_PLL_CNTL,
277 .shift = 9,
278 .width = 5,
279 },
280 .od = {
281 .reg_off = HHI_GP0_PLL_CNTL,
282 .shift = 16,
283 .width = 2,
284 },
285 .params = {
286 .params_table = axg_gp0_params_table,
287 .params_count = ARRAY_SIZE(axg_gp0_params_table),
288 .no_init_reset = true,
289 .reset_lock_loop = true,
290 },
291 .rate_table = axg_gp0_pll_rate_table,
292 .rate_count = ARRAY_SIZE(axg_gp0_pll_rate_table),
293 .lock = &meson_clk_lock,
294 .hw.init = &(struct clk_init_data){
295 .name = "gp0_pll",
296 .ops = &meson_clk_pll_ops,
297 .parent_names = (const char *[]){ "xtal" },
298 .num_parents = 1,
299 },
300};
301
302
303static struct clk_fixed_factor axg_fclk_div2 = {
304 .mult = 1,
305 .div = 2,
306 .hw.init = &(struct clk_init_data){
307 .name = "fclk_div2",
308 .ops = &clk_fixed_factor_ops,
309 .parent_names = (const char *[]){ "fixed_pll" },
310 .num_parents = 1,
311 },
312};
313
314static struct clk_fixed_factor axg_fclk_div3 = {
315 .mult = 1,
316 .div = 3,
317 .hw.init = &(struct clk_init_data){
318 .name = "fclk_div3",
319 .ops = &clk_fixed_factor_ops,
320 .parent_names = (const char *[]){ "fixed_pll" },
321 .num_parents = 1,
322 },
323};
324
325static struct clk_fixed_factor axg_fclk_div4 = {
326 .mult = 1,
327 .div = 4,
328 .hw.init = &(struct clk_init_data){
329 .name = "fclk_div4",
330 .ops = &clk_fixed_factor_ops,
331 .parent_names = (const char *[]){ "fixed_pll" },
332 .num_parents = 1,
333 },
334};
335
336static struct clk_fixed_factor axg_fclk_div5 = {
337 .mult = 1,
338 .div = 5,
339 .hw.init = &(struct clk_init_data){
340 .name = "fclk_div5",
341 .ops = &clk_fixed_factor_ops,
342 .parent_names = (const char *[]){ "fixed_pll" },
343 .num_parents = 1,
344 },
345};
346
347static struct clk_fixed_factor axg_fclk_div7 = {
348 .mult = 1,
349 .div = 7,
350 .hw.init = &(struct clk_init_data){
351 .name = "fclk_div7",
352 .ops = &clk_fixed_factor_ops,
353 .parent_names = (const char *[]){ "fixed_pll" },
354 .num_parents = 1,
355 },
356};
357
358static struct meson_clk_mpll axg_mpll0 = {
359 .sdm = {
360 .reg_off = HHI_MPLL_CNTL7,
361 .shift = 0,
362 .width = 14,
363 },
364 .sdm_en = {
365 .reg_off = HHI_MPLL_CNTL7,
366 .shift = 15,
367 .width = 1,
368 },
369 .n2 = {
370 .reg_off = HHI_MPLL_CNTL7,
371 .shift = 16,
372 .width = 9,
373 },
374 .en = {
375 .reg_off = HHI_MPLL_CNTL7,
376 .shift = 14,
377 .width = 1,
378 },
379 .ssen = {
380 .reg_off = HHI_MPLL_CNTL,
381 .shift = 25,
382 .width = 1,
383 },
384 .lock = &meson_clk_lock,
385 .hw.init = &(struct clk_init_data){
386 .name = "mpll0",
387 .ops = &meson_clk_mpll_ops,
388 .parent_names = (const char *[]){ "fixed_pll" },
389 .num_parents = 1,
390 },
391};
392
393static struct meson_clk_mpll axg_mpll1 = {
394 .sdm = {
395 .reg_off = HHI_MPLL_CNTL8,
396 .shift = 0,
397 .width = 14,
398 },
399 .sdm_en = {
400 .reg_off = HHI_MPLL_CNTL8,
401 .shift = 15,
402 .width = 1,
403 },
404 .n2 = {
405 .reg_off = HHI_MPLL_CNTL8,
406 .shift = 16,
407 .width = 9,
408 },
409 .en = {
410 .reg_off = HHI_MPLL_CNTL8,
411 .shift = 14,
412 .width = 1,
413 },
414 .lock = &meson_clk_lock,
415 .hw.init = &(struct clk_init_data){
416 .name = "mpll1",
417 .ops = &meson_clk_mpll_ops,
418 .parent_names = (const char *[]){ "fixed_pll" },
419 .num_parents = 1,
420 },
421};
422
423static struct meson_clk_mpll axg_mpll2 = {
424 .sdm = {
425 .reg_off = HHI_MPLL_CNTL9,
426 .shift = 0,
427 .width = 14,
428 },
429 .sdm_en = {
430 .reg_off = HHI_MPLL_CNTL9,
431 .shift = 15,
432 .width = 1,
433 },
434 .n2 = {
435 .reg_off = HHI_MPLL_CNTL9,
436 .shift = 16,
437 .width = 9,
438 },
439 .en = {
440 .reg_off = HHI_MPLL_CNTL9,
441 .shift = 14,
442 .width = 1,
443 },
444 .lock = &meson_clk_lock,
445 .hw.init = &(struct clk_init_data){
446 .name = "mpll2",
447 .ops = &meson_clk_mpll_ops,
448 .parent_names = (const char *[]){ "fixed_pll" },
449 .num_parents = 1,
450 },
451};
452
453static struct meson_clk_mpll axg_mpll3 = {
454 .sdm = {
455 .reg_off = HHI_MPLL3_CNTL0,
456 .shift = 12,
457 .width = 14,
458 },
459 .sdm_en = {
460 .reg_off = HHI_MPLL3_CNTL0,
461 .shift = 11,
462 .width = 1,
463 },
464 .n2 = {
465 .reg_off = HHI_MPLL3_CNTL0,
466 .shift = 2,
467 .width = 9,
468 },
469 .en = {
470 .reg_off = HHI_MPLL3_CNTL0,
471 .shift = 0,
472 .width = 1,
473 },
474 .lock = &meson_clk_lock,
475 .hw.init = &(struct clk_init_data){
476 .name = "mpll3",
477 .ops = &meson_clk_mpll_ops,
478 .parent_names = (const char *[]){ "fixed_pll" },
479 .num_parents = 1,
480 },
481};
482
483/*
484 * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers
485 * and should be modeled with their respective PLLs via the forthcoming
486 * coordinated clock rates feature
487 */
488static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
489static const char * const clk81_parent_names[] = {
490 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
491 "fclk_div3", "fclk_div5"
492};
493
494static struct clk_mux axg_mpeg_clk_sel = {
495 .reg = (void *)HHI_MPEG_CLK_CNTL,
496 .mask = 0x7,
497 .shift = 12,
498 .flags = CLK_MUX_READ_ONLY,
499 .table = mux_table_clk81,
500 .lock = &meson_clk_lock,
501 .hw.init = &(struct clk_init_data){
502 .name = "mpeg_clk_sel",
503 .ops = &clk_mux_ro_ops,
504 .parent_names = clk81_parent_names,
505 .num_parents = ARRAY_SIZE(clk81_parent_names),
506 },
507};
508
509static struct clk_divider axg_mpeg_clk_div = {
510 .reg = (void *)HHI_MPEG_CLK_CNTL,
511 .shift = 0,
512 .width = 7,
513 .lock = &meson_clk_lock,
514 .hw.init = &(struct clk_init_data){
515 .name = "mpeg_clk_div",
516 .ops = &clk_divider_ops,
517 .parent_names = (const char *[]){ "mpeg_clk_sel" },
518 .num_parents = 1,
519 .flags = CLK_SET_RATE_PARENT,
520 },
521};
522
523static struct clk_gate axg_clk81 = {
524 .reg = (void *)HHI_MPEG_CLK_CNTL,
525 .bit_idx = 7,
526 .lock = &meson_clk_lock,
527 .hw.init = &(struct clk_init_data){
528 .name = "clk81",
529 .ops = &clk_gate_ops,
530 .parent_names = (const char *[]){ "mpeg_clk_div" },
531 .num_parents = 1,
532 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
533 },
534};
535
536static const char * const axg_sd_emmc_clk0_parent_names[] = {
537 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
538
539 /*
540 * Following these parent clocks, we should also have had mpll2, mpll3
541 * and gp0_pll but these clocks are too precious to be used here. All
542 * the necessary rates for MMC and NAND operation can be acheived using
543 * xtal or fclk_div clocks
544 */
545};
546
547/* SDcard clock */
548static struct clk_mux axg_sd_emmc_b_clk0_sel = {
549 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
550 .mask = 0x7,
551 .shift = 25,
552 .lock = &meson_clk_lock,
553 .hw.init = &(struct clk_init_data) {
554 .name = "sd_emmc_b_clk0_sel",
555 .ops = &clk_mux_ops,
556 .parent_names = axg_sd_emmc_clk0_parent_names,
557 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
558 .flags = CLK_SET_RATE_PARENT,
559 },
560};
561
562static struct clk_divider axg_sd_emmc_b_clk0_div = {
563 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
564 .shift = 16,
565 .width = 7,
566 .lock = &meson_clk_lock,
567 .flags = CLK_DIVIDER_ROUND_CLOSEST,
568 .hw.init = &(struct clk_init_data) {
569 .name = "sd_emmc_b_clk0_div",
570 .ops = &clk_divider_ops,
571 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
572 .num_parents = 1,
573 .flags = CLK_SET_RATE_PARENT,
574 },
575};
576
577static struct clk_gate axg_sd_emmc_b_clk0 = {
578 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
579 .bit_idx = 23,
580 .lock = &meson_clk_lock,
581 .hw.init = &(struct clk_init_data){
582 .name = "sd_emmc_b_clk0",
583 .ops = &clk_gate_ops,
584 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
585 .num_parents = 1,
586 .flags = CLK_SET_RATE_PARENT,
587 },
588};
589
590/* EMMC/NAND clock */
591static struct clk_mux axg_sd_emmc_c_clk0_sel = {
592 .reg = (void *)HHI_NAND_CLK_CNTL,
593 .mask = 0x7,
594 .shift = 9,
595 .lock = &meson_clk_lock,
596 .hw.init = &(struct clk_init_data) {
597 .name = "sd_emmc_c_clk0_sel",
598 .ops = &clk_mux_ops,
599 .parent_names = axg_sd_emmc_clk0_parent_names,
600 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
601 .flags = CLK_SET_RATE_PARENT,
602 },
603};
604
605static struct clk_divider axg_sd_emmc_c_clk0_div = {
606 .reg = (void *)HHI_NAND_CLK_CNTL,
607 .shift = 0,
608 .width = 7,
609 .lock = &meson_clk_lock,
610 .flags = CLK_DIVIDER_ROUND_CLOSEST,
611 .hw.init = &(struct clk_init_data) {
612 .name = "sd_emmc_c_clk0_div",
613 .ops = &clk_divider_ops,
614 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
615 .num_parents = 1,
616 .flags = CLK_SET_RATE_PARENT,
617 },
618};
619
620static struct clk_gate axg_sd_emmc_c_clk0 = {
621 .reg = (void *)HHI_NAND_CLK_CNTL,
622 .bit_idx = 7,
623 .lock = &meson_clk_lock,
624 .hw.init = &(struct clk_init_data){
625 .name = "sd_emmc_c_clk0",
626 .ops = &clk_gate_ops,
627 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
628 .num_parents = 1,
629 .flags = CLK_SET_RATE_PARENT,
630 },
631};
632
633/* Everything Else (EE) domain gates */
634static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
635static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
636static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
637static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
638static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
639static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
640static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
641static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
642static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
643static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
644static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
645static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
646static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
647static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
648static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
649static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
650static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
651static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
652static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
653static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
654
655static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
656static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
657static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
658static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
659static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
660static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
661static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
662static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
663static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
664static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
665static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
666
667static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
668static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
669static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
670static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
671static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
672static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
673static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
674static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
675
676/* Always On (AO) domain gates */
677
678static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
679static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
680static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
681static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
682static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
683
684/* Array of all clocks provided by this provider */
685
686static struct clk_hw_onecell_data axg_hw_onecell_data = {
687 .hws = {
688 [CLKID_SYS_PLL] = &axg_sys_pll.hw,
689 [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
690 [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
691 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
692 [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
693 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
694 [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
695 [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
696 [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
697 [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
698 [CLKID_CLK81] = &axg_clk81.hw,
699 [CLKID_MPLL0] = &axg_mpll0.hw,
700 [CLKID_MPLL1] = &axg_mpll1.hw,
701 [CLKID_MPLL2] = &axg_mpll2.hw,
702 [CLKID_MPLL3] = &axg_mpll3.hw,
703 [CLKID_DDR] = &axg_ddr.hw,
704 [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
705 [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
706 [CLKID_ISA] = &axg_isa.hw,
707 [CLKID_PL301] = &axg_pl301.hw,
708 [CLKID_PERIPHS] = &axg_periphs.hw,
709 [CLKID_SPICC0] = &axg_spicc_0.hw,
710 [CLKID_I2C] = &axg_i2c.hw,
711 [CLKID_RNG0] = &axg_rng0.hw,
712 [CLKID_UART0] = &axg_uart0.hw,
713 [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
714 [CLKID_SPICC1] = &axg_spicc_1.hw,
715 [CLKID_PCIE_A] = &axg_pcie_a.hw,
716 [CLKID_PCIE_B] = &axg_pcie_b.hw,
717 [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
718 [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
719 [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
720 [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
721 [CLKID_DMA] = &axg_dma.hw,
722 [CLKID_SPI] = &axg_spi.hw,
723 [CLKID_AUDIO] = &axg_audio.hw,
724 [CLKID_ETH] = &axg_eth_core.hw,
725 [CLKID_UART1] = &axg_uart1.hw,
726 [CLKID_G2D] = &axg_g2d.hw,
727 [CLKID_USB0] = &axg_usb0.hw,
728 [CLKID_USB1] = &axg_usb1.hw,
729 [CLKID_RESET] = &axg_reset.hw,
730 [CLKID_USB] = &axg_usb_general.hw,
731 [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
732 [CLKID_EFUSE] = &axg_efuse.hw,
733 [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
734 [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
735 [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
736 [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
737 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
738 [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
739 [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
740 [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
741 [CLKID_GIC] = &axg_gic.hw,
742 [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
743 [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
744 [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
745 [CLKID_AO_IFACE] = &axg_ao_iface.hw,
746 [CLKID_AO_I2C] = &axg_ao_i2c.hw,
747 [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
748 [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
749 [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
750 [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
751 [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
752 [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
753 [NR_CLKS] = NULL,
754 },
755 .num = NR_CLKS,
756};
757
758/* Convenience tables to populate base addresses in .probe */
759
760static struct meson_clk_pll *const axg_clk_plls[] = {
761 &axg_fixed_pll,
762 &axg_sys_pll,
763 &axg_gp0_pll,
764};
765
766static struct meson_clk_mpll *const axg_clk_mplls[] = {
767 &axg_mpll0,
768 &axg_mpll1,
769 &axg_mpll2,
770 &axg_mpll3,
771};
772
773static struct clk_gate *const axg_clk_gates[] = {
774 &axg_clk81,
775 &axg_ddr,
776 &axg_audio_locker,
777 &axg_mipi_dsi_host,
778 &axg_isa,
779 &axg_pl301,
780 &axg_periphs,
781 &axg_spicc_0,
782 &axg_i2c,
783 &axg_rng0,
784 &axg_uart0,
785 &axg_mipi_dsi_phy,
786 &axg_spicc_1,
787 &axg_pcie_a,
788 &axg_pcie_b,
789 &axg_hiu_reg,
790 &axg_assist_misc,
791 &axg_emmc_b,
792 &axg_emmc_c,
793 &axg_dma,
794 &axg_spi,
795 &axg_audio,
796 &axg_eth_core,
797 &axg_uart1,
798 &axg_g2d,
799 &axg_usb0,
800 &axg_usb1,
801 &axg_reset,
802 &axg_usb_general,
803 &axg_ahb_arb0,
804 &axg_efuse,
805 &axg_boot_rom,
806 &axg_ahb_data_bus,
807 &axg_ahb_ctrl_bus,
808 &axg_usb1_to_ddr,
809 &axg_usb0_to_ddr,
810 &axg_mmc_pclk,
811 &axg_vpu_intr,
812 &axg_sec_ahb_ahb3_bridge,
813 &axg_gic,
814 &axg_ao_media_cpu,
815 &axg_ao_ahb_sram,
816 &axg_ao_ahb_bus,
817 &axg_ao_iface,
818 &axg_ao_i2c,
819 &axg_sd_emmc_b_clk0,
820 &axg_sd_emmc_c_clk0,
821};
822
823static struct clk_mux *const axg_clk_muxes[] = {
824 &axg_mpeg_clk_sel,
825 &axg_sd_emmc_b_clk0_sel,
826 &axg_sd_emmc_c_clk0_sel,
827};
828
829static struct clk_divider *const axg_clk_dividers[] = {
830 &axg_mpeg_clk_div,
831 &axg_sd_emmc_b_clk0_div,
832 &axg_sd_emmc_c_clk0_div,
833};
834
835struct clkc_data {
836 struct clk_gate *const *clk_gates;
837 unsigned int clk_gates_count;
838 struct meson_clk_mpll *const *clk_mplls;
839 unsigned int clk_mplls_count;
840 struct meson_clk_pll *const *clk_plls;
841 unsigned int clk_plls_count;
842 struct clk_mux *const *clk_muxes;
843 unsigned int clk_muxes_count;
844 struct clk_divider *const *clk_dividers;
845 unsigned int clk_dividers_count;
846 struct clk_hw_onecell_data *hw_onecell_data;
847};
848
849static const struct clkc_data axg_clkc_data = {
850 .clk_gates = axg_clk_gates,
851 .clk_gates_count = ARRAY_SIZE(axg_clk_gates),
852 .clk_mplls = axg_clk_mplls,
853 .clk_mplls_count = ARRAY_SIZE(axg_clk_mplls),
854 .clk_plls = axg_clk_plls,
855 .clk_plls_count = ARRAY_SIZE(axg_clk_plls),
856 .clk_muxes = axg_clk_muxes,
857 .clk_muxes_count = ARRAY_SIZE(axg_clk_muxes),
858 .clk_dividers = axg_clk_dividers,
859 .clk_dividers_count = ARRAY_SIZE(axg_clk_dividers),
860 .hw_onecell_data = &axg_hw_onecell_data,
861};
862
863static const struct of_device_id clkc_match_table[] = {
864 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
865 {}
866};
867
868static int axg_clkc_probe(struct platform_device *pdev)
869{
870 struct device *dev = &pdev->dev;
871 const struct clkc_data *clkc_data;
872 struct resource *res;
873 void __iomem *clk_base;
874 int ret, clkid, i;
875
876 clkc_data = of_device_get_match_data(&pdev->dev);
877 if (!clkc_data)
878 return -EINVAL;
879
880 /* Generic clocks and PLLs */
881 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
882 clk_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
883 if (IS_ERR(clk_base)) {
884 dev_err(&pdev->dev, "Unable to map clk base\n");
885 return -ENXIO;
886 }
887
888 /* Populate base address for PLLs */
889 for (i = 0; i < clkc_data->clk_plls_count; i++)
890 clkc_data->clk_plls[i]->base = clk_base;
891
892 /* Populate base address for MPLLs */
893 for (i = 0; i < clkc_data->clk_mplls_count; i++)
894 clkc_data->clk_mplls[i]->base = clk_base;
895
896 /* Populate base address for gates */
897 for (i = 0; i < clkc_data->clk_gates_count; i++)
898 clkc_data->clk_gates[i]->reg = clk_base +
899 (u64)clkc_data->clk_gates[i]->reg;
900
901 /* Populate base address for muxes */
902 for (i = 0; i < clkc_data->clk_muxes_count; i++)
903 clkc_data->clk_muxes[i]->reg = clk_base +
904 (u64)clkc_data->clk_muxes[i]->reg;
905
906 /* Populate base address for dividers */
907 for (i = 0; i < clkc_data->clk_dividers_count; i++)
908 clkc_data->clk_dividers[i]->reg = clk_base +
909 (u64)clkc_data->clk_dividers[i]->reg;
910
911 for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) {
912 /* array might be sparse */
913 if (!clkc_data->hw_onecell_data->hws[clkid])
914 continue;
915
916 ret = devm_clk_hw_register(dev,
917 clkc_data->hw_onecell_data->hws[clkid]);
918 if (ret) {
919 dev_err(&pdev->dev, "Clock registration failed\n");
920 return ret;
921 }
922 }
923
924 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
925 clkc_data->hw_onecell_data);
926}
927
928static struct platform_driver axg_driver = {
929 .probe = axg_clkc_probe,
930 .driver = {
931 .name = "axg-clkc",
932 .of_match_table = clkc_match_table,
933 },
934};
935
936builtin_platform_driver(axg_driver);
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
new file mode 100644
index 000000000000..ce0bafdb6b28
--- /dev/null
+++ b/drivers/clk/meson/axg.h
@@ -0,0 +1,126 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2016 AmLogic, Inc.
4 * Author: Michael Turquette <mturquette@baylibre.com>
5 *
6 * Copyright (c) 2017 Amlogic, inc.
7 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
8 *
9 */
10#ifndef __AXG_H
11#define __AXG_H
12
13/*
14 * Clock controller register offsets
15 *
16 * Register offsets from the data sheet must be multiplied by 4 before
17 * adding them to the base address to get the right value.
18 */
19#define HHI_GP0_PLL_CNTL 0x40
20#define HHI_GP0_PLL_CNTL2 0x44
21#define HHI_GP0_PLL_CNTL3 0x48
22#define HHI_GP0_PLL_CNTL4 0x4c
23#define HHI_GP0_PLL_CNTL5 0x50
24#define HHI_GP0_PLL_STS 0x54
25#define HHI_GP0_PLL_CNTL1 0x58
26#define HHI_HIFI_PLL_CNTL 0x80
27#define HHI_HIFI_PLL_CNTL2 0x84
28#define HHI_HIFI_PLL_CNTL3 0x88
29#define HHI_HIFI_PLL_CNTL4 0x8C
30#define HHI_HIFI_PLL_CNTL5 0x90
31#define HHI_HIFI_PLL_STS 0x94
32#define HHI_HIFI_PLL_CNTL1 0x98
33
34#define HHI_XTAL_DIVN_CNTL 0xbc
35#define HHI_GCLK2_MPEG0 0xc0
36#define HHI_GCLK2_MPEG1 0xc4
37#define HHI_GCLK2_MPEG2 0xc8
38#define HHI_GCLK2_OTHER 0xd0
39#define HHI_GCLK2_AO 0xd4
40#define HHI_PCIE_PLL_CNTL 0xd8
41#define HHI_PCIE_PLL_CNTL1 0xdC
42#define HHI_PCIE_PLL_CNTL2 0xe0
43#define HHI_PCIE_PLL_CNTL3 0xe4
44#define HHI_PCIE_PLL_CNTL4 0xe8
45#define HHI_PCIE_PLL_CNTL5 0xec
46#define HHI_PCIE_PLL_CNTL6 0xf0
47#define HHI_PCIE_PLL_STS 0xf4
48
49#define HHI_MEM_PD_REG0 0x100
50#define HHI_VPU_MEM_PD_REG0 0x104
51#define HHI_VIID_CLK_DIV 0x128
52#define HHI_VIID_CLK_CNTL 0x12c
53
54#define HHI_GCLK_MPEG0 0x140
55#define HHI_GCLK_MPEG1 0x144
56#define HHI_GCLK_MPEG2 0x148
57#define HHI_GCLK_OTHER 0x150
58#define HHI_GCLK_AO 0x154
59#define HHI_SYS_CPU_CLK_CNTL1 0x15c
60#define HHI_SYS_CPU_RESET_CNTL 0x160
61#define HHI_VID_CLK_DIV 0x164
62#define HHI_SPICC_HCLK_CNTL 0x168
63
64#define HHI_MPEG_CLK_CNTL 0x174
65#define HHI_VID_CLK_CNTL 0x17c
66#define HHI_TS_CLK_CNTL 0x190
67#define HHI_VID_CLK_CNTL2 0x194
68#define HHI_SYS_CPU_CLK_CNTL0 0x19c
69#define HHI_VID_PLL_CLK_DIV 0x1a0
70#define HHI_VPU_CLK_CNTL 0x1bC
71
72#define HHI_VAPBCLK_CNTL 0x1F4
73
74#define HHI_GEN_CLK_CNTL 0x228
75
76#define HHI_VDIN_MEAS_CLK_CNTL 0x250
77#define HHI_NAND_CLK_CNTL 0x25C
78#define HHI_SD_EMMC_CLK_CNTL 0x264
79
80#define HHI_MPLL_CNTL 0x280
81#define HHI_MPLL_CNTL2 0x284
82#define HHI_MPLL_CNTL3 0x288
83#define HHI_MPLL_CNTL4 0x28C
84#define HHI_MPLL_CNTL5 0x290
85#define HHI_MPLL_CNTL6 0x294
86#define HHI_MPLL_CNTL7 0x298
87#define HHI_MPLL_CNTL8 0x29C
88#define HHI_MPLL_CNTL9 0x2A0
89#define HHI_MPLL_CNTL10 0x2A4
90
91#define HHI_MPLL3_CNTL0 0x2E0
92#define HHI_MPLL3_CNTL1 0x2E4
93#define HHI_PLL_TOP_MISC 0x2E8
94
95#define HHI_SYS_PLL_CNTL1 0x2FC
96#define HHI_SYS_PLL_CNTL 0x300
97#define HHI_SYS_PLL_CNTL2 0x304
98#define HHI_SYS_PLL_CNTL3 0x308
99#define HHI_SYS_PLL_CNTL4 0x30c
100#define HHI_SYS_PLL_CNTL5 0x310
101#define HHI_SYS_PLL_STS 0x314
102#define HHI_DPLL_TOP_I 0x318
103#define HHI_DPLL_TOP2_I 0x31C
104
105/*
106 * CLKID index values
107 *
108 * These indices are entirely contrived and do not map onto the hardware.
109 * It has now been decided to expose everything by default in the DT header:
110 * include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
111 * to expose, such as the internal muxes and dividers of composite clocks,
112 * will remain defined here.
113 */
114#define CLKID_MPEG_SEL 8
115#define CLKID_MPEG_DIV 9
116#define CLKID_SD_EMMC_B_CLK0_SEL 61
117#define CLKID_SD_EMMC_B_CLK0_DIV 62
118#define CLKID_SD_EMMC_C_CLK0_SEL 63
119#define CLKID_SD_EMMC_C_CLK0_DIV 64
120
121#define NR_CLKS 65
122
123/* include the CLKIDs that have been made part of the DT binding */
124#include <dt-bindings/clock/axg-clkc.h>
125
126#endif /* __AXG_H */
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 1629da9b4141..c2ff0520ce53 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -134,7 +134,7 @@ struct meson_clk_audio_divider {
134struct clk_gate _name = { \ 134struct clk_gate _name = { \
135 .reg = (void __iomem *) _reg, \ 135 .reg = (void __iomem *) _reg, \
136 .bit_idx = (_bit), \ 136 .bit_idx = (_bit), \
137 .lock = &clk_lock, \ 137 .lock = &meson_clk_lock, \
138 .hw.init = &(struct clk_init_data) { \ 138 .hw.init = &(struct clk_init_data) { \
139 .name = #_name, \ 139 .name = #_name, \
140 .ops = &clk_gate_ops, \ 140 .ops = &clk_gate_ops, \
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 74306ac3df23..af24455af5b4 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -27,7 +27,7 @@
27#include "clkc.h" 27#include "clkc.h"
28#include "gxbb.h" 28#include "gxbb.h"
29 29
30static DEFINE_SPINLOCK(clk_lock); 30static DEFINE_SPINLOCK(meson_clk_lock);
31 31
32static const struct pll_rate_table sys_pll_rate_table[] = { 32static const struct pll_rate_table sys_pll_rate_table[] = {
33 PLL_RATE(24000000, 56, 1, 2), 33 PLL_RATE(24000000, 56, 1, 2),
@@ -294,7 +294,7 @@ static struct meson_clk_pll gxbb_fixed_pll = {
294 .shift = 16, 294 .shift = 16,
295 .width = 2, 295 .width = 2,
296 }, 296 },
297 .lock = &clk_lock, 297 .lock = &meson_clk_lock,
298 .hw.init = &(struct clk_init_data){ 298 .hw.init = &(struct clk_init_data){
299 .name = "fixed_pll", 299 .name = "fixed_pll",
300 .ops = &meson_clk_pll_ro_ops, 300 .ops = &meson_clk_pll_ro_ops,
@@ -330,7 +330,7 @@ static struct meson_clk_pll gxbb_hdmi_pll = {
330 .shift = 22, 330 .shift = 22,
331 .width = 2, 331 .width = 2,
332 }, 332 },
333 .lock = &clk_lock, 333 .lock = &meson_clk_lock,
334 .hw.init = &(struct clk_init_data){ 334 .hw.init = &(struct clk_init_data){
335 .name = "hdmi_pll", 335 .name = "hdmi_pll",
336 .ops = &meson_clk_pll_ro_ops, 336 .ops = &meson_clk_pll_ro_ops,
@@ -358,7 +358,7 @@ static struct meson_clk_pll gxbb_sys_pll = {
358 }, 358 },
359 .rate_table = sys_pll_rate_table, 359 .rate_table = sys_pll_rate_table,
360 .rate_count = ARRAY_SIZE(sys_pll_rate_table), 360 .rate_count = ARRAY_SIZE(sys_pll_rate_table),
361 .lock = &clk_lock, 361 .lock = &meson_clk_lock,
362 .hw.init = &(struct clk_init_data){ 362 .hw.init = &(struct clk_init_data){
363 .name = "sys_pll", 363 .name = "sys_pll",
364 .ops = &meson_clk_pll_ro_ops, 364 .ops = &meson_clk_pll_ro_ops,
@@ -399,7 +399,7 @@ static struct meson_clk_pll gxbb_gp0_pll = {
399 }, 399 },
400 .rate_table = gxbb_gp0_pll_rate_table, 400 .rate_table = gxbb_gp0_pll_rate_table,
401 .rate_count = ARRAY_SIZE(gxbb_gp0_pll_rate_table), 401 .rate_count = ARRAY_SIZE(gxbb_gp0_pll_rate_table),
402 .lock = &clk_lock, 402 .lock = &meson_clk_lock,
403 .hw.init = &(struct clk_init_data){ 403 .hw.init = &(struct clk_init_data){
404 .name = "gp0_pll", 404 .name = "gp0_pll",
405 .ops = &meson_clk_pll_ops, 405 .ops = &meson_clk_pll_ops,
@@ -442,7 +442,7 @@ static struct meson_clk_pll gxl_gp0_pll = {
442 }, 442 },
443 .rate_table = gxl_gp0_pll_rate_table, 443 .rate_table = gxl_gp0_pll_rate_table,
444 .rate_count = ARRAY_SIZE(gxl_gp0_pll_rate_table), 444 .rate_count = ARRAY_SIZE(gxl_gp0_pll_rate_table),
445 .lock = &clk_lock, 445 .lock = &meson_clk_lock,
446 .hw.init = &(struct clk_init_data){ 446 .hw.init = &(struct clk_init_data){
447 .name = "gp0_pll", 447 .name = "gp0_pll",
448 .ops = &meson_clk_pll_ops, 448 .ops = &meson_clk_pll_ops,
@@ -533,7 +533,7 @@ static struct meson_clk_mpll gxbb_mpll0 = {
533 .shift = 25, 533 .shift = 25,
534 .width = 1, 534 .width = 1,
535 }, 535 },
536 .lock = &clk_lock, 536 .lock = &meson_clk_lock,
537 .hw.init = &(struct clk_init_data){ 537 .hw.init = &(struct clk_init_data){
538 .name = "mpll0", 538 .name = "mpll0",
539 .ops = &meson_clk_mpll_ops, 539 .ops = &meson_clk_mpll_ops,
@@ -563,7 +563,7 @@ static struct meson_clk_mpll gxbb_mpll1 = {
563 .shift = 14, 563 .shift = 14,
564 .width = 1, 564 .width = 1,
565 }, 565 },
566 .lock = &clk_lock, 566 .lock = &meson_clk_lock,
567 .hw.init = &(struct clk_init_data){ 567 .hw.init = &(struct clk_init_data){
568 .name = "mpll1", 568 .name = "mpll1",
569 .ops = &meson_clk_mpll_ops, 569 .ops = &meson_clk_mpll_ops,
@@ -593,7 +593,7 @@ static struct meson_clk_mpll gxbb_mpll2 = {
593 .shift = 14, 593 .shift = 14,
594 .width = 1, 594 .width = 1,
595 }, 595 },
596 .lock = &clk_lock, 596 .lock = &meson_clk_lock,
597 .hw.init = &(struct clk_init_data){ 597 .hw.init = &(struct clk_init_data){
598 .name = "mpll2", 598 .name = "mpll2",
599 .ops = &meson_clk_mpll_ops, 599 .ops = &meson_clk_mpll_ops,
@@ -620,7 +620,7 @@ static struct clk_mux gxbb_mpeg_clk_sel = {
620 .shift = 12, 620 .shift = 12,
621 .flags = CLK_MUX_READ_ONLY, 621 .flags = CLK_MUX_READ_ONLY,
622 .table = mux_table_clk81, 622 .table = mux_table_clk81,
623 .lock = &clk_lock, 623 .lock = &meson_clk_lock,
624 .hw.init = &(struct clk_init_data){ 624 .hw.init = &(struct clk_init_data){
625 .name = "mpeg_clk_sel", 625 .name = "mpeg_clk_sel",
626 .ops = &clk_mux_ro_ops, 626 .ops = &clk_mux_ro_ops,
@@ -639,7 +639,7 @@ static struct clk_divider gxbb_mpeg_clk_div = {
639 .reg = (void *)HHI_MPEG_CLK_CNTL, 639 .reg = (void *)HHI_MPEG_CLK_CNTL,
640 .shift = 0, 640 .shift = 0,
641 .width = 7, 641 .width = 7,
642 .lock = &clk_lock, 642 .lock = &meson_clk_lock,
643 .hw.init = &(struct clk_init_data){ 643 .hw.init = &(struct clk_init_data){
644 .name = "mpeg_clk_div", 644 .name = "mpeg_clk_div",
645 .ops = &clk_divider_ops, 645 .ops = &clk_divider_ops,
@@ -653,7 +653,7 @@ static struct clk_divider gxbb_mpeg_clk_div = {
653static struct clk_gate gxbb_clk81 = { 653static struct clk_gate gxbb_clk81 = {
654 .reg = (void *)HHI_MPEG_CLK_CNTL, 654 .reg = (void *)HHI_MPEG_CLK_CNTL,
655 .bit_idx = 7, 655 .bit_idx = 7,
656 .lock = &clk_lock, 656 .lock = &meson_clk_lock,
657 .hw.init = &(struct clk_init_data){ 657 .hw.init = &(struct clk_init_data){
658 .name = "clk81", 658 .name = "clk81",
659 .ops = &clk_gate_ops, 659 .ops = &clk_gate_ops,
@@ -667,7 +667,7 @@ static struct clk_mux gxbb_sar_adc_clk_sel = {
667 .reg = (void *)HHI_SAR_CLK_CNTL, 667 .reg = (void *)HHI_SAR_CLK_CNTL,
668 .mask = 0x3, 668 .mask = 0x3,
669 .shift = 9, 669 .shift = 9,
670 .lock = &clk_lock, 670 .lock = &meson_clk_lock,
671 .hw.init = &(struct clk_init_data){ 671 .hw.init = &(struct clk_init_data){
672 .name = "sar_adc_clk_sel", 672 .name = "sar_adc_clk_sel",
673 .ops = &clk_mux_ops, 673 .ops = &clk_mux_ops,
@@ -681,7 +681,7 @@ static struct clk_divider gxbb_sar_adc_clk_div = {
681 .reg = (void *)HHI_SAR_CLK_CNTL, 681 .reg = (void *)HHI_SAR_CLK_CNTL,
682 .shift = 0, 682 .shift = 0,
683 .width = 8, 683 .width = 8,
684 .lock = &clk_lock, 684 .lock = &meson_clk_lock,
685 .hw.init = &(struct clk_init_data){ 685 .hw.init = &(struct clk_init_data){
686 .name = "sar_adc_clk_div", 686 .name = "sar_adc_clk_div",
687 .ops = &clk_divider_ops, 687 .ops = &clk_divider_ops,
@@ -693,7 +693,7 @@ static struct clk_divider gxbb_sar_adc_clk_div = {
693static struct clk_gate gxbb_sar_adc_clk = { 693static struct clk_gate gxbb_sar_adc_clk = {
694 .reg = (void *)HHI_SAR_CLK_CNTL, 694 .reg = (void *)HHI_SAR_CLK_CNTL,
695 .bit_idx = 8, 695 .bit_idx = 8,
696 .lock = &clk_lock, 696 .lock = &meson_clk_lock,
697 .hw.init = &(struct clk_init_data){ 697 .hw.init = &(struct clk_init_data){
698 .name = "sar_adc_clk", 698 .name = "sar_adc_clk",
699 .ops = &clk_gate_ops, 699 .ops = &clk_gate_ops,
@@ -719,7 +719,7 @@ static struct clk_mux gxbb_mali_0_sel = {
719 .mask = 0x7, 719 .mask = 0x7,
720 .shift = 9, 720 .shift = 9,
721 .table = mux_table_mali_0_1, 721 .table = mux_table_mali_0_1,
722 .lock = &clk_lock, 722 .lock = &meson_clk_lock,
723 .hw.init = &(struct clk_init_data){ 723 .hw.init = &(struct clk_init_data){
724 .name = "mali_0_sel", 724 .name = "mali_0_sel",
725 .ops = &clk_mux_ops, 725 .ops = &clk_mux_ops,
@@ -738,7 +738,7 @@ static struct clk_divider gxbb_mali_0_div = {
738 .reg = (void *)HHI_MALI_CLK_CNTL, 738 .reg = (void *)HHI_MALI_CLK_CNTL,
739 .shift = 0, 739 .shift = 0,
740 .width = 7, 740 .width = 7,
741 .lock = &clk_lock, 741 .lock = &meson_clk_lock,
742 .hw.init = &(struct clk_init_data){ 742 .hw.init = &(struct clk_init_data){
743 .name = "mali_0_div", 743 .name = "mali_0_div",
744 .ops = &clk_divider_ops, 744 .ops = &clk_divider_ops,
@@ -751,7 +751,7 @@ static struct clk_divider gxbb_mali_0_div = {
751static struct clk_gate gxbb_mali_0 = { 751static struct clk_gate gxbb_mali_0 = {
752 .reg = (void *)HHI_MALI_CLK_CNTL, 752 .reg = (void *)HHI_MALI_CLK_CNTL,
753 .bit_idx = 8, 753 .bit_idx = 8,
754 .lock = &clk_lock, 754 .lock = &meson_clk_lock,
755 .hw.init = &(struct clk_init_data){ 755 .hw.init = &(struct clk_init_data){
756 .name = "mali_0", 756 .name = "mali_0",
757 .ops = &clk_gate_ops, 757 .ops = &clk_gate_ops,
@@ -766,7 +766,7 @@ static struct clk_mux gxbb_mali_1_sel = {
766 .mask = 0x7, 766 .mask = 0x7,
767 .shift = 25, 767 .shift = 25,
768 .table = mux_table_mali_0_1, 768 .table = mux_table_mali_0_1,
769 .lock = &clk_lock, 769 .lock = &meson_clk_lock,
770 .hw.init = &(struct clk_init_data){ 770 .hw.init = &(struct clk_init_data){
771 .name = "mali_1_sel", 771 .name = "mali_1_sel",
772 .ops = &clk_mux_ops, 772 .ops = &clk_mux_ops,
@@ -785,7 +785,7 @@ static struct clk_divider gxbb_mali_1_div = {
785 .reg = (void *)HHI_MALI_CLK_CNTL, 785 .reg = (void *)HHI_MALI_CLK_CNTL,
786 .shift = 16, 786 .shift = 16,
787 .width = 7, 787 .width = 7,
788 .lock = &clk_lock, 788 .lock = &meson_clk_lock,
789 .hw.init = &(struct clk_init_data){ 789 .hw.init = &(struct clk_init_data){
790 .name = "mali_1_div", 790 .name = "mali_1_div",
791 .ops = &clk_divider_ops, 791 .ops = &clk_divider_ops,
@@ -798,7 +798,7 @@ static struct clk_divider gxbb_mali_1_div = {
798static struct clk_gate gxbb_mali_1 = { 798static struct clk_gate gxbb_mali_1 = {
799 .reg = (void *)HHI_MALI_CLK_CNTL, 799 .reg = (void *)HHI_MALI_CLK_CNTL,
800 .bit_idx = 24, 800 .bit_idx = 24,
801 .lock = &clk_lock, 801 .lock = &meson_clk_lock,
802 .hw.init = &(struct clk_init_data){ 802 .hw.init = &(struct clk_init_data){
803 .name = "mali_1", 803 .name = "mali_1",
804 .ops = &clk_gate_ops, 804 .ops = &clk_gate_ops,
@@ -818,7 +818,7 @@ static struct clk_mux gxbb_mali = {
818 .mask = 1, 818 .mask = 1,
819 .shift = 31, 819 .shift = 31,
820 .table = mux_table_mali, 820 .table = mux_table_mali,
821 .lock = &clk_lock, 821 .lock = &meson_clk_lock,
822 .hw.init = &(struct clk_init_data){ 822 .hw.init = &(struct clk_init_data){
823 .name = "mali", 823 .name = "mali",
824 .ops = &clk_mux_ops, 824 .ops = &clk_mux_ops,
@@ -834,7 +834,7 @@ static struct clk_mux gxbb_cts_amclk_sel = {
834 .shift = 9, 834 .shift = 9,
835 /* Default parent unknown (register reset value: 0) */ 835 /* Default parent unknown (register reset value: 0) */
836 .table = (u32[]){ 1, 2, 3 }, 836 .table = (u32[]){ 1, 2, 3 },
837 .lock = &clk_lock, 837 .lock = &meson_clk_lock,
838 .hw.init = &(struct clk_init_data){ 838 .hw.init = &(struct clk_init_data){
839 .name = "cts_amclk_sel", 839 .name = "cts_amclk_sel",
840 .ops = &clk_mux_ops, 840 .ops = &clk_mux_ops,
@@ -851,7 +851,7 @@ static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
851 .width = 8, 851 .width = 8,
852 }, 852 },
853 .flags = CLK_DIVIDER_ROUND_CLOSEST, 853 .flags = CLK_DIVIDER_ROUND_CLOSEST,
854 .lock = &clk_lock, 854 .lock = &meson_clk_lock,
855 .hw.init = &(struct clk_init_data){ 855 .hw.init = &(struct clk_init_data){
856 .name = "cts_amclk_div", 856 .name = "cts_amclk_div",
857 .ops = &meson_clk_audio_divider_ops, 857 .ops = &meson_clk_audio_divider_ops,
@@ -864,7 +864,7 @@ static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
864static struct clk_gate gxbb_cts_amclk = { 864static struct clk_gate gxbb_cts_amclk = {
865 .reg = (void *) HHI_AUD_CLK_CNTL, 865 .reg = (void *) HHI_AUD_CLK_CNTL,
866 .bit_idx = 8, 866 .bit_idx = 8,
867 .lock = &clk_lock, 867 .lock = &meson_clk_lock,
868 .hw.init = &(struct clk_init_data){ 868 .hw.init = &(struct clk_init_data){
869 .name = "cts_amclk", 869 .name = "cts_amclk",
870 .ops = &clk_gate_ops, 870 .ops = &clk_gate_ops,
@@ -880,7 +880,7 @@ static struct clk_mux gxbb_cts_mclk_i958_sel = {
880 .shift = 25, 880 .shift = 25,
881 /* Default parent unknown (register reset value: 0) */ 881 /* Default parent unknown (register reset value: 0) */
882 .table = (u32[]){ 1, 2, 3 }, 882 .table = (u32[]){ 1, 2, 3 },
883 .lock = &clk_lock, 883 .lock = &meson_clk_lock,
884 .hw.init = &(struct clk_init_data) { 884 .hw.init = &(struct clk_init_data) {
885 .name = "cts_mclk_i958_sel", 885 .name = "cts_mclk_i958_sel",
886 .ops = &clk_mux_ops, 886 .ops = &clk_mux_ops,
@@ -894,7 +894,7 @@ static struct clk_divider gxbb_cts_mclk_i958_div = {
894 .reg = (void *)HHI_AUD_CLK_CNTL2, 894 .reg = (void *)HHI_AUD_CLK_CNTL2,
895 .shift = 16, 895 .shift = 16,
896 .width = 8, 896 .width = 8,
897 .lock = &clk_lock, 897 .lock = &meson_clk_lock,
898 .flags = CLK_DIVIDER_ROUND_CLOSEST, 898 .flags = CLK_DIVIDER_ROUND_CLOSEST,
899 .hw.init = &(struct clk_init_data) { 899 .hw.init = &(struct clk_init_data) {
900 .name = "cts_mclk_i958_div", 900 .name = "cts_mclk_i958_div",
@@ -908,7 +908,7 @@ static struct clk_divider gxbb_cts_mclk_i958_div = {
908static struct clk_gate gxbb_cts_mclk_i958 = { 908static struct clk_gate gxbb_cts_mclk_i958 = {
909 .reg = (void *)HHI_AUD_CLK_CNTL2, 909 .reg = (void *)HHI_AUD_CLK_CNTL2,
910 .bit_idx = 24, 910 .bit_idx = 24,
911 .lock = &clk_lock, 911 .lock = &meson_clk_lock,
912 .hw.init = &(struct clk_init_data){ 912 .hw.init = &(struct clk_init_data){
913 .name = "cts_mclk_i958", 913 .name = "cts_mclk_i958",
914 .ops = &clk_gate_ops, 914 .ops = &clk_gate_ops,
@@ -922,7 +922,7 @@ static struct clk_mux gxbb_cts_i958 = {
922 .reg = (void *)HHI_AUD_CLK_CNTL2, 922 .reg = (void *)HHI_AUD_CLK_CNTL2,
923 .mask = 0x1, 923 .mask = 0x1,
924 .shift = 27, 924 .shift = 27,
925 .lock = &clk_lock, 925 .lock = &meson_clk_lock,
926 .hw.init = &(struct clk_init_data){ 926 .hw.init = &(struct clk_init_data){
927 .name = "cts_i958", 927 .name = "cts_i958",
928 .ops = &clk_mux_ops, 928 .ops = &clk_mux_ops,
@@ -940,7 +940,7 @@ static struct clk_divider gxbb_32k_clk_div = {
940 .reg = (void *)HHI_32K_CLK_CNTL, 940 .reg = (void *)HHI_32K_CLK_CNTL,
941 .shift = 0, 941 .shift = 0,
942 .width = 14, 942 .width = 14,
943 .lock = &clk_lock, 943 .lock = &meson_clk_lock,
944 .hw.init = &(struct clk_init_data){ 944 .hw.init = &(struct clk_init_data){
945 .name = "32k_clk_div", 945 .name = "32k_clk_div",
946 .ops = &clk_divider_ops, 946 .ops = &clk_divider_ops,
@@ -953,7 +953,7 @@ static struct clk_divider gxbb_32k_clk_div = {
953static struct clk_gate gxbb_32k_clk = { 953static struct clk_gate gxbb_32k_clk = {
954 .reg = (void *)HHI_32K_CLK_CNTL, 954 .reg = (void *)HHI_32K_CLK_CNTL,
955 .bit_idx = 15, 955 .bit_idx = 15,
956 .lock = &clk_lock, 956 .lock = &meson_clk_lock,
957 .hw.init = &(struct clk_init_data){ 957 .hw.init = &(struct clk_init_data){
958 .name = "32k_clk", 958 .name = "32k_clk",
959 .ops = &clk_gate_ops, 959 .ops = &clk_gate_ops,
@@ -971,7 +971,7 @@ static struct clk_mux gxbb_32k_clk_sel = {
971 .reg = (void *)HHI_32K_CLK_CNTL, 971 .reg = (void *)HHI_32K_CLK_CNTL,
972 .mask = 0x3, 972 .mask = 0x3,
973 .shift = 16, 973 .shift = 16,
974 .lock = &clk_lock, 974 .lock = &meson_clk_lock,
975 .hw.init = &(struct clk_init_data){ 975 .hw.init = &(struct clk_init_data){
976 .name = "32k_clk_sel", 976 .name = "32k_clk_sel",
977 .ops = &clk_mux_ops, 977 .ops = &clk_mux_ops,
@@ -997,7 +997,7 @@ static struct clk_mux gxbb_sd_emmc_a_clk0_sel = {
997 .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 997 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
998 .mask = 0x7, 998 .mask = 0x7,
999 .shift = 9, 999 .shift = 9,
1000 .lock = &clk_lock, 1000 .lock = &meson_clk_lock,
1001 .hw.init = &(struct clk_init_data) { 1001 .hw.init = &(struct clk_init_data) {
1002 .name = "sd_emmc_a_clk0_sel", 1002 .name = "sd_emmc_a_clk0_sel",
1003 .ops = &clk_mux_ops, 1003 .ops = &clk_mux_ops,
@@ -1011,7 +1011,7 @@ static struct clk_divider gxbb_sd_emmc_a_clk0_div = {
1011 .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1011 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1012 .shift = 0, 1012 .shift = 0,
1013 .width = 7, 1013 .width = 7,
1014 .lock = &clk_lock, 1014 .lock = &meson_clk_lock,
1015 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1015 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1016 .hw.init = &(struct clk_init_data) { 1016 .hw.init = &(struct clk_init_data) {
1017 .name = "sd_emmc_a_clk0_div", 1017 .name = "sd_emmc_a_clk0_div",
@@ -1025,7 +1025,7 @@ static struct clk_divider gxbb_sd_emmc_a_clk0_div = {
1025static struct clk_gate gxbb_sd_emmc_a_clk0 = { 1025static struct clk_gate gxbb_sd_emmc_a_clk0 = {
1026 .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1026 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1027 .bit_idx = 7, 1027 .bit_idx = 7,
1028 .lock = &clk_lock, 1028 .lock = &meson_clk_lock,
1029 .hw.init = &(struct clk_init_data){ 1029 .hw.init = &(struct clk_init_data){
1030 .name = "sd_emmc_a_clk0", 1030 .name = "sd_emmc_a_clk0",
1031 .ops = &clk_gate_ops, 1031 .ops = &clk_gate_ops,
@@ -1040,7 +1040,7 @@ static struct clk_mux gxbb_sd_emmc_b_clk0_sel = {
1040 .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1040 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1041 .mask = 0x7, 1041 .mask = 0x7,
1042 .shift = 25, 1042 .shift = 25,
1043 .lock = &clk_lock, 1043 .lock = &meson_clk_lock,
1044 .hw.init = &(struct clk_init_data) { 1044 .hw.init = &(struct clk_init_data) {
1045 .name = "sd_emmc_b_clk0_sel", 1045 .name = "sd_emmc_b_clk0_sel",
1046 .ops = &clk_mux_ops, 1046 .ops = &clk_mux_ops,
@@ -1054,7 +1054,7 @@ static struct clk_divider gxbb_sd_emmc_b_clk0_div = {
1054 .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1054 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1055 .shift = 16, 1055 .shift = 16,
1056 .width = 7, 1056 .width = 7,
1057 .lock = &clk_lock, 1057 .lock = &meson_clk_lock,
1058 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1058 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1059 .hw.init = &(struct clk_init_data) { 1059 .hw.init = &(struct clk_init_data) {
1060 .name = "sd_emmc_b_clk0_div", 1060 .name = "sd_emmc_b_clk0_div",
@@ -1068,7 +1068,7 @@ static struct clk_divider gxbb_sd_emmc_b_clk0_div = {
1068static struct clk_gate gxbb_sd_emmc_b_clk0 = { 1068static struct clk_gate gxbb_sd_emmc_b_clk0 = {
1069 .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1069 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1070 .bit_idx = 23, 1070 .bit_idx = 23,
1071 .lock = &clk_lock, 1071 .lock = &meson_clk_lock,
1072 .hw.init = &(struct clk_init_data){ 1072 .hw.init = &(struct clk_init_data){
1073 .name = "sd_emmc_b_clk0", 1073 .name = "sd_emmc_b_clk0",
1074 .ops = &clk_gate_ops, 1074 .ops = &clk_gate_ops,
@@ -1083,7 +1083,7 @@ static struct clk_mux gxbb_sd_emmc_c_clk0_sel = {
1083 .reg = (void *)HHI_NAND_CLK_CNTL, 1083 .reg = (void *)HHI_NAND_CLK_CNTL,
1084 .mask = 0x7, 1084 .mask = 0x7,
1085 .shift = 9, 1085 .shift = 9,
1086 .lock = &clk_lock, 1086 .lock = &meson_clk_lock,
1087 .hw.init = &(struct clk_init_data) { 1087 .hw.init = &(struct clk_init_data) {
1088 .name = "sd_emmc_c_clk0_sel", 1088 .name = "sd_emmc_c_clk0_sel",
1089 .ops = &clk_mux_ops, 1089 .ops = &clk_mux_ops,
@@ -1097,7 +1097,7 @@ static struct clk_divider gxbb_sd_emmc_c_clk0_div = {
1097 .reg = (void *)HHI_NAND_CLK_CNTL, 1097 .reg = (void *)HHI_NAND_CLK_CNTL,
1098 .shift = 0, 1098 .shift = 0,
1099 .width = 7, 1099 .width = 7,
1100 .lock = &clk_lock, 1100 .lock = &meson_clk_lock,
1101 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1101 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1102 .hw.init = &(struct clk_init_data) { 1102 .hw.init = &(struct clk_init_data) {
1103 .name = "sd_emmc_c_clk0_div", 1103 .name = "sd_emmc_c_clk0_div",
@@ -1111,7 +1111,7 @@ static struct clk_divider gxbb_sd_emmc_c_clk0_div = {
1111static struct clk_gate gxbb_sd_emmc_c_clk0 = { 1111static struct clk_gate gxbb_sd_emmc_c_clk0 = {
1112 .reg = (void *)HHI_NAND_CLK_CNTL, 1112 .reg = (void *)HHI_NAND_CLK_CNTL,
1113 .bit_idx = 7, 1113 .bit_idx = 7,
1114 .lock = &clk_lock, 1114 .lock = &meson_clk_lock,
1115 .hw.init = &(struct clk_init_data){ 1115 .hw.init = &(struct clk_init_data){
1116 .name = "sd_emmc_c_clk0", 1116 .name = "sd_emmc_c_clk0",
1117 .ops = &clk_gate_ops, 1117 .ops = &clk_gate_ops,
@@ -1132,7 +1132,7 @@ static struct clk_mux gxbb_vpu_0_sel = {
1132 .reg = (void *)HHI_VPU_CLK_CNTL, 1132 .reg = (void *)HHI_VPU_CLK_CNTL,
1133 .mask = 0x3, 1133 .mask = 0x3,
1134 .shift = 9, 1134 .shift = 9,
1135 .lock = &clk_lock, 1135 .lock = &meson_clk_lock,
1136 .table = mux_table_vpu, 1136 .table = mux_table_vpu,
1137 .hw.init = &(struct clk_init_data){ 1137 .hw.init = &(struct clk_init_data){
1138 .name = "vpu_0_sel", 1138 .name = "vpu_0_sel",
@@ -1151,7 +1151,7 @@ static struct clk_divider gxbb_vpu_0_div = {
1151 .reg = (void *)HHI_VPU_CLK_CNTL, 1151 .reg = (void *)HHI_VPU_CLK_CNTL,
1152 .shift = 0, 1152 .shift = 0,
1153 .width = 7, 1153 .width = 7,
1154 .lock = &clk_lock, 1154 .lock = &meson_clk_lock,
1155 .hw.init = &(struct clk_init_data){ 1155 .hw.init = &(struct clk_init_data){
1156 .name = "vpu_0_div", 1156 .name = "vpu_0_div",
1157 .ops = &clk_divider_ops, 1157 .ops = &clk_divider_ops,
@@ -1164,7 +1164,7 @@ static struct clk_divider gxbb_vpu_0_div = {
1164static struct clk_gate gxbb_vpu_0 = { 1164static struct clk_gate gxbb_vpu_0 = {
1165 .reg = (void *)HHI_VPU_CLK_CNTL, 1165 .reg = (void *)HHI_VPU_CLK_CNTL,
1166 .bit_idx = 8, 1166 .bit_idx = 8,
1167 .lock = &clk_lock, 1167 .lock = &meson_clk_lock,
1168 .hw.init = &(struct clk_init_data) { 1168 .hw.init = &(struct clk_init_data) {
1169 .name = "vpu_0", 1169 .name = "vpu_0",
1170 .ops = &clk_gate_ops, 1170 .ops = &clk_gate_ops,
@@ -1178,7 +1178,7 @@ static struct clk_mux gxbb_vpu_1_sel = {
1178 .reg = (void *)HHI_VPU_CLK_CNTL, 1178 .reg = (void *)HHI_VPU_CLK_CNTL,
1179 .mask = 0x3, 1179 .mask = 0x3,
1180 .shift = 25, 1180 .shift = 25,
1181 .lock = &clk_lock, 1181 .lock = &meson_clk_lock,
1182 .table = mux_table_vpu, 1182 .table = mux_table_vpu,
1183 .hw.init = &(struct clk_init_data){ 1183 .hw.init = &(struct clk_init_data){
1184 .name = "vpu_1_sel", 1184 .name = "vpu_1_sel",
@@ -1197,7 +1197,7 @@ static struct clk_divider gxbb_vpu_1_div = {
1197 .reg = (void *)HHI_VPU_CLK_CNTL, 1197 .reg = (void *)HHI_VPU_CLK_CNTL,
1198 .shift = 16, 1198 .shift = 16,
1199 .width = 7, 1199 .width = 7,
1200 .lock = &clk_lock, 1200 .lock = &meson_clk_lock,
1201 .hw.init = &(struct clk_init_data){ 1201 .hw.init = &(struct clk_init_data){
1202 .name = "vpu_1_div", 1202 .name = "vpu_1_div",
1203 .ops = &clk_divider_ops, 1203 .ops = &clk_divider_ops,
@@ -1210,7 +1210,7 @@ static struct clk_divider gxbb_vpu_1_div = {
1210static struct clk_gate gxbb_vpu_1 = { 1210static struct clk_gate gxbb_vpu_1 = {
1211 .reg = (void *)HHI_VPU_CLK_CNTL, 1211 .reg = (void *)HHI_VPU_CLK_CNTL,
1212 .bit_idx = 24, 1212 .bit_idx = 24,
1213 .lock = &clk_lock, 1213 .lock = &meson_clk_lock,
1214 .hw.init = &(struct clk_init_data) { 1214 .hw.init = &(struct clk_init_data) {
1215 .name = "vpu_1", 1215 .name = "vpu_1",
1216 .ops = &clk_gate_ops, 1216 .ops = &clk_gate_ops,
@@ -1224,7 +1224,7 @@ static struct clk_mux gxbb_vpu = {
1224 .reg = (void *)HHI_VPU_CLK_CNTL, 1224 .reg = (void *)HHI_VPU_CLK_CNTL,
1225 .mask = 1, 1225 .mask = 1,
1226 .shift = 31, 1226 .shift = 31,
1227 .lock = &clk_lock, 1227 .lock = &meson_clk_lock,
1228 .hw.init = &(struct clk_init_data){ 1228 .hw.init = &(struct clk_init_data){
1229 .name = "vpu", 1229 .name = "vpu",
1230 .ops = &clk_mux_ops, 1230 .ops = &clk_mux_ops,
@@ -1249,7 +1249,7 @@ static struct clk_mux gxbb_vapb_0_sel = {
1249 .reg = (void *)HHI_VAPBCLK_CNTL, 1249 .reg = (void *)HHI_VAPBCLK_CNTL,
1250 .mask = 0x3, 1250 .mask = 0x3,
1251 .shift = 9, 1251 .shift = 9,
1252 .lock = &clk_lock, 1252 .lock = &meson_clk_lock,
1253 .table = mux_table_vapb, 1253 .table = mux_table_vapb,
1254 .hw.init = &(struct clk_init_data){ 1254 .hw.init = &(struct clk_init_data){
1255 .name = "vapb_0_sel", 1255 .name = "vapb_0_sel",
@@ -1268,7 +1268,7 @@ static struct clk_divider gxbb_vapb_0_div = {
1268 .reg = (void *)HHI_VAPBCLK_CNTL, 1268 .reg = (void *)HHI_VAPBCLK_CNTL,
1269 .shift = 0, 1269 .shift = 0,
1270 .width = 7, 1270 .width = 7,
1271 .lock = &clk_lock, 1271 .lock = &meson_clk_lock,
1272 .hw.init = &(struct clk_init_data){ 1272 .hw.init = &(struct clk_init_data){
1273 .name = "vapb_0_div", 1273 .name = "vapb_0_div",
1274 .ops = &clk_divider_ops, 1274 .ops = &clk_divider_ops,
@@ -1281,7 +1281,7 @@ static struct clk_divider gxbb_vapb_0_div = {
1281static struct clk_gate gxbb_vapb_0 = { 1281static struct clk_gate gxbb_vapb_0 = {
1282 .reg = (void *)HHI_VAPBCLK_CNTL, 1282 .reg = (void *)HHI_VAPBCLK_CNTL,
1283 .bit_idx = 8, 1283 .bit_idx = 8,
1284 .lock = &clk_lock, 1284 .lock = &meson_clk_lock,
1285 .hw.init = &(struct clk_init_data) { 1285 .hw.init = &(struct clk_init_data) {
1286 .name = "vapb_0", 1286 .name = "vapb_0",
1287 .ops = &clk_gate_ops, 1287 .ops = &clk_gate_ops,
@@ -1295,7 +1295,7 @@ static struct clk_mux gxbb_vapb_1_sel = {
1295 .reg = (void *)HHI_VAPBCLK_CNTL, 1295 .reg = (void *)HHI_VAPBCLK_CNTL,
1296 .mask = 0x3, 1296 .mask = 0x3,
1297 .shift = 25, 1297 .shift = 25,
1298 .lock = &clk_lock, 1298 .lock = &meson_clk_lock,
1299 .table = mux_table_vapb, 1299 .table = mux_table_vapb,
1300 .hw.init = &(struct clk_init_data){ 1300 .hw.init = &(struct clk_init_data){
1301 .name = "vapb_1_sel", 1301 .name = "vapb_1_sel",
@@ -1314,7 +1314,7 @@ static struct clk_divider gxbb_vapb_1_div = {
1314 .reg = (void *)HHI_VAPBCLK_CNTL, 1314 .reg = (void *)HHI_VAPBCLK_CNTL,
1315 .shift = 16, 1315 .shift = 16,
1316 .width = 7, 1316 .width = 7,
1317 .lock = &clk_lock, 1317 .lock = &meson_clk_lock,
1318 .hw.init = &(struct clk_init_data){ 1318 .hw.init = &(struct clk_init_data){
1319 .name = "vapb_1_div", 1319 .name = "vapb_1_div",
1320 .ops = &clk_divider_ops, 1320 .ops = &clk_divider_ops,
@@ -1327,7 +1327,7 @@ static struct clk_divider gxbb_vapb_1_div = {
1327static struct clk_gate gxbb_vapb_1 = { 1327static struct clk_gate gxbb_vapb_1 = {
1328 .reg = (void *)HHI_VAPBCLK_CNTL, 1328 .reg = (void *)HHI_VAPBCLK_CNTL,
1329 .bit_idx = 24, 1329 .bit_idx = 24,
1330 .lock = &clk_lock, 1330 .lock = &meson_clk_lock,
1331 .hw.init = &(struct clk_init_data) { 1331 .hw.init = &(struct clk_init_data) {
1332 .name = "vapb_1", 1332 .name = "vapb_1",
1333 .ops = &clk_gate_ops, 1333 .ops = &clk_gate_ops,
@@ -1341,7 +1341,7 @@ static struct clk_mux gxbb_vapb_sel = {
1341 .reg = (void *)HHI_VAPBCLK_CNTL, 1341 .reg = (void *)HHI_VAPBCLK_CNTL,
1342 .mask = 1, 1342 .mask = 1,
1343 .shift = 31, 1343 .shift = 31,
1344 .lock = &clk_lock, 1344 .lock = &meson_clk_lock,
1345 .hw.init = &(struct clk_init_data){ 1345 .hw.init = &(struct clk_init_data){
1346 .name = "vapb_sel", 1346 .name = "vapb_sel",
1347 .ops = &clk_mux_ops, 1347 .ops = &clk_mux_ops,
@@ -1358,7 +1358,7 @@ static struct clk_mux gxbb_vapb_sel = {
1358static struct clk_gate gxbb_vapb = { 1358static struct clk_gate gxbb_vapb = {
1359 .reg = (void *)HHI_VAPBCLK_CNTL, 1359 .reg = (void *)HHI_VAPBCLK_CNTL,
1360 .bit_idx = 30, 1360 .bit_idx = 30,
1361 .lock = &clk_lock, 1361 .lock = &meson_clk_lock,
1362 .hw.init = &(struct clk_init_data) { 1362 .hw.init = &(struct clk_init_data) {
1363 .name = "vapb", 1363 .name = "vapb",
1364 .ops = &clk_gate_ops, 1364 .ops = &clk_gate_ops,
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 20ab7190d328..3ffea80c1308 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -32,7 +32,7 @@
32#include "clkc.h" 32#include "clkc.h"
33#include "meson8b.h" 33#include "meson8b.h"
34 34
35static DEFINE_SPINLOCK(clk_lock); 35static DEFINE_SPINLOCK(meson_clk_lock);
36 36
37static void __iomem *clk_base; 37static void __iomem *clk_base;
38 38
@@ -136,7 +136,7 @@ static struct meson_clk_pll meson8b_fixed_pll = {
136 .shift = 16, 136 .shift = 16,
137 .width = 2, 137 .width = 2,
138 }, 138 },
139 .lock = &clk_lock, 139 .lock = &meson_clk_lock,
140 .hw.init = &(struct clk_init_data){ 140 .hw.init = &(struct clk_init_data){
141 .name = "fixed_pll", 141 .name = "fixed_pll",
142 .ops = &meson_clk_pll_ro_ops, 142 .ops = &meson_clk_pll_ro_ops,
@@ -162,7 +162,7 @@ static struct meson_clk_pll meson8b_vid_pll = {
162 .shift = 16, 162 .shift = 16,
163 .width = 2, 163 .width = 2,
164 }, 164 },
165 .lock = &clk_lock, 165 .lock = &meson_clk_lock,
166 .hw.init = &(struct clk_init_data){ 166 .hw.init = &(struct clk_init_data){
167 .name = "vid_pll", 167 .name = "vid_pll",
168 .ops = &meson_clk_pll_ro_ops, 168 .ops = &meson_clk_pll_ro_ops,
@@ -190,7 +190,7 @@ static struct meson_clk_pll meson8b_sys_pll = {
190 }, 190 },
191 .rate_table = sys_pll_rate_table, 191 .rate_table = sys_pll_rate_table,
192 .rate_count = ARRAY_SIZE(sys_pll_rate_table), 192 .rate_count = ARRAY_SIZE(sys_pll_rate_table),
193 .lock = &clk_lock, 193 .lock = &meson_clk_lock,
194 .hw.init = &(struct clk_init_data){ 194 .hw.init = &(struct clk_init_data){
195 .name = "sys_pll", 195 .name = "sys_pll",
196 .ops = &meson_clk_pll_ops, 196 .ops = &meson_clk_pll_ops,
@@ -281,7 +281,7 @@ static struct meson_clk_mpll meson8b_mpll0 = {
281 .shift = 25, 281 .shift = 25,
282 .width = 1, 282 .width = 1,
283 }, 283 },
284 .lock = &clk_lock, 284 .lock = &meson_clk_lock,
285 .hw.init = &(struct clk_init_data){ 285 .hw.init = &(struct clk_init_data){
286 .name = "mpll0", 286 .name = "mpll0",
287 .ops = &meson_clk_mpll_ops, 287 .ops = &meson_clk_mpll_ops,
@@ -311,7 +311,7 @@ static struct meson_clk_mpll meson8b_mpll1 = {
311 .shift = 14, 311 .shift = 14,
312 .width = 1, 312 .width = 1,
313 }, 313 },
314 .lock = &clk_lock, 314 .lock = &meson_clk_lock,
315 .hw.init = &(struct clk_init_data){ 315 .hw.init = &(struct clk_init_data){
316 .name = "mpll1", 316 .name = "mpll1",
317 .ops = &meson_clk_mpll_ops, 317 .ops = &meson_clk_mpll_ops,
@@ -341,7 +341,7 @@ static struct meson_clk_mpll meson8b_mpll2 = {
341 .shift = 14, 341 .shift = 14,
342 .width = 1, 342 .width = 1,
343 }, 343 },
344 .lock = &clk_lock, 344 .lock = &meson_clk_lock,
345 .hw.init = &(struct clk_init_data){ 345 .hw.init = &(struct clk_init_data){
346 .name = "mpll2", 346 .name = "mpll2",
347 .ops = &meson_clk_mpll_ops, 347 .ops = &meson_clk_mpll_ops,
@@ -375,7 +375,7 @@ struct clk_mux meson8b_mpeg_clk_sel = {
375 .shift = 12, 375 .shift = 12,
376 .flags = CLK_MUX_READ_ONLY, 376 .flags = CLK_MUX_READ_ONLY,
377 .table = mux_table_clk81, 377 .table = mux_table_clk81,
378 .lock = &clk_lock, 378 .lock = &meson_clk_lock,
379 .hw.init = &(struct clk_init_data){ 379 .hw.init = &(struct clk_init_data){
380 .name = "mpeg_clk_sel", 380 .name = "mpeg_clk_sel",
381 .ops = &clk_mux_ro_ops, 381 .ops = &clk_mux_ro_ops,
@@ -395,7 +395,7 @@ struct clk_divider meson8b_mpeg_clk_div = {
395 .reg = (void *)HHI_MPEG_CLK_CNTL, 395 .reg = (void *)HHI_MPEG_CLK_CNTL,
396 .shift = 0, 396 .shift = 0,
397 .width = 7, 397 .width = 7,
398 .lock = &clk_lock, 398 .lock = &meson_clk_lock,
399 .hw.init = &(struct clk_init_data){ 399 .hw.init = &(struct clk_init_data){
400 .name = "mpeg_clk_div", 400 .name = "mpeg_clk_div",
401 .ops = &clk_divider_ops, 401 .ops = &clk_divider_ops,
@@ -408,7 +408,7 @@ struct clk_divider meson8b_mpeg_clk_div = {
408struct clk_gate meson8b_clk81 = { 408struct clk_gate meson8b_clk81 = {
409 .reg = (void *)HHI_MPEG_CLK_CNTL, 409 .reg = (void *)HHI_MPEG_CLK_CNTL,
410 .bit_idx = 7, 410 .bit_idx = 7,
411 .lock = &clk_lock, 411 .lock = &meson_clk_lock,
412 .hw.init = &(struct clk_init_data){ 412 .hw.init = &(struct clk_init_data){
413 .name = "clk81", 413 .name = "clk81",
414 .ops = &clk_gate_ops, 414 .ops = &clk_gate_ops,
@@ -773,7 +773,7 @@ static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
773 773
774 reset = &meson8b_clk_reset_bits[id]; 774 reset = &meson8b_clk_reset_bits[id];
775 775
776 spin_lock_irqsave(&clk_lock, flags); 776 spin_lock_irqsave(&meson_clk_lock, flags);
777 777
778 val = readl(meson8b_clk_reset->base + reset->reg); 778 val = readl(meson8b_clk_reset->base + reset->reg);
779 if (assert) 779 if (assert)
@@ -782,7 +782,7 @@ static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
782 val &= ~BIT(reset->bit_idx); 782 val &= ~BIT(reset->bit_idx);
783 writel(val, meson8b_clk_reset->base + reset->reg); 783 writel(val, meson8b_clk_reset->base + reset->reg);
784 784
785 spin_unlock_irqrestore(&clk_lock, flags); 785 spin_unlock_irqrestore(&meson_clk_lock, flags);
786 786
787 return 0; 787 return 0;
788} 788}
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
new file mode 100644
index 000000000000..941ac70e7f30
--- /dev/null
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -0,0 +1,71 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Meson-AXG clock tree IDs
4 *
5 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
6 */
7
8#ifndef __AXG_CLKC_H
9#define __AXG_CLKC_H
10
11#define CLKID_SYS_PLL 0
12#define CLKID_FIXED_PLL 1
13#define CLKID_FCLK_DIV2 2
14#define CLKID_FCLK_DIV3 3
15#define CLKID_FCLK_DIV4 4
16#define CLKID_FCLK_DIV5 5
17#define CLKID_FCLK_DIV7 6
18#define CLKID_GP0_PLL 7
19#define CLKID_CLK81 10
20#define CLKID_MPLL0 11
21#define CLKID_MPLL1 12
22#define CLKID_MPLL2 13
23#define CLKID_MPLL3 14
24#define CLKID_DDR 15
25#define CLKID_AUDIO_LOCKER 16
26#define CLKID_MIPI_DSI_HOST 17
27#define CLKID_ISA 18
28#define CLKID_PL301 19
29#define CLKID_PERIPHS 20
30#define CLKID_SPICC0 21
31#define CLKID_I2C 22
32#define CLKID_RNG0 23
33#define CLKID_UART0 24
34#define CLKID_MIPI_DSI_PHY 25
35#define CLKID_SPICC1 26
36#define CLKID_PCIE_A 27
37#define CLKID_PCIE_B 28
38#define CLKID_HIU_IFACE 29
39#define CLKID_ASSIST_MISC 30
40#define CLKID_SD_EMMC_B 31
41#define CLKID_SD_EMMC_C 32
42#define CLKID_DMA 33
43#define CLKID_SPI 34
44#define CLKID_AUDIO 35
45#define CLKID_ETH 36
46#define CLKID_UART1 37
47#define CLKID_G2D 38
48#define CLKID_USB0 39
49#define CLKID_USB1 40
50#define CLKID_RESET 41
51#define CLKID_USB 42
52#define CLKID_AHB_ARB0 43
53#define CLKID_EFUSE 44
54#define CLKID_BOOT_ROM 45
55#define CLKID_AHB_DATA_BUS 46
56#define CLKID_AHB_CTRL_BUS 47
57#define CLKID_USB1_DDR_BRIDGE 48
58#define CLKID_USB0_DDR_BRIDGE 49
59#define CLKID_MMC_PCLK 50
60#define CLKID_VPU_INTR 51
61#define CLKID_SEC_AHB_AHB3_BRIDGE 52
62#define CLKID_GIC 53
63#define CLKID_AO_MEDIA_CPU 54
64#define CLKID_AO_AHB_SRAM 55
65#define CLKID_AO_AHB_BUS 56
66#define CLKID_AO_IFACE 57
67#define CLKID_AO_I2C 58
68#define CLKID_SD_EMMC_B_CLK0 59
69#define CLKID_SD_EMMC_C_CLK0 60
70
71#endif /* __AXG_CLKC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-21 00:54:27 -0400