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authorLinus Torvalds <torvalds@linux-foundation.org>2017-09-05 14:49:48 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2017-09-05 14:49:48 -0400
commit70b8e9eb3b50d8bded63f808b09c4844ef63c3b8 (patch)
tree42b5b22becc9e9542923be3bc78525e0d9f5c67c
parentd16605c9128a498f9b8575b5c43be95c45dbcfab (diff)
parent02b6bddb0b0a4e27fad6623d82579f2a1e35d3d3 (diff)
Merge tag 'gpio-v4.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij: "This is the bulk of the GPIO changes for the v4.14 cycle. Not so much changes this time, phew. David Daney and Bartosz Golaszewski did all the really interesting work in infrastructure improvement across GPIO and IRQ core, hats off for them and to tglx and Marc Z for general help with these patch sets. Core changes: - Allow the GPIO irqchip to allocate IRQs dynamically. This is an important change on systems where only a restricted number of IRQs, lesser than the number of GPIO lines, can be utilized. Now we can allocate these on a first-come-first-served basis instead of hogging up valuable IRQ lines. - Serious fix-up of the kerneldoc documentation and inclusion into the kerneldoc builds. - Pulled in the IRQ simulator from the IRQ core tree and use this in the GPIO mockup driver for exhaustive testing of interrupt abilities. New drivers: - New driver for ThunderX and OCTEON-TX. This is especially interesting as it picks up improvements from the IRQ core that allow us to handle fasteoi ACKs upwards in a hierarchy when there are IRQ flag latches on several levels in a hierarchy. Very interesting work here. - New subdriver for Renesas R-Car r8a7745 (RZ/G1E). Misc: - Several fixes and improvements for Xilinx Zynq GPIO. - Support an enablement GPIO for the 74x164 GPIO. - Switch a bunch of chips to use devres to allocate irq descriptors. - A bunch of constification fixes" * tag 'gpio-v4.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (63 commits) gpio: mockup: remove unused variable gc gpio: pl061: constify amba_id Revert "gpiolib: request the gpio before querying its direction" gpio: twl6040: remove unneeded forward declaration gpio: zevio: make gpio_chip const gpio: add gpio_add_lookup_tables() to add several tables at once gpio: rcar: Add r8a7745 (RZ/G1E) support gpio: brcmstb: check return value of gpiochip_irqchip_add() MAINTAINERS: Add entry for THUNDERX GPIO Driver. gpio: Add gpio driver support for ThunderX and OCTEON-TX gpio: mockup: use irq_sim gpio: mxs: use devres for irq generic chip gpio: mxc: use devres for irq generic chip gpio: pch: use devres for irq generic chip gpio: ml-ioh: use devres for irq generic chip gpio: sta2x11: use devres for irq generic chip gpio: sta2x11: disallow unbinding the driver gpio: mxs: disallow unbinding the driver gpio: mxc: disallow unbinding the driver gpio: aspeed: Remove reference to clock name in debounce warning message ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-74x164.txt3
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-aspeed.txt2
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-davinci.txt91
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-vf610.txt4
-rw-r--r--Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt16
-rw-r--r--Documentation/driver-api/gpio.rst45
-rw-r--r--Documentation/driver-api/index.rst1
-rw-r--r--MAINTAINERS5
-rw-r--r--drivers/gpio/Kconfig26
-rw-r--r--drivers/gpio/Makefile2
-rw-r--r--drivers/gpio/devres.c3
-rw-r--r--drivers/gpio/gpio-74x164.c10
-rw-r--r--drivers/gpio/gpio-altera-a10sr.c2
-rw-r--r--drivers/gpio/gpio-altera.c4
-rw-r--r--drivers/gpio/gpio-aspeed.c2
-rw-r--r--drivers/gpio/gpio-brcmstb.c11
-rw-r--r--drivers/gpio/gpio-davinci.c22
-rw-r--r--drivers/gpio/gpio-ge.c6
-rw-r--r--drivers/gpio/gpio-grgpio.c2
-rw-r--r--drivers/gpio/gpio-it87.c3
-rw-r--r--drivers/gpio/gpio-max77620.c2
-rw-r--r--drivers/gpio/gpio-mb86s7x.c4
-rw-r--r--drivers/gpio/gpio-ml-ioh.c12
-rw-r--r--drivers/gpio/gpio-mockup.c79
-rw-r--r--drivers/gpio/gpio-mpc8xxx.c4
-rw-r--r--drivers/gpio/gpio-msic.c4
-rw-r--r--drivers/gpio/gpio-mxc.c27
-rw-r--r--drivers/gpio/gpio-mxs.c15
-rw-r--r--drivers/gpio/gpio-omap.c2
-rw-r--r--drivers/gpio/gpio-pca953x.c8
-rw-r--r--drivers/gpio/gpio-pch.c12
-rw-r--r--drivers/gpio/gpio-pl061.c2
-rw-r--r--drivers/gpio/gpio-pxa.c8
-rw-r--r--drivers/gpio/gpio-rcar.c10
-rw-r--r--drivers/gpio/gpio-sta2x11.c14
-rw-r--r--drivers/gpio/gpio-tb10x.c3
-rw-r--r--drivers/gpio/gpio-tegra.c129
-rw-r--r--drivers/gpio/gpio-thunderx.c639
-rw-r--r--drivers/gpio/gpio-tps68470.c176
-rw-r--r--drivers/gpio/gpio-twl6040.c2
-rw-r--r--drivers/gpio/gpio-tz1090.c10
-rw-r--r--drivers/gpio/gpio-vf610.c47
-rw-r--r--drivers/gpio/gpio-xilinx.c4
-rw-r--r--drivers/gpio/gpio-zevio.c2
-rw-r--r--drivers/gpio/gpio-zynq.c160
-rw-r--r--drivers/gpio/gpiolib-acpi.c4
-rw-r--r--drivers/gpio/gpiolib-of.c36
-rw-r--r--drivers/gpio/gpiolib-sysfs.c8
-rw-r--r--drivers/gpio/gpiolib.c130
-rw-r--r--drivers/gpio/gpiolib.h2
-rw-r--r--include/linux/gpio/driver.h24
-rw-r--r--include/linux/gpio/machine.h3
52 files changed, 1516 insertions, 326 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio-74x164.txt b/Documentation/devicetree/bindings/gpio/gpio-74x164.txt
index ce1b2231bf5d..2a97553d8d76 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-74x164.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-74x164.txt
@@ -12,6 +12,9 @@ Required properties:
12 1 = active low 12 1 = active low
13- registers-number: Number of daisy-chained shift registers 13- registers-number: Number of daisy-chained shift registers
14 14
15Optional properties:
16- enable-gpios: GPIO connected to the OE (Output Enable) pin.
17
15Example: 18Example:
16 19
17gpio5: gpio5@0 { 20gpio5: gpio5@0 {
diff --git a/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
index c756afa88cc6..fc6378c778c5 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-aspeed.txt
@@ -18,7 +18,7 @@ Required properties:
18Optional properties: 18Optional properties:
19 19
20- interrupt-parent : The parent interrupt controller, optional if inherited 20- interrupt-parent : The parent interrupt controller, optional if inherited
21- clocks : A phandle to the HPLL clock node for debounce timings 21- clocks : A phandle to the clock to use for debounce timings
22 22
23The gpio and interrupt properties are further described in their respective 23The gpio and interrupt properties are further described in their respective
24bindings documentation: 24bindings documentation:
diff --git a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
index 5079ba7d6568..8beb0539b6d8 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
@@ -1,7 +1,10 @@
1Davinci/Keystone GPIO controller bindings 1Davinci/Keystone GPIO controller bindings
2 2
3Required Properties: 3Required Properties:
4- compatible: should be "ti,dm6441-gpio", "ti,keystone-gpio" 4- compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs
5 "ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L,
6 66AK2E SoCs
7 "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G
5 8
6- reg: Physical base address of the controller and the size of memory mapped 9- reg: Physical base address of the controller and the size of memory mapped
7 registers. 10 registers.
@@ -20,7 +23,21 @@ Required Properties:
20- ti,ngpio: The number of GPIO pins supported. 23- ti,ngpio: The number of GPIO pins supported.
21 24
22- ti,davinci-gpio-unbanked: The number of GPIOs that have an individual interrupt 25- ti,davinci-gpio-unbanked: The number of GPIOs that have an individual interrupt
23 line to processor. 26 line to processor.
27
28- clocks: Should contain the device's input clock, and should be defined as per
29 the appropriate clock bindings consumer usage in,
30
31 Documentation/devicetree/bindings/clock/keystone-gate.txt
32 for 66AK2HK/66AK2L/66AK2E SoCs or,
33
34 Documentation/devicetree/bindings/clock/ti,sci-clk.txt
35 for 66AK2G SoCs
36
37- clock-names: Name should be "gpio";
38
39Currently clock-names and clocks are needed for all keystone 2 platforms
40Davinci platforms do not have DT clocks as of now.
24 41
25The GPIO controller also acts as an interrupt controller. It uses the default 42The GPIO controller also acts as an interrupt controller. It uses the default
26two cells specifier as described in Documentation/devicetree/bindings/ 43two cells specifier as described in Documentation/devicetree/bindings/
@@ -60,3 +77,73 @@ leds {
60 ... 77 ...
61 }; 78 };
62}; 79};
80
81Example for 66AK2G:
82
83gpio0: gpio@2603000 {
84 compatible = "ti,k2g-gpio", "ti,keystone-gpio";
85 reg = <0x02603000 0x100>;
86 gpio-controller;
87 #gpio-cells = <2>;
88 interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
89 <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
90 <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
91 <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
92 <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
93 <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
94 <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
95 <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
96 <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;
97 interrupt-controller;
98 #interrupt-cells = <2>;
99 ti,ngpio = <144>;
100 ti,davinci-gpio-unbanked = <0>;
101 clocks = <&k2g_clks 0x001b 0x0>;
102 clock-names = "gpio";
103};
104
105Example for 66AK2HK/66AK2L/66AK2E:
106
107gpio0: gpio@260bf00 {
108 compatible = "ti,keystone-gpio";
109 reg = <0x0260bf00 0x100>;
110 gpio-controller;
111 #gpio-cells = <2>;
112 /* HW Interrupts mapped to GPIO pins */
113 interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
114 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
115 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
116 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
117 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
118 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
119 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
120 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
121 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
122 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
123 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
124 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
125 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
126 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
127 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
128 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
129 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
130 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
131 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
132 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
133 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
134 <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
135 <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
136 <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
137 <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
138 <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
139 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
140 <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
141 <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
142 <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
143 <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
144 <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
145 clocks = <&clkgpio>;
146 clock-names = "gpio";
147 ti,ngpio = <32>;
148 ti,davinci-gpio-unbanked = <32>;
149};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt
index 436cc99c6598..0ccbae44019c 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt
@@ -5,7 +5,9 @@ functionality. Each pair serves 32 GPIOs. The VF610 has 5 instances of
5each, and each PORT module has its own interrupt. 5each, and each PORT module has its own interrupt.
6 6
7Required properties for GPIO node: 7Required properties for GPIO node:
8- compatible : Should be "fsl,<soc>-gpio", currently "fsl,vf610-gpio" 8- compatible : Should be "fsl,<soc>-gpio", below is supported list:
9 "fsl,vf610-gpio"
10 "fsl,imx7ulp-gpio"
9- reg : The first reg tuple represents the PORT module, the second tuple 11- reg : The first reg tuple represents the PORT module, the second tuple
10 the GPIO module. 12 the GPIO module.
11- interrupts : Should be the port interrupt shared by all 32 pins. 13- interrupts : Should be the port interrupt shared by all 32 pins.
diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
index 6826a371fb69..51c86f69995e 100644
--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
@@ -2,8 +2,9 @@
2 2
3Required Properties: 3Required Properties:
4 4
5 - compatible: should contain one of the following. 5 - compatible: should contain one or more of the following:
6 - "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller. 6 - "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller.
7 - "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller.
7 - "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller. 8 - "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller.
8 - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller. 9 - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
9 - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller. 10 - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
@@ -13,7 +14,14 @@ Required Properties:
13 - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller. 14 - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller.
14 - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller. 15 - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
15 - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller. 16 - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller.
16 - "renesas,gpio-rcar": for generic R-Car GPIO controller. 17 - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
18 - "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO controller.
19 - "renesas,rcar-gen3-gpio": for a generic R-Car Gen3 GPIO controller.
20 - "renesas,gpio-rcar": deprecated.
21
22 When compatible with the generic version nodes must list the
23 SoC-specific version corresponding to the platform first followed by
24 the generic version.
17 25
18 - reg: Base address and length of each memory resource used by the GPIO 26 - reg: Base address and length of each memory resource used by the GPIO
19 controller hardware module. 27 controller hardware module.
@@ -43,7 +51,7 @@ interrupt-controller/interrupts.txt.
43Example: R8A7779 (R-Car H1) GPIO controller nodes 51Example: R8A7779 (R-Car H1) GPIO controller nodes
44 52
45 gpio0: gpio@ffc40000 { 53 gpio0: gpio@ffc40000 {
46 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 54 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
47 reg = <0xffc40000 0x2c>; 55 reg = <0xffc40000 0x2c>;
48 interrupt-parent = <&gic>; 56 interrupt-parent = <&gic>;
49 interrupts = <0 141 0x4>; 57 interrupts = <0 141 0x4>;
@@ -55,7 +63,7 @@ Example: R8A7779 (R-Car H1) GPIO controller nodes
55 }; 63 };
56 ... 64 ...
57 gpio6: gpio@ffc46000 { 65 gpio6: gpio@ffc46000 {
58 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 66 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
59 reg = <0xffc46000 0x2c>; 67 reg = <0xffc46000 0x2c>;
60 interrupt-parent = <&gic>; 68 interrupt-parent = <&gic>;
61 interrupts = <0 147 0x4>; 69 interrupts = <0 147 0x4>;
diff --git a/Documentation/driver-api/gpio.rst b/Documentation/driver-api/gpio.rst
new file mode 100644
index 000000000000..6dd4aa647f27
--- /dev/null
+++ b/Documentation/driver-api/gpio.rst
@@ -0,0 +1,45 @@
1===================================
2General Purpose Input/Output (GPIO)
3===================================
4
5Core
6====
7
8.. kernel-doc:: include/linux/gpio/driver.h
9 :internal:
10
11.. kernel-doc:: drivers/gpio/gpiolib.c
12 :export:
13
14Legacy API
15==========
16
17The functions listed in this section are deprecated. The GPIO descriptor based
18API described above should be used in new code.
19
20.. kernel-doc:: drivers/gpio/gpiolib-legacy.c
21 :export:
22
23ACPI support
24============
25
26.. kernel-doc:: drivers/gpio/gpiolib-acpi.c
27 :export:
28
29Device tree support
30===================
31
32.. kernel-doc:: drivers/gpio/gpiolib-of.c
33 :export:
34
35Device-managed API
36==================
37
38.. kernel-doc:: drivers/gpio/devres.c
39 :export:
40
41sysfs helpers
42=============
43
44.. kernel-doc:: drivers/gpio/gpiolib-sysfs.c
45 :export:
diff --git a/Documentation/driver-api/index.rst b/Documentation/driver-api/index.rst
index 7c94ab50afed..9c20624842b7 100644
--- a/Documentation/driver-api/index.rst
+++ b/Documentation/driver-api/index.rst
@@ -44,6 +44,7 @@ available subsections can be seen below.
44 uio-howto 44 uio-howto
45 firmware/index 45 firmware/index
46 pinctl 46 pinctl
47 gpio
47 misc_devices 48 misc_devices
48 49
49.. only:: subproject and html 50.. only:: subproject and html
diff --git a/MAINTAINERS b/MAINTAINERS
index c8b2c7e798fa..ed838cf34d33 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13018,6 +13018,11 @@ M: Yehezkel Bernat <yehezkel.bernat@intel.com>
13018S: Maintained 13018S: Maintained
13019F: drivers/thunderbolt/ 13019F: drivers/thunderbolt/
13020 13020
13021THUNDERX GPIO DRIVER
13022M: David Daney <david.daney@cavium.com>
13023S: Maintained
13024F: drivers/gpio/gpio-thunderx.c
13025
13021TI AM437X VPFE DRIVER 13026TI AM437X VPFE DRIVER
13022M: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> 13027M: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
13023L: linux-media@vger.kernel.org 13028L: linux-media@vger.kernel.org
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 461d6fc3688b..3388d54ba114 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -311,7 +311,7 @@ config GPIO_MOCKUP
311 depends on GPIOLIB && SYSFS 311 depends on GPIOLIB && SYSFS
312 select GPIO_SYSFS 312 select GPIO_SYSFS
313 select GPIOLIB_IRQCHIP 313 select GPIOLIB_IRQCHIP
314 select IRQ_WORK 314 select IRQ_SIM
315 help 315 help
316 This enables GPIO Testing driver, which provides a way to test GPIO 316 This enables GPIO Testing driver, which provides a way to test GPIO
317 subsystem through sysfs(or char device) and debugfs. GPIO_SYSFS 317 subsystem through sysfs(or char device) and debugfs. GPIO_SYSFS
@@ -450,6 +450,15 @@ config GPIO_TS4800
450 help 450 help
451 This driver support TS-4800 FPGA GPIO controllers. 451 This driver support TS-4800 FPGA GPIO controllers.
452 452
453config GPIO_THUNDERX
454 tristate "Cavium ThunderX/OCTEON-TX GPIO"
455 depends on ARCH_THUNDER || (64BIT && COMPILE_TEST)
456 depends on PCI_MSI && IRQ_DOMAIN_HIERARCHY
457 select IRQ_FASTEOI_HIERARCHY_HANDLERS
458 help
459 Say yes here to support the on-chip GPIO lines on the ThunderX
460 and OCTEON-TX families of SoCs.
461
453config GPIO_TZ1090 462config GPIO_TZ1090
454 bool "Toumaz Xenif TZ1090 GPIO support" 463 bool "Toumaz Xenif TZ1090 GPIO support"
455 depends on SOC_TZ1090 464 depends on SOC_TZ1090
@@ -1065,6 +1074,21 @@ config GPIO_TPS65912
1065 help 1074 help
1066 This driver supports TPS65912 gpio chip 1075 This driver supports TPS65912 gpio chip
1067 1076
1077config GPIO_TPS68470
1078 bool "TPS68470 GPIO"
1079 depends on MFD_TPS68470
1080 help
1081 Select this option to enable GPIO driver for the TPS68470
1082 chip family.
1083 There are 7 GPIOs and few sensor related GPIOs supported
1084 by the TPS68470. While the 7 GPIOs can be configured as
1085 input or output as appropriate, the sensor related GPIOs
1086 are "output only" GPIOs.
1087
1088 This driver config is bool, as the GPIO functionality
1089 of the TPS68470 must be available before dependent
1090 drivers are loaded.
1091
1068config GPIO_TWL4030 1092config GPIO_TWL4030
1069 tristate "TWL4030, TWL5030, and TPS659x0 GPIOs" 1093 tristate "TWL4030, TWL5030, and TPS659x0 GPIOs"
1070 depends on TWL4030_CORE 1094 depends on TWL4030_CORE
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index a9fda6c55113..aeb70e9de6f2 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -113,6 +113,7 @@ obj-$(CONFIG_GPIO_SYSCON) += gpio-syscon.o
113obj-$(CONFIG_GPIO_TB10X) += gpio-tb10x.o 113obj-$(CONFIG_GPIO_TB10X) += gpio-tb10x.o
114obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o 114obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o
115obj-$(CONFIG_GPIO_TEGRA) += gpio-tegra.o 115obj-$(CONFIG_GPIO_TEGRA) += gpio-tegra.o
116obj-$(CONFIG_GPIO_THUNDERX) += gpio-thunderx.o
116obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o 117obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o
117obj-$(CONFIG_GPIO_PALMAS) += gpio-palmas.o 118obj-$(CONFIG_GPIO_PALMAS) += gpio-palmas.o
118obj-$(CONFIG_GPIO_TPIC2810) += gpio-tpic2810.o 119obj-$(CONFIG_GPIO_TPIC2810) += gpio-tpic2810.o
@@ -121,6 +122,7 @@ obj-$(CONFIG_GPIO_TPS65218) += gpio-tps65218.o
121obj-$(CONFIG_GPIO_TPS6586X) += gpio-tps6586x.o 122obj-$(CONFIG_GPIO_TPS6586X) += gpio-tps6586x.o
122obj-$(CONFIG_GPIO_TPS65910) += gpio-tps65910.o 123obj-$(CONFIG_GPIO_TPS65910) += gpio-tps65910.o
123obj-$(CONFIG_GPIO_TPS65912) += gpio-tps65912.o 124obj-$(CONFIG_GPIO_TPS65912) += gpio-tps65912.o
125obj-$(CONFIG_GPIO_TPS68470) += gpio-tps68470.o
124obj-$(CONFIG_GPIO_TS4800) += gpio-ts4800.o 126obj-$(CONFIG_GPIO_TS4800) += gpio-ts4800.o
125obj-$(CONFIG_GPIO_TS4900) += gpio-ts4900.o 127obj-$(CONFIG_GPIO_TS4900) += gpio-ts4900.o
126obj-$(CONFIG_GPIO_TS5500) += gpio-ts5500.o 128obj-$(CONFIG_GPIO_TS5500) += gpio-ts5500.o
diff --git a/drivers/gpio/devres.c b/drivers/gpio/devres.c
index a75511d1ea5d..afbff155a0ba 100644
--- a/drivers/gpio/devres.c
+++ b/drivers/gpio/devres.c
@@ -132,6 +132,7 @@ EXPORT_SYMBOL(devm_gpiod_get_index);
132 * @index: index of the GPIO to obtain in the consumer 132 * @index: index of the GPIO to obtain in the consumer
133 * @child: firmware node (child of @dev) 133 * @child: firmware node (child of @dev)
134 * @flags: GPIO initialization flags 134 * @flags: GPIO initialization flags
135 * @label: label to attach to the requested GPIO
135 * 136 *
136 * GPIO descriptors returned from this function are automatically disposed on 137 * GPIO descriptors returned from this function are automatically disposed on
137 * driver detach. 138 * driver detach.
@@ -271,6 +272,7 @@ EXPORT_SYMBOL(devm_gpiod_get_array_optional);
271 272
272/** 273/**
273 * devm_gpiod_put - Resource-managed gpiod_put() 274 * devm_gpiod_put - Resource-managed gpiod_put()
275 * @dev: GPIO consumer
274 * @desc: GPIO descriptor to dispose of 276 * @desc: GPIO descriptor to dispose of
275 * 277 *
276 * Dispose of a GPIO descriptor obtained with devm_gpiod_get() or 278 * Dispose of a GPIO descriptor obtained with devm_gpiod_get() or
@@ -286,6 +288,7 @@ EXPORT_SYMBOL(devm_gpiod_put);
286 288
287/** 289/**
288 * devm_gpiod_put_array - Resource-managed gpiod_put_array() 290 * devm_gpiod_put_array - Resource-managed gpiod_put_array()
291 * @dev: GPIO consumer
289 * @descs: GPIO descriptor array to dispose of 292 * @descs: GPIO descriptor array to dispose of
290 * 293 *
291 * Dispose of an array of GPIO descriptors obtained with devm_gpiod_get_array(). 294 * Dispose of an array of GPIO descriptors obtained with devm_gpiod_get_array().
diff --git a/drivers/gpio/gpio-74x164.c b/drivers/gpio/gpio-74x164.c
index a6607faf2fdf..6b535ec858cc 100644
--- a/drivers/gpio/gpio-74x164.c
+++ b/drivers/gpio/gpio-74x164.c
@@ -9,6 +9,7 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include <linux/gpio/consumer.h>
12#include <linux/init.h> 13#include <linux/init.h>
13#include <linux/mutex.h> 14#include <linux/mutex.h>
14#include <linux/spi/spi.h> 15#include <linux/spi/spi.h>
@@ -31,6 +32,7 @@ struct gen_74x164_chip {
31 * numbering, store the bytes in reverse order. 32 * numbering, store the bytes in reverse order.
32 */ 33 */
33 u8 buffer[0]; 34 u8 buffer[0];
35 struct gpio_desc *gpiod_oe;
34}; 36};
35 37
36static int __gen_74x164_write_config(struct gen_74x164_chip *chip) 38static int __gen_74x164_write_config(struct gen_74x164_chip *chip)
@@ -126,6 +128,13 @@ static int gen_74x164_probe(struct spi_device *spi)
126 if (!chip) 128 if (!chip)
127 return -ENOMEM; 129 return -ENOMEM;
128 130
131 chip->gpiod_oe = devm_gpiod_get_optional(&spi->dev, "enable",
132 GPIOD_OUT_LOW);
133 if (IS_ERR(chip->gpiod_oe))
134 return PTR_ERR(chip->gpiod_oe);
135
136 gpiod_set_value_cansleep(chip->gpiod_oe, 1);
137
129 spi_set_drvdata(spi, chip); 138 spi_set_drvdata(spi, chip);
130 139
131 chip->gpio_chip.label = spi->modalias; 140 chip->gpio_chip.label = spi->modalias;
@@ -164,6 +173,7 @@ static int gen_74x164_remove(struct spi_device *spi)
164{ 173{
165 struct gen_74x164_chip *chip = spi_get_drvdata(spi); 174 struct gen_74x164_chip *chip = spi_get_drvdata(spi);
166 175
176 gpiod_set_value_cansleep(chip->gpiod_oe, 0);
167 gpiochip_remove(&chip->gpio_chip); 177 gpiochip_remove(&chip->gpio_chip);
168 mutex_destroy(&chip->lock); 178 mutex_destroy(&chip->lock);
169 179
diff --git a/drivers/gpio/gpio-altera-a10sr.c b/drivers/gpio/gpio-altera-a10sr.c
index 16a8951b2bed..6b11f1314248 100644
--- a/drivers/gpio/gpio-altera-a10sr.c
+++ b/drivers/gpio/gpio-altera-a10sr.c
@@ -71,7 +71,7 @@ static int altr_a10sr_gpio_direction_output(struct gpio_chip *gc,
71 return -EINVAL; 71 return -EINVAL;
72} 72}
73 73
74static struct gpio_chip altr_a10sr_gc = { 74static const struct gpio_chip altr_a10sr_gc = {
75 .label = "altr_a10sr_gpio", 75 .label = "altr_a10sr_gpio",
76 .owner = THIS_MODULE, 76 .owner = THIS_MODULE,
77 .get = altr_a10sr_gpio_get, 77 .get = altr_a10sr_gpio_get,
diff --git a/drivers/gpio/gpio-altera.c b/drivers/gpio/gpio-altera.c
index 17485dc20384..ccc02ed65b3c 100644
--- a/drivers/gpio/gpio-altera.c
+++ b/drivers/gpio/gpio-altera.c
@@ -324,8 +324,8 @@ skip_irq:
324 return 0; 324 return 0;
325teardown: 325teardown:
326 of_mm_gpiochip_remove(&altera_gc->mmchip); 326 of_mm_gpiochip_remove(&altera_gc->mmchip);
327 pr_err("%s: registration failed with status %d\n", 327 pr_err("%pOF: registration failed with status %d\n",
328 node->full_name, ret); 328 node, ret);
329 329
330 return ret; 330 return ret;
331} 331}
diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
index 4ca436e66bdb..bfc53995064a 100644
--- a/drivers/gpio/gpio-aspeed.c
+++ b/drivers/gpio/gpio-aspeed.c
@@ -834,7 +834,7 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)
834 gpio->clk = of_clk_get(pdev->dev.of_node, 0); 834 gpio->clk = of_clk_get(pdev->dev.of_node, 0);
835 if (IS_ERR(gpio->clk)) { 835 if (IS_ERR(gpio->clk)) {
836 dev_warn(&pdev->dev, 836 dev_warn(&pdev->dev,
837 "No HPLL clock phandle provided, debouncing disabled\n"); 837 "Failed to get clock from devicetree, debouncing disabled\n");
838 gpio->clk = NULL; 838 gpio->clk = NULL;
839 } 839 }
840 840
diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c
index e6489143721a..dd0308cc8bb0 100644
--- a/drivers/gpio/gpio-brcmstb.c
+++ b/drivers/gpio/gpio-brcmstb.c
@@ -339,6 +339,7 @@ static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
339 struct brcmstb_gpio_priv *priv = bank->parent_priv; 339 struct brcmstb_gpio_priv *priv = bank->parent_priv;
340 struct device *dev = &pdev->dev; 340 struct device *dev = &pdev->dev;
341 struct device_node *np = dev->of_node; 341 struct device_node *np = dev->of_node;
342 int err;
342 343
343 bank->irq_chip.name = dev_name(dev); 344 bank->irq_chip.name = dev_name(dev);
344 bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask; 345 bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
@@ -355,8 +356,6 @@ static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
355 dev_warn(dev, 356 dev_warn(dev,
356 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep"); 357 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
357 } else { 358 } else {
358 int err;
359
360 /* 359 /*
361 * Set wakeup capability before requesting wakeup 360 * Set wakeup capability before requesting wakeup
362 * interrupt, so we can process boot-time "wakeups" 361 * interrupt, so we can process boot-time "wakeups"
@@ -383,8 +382,10 @@ static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
383 if (priv->can_wake) 382 if (priv->can_wake)
384 bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake; 383 bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
385 384
386 gpiochip_irqchip_add(&bank->gc, &bank->irq_chip, 0, 385 err = gpiochip_irqchip_add(&bank->gc, &bank->irq_chip, 0,
387 handle_simple_irq, IRQ_TYPE_NONE); 386 handle_simple_irq, IRQ_TYPE_NONE);
387 if (err)
388 return err;
388 gpiochip_set_chained_irqchip(&bank->gc, &bank->irq_chip, 389 gpiochip_set_chained_irqchip(&bank->gc, &bank->irq_chip,
389 priv->parent_irq, brcmstb_gpio_irq_handler); 390 priv->parent_irq, brcmstb_gpio_irq_handler);
390 391
@@ -483,7 +484,7 @@ static int brcmstb_gpio_probe(struct platform_device *pdev)
483 484
484 gc->of_node = np; 485 gc->of_node = np;
485 gc->owner = THIS_MODULE; 486 gc->owner = THIS_MODULE;
486 gc->label = np->full_name; 487 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", dev->of_node);
487 gc->base = gpio_base; 488 gc->base = gpio_base;
488 gc->of_gpio_n_cells = 2; 489 gc->of_gpio_n_cells = 2;
489 gc->of_xlate = brcmstb_gpio_of_xlate; 490 gc->of_xlate = brcmstb_gpio_of_xlate;
diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
index 65cb359308e3..f75d8443ecaf 100644
--- a/drivers/gpio/gpio-davinci.c
+++ b/drivers/gpio/gpio-davinci.c
@@ -166,7 +166,7 @@ of_err:
166static int davinci_gpio_probe(struct platform_device *pdev) 166static int davinci_gpio_probe(struct platform_device *pdev)
167{ 167{
168 static int ctrl_num, bank_base; 168 static int ctrl_num, bank_base;
169 int gpio, bank; 169 int gpio, bank, ret = 0;
170 unsigned ngpio, nbank; 170 unsigned ngpio, nbank;
171 struct davinci_gpio_controller *chips; 171 struct davinci_gpio_controller *chips;
172 struct davinci_gpio_platform_data *pdata; 172 struct davinci_gpio_platform_data *pdata;
@@ -232,10 +232,23 @@ static int davinci_gpio_probe(struct platform_device *pdev)
232 for (gpio = 0, bank = 0; gpio < ngpio; gpio += 32, bank++) 232 for (gpio = 0, bank = 0; gpio < ngpio; gpio += 32, bank++)
233 chips->regs[bank] = gpio_base + offset_array[bank]; 233 chips->regs[bank] = gpio_base + offset_array[bank];
234 234
235 gpiochip_add_data(&chips->chip, chips); 235 ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
236 if (ret)
237 goto err;
238
236 platform_set_drvdata(pdev, chips); 239 platform_set_drvdata(pdev, chips);
237 davinci_gpio_irq_setup(pdev); 240 ret = davinci_gpio_irq_setup(pdev);
241 if (ret)
242 goto err;
243
238 return 0; 244 return 0;
245
246err:
247 /* Revert the static variable increments */
248 ctrl_num--;
249 bank_base -= ngpio;
250
251 return ret;
239} 252}
240 253
241/*--------------------------------------------------------------------------*/ 254/*--------------------------------------------------------------------------*/
@@ -477,8 +490,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
477 490
478 clk = devm_clk_get(dev, "gpio"); 491 clk = devm_clk_get(dev, "gpio");
479 if (IS_ERR(clk)) { 492 if (IS_ERR(clk)) {
480 printk(KERN_ERR "Error %ld getting gpio clock?\n", 493 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
481 PTR_ERR(clk));
482 return PTR_ERR(clk); 494 return PTR_ERR(clk);
483 } 495 }
484 ret = clk_prepare_enable(clk); 496 ret = clk_prepare_enable(clk);
diff --git a/drivers/gpio/gpio-ge.c b/drivers/gpio/gpio-ge.c
index 8650b2916f87..6f5a7fe9787d 100644
--- a/drivers/gpio/gpio-ge.c
+++ b/drivers/gpio/gpio-ge.c
@@ -76,8 +76,7 @@ static int __init gef_gpio_probe(struct platform_device *pdev)
76 } 76 }
77 77
78 /* Setup pointers to chip functions */ 78 /* Setup pointers to chip functions */
79 gc->label = devm_kstrdup(&pdev->dev, pdev->dev.of_node->full_name, 79 gc->label = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%pOF", pdev->dev.of_node);
80 GFP_KERNEL);
81 if (!gc->label) { 80 if (!gc->label) {
82 ret = -ENOMEM; 81 ret = -ENOMEM;
83 goto err0; 82 goto err0;
@@ -96,8 +95,7 @@ static int __init gef_gpio_probe(struct platform_device *pdev)
96 return 0; 95 return 0;
97err0: 96err0:
98 iounmap(regs); 97 iounmap(regs);
99 pr_err("%s: GPIO chip registration failed\n", 98 pr_err("%pOF: GPIO chip registration failed\n", pdev->dev.of_node);
100 pdev->dev.of_node->full_name);
101 return ret; 99 return ret;
102}; 100};
103 101
diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c
index 7847dd34f86f..6544a16ab02e 100644
--- a/drivers/gpio/gpio-grgpio.c
+++ b/drivers/gpio/gpio-grgpio.c
@@ -367,7 +367,7 @@ static int grgpio_probe(struct platform_device *ofdev)
367 gc->of_node = np; 367 gc->of_node = np;
368 gc->owner = THIS_MODULE; 368 gc->owner = THIS_MODULE;
369 gc->to_irq = grgpio_to_irq; 369 gc->to_irq = grgpio_to_irq;
370 gc->label = np->full_name; 370 gc->label = devm_kasprintf(&ofdev->dev, GFP_KERNEL, "%pOF", np);
371 gc->base = -1; 371 gc->base = -1;
372 372
373 err = of_property_read_u32(np, "nbits", &prop); 373 err = of_property_read_u32(np, "nbits", &prop);
diff --git a/drivers/gpio/gpio-it87.c b/drivers/gpio/gpio-it87.c
index 45d29e488dbb..d43d0a2cc4c5 100644
--- a/drivers/gpio/gpio-it87.c
+++ b/drivers/gpio/gpio-it87.c
@@ -2,6 +2,7 @@
2 * GPIO interface for IT87xx Super I/O chips 2 * GPIO interface for IT87xx Super I/O chips
3 * 3 *
4 * Author: Diego Elio Pettenò <flameeyes@flameeyes.eu> 4 * Author: Diego Elio Pettenò <flameeyes@flameeyes.eu>
5 * Copyright (c) 2017 Google, Inc.
5 * 6 *
6 * Based on it87_wdt.c by Oliver Schuster 7 * Based on it87_wdt.c by Oliver Schuster
7 * gpio-it8761e.c by Denis Turischev 8 * gpio-it8761e.c by Denis Turischev
@@ -39,6 +40,7 @@
39#define IT8728_ID 0x8728 40#define IT8728_ID 0x8728
40#define IT8732_ID 0x8732 41#define IT8732_ID 0x8732
41#define IT8761_ID 0x8761 42#define IT8761_ID 0x8761
43#define IT8772_ID 0x8772
42 44
43/* IO Ports */ 45/* IO Ports */
44#define REG 0x2e 46#define REG 0x2e
@@ -314,6 +316,7 @@ static int __init it87_gpio_init(void)
314 break; 316 break;
315 case IT8728_ID: 317 case IT8728_ID:
316 case IT8732_ID: 318 case IT8732_ID:
319 case IT8772_ID:
317 gpio_ba_reg = 0x62; 320 gpio_ba_reg = 0x62;
318 it87_gpio->io_size = 8; 321 it87_gpio->io_size = 8;
319 it87_gpio->output_base = 0xc8; 322 it87_gpio->output_base = 0xc8;
diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
index 743459d9477d..538bce4b5b42 100644
--- a/drivers/gpio/gpio-max77620.c
+++ b/drivers/gpio/gpio-max77620.c
@@ -82,7 +82,7 @@ static const struct regmap_irq max77620_gpio_irqs[] = {
82 }, 82 },
83}; 83};
84 84
85static struct regmap_irq_chip max77620_gpio_irq_chip = { 85static const struct regmap_irq_chip max77620_gpio_irq_chip = {
86 .name = "max77620-gpio", 86 .name = "max77620-gpio",
87 .irqs = max77620_gpio_irqs, 87 .irqs = max77620_gpio_irqs,
88 .num_irqs = ARRAY_SIZE(max77620_gpio_irqs), 88 .num_irqs = ARRAY_SIZE(max77620_gpio_irqs),
diff --git a/drivers/gpio/gpio-mb86s7x.c b/drivers/gpio/gpio-mb86s7x.c
index ffb73f688ae1..94d772677ed6 100644
--- a/drivers/gpio/gpio-mb86s7x.c
+++ b/drivers/gpio/gpio-mb86s7x.c
@@ -168,7 +168,9 @@ static int mb86s70_gpio_probe(struct platform_device *pdev)
168 if (IS_ERR(gchip->clk)) 168 if (IS_ERR(gchip->clk))
169 return PTR_ERR(gchip->clk); 169 return PTR_ERR(gchip->clk);
170 170
171 clk_prepare_enable(gchip->clk); 171 ret = clk_prepare_enable(gchip->clk);
172 if (ret)
173 return ret;
172 174
173 spin_lock_init(&gchip->lock); 175 spin_lock_init(&gchip->lock);
174 176
diff --git a/drivers/gpio/gpio-ml-ioh.c b/drivers/gpio/gpio-ml-ioh.c
index 74fdce096c26..4b80e996d976 100644
--- a/drivers/gpio/gpio-ml-ioh.c
+++ b/drivers/gpio/gpio-ml-ioh.c
@@ -391,9 +391,10 @@ static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
391{ 391{
392 struct irq_chip_generic *gc; 392 struct irq_chip_generic *gc;
393 struct irq_chip_type *ct; 393 struct irq_chip_type *ct;
394 int rv;
394 395
395 gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base, 396 gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start,
396 handle_simple_irq); 397 chip->base, handle_simple_irq);
397 if (!gc) 398 if (!gc)
398 return -ENOMEM; 399 return -ENOMEM;
399 400
@@ -406,10 +407,11 @@ static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
406 ct->chip.irq_disable = ioh_irq_disable; 407 ct->chip.irq_disable = ioh_irq_disable;
407 ct->chip.irq_enable = ioh_irq_enable; 408 ct->chip.irq_enable = ioh_irq_enable;
408 409
409 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, 410 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
410 IRQ_NOREQUEST | IRQ_NOPROBE, 0); 411 IRQ_GC_INIT_MASK_CACHE,
412 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
411 413
412 return 0; 414 return rv;
413} 415}
414 416
415static int ioh_gpio_probe(struct pci_dev *pdev, 417static int ioh_gpio_probe(struct pci_dev *pdev,
diff --git a/drivers/gpio/gpio-mockup.c b/drivers/gpio/gpio-mockup.c
index a6565e128f9e..9532d86a82f7 100644
--- a/drivers/gpio/gpio-mockup.c
+++ b/drivers/gpio/gpio-mockup.c
@@ -20,7 +20,7 @@
20#include <linux/slab.h> 20#include <linux/slab.h>
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/irq_work.h> 23#include <linux/irq_sim.h>
24#include <linux/debugfs.h> 24#include <linux/debugfs.h>
25#include <linux/uaccess.h> 25#include <linux/uaccess.h>
26 26
@@ -47,18 +47,12 @@ enum {
47struct gpio_mockup_line_status { 47struct gpio_mockup_line_status {
48 int dir; 48 int dir;
49 bool value; 49 bool value;
50 bool irq_enabled;
51};
52
53struct gpio_mockup_irq_context {
54 struct irq_work work;
55 int irq;
56}; 50};
57 51
58struct gpio_mockup_chip { 52struct gpio_mockup_chip {
59 struct gpio_chip gc; 53 struct gpio_chip gc;
60 struct gpio_mockup_line_status *lines; 54 struct gpio_mockup_line_status *lines;
61 struct gpio_mockup_irq_context irq_ctx; 55 struct irq_sim irqsim;
62 struct dentry *dbg_dir; 56 struct dentry *dbg_dir;
63}; 57};
64 58
@@ -144,65 +138,11 @@ static int gpio_mockup_name_lines(struct device *dev,
144 return 0; 138 return 0;
145} 139}
146 140
147static int gpio_mockup_to_irq(struct gpio_chip *chip, unsigned int offset) 141static int gpio_mockup_to_irq(struct gpio_chip *gc, unsigned int offset)
148{
149 return chip->irq_base + offset;
150}
151
152static void gpio_mockup_irqmask(struct irq_data *data)
153{
154 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
155 struct gpio_mockup_chip *chip = gpiochip_get_data(gc);
156
157 chip->lines[data->irq - gc->irq_base].irq_enabled = false;
158}
159
160static void gpio_mockup_irqunmask(struct irq_data *data)
161{ 142{
162 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
163 struct gpio_mockup_chip *chip = gpiochip_get_data(gc); 143 struct gpio_mockup_chip *chip = gpiochip_get_data(gc);
164 144
165 chip->lines[data->irq - gc->irq_base].irq_enabled = true; 145 return irq_sim_irqnum(&chip->irqsim, offset);
166}
167
168static struct irq_chip gpio_mockup_irqchip = {
169 .name = GPIO_MOCKUP_NAME,
170 .irq_mask = gpio_mockup_irqmask,
171 .irq_unmask = gpio_mockup_irqunmask,
172};
173
174static void gpio_mockup_handle_irq(struct irq_work *work)
175{
176 struct gpio_mockup_irq_context *irq_ctx;
177
178 irq_ctx = container_of(work, struct gpio_mockup_irq_context, work);
179 handle_simple_irq(irq_to_desc(irq_ctx->irq));
180}
181
182static int gpio_mockup_irqchip_setup(struct device *dev,
183 struct gpio_mockup_chip *chip)
184{
185 struct gpio_chip *gc = &chip->gc;
186 int irq_base, i;
187
188 irq_base = devm_irq_alloc_descs(dev, -1, 0, gc->ngpio, 0);
189 if (irq_base < 0)
190 return irq_base;
191
192 gc->irq_base = irq_base;
193 gc->irqchip = &gpio_mockup_irqchip;
194
195 for (i = 0; i < gc->ngpio; i++) {
196 irq_set_chip(irq_base + i, gc->irqchip);
197 irq_set_chip_data(irq_base + i, gc);
198 irq_set_handler(irq_base + i, &handle_simple_irq);
199 irq_modify_status(irq_base + i,
200 IRQ_NOREQUEST | IRQ_NOAUTOEN, IRQ_NOPROBE);
201 }
202
203 init_irq_work(&chip->irq_ctx.work, gpio_mockup_handle_irq);
204
205 return 0;
206} 146}
207 147
208static ssize_t gpio_mockup_event_write(struct file *file, 148static ssize_t gpio_mockup_event_write(struct file *file,
@@ -213,7 +153,6 @@ static ssize_t gpio_mockup_event_write(struct file *file,
213 struct gpio_mockup_chip *chip; 153 struct gpio_mockup_chip *chip;
214 struct seq_file *sfile; 154 struct seq_file *sfile;
215 struct gpio_desc *desc; 155 struct gpio_desc *desc;
216 struct gpio_chip *gc;
217 int rv, val; 156 int rv, val;
218 157
219 rv = kstrtoint_from_user(usr_buf, size, 0, &val); 158 rv = kstrtoint_from_user(usr_buf, size, 0, &val);
@@ -226,13 +165,9 @@ static ssize_t gpio_mockup_event_write(struct file *file,
226 priv = sfile->private; 165 priv = sfile->private;
227 desc = priv->desc; 166 desc = priv->desc;
228 chip = priv->chip; 167 chip = priv->chip;
229 gc = &chip->gc;
230 168
231 if (chip->lines[priv->offset].irq_enabled) { 169 gpiod_set_value_cansleep(desc, val);
232 gpiod_set_value_cansleep(desc, val); 170 irq_sim_fire(&chip->irqsim, priv->offset);
233 priv->chip->irq_ctx.irq = gc->irq_base + priv->offset;
234 irq_work_queue(&priv->chip->irq_ctx.work);
235 }
236 171
237 return size; 172 return size;
238} 173}
@@ -319,7 +254,7 @@ static int gpio_mockup_add(struct device *dev,
319 return ret; 254 return ret;
320 } 255 }
321 256
322 ret = gpio_mockup_irqchip_setup(dev, chip); 257 ret = devm_irq_sim_init(dev, &chip->irqsim, gc->ngpio);
323 if (ret) 258 if (ret)
324 return ret; 259 return ret;
325 260
diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
index 793518a30afe..8c93dec498fa 100644
--- a/drivers/gpio/gpio-mpc8xxx.c
+++ b/drivers/gpio/gpio-mpc8xxx.c
@@ -348,8 +348,8 @@ static int mpc8xxx_probe(struct platform_device *pdev)
348 348
349 ret = gpiochip_add_data(gc, mpc8xxx_gc); 349 ret = gpiochip_add_data(gc, mpc8xxx_gc);
350 if (ret) { 350 if (ret) {
351 pr_err("%s: GPIO chip registration failed with status %d\n", 351 pr_err("%pOF: GPIO chip registration failed with status %d\n",
352 np->full_name, ret); 352 np, ret);
353 goto err; 353 goto err;
354 } 354 }
355 355
diff --git a/drivers/gpio/gpio-msic.c b/drivers/gpio/gpio-msic.c
index 1b7ce7f85886..6cb67595d15f 100644
--- a/drivers/gpio/gpio-msic.c
+++ b/drivers/gpio/gpio-msic.c
@@ -265,8 +265,8 @@ static int platform_msic_gpio_probe(struct platform_device *pdev)
265 int i; 265 int i;
266 266
267 if (irq < 0) { 267 if (irq < 0) {
268 dev_err(dev, "no IRQ line\n"); 268 dev_err(dev, "no IRQ line: %d\n", irq);
269 return -EINVAL; 269 return irq;
270 } 270 }
271 271
272 if (!pdata || !pdata->gpio_base) { 272 if (!pdata || !pdata->gpio_base) {
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index 92692251ade1..5245a2fe62ae 100644
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -66,6 +66,7 @@ struct mxc_gpio_port {
66 int irq_high; 66 int irq_high;
67 struct irq_domain *domain; 67 struct irq_domain *domain;
68 struct gpio_chip gc; 68 struct gpio_chip gc;
69 struct device *dev;
69 u32 both_edges; 70 u32 both_edges;
70}; 71};
71 72
@@ -324,29 +325,31 @@ static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
324 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 325 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
325 struct mxc_gpio_port *port = gc->private; 326 struct mxc_gpio_port *port = gc->private;
326 u32 gpio_idx = d->hwirq; 327 u32 gpio_idx = d->hwirq;
328 int ret;
327 329
328 if (enable) { 330 if (enable) {
329 if (port->irq_high && (gpio_idx >= 16)) 331 if (port->irq_high && (gpio_idx >= 16))
330 enable_irq_wake(port->irq_high); 332 ret = enable_irq_wake(port->irq_high);
331 else 333 else
332 enable_irq_wake(port->irq); 334 ret = enable_irq_wake(port->irq);
333 } else { 335 } else {
334 if (port->irq_high && (gpio_idx >= 16)) 336 if (port->irq_high && (gpio_idx >= 16))
335 disable_irq_wake(port->irq_high); 337 ret = disable_irq_wake(port->irq_high);
336 else 338 else
337 disable_irq_wake(port->irq); 339 ret = disable_irq_wake(port->irq);
338 } 340 }
339 341
340 return 0; 342 return ret;
341} 343}
342 344
343static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) 345static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
344{ 346{
345 struct irq_chip_generic *gc; 347 struct irq_chip_generic *gc;
346 struct irq_chip_type *ct; 348 struct irq_chip_type *ct;
349 int rv;
347 350
348 gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base, 351 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
349 port->base, handle_level_irq); 352 port->base, handle_level_irq);
350 if (!gc) 353 if (!gc)
351 return -ENOMEM; 354 return -ENOMEM;
352 gc->private = port; 355 gc->private = port;
@@ -361,10 +364,11 @@ static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
361 ct->regs.ack = GPIO_ISR; 364 ct->regs.ack = GPIO_ISR;
362 ct->regs.mask = GPIO_IMR; 365 ct->regs.mask = GPIO_IMR;
363 366
364 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK, 367 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
365 IRQ_NOREQUEST, 0); 368 IRQ_GC_INIT_NESTED_LOCK,
369 IRQ_NOREQUEST, 0);
366 370
367 return 0; 371 return rv;
368} 372}
369 373
370static void mxc_gpio_get_hw(struct platform_device *pdev) 374static void mxc_gpio_get_hw(struct platform_device *pdev)
@@ -418,6 +422,8 @@ static int mxc_gpio_probe(struct platform_device *pdev)
418 if (!port) 422 if (!port)
419 return -ENOMEM; 423 return -ENOMEM;
420 424
425 port->dev = &pdev->dev;
426
421 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 427 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
422 port->base = devm_ioremap_resource(&pdev->dev, iores); 428 port->base = devm_ioremap_resource(&pdev->dev, iores);
423 if (IS_ERR(port->base)) 429 if (IS_ERR(port->base))
@@ -507,6 +513,7 @@ static struct platform_driver mxc_gpio_driver = {
507 .driver = { 513 .driver = {
508 .name = "gpio-mxc", 514 .name = "gpio-mxc",
509 .of_match_table = mxc_gpio_dt_ids, 515 .of_match_table = mxc_gpio_dt_ids,
516 .suppress_bind_attrs = true,
510 }, 517 },
511 .probe = mxc_gpio_probe, 518 .probe = mxc_gpio_probe,
512 .id_table = mxc_gpio_devtype, 519 .id_table = mxc_gpio_devtype,
diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
index 6ae583f36733..435def22445d 100644
--- a/drivers/gpio/gpio-mxs.c
+++ b/drivers/gpio/gpio-mxs.c
@@ -66,6 +66,7 @@ struct mxs_gpio_port {
66 int irq; 66 int irq;
67 struct irq_domain *domain; 67 struct irq_domain *domain;
68 struct gpio_chip gc; 68 struct gpio_chip gc;
69 struct device *dev;
69 enum mxs_gpio_id devid; 70 enum mxs_gpio_id devid;
70 u32 both_edges; 71 u32 both_edges;
71}; 72};
@@ -209,9 +210,10 @@ static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
209{ 210{
210 struct irq_chip_generic *gc; 211 struct irq_chip_generic *gc;
211 struct irq_chip_type *ct; 212 struct irq_chip_type *ct;
213 int rv;
212 214
213 gc = irq_alloc_generic_chip("gpio-mxs", 2, irq_base, 215 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
214 port->base, handle_level_irq); 216 port->base, handle_level_irq);
215 if (!gc) 217 if (!gc)
216 return -ENOMEM; 218 return -ENOMEM;
217 219
@@ -242,10 +244,11 @@ static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
242 ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR; 244 ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
243 ct->handler = handle_level_irq; 245 ct->handler = handle_level_irq;
244 246
245 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK, 247 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
246 IRQ_NOREQUEST, 0); 248 IRQ_GC_INIT_NESTED_LOCK,
249 IRQ_NOREQUEST, 0);
247 250
248 return 0; 251 return rv;
249} 252}
250 253
251static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 254static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
@@ -304,6 +307,7 @@ static int mxs_gpio_probe(struct platform_device *pdev)
304 if (port->id < 0) 307 if (port->id < 0)
305 return port->id; 308 return port->id;
306 port->devid = (enum mxs_gpio_id) of_id->data; 309 port->devid = (enum mxs_gpio_id) of_id->data;
310 port->dev = &pdev->dev;
307 port->irq = platform_get_irq(pdev, 0); 311 port->irq = platform_get_irq(pdev, 0);
308 if (port->irq < 0) 312 if (port->irq < 0)
309 return port->irq; 313 return port->irq;
@@ -379,6 +383,7 @@ static struct platform_driver mxs_gpio_driver = {
379 .driver = { 383 .driver = {
380 .name = "gpio-mxs", 384 .name = "gpio-mxs",
381 .of_match_table = mxs_gpio_dt_ids, 385 .of_match_table = mxs_gpio_dt_ids,
386 .suppress_bind_attrs = true,
382 }, 387 },
383 .probe = mxs_gpio_probe, 388 .probe = mxs_gpio_probe,
384 .id_table = mxs_gpio_ids, 389 .id_table = mxs_gpio_ids,
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index f8c550de6c72..dbf869fb63ce 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1247,6 +1247,8 @@ static int omap_gpio_probe(struct platform_device *pdev)
1247 if (ret) { 1247 if (ret) {
1248 pm_runtime_put_sync(dev); 1248 pm_runtime_put_sync(dev);
1249 pm_runtime_disable(dev); 1249 pm_runtime_disable(dev);
1250 if (bank->dbck_flag)
1251 clk_unprepare(bank->dbck);
1250 return ret; 1252 return ret;
1251 } 1253 }
1252 1254
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index 4c9e21300a26..1b9dbf691ae7 100644
--- a/drivers/gpio/gpio-pca953x.c
+++ b/drivers/gpio/gpio-pca953x.c
@@ -187,10 +187,9 @@ static int pca953x_write_regs_8(struct pca953x_chip *chip, int reg, u8 *val)
187 187
188static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) 188static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
189{ 189{
190 __le16 word = cpu_to_le16(get_unaligned((u16 *)val)); 190 u16 word = get_unaligned((u16 *)val);
191 191
192 return i2c_smbus_write_word_data(chip->client, 192 return i2c_smbus_write_word_data(chip->client, reg << 1, word);
193 reg << 1, (__force u16)word);
194} 193}
195 194
196static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) 195static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
@@ -241,8 +240,7 @@ static int pca953x_read_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
241 int ret; 240 int ret;
242 241
243 ret = i2c_smbus_read_word_data(chip->client, reg << 1); 242 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
244 val[0] = (u16)ret & 0xFF; 243 put_unaligned(ret, (u16 *)val);
245 val[1] = (u16)ret >> 8;
246 244
247 return ret; 245 return ret;
248} 246}
diff --git a/drivers/gpio/gpio-pch.c b/drivers/gpio/gpio-pch.c
index f6600f8ada52..68c6d0c5a6d1 100644
--- a/drivers/gpio/gpio-pch.c
+++ b/drivers/gpio/gpio-pch.c
@@ -337,9 +337,10 @@ static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
337{ 337{
338 struct irq_chip_generic *gc; 338 struct irq_chip_generic *gc;
339 struct irq_chip_type *ct; 339 struct irq_chip_type *ct;
340 int rv;
340 341
341 gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base, 342 gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
342 handle_simple_irq); 343 chip->base, handle_simple_irq);
343 if (!gc) 344 if (!gc)
344 return -ENOMEM; 345 return -ENOMEM;
345 346
@@ -351,10 +352,11 @@ static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
351 ct->chip.irq_unmask = pch_irq_unmask; 352 ct->chip.irq_unmask = pch_irq_unmask;
352 ct->chip.irq_set_type = pch_irq_type; 353 ct->chip.irq_set_type = pch_irq_type;
353 354
354 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, 355 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
355 IRQ_NOREQUEST | IRQ_NOPROBE, 0); 356 IRQ_GC_INIT_MASK_CACHE,
357 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
356 358
357 return 0; 359 return rv;
358} 360}
359 361
360static int pch_gpio_probe(struct pci_dev *pdev, 362static int pch_gpio_probe(struct pci_dev *pdev,
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index 3d3d6b6645a7..6aaaab79c205 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -405,7 +405,7 @@ static const struct dev_pm_ops pl061_dev_pm_ops = {
405}; 405};
406#endif 406#endif
407 407
408static struct amba_id pl061_ids[] = { 408static const struct amba_id pl061_ids[] = {
409 { 409 {
410 .id = 0x00041061, 410 .id = 0x00041061,
411 .mask = 0x000fffff, 411 .mask = 0x000fffff,
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 832f3e46ba9f..6029899789f3 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -451,7 +451,9 @@ static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
451 for_each_set_bit(n, &gedr, BITS_PER_LONG) { 451 for_each_set_bit(n, &gedr, BITS_PER_LONG) {
452 loop = 1; 452 loop = 1;
453 453
454 generic_handle_irq(gpio_to_irq(gpio + n)); 454 generic_handle_irq(
455 irq_find_mapping(pchip->irqdomain,
456 gpio + n));
455 } 457 }
456 } 458 }
457 handled += loop; 459 handled += loop;
@@ -465,9 +467,9 @@ static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
465 struct pxa_gpio_chip *pchip = d; 467 struct pxa_gpio_chip *pchip = d;
466 468
467 if (in_irq == pchip->irq0) { 469 if (in_irq == pchip->irq0) {
468 generic_handle_irq(gpio_to_irq(0)); 470 generic_handle_irq(irq_find_mapping(pchip->irqdomain, 0));
469 } else if (in_irq == pchip->irq1) { 471 } else if (in_irq == pchip->irq1) {
470 generic_handle_irq(gpio_to_irq(1)); 472 generic_handle_irq(irq_find_mapping(pchip->irqdomain, 1));
471 } else { 473 } else {
472 pr_err("%s() unknown irq %d\n", __func__, in_irq); 474 pr_err("%s() unknown irq %d\n", __func__, in_irq);
473 return IRQ_NONE; 475 return IRQ_NONE;
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 4a1536a050bc..1f0871553fd2 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -371,6 +371,16 @@ static const struct of_device_id gpio_rcar_of_table[] = {
371 /* Gen3 GPIO is identical to Gen2. */ 371 /* Gen3 GPIO is identical to Gen2. */
372 .data = &gpio_rcar_info_gen2, 372 .data = &gpio_rcar_info_gen2,
373 }, { 373 }, {
374 .compatible = "renesas,rcar-gen1-gpio",
375 .data = &gpio_rcar_info_gen1,
376 }, {
377 .compatible = "renesas,rcar-gen2-gpio",
378 .data = &gpio_rcar_info_gen2,
379 }, {
380 .compatible = "renesas,rcar-gen3-gpio",
381 /* Gen3 GPIO is identical to Gen2. */
382 .data = &gpio_rcar_info_gen2,
383 }, {
374 .compatible = "renesas,gpio-rcar", 384 .compatible = "renesas,gpio-rcar",
375 .data = &gpio_rcar_info_gen1, 385 .data = &gpio_rcar_info_gen1,
376 }, { 386 }, {
diff --git a/drivers/gpio/gpio-sta2x11.c b/drivers/gpio/gpio-sta2x11.c
index 9e705162da8d..407359da08f9 100644
--- a/drivers/gpio/gpio-sta2x11.c
+++ b/drivers/gpio/gpio-sta2x11.c
@@ -324,9 +324,11 @@ static int gsta_alloc_irq_chip(struct gsta_gpio *chip)
324{ 324{
325 struct irq_chip_generic *gc; 325 struct irq_chip_generic *gc;
326 struct irq_chip_type *ct; 326 struct irq_chip_type *ct;
327 int rv;
327 328
328 gc = irq_alloc_generic_chip(KBUILD_MODNAME, 1, chip->irq_base, 329 gc = devm_irq_alloc_generic_chip(chip->dev, KBUILD_MODNAME, 1,
329 chip->reg_base, handle_simple_irq); 330 chip->irq_base,
331 chip->reg_base, handle_simple_irq);
330 if (!gc) 332 if (!gc)
331 return -ENOMEM; 333 return -ENOMEM;
332 334
@@ -338,8 +340,11 @@ static int gsta_alloc_irq_chip(struct gsta_gpio *chip)
338 ct->chip.irq_enable = gsta_irq_enable; 340 ct->chip.irq_enable = gsta_irq_enable;
339 341
340 /* FIXME: this makes at most 32 interrupts. Request 0 by now */ 342 /* FIXME: this makes at most 32 interrupts. Request 0 by now */
341 irq_setup_generic_chip(gc, 0 /* IRQ_MSK(GSTA_GPIO_PER_BLOCK) */, 0, 343 rv = devm_irq_setup_generic_chip(chip->dev, gc,
342 IRQ_NOREQUEST | IRQ_NOPROBE, 0); 344 0 /* IRQ_MSK(GSTA_GPIO_PER_BLOCK) */,
345 0, IRQ_NOREQUEST | IRQ_NOPROBE, 0);
346 if (rv)
347 return rv;
343 348
344 /* Set up all all 128 interrupts: code from setup_generic_chip */ 349 /* Set up all all 128 interrupts: code from setup_generic_chip */
345 { 350 {
@@ -432,6 +437,7 @@ static int gsta_probe(struct platform_device *dev)
432static struct platform_driver sta2x11_gpio_platform_driver = { 437static struct platform_driver sta2x11_gpio_platform_driver = {
433 .driver = { 438 .driver = {
434 .name = "sta2x11-gpio", 439 .name = "sta2x11-gpio",
440 .suppress_bind_attrs = true,
435 }, 441 },
436 .probe = gsta_probe, 442 .probe = gsta_probe,
437}; 443};
diff --git a/drivers/gpio/gpio-tb10x.c b/drivers/gpio/gpio-tb10x.c
index 80b6959ae995..091ffaaec635 100644
--- a/drivers/gpio/gpio-tb10x.c
+++ b/drivers/gpio/gpio-tb10x.c
@@ -191,7 +191,8 @@ static int tb10x_gpio_probe(struct platform_device *pdev)
191 if (IS_ERR(tb10x_gpio->base)) 191 if (IS_ERR(tb10x_gpio->base))
192 return PTR_ERR(tb10x_gpio->base); 192 return PTR_ERR(tb10x_gpio->base);
193 193
194 tb10x_gpio->gc.label = of_node_full_name(dn); 194 tb10x_gpio->gc.label =
195 devm_kasprintf(&pdev->dev, GFP_KERNEL, "%pOF", pdev->dev.of_node);
195 tb10x_gpio->gc.parent = &pdev->dev; 196 tb10x_gpio->gc.parent = &pdev->dev;
196 tb10x_gpio->gc.owner = THIS_MODULE; 197 tb10x_gpio->gc.owner = THIS_MODULE;
197 tb10x_gpio->gc.direction_input = tb10x_gpio_direction_in; 198 tb10x_gpio->gc.direction_input = tb10x_gpio_direction_in;
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 506c6a67c5fc..fbaf974277df 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -67,8 +67,8 @@
67struct tegra_gpio_info; 67struct tegra_gpio_info;
68 68
69struct tegra_gpio_bank { 69struct tegra_gpio_bank {
70 int bank; 70 unsigned int bank;
71 int irq; 71 unsigned int irq;
72 spinlock_t lvl_lock[4]; 72 spinlock_t lvl_lock[4];
73 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */ 73 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
74#ifdef CONFIG_PM_SLEEP 74#ifdef CONFIG_PM_SLEEP
@@ -112,13 +112,14 @@ static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
112 return __raw_readl(tgi->regs + reg); 112 return __raw_readl(tgi->regs + reg);
113} 113}
114 114
115static int tegra_gpio_compose(int bank, int port, int bit) 115static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
116 unsigned int bit)
116{ 117{
117 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); 118 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
118} 119}
119 120
120static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg, 121static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
121 int gpio, int value) 122 unsigned int gpio, u32 value)
122{ 123{
123 u32 val; 124 u32 val;
124 125
@@ -128,22 +129,22 @@ static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
128 tegra_gpio_writel(tgi, val, reg); 129 tegra_gpio_writel(tgi, val, reg);
129} 130}
130 131
131static void tegra_gpio_enable(struct tegra_gpio_info *tgi, int gpio) 132static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
132{ 133{
133 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1); 134 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
134} 135}
135 136
136static void tegra_gpio_disable(struct tegra_gpio_info *tgi, int gpio) 137static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
137{ 138{
138 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0); 139 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
139} 140}
140 141
141static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset) 142static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
142{ 143{
143 return pinctrl_request_gpio(offset); 144 return pinctrl_request_gpio(offset);
144} 145}
145 146
146static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset) 147static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
147{ 148{
148 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 149 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
149 150
@@ -151,17 +152,18 @@ static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
151 tegra_gpio_disable(tgi, offset); 152 tegra_gpio_disable(tgi, offset);
152} 153}
153 154
154static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 155static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
156 int value)
155{ 157{
156 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 158 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
157 159
158 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value); 160 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
159} 161}
160 162
161static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) 163static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
162{ 164{
163 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 165 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
164 int bval = BIT(GPIO_BIT(offset)); 166 unsigned int bval = BIT(GPIO_BIT(offset));
165 167
166 /* If gpio is in output mode then read from the out value */ 168 /* If gpio is in output mode then read from the out value */
167 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval) 169 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
@@ -170,7 +172,8 @@ static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
170 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval); 172 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
171} 173}
172 174
173static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 175static int tegra_gpio_direction_input(struct gpio_chip *chip,
176 unsigned int offset)
174{ 177{
175 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 178 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
176 179
@@ -179,8 +182,9 @@ static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
179 return 0; 182 return 0;
180} 183}
181 184
182static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 185static int tegra_gpio_direction_output(struct gpio_chip *chip,
183 int value) 186 unsigned int offset,
187 int value)
184{ 188{
185 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 189 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
186 190
@@ -190,7 +194,8 @@ static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
190 return 0; 194 return 0;
191} 195}
192 196
193static int tegra_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 197static int tegra_gpio_get_direction(struct gpio_chip *chip,
198 unsigned int offset)
194{ 199{
195 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 200 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
196 u32 pin_mask = BIT(GPIO_BIT(offset)); 201 u32 pin_mask = BIT(GPIO_BIT(offset));
@@ -212,7 +217,7 @@ static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
212 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; 217 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
213 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000); 218 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
214 unsigned long flags; 219 unsigned long flags;
215 int port; 220 unsigned int port;
216 221
217 if (!debounce_ms) { 222 if (!debounce_ms) {
218 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), 223 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
@@ -250,7 +255,7 @@ static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
250 return tegra_gpio_set_debounce(chip, offset, debounce); 255 return tegra_gpio_set_debounce(chip, offset, debounce);
251} 256}
252 257
253static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 258static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
254{ 259{
255 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 260 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
256 261
@@ -261,7 +266,7 @@ static void tegra_gpio_irq_ack(struct irq_data *d)
261{ 266{
262 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 267 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
263 struct tegra_gpio_info *tgi = bank->tgi; 268 struct tegra_gpio_info *tgi = bank->tgi;
264 int gpio = d->hwirq; 269 unsigned int gpio = d->hwirq;
265 270
266 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio)); 271 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
267} 272}
@@ -270,7 +275,7 @@ static void tegra_gpio_irq_mask(struct irq_data *d)
270{ 275{
271 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 276 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
272 struct tegra_gpio_info *tgi = bank->tgi; 277 struct tegra_gpio_info *tgi = bank->tgi;
273 int gpio = d->hwirq; 278 unsigned int gpio = d->hwirq;
274 279
275 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0); 280 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
276} 281}
@@ -279,20 +284,18 @@ static void tegra_gpio_irq_unmask(struct irq_data *d)
279{ 284{
280 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 285 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
281 struct tegra_gpio_info *tgi = bank->tgi; 286 struct tegra_gpio_info *tgi = bank->tgi;
282 int gpio = d->hwirq; 287 unsigned int gpio = d->hwirq;
283 288
284 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1); 289 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
285} 290}
286 291
287static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) 292static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
288{ 293{
289 int gpio = d->hwirq; 294 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
290 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 295 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
291 struct tegra_gpio_info *tgi = bank->tgi; 296 struct tegra_gpio_info *tgi = bank->tgi;
292 int port = GPIO_PORT(gpio);
293 int lvl_type;
294 int val;
295 unsigned long flags; 297 unsigned long flags;
298 u32 val;
296 int ret; 299 int ret;
297 300
298 switch (type & IRQ_TYPE_SENSE_MASK) { 301 switch (type & IRQ_TYPE_SENSE_MASK) {
@@ -323,7 +326,7 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
323 ret = gpiochip_lock_as_irq(&tgi->gc, gpio); 326 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
324 if (ret) { 327 if (ret) {
325 dev_err(tgi->dev, 328 dev_err(tgi->dev,
326 "unable to lock Tegra GPIO %d as IRQ\n", gpio); 329 "unable to lock Tegra GPIO %u as IRQ\n", gpio);
327 return ret; 330 return ret;
328 } 331 }
329 332
@@ -351,17 +354,15 @@ static void tegra_gpio_irq_shutdown(struct irq_data *d)
351{ 354{
352 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 355 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
353 struct tegra_gpio_info *tgi = bank->tgi; 356 struct tegra_gpio_info *tgi = bank->tgi;
354 int gpio = d->hwirq; 357 unsigned int gpio = d->hwirq;
355 358
356 gpiochip_unlock_as_irq(&tgi->gc, gpio); 359 gpiochip_unlock_as_irq(&tgi->gc, gpio);
357} 360}
358 361
359static void tegra_gpio_irq_handler(struct irq_desc *desc) 362static void tegra_gpio_irq_handler(struct irq_desc *desc)
360{ 363{
361 int port; 364 unsigned int port, pin, gpio;
362 int pin;
363 bool unmasked = false; 365 bool unmasked = false;
364 int gpio;
365 u32 lvl; 366 u32 lvl;
366 unsigned long sta; 367 unsigned long sta;
367 struct irq_chip *chip = irq_desc_get_chip(desc); 368 struct irq_chip *chip = irq_desc_get_chip(desc);
@@ -389,7 +390,8 @@ static void tegra_gpio_irq_handler(struct irq_desc *desc)
389 chained_irq_exit(chip, desc); 390 chained_irq_exit(chip, desc);
390 } 391 }
391 392
392 generic_handle_irq(gpio_to_irq(gpio + pin)); 393 generic_handle_irq(irq_find_mapping(tgi->irq_domain,
394 gpio + pin));
393 } 395 }
394 } 396 }
395 397
@@ -404,8 +406,7 @@ static int tegra_gpio_resume(struct device *dev)
404 struct platform_device *pdev = to_platform_device(dev); 406 struct platform_device *pdev = to_platform_device(dev);
405 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev); 407 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
406 unsigned long flags; 408 unsigned long flags;
407 int b; 409 unsigned int b, p;
408 int p;
409 410
410 local_irq_save(flags); 411 local_irq_save(flags);
411 412
@@ -413,7 +414,8 @@ static int tegra_gpio_resume(struct device *dev)
413 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; 414 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
414 415
415 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 416 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
416 unsigned int gpio = (b<<5) | (p<<3); 417 unsigned int gpio = (b << 5) | (p << 3);
418
417 tegra_gpio_writel(tgi, bank->cnf[p], 419 tegra_gpio_writel(tgi, bank->cnf[p],
418 GPIO_CNF(tgi, gpio)); 420 GPIO_CNF(tgi, gpio));
419 421
@@ -444,15 +446,15 @@ static int tegra_gpio_suspend(struct device *dev)
444 struct platform_device *pdev = to_platform_device(dev); 446 struct platform_device *pdev = to_platform_device(dev);
445 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev); 447 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
446 unsigned long flags; 448 unsigned long flags;
447 int b; 449 unsigned int b, p;
448 int p;
449 450
450 local_irq_save(flags); 451 local_irq_save(flags);
451 for (b = 0; b < tgi->bank_count; b++) { 452 for (b = 0; b < tgi->bank_count; b++) {
452 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; 453 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
453 454
454 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 455 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
455 unsigned int gpio = (b<<5) | (p<<3); 456 unsigned int gpio = (b << 5) | (p << 3);
457
456 bank->cnf[p] = tegra_gpio_readl(tgi, 458 bank->cnf[p] = tegra_gpio_readl(tgi,
457 GPIO_CNF(tgi, gpio)); 459 GPIO_CNF(tgi, gpio));
458 bank->out[p] = tegra_gpio_readl(tgi, 460 bank->out[p] = tegra_gpio_readl(tgi,
@@ -483,7 +485,7 @@ static int tegra_gpio_suspend(struct device *dev)
483static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) 485static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
484{ 486{
485 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 487 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
486 int gpio = d->hwirq; 488 unsigned int gpio = d->hwirq;
487 u32 port, bit, mask; 489 u32 port, bit, mask;
488 490
489 port = GPIO_PORT(gpio); 491 port = GPIO_PORT(gpio);
@@ -507,14 +509,14 @@ static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
507static int dbg_gpio_show(struct seq_file *s, void *unused) 509static int dbg_gpio_show(struct seq_file *s, void *unused)
508{ 510{
509 struct tegra_gpio_info *tgi = s->private; 511 struct tegra_gpio_info *tgi = s->private;
510 int i; 512 unsigned int i, j;
511 int j;
512 513
513 for (i = 0; i < tgi->bank_count; i++) { 514 for (i = 0; i < tgi->bank_count; i++) {
514 for (j = 0; j < 4; j++) { 515 for (j = 0; j < 4; j++) {
515 int gpio = tegra_gpio_compose(i, j, 0); 516 unsigned int gpio = tegra_gpio_compose(i, j, 0);
517
516 seq_printf(s, 518 seq_printf(s,
517 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", 519 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
518 i, j, 520 i, j,
519 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)), 521 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
520 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)), 522 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
@@ -542,7 +544,7 @@ static const struct file_operations debug_fops = {
542 544
543static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) 545static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
544{ 546{
545 (void) debugfs_create_file("tegra_gpio", S_IRUGO, 547 (void) debugfs_create_file("tegra_gpio", 0444,
546 NULL, tgi, &debug_fops); 548 NULL, tgi, &debug_fops);
547} 549}
548 550
@@ -566,35 +568,25 @@ static struct lock_class_key gpio_lock_class;
566 568
567static int tegra_gpio_probe(struct platform_device *pdev) 569static int tegra_gpio_probe(struct platform_device *pdev)
568{ 570{
569 const struct tegra_gpio_soc_config *config;
570 struct tegra_gpio_info *tgi; 571 struct tegra_gpio_info *tgi;
571 struct resource *res; 572 struct resource *res;
572 struct tegra_gpio_bank *bank; 573 struct tegra_gpio_bank *bank;
574 unsigned int gpio, i, j;
573 int ret; 575 int ret;
574 int gpio;
575 int i;
576 int j;
577
578 config = of_device_get_match_data(&pdev->dev);
579 if (!config) {
580 dev_err(&pdev->dev, "Error: No device match found\n");
581 return -ENODEV;
582 }
583 576
584 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL); 577 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
585 if (!tgi) 578 if (!tgi)
586 return -ENODEV; 579 return -ENODEV;
587 580
588 tgi->soc = config; 581 tgi->soc = of_device_get_match_data(&pdev->dev);
589 tgi->dev = &pdev->dev; 582 tgi->dev = &pdev->dev;
590 583
591 for (;;) { 584 ret = platform_irq_count(pdev);
592 res = platform_get_resource(pdev, IORESOURCE_IRQ, 585 if (ret < 0)
593 tgi->bank_count); 586 return ret;
594 if (!res) 587
595 break; 588 tgi->bank_count = ret;
596 tgi->bank_count++; 589
597 }
598 if (!tgi->bank_count) { 590 if (!tgi->bank_count) {
599 dev_err(&pdev->dev, "Missing IRQ resource\n"); 591 dev_err(&pdev->dev, "Missing IRQ resource\n");
600 return -ENODEV; 592 return -ENODEV;
@@ -626,13 +618,13 @@ static int tegra_gpio_probe(struct platform_device *pdev)
626 618
627 platform_set_drvdata(pdev, tgi); 619 platform_set_drvdata(pdev, tgi);
628 620
629 if (config->debounce_supported) 621 if (tgi->soc->debounce_supported)
630 tgi->gc.set_config = tegra_gpio_set_config; 622 tgi->gc.set_config = tegra_gpio_set_config;
631 623
632 tgi->bank_info = devm_kzalloc(&pdev->dev, tgi->bank_count * 624 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
633 sizeof(*tgi->bank_info), GFP_KERNEL); 625 sizeof(*tgi->bank_info), GFP_KERNEL);
634 if (!tgi->bank_info) 626 if (!tgi->bank_info)
635 return -ENODEV; 627 return -ENOMEM;
636 628
637 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node, 629 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
638 tgi->gc.ngpio, 630 tgi->gc.ngpio,
@@ -641,15 +633,15 @@ static int tegra_gpio_probe(struct platform_device *pdev)
641 return -ENODEV; 633 return -ENODEV;
642 634
643 for (i = 0; i < tgi->bank_count; i++) { 635 for (i = 0; i < tgi->bank_count; i++) {
644 res = platform_get_resource(pdev, IORESOURCE_IRQ, i); 636 ret = platform_get_irq(pdev, i);
645 if (!res) { 637 if (ret < 0) {
646 dev_err(&pdev->dev, "Missing IRQ resource\n"); 638 dev_err(&pdev->dev, "Missing IRQ resource: %d\n", ret);
647 return -ENODEV; 639 return ret;
648 } 640 }
649 641
650 bank = &tgi->bank_info[i]; 642 bank = &tgi->bank_info[i];
651 bank->bank = i; 643 bank->bank = i;
652 bank->irq = res->start; 644 bank->irq = ret;
653 bank->tgi = tgi; 645 bank->tgi = tgi;
654 } 646 }
655 647
@@ -661,6 +653,7 @@ static int tegra_gpio_probe(struct platform_device *pdev)
661 for (i = 0; i < tgi->bank_count; i++) { 653 for (i = 0; i < tgi->bank_count; i++) {
662 for (j = 0; j < 4; j++) { 654 for (j = 0; j < 4; j++) {
663 int gpio = tegra_gpio_compose(i, j, 0); 655 int gpio = tegra_gpio_compose(i, j, 0);
656
664 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio)); 657 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
665 } 658 }
666 } 659 }
diff --git a/drivers/gpio/gpio-thunderx.c b/drivers/gpio/gpio-thunderx.c
new file mode 100644
index 000000000000..57efb251f9c4
--- /dev/null
+++ b/drivers/gpio/gpio-thunderx.c
@@ -0,0 +1,639 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2016, 2017 Cavium Inc.
7 */
8
9#include <linux/bitops.h>
10#include <linux/gpio/driver.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/irq.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/pci.h>
17#include <linux/spinlock.h>
18
19
20#define GPIO_RX_DAT 0x0
21#define GPIO_TX_SET 0x8
22#define GPIO_TX_CLR 0x10
23#define GPIO_CONST 0x90
24#define GPIO_CONST_GPIOS_MASK 0xff
25#define GPIO_BIT_CFG 0x400
26#define GPIO_BIT_CFG_TX_OE BIT(0)
27#define GPIO_BIT_CFG_PIN_XOR BIT(1)
28#define GPIO_BIT_CFG_INT_EN BIT(2)
29#define GPIO_BIT_CFG_INT_TYPE BIT(3)
30#define GPIO_BIT_CFG_FIL_MASK GENMASK(11, 4)
31#define GPIO_BIT_CFG_FIL_CNT_SHIFT 4
32#define GPIO_BIT_CFG_FIL_SEL_SHIFT 8
33#define GPIO_BIT_CFG_TX_OD BIT(12)
34#define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(25, 16)
35#define GPIO_INTR 0x800
36#define GPIO_INTR_INTR BIT(0)
37#define GPIO_INTR_INTR_W1S BIT(1)
38#define GPIO_INTR_ENA_W1C BIT(2)
39#define GPIO_INTR_ENA_W1S BIT(3)
40#define GPIO_2ND_BANK 0x1400
41
42#define GLITCH_FILTER_400NS ((4u << GPIO_BIT_CFG_FIL_SEL_SHIFT) | \
43 (9u << GPIO_BIT_CFG_FIL_CNT_SHIFT))
44
45struct thunderx_gpio;
46
47struct thunderx_line {
48 struct thunderx_gpio *txgpio;
49 unsigned int line;
50 unsigned int fil_bits;
51};
52
53struct thunderx_gpio {
54 struct gpio_chip chip;
55 u8 __iomem *register_base;
56 struct irq_domain *irqd;
57 struct msix_entry *msix_entries; /* per line MSI-X */
58 struct thunderx_line *line_entries; /* per line irq info */
59 raw_spinlock_t lock;
60 unsigned long invert_mask[2];
61 unsigned long od_mask[2];
62 int base_msi;
63};
64
65static unsigned int bit_cfg_reg(unsigned int line)
66{
67 return 8 * line + GPIO_BIT_CFG;
68}
69
70static unsigned int intr_reg(unsigned int line)
71{
72 return 8 * line + GPIO_INTR;
73}
74
75static bool thunderx_gpio_is_gpio_nowarn(struct thunderx_gpio *txgpio,
76 unsigned int line)
77{
78 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
79
80 return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0;
81}
82
83/*
84 * Check (and WARN) that the pin is available for GPIO. We will not
85 * allow modification of the state of non-GPIO pins from this driver.
86 */
87static bool thunderx_gpio_is_gpio(struct thunderx_gpio *txgpio,
88 unsigned int line)
89{
90 bool rv = thunderx_gpio_is_gpio_nowarn(txgpio, line);
91
92 WARN_RATELIMIT(!rv, "Pin %d not available for GPIO\n", line);
93
94 return rv;
95}
96
97static int thunderx_gpio_request(struct gpio_chip *chip, unsigned int line)
98{
99 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
100
101 return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO;
102}
103
104static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line)
105{
106 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
107
108 if (!thunderx_gpio_is_gpio(txgpio, line))
109 return -EIO;
110
111 raw_spin_lock(&txgpio->lock);
112 clear_bit(line, txgpio->invert_mask);
113 clear_bit(line, txgpio->od_mask);
114 writeq(txgpio->line_entries[line].fil_bits,
115 txgpio->register_base + bit_cfg_reg(line));
116 raw_spin_unlock(&txgpio->lock);
117 return 0;
118}
119
120static void thunderx_gpio_set(struct gpio_chip *chip, unsigned int line,
121 int value)
122{
123 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
124 int bank = line / 64;
125 int bank_bit = line % 64;
126
127 void __iomem *reg = txgpio->register_base +
128 (bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR);
129
130 writeq(BIT_ULL(bank_bit), reg);
131}
132
133static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line,
134 int value)
135{
136 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
137 u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE;
138
139 if (!thunderx_gpio_is_gpio(txgpio, line))
140 return -EIO;
141
142 raw_spin_lock(&txgpio->lock);
143
144 thunderx_gpio_set(chip, line, value);
145
146 if (test_bit(line, txgpio->invert_mask))
147 bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
148
149 if (test_bit(line, txgpio->od_mask))
150 bit_cfg |= GPIO_BIT_CFG_TX_OD;
151
152 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
153
154 raw_spin_unlock(&txgpio->lock);
155 return 0;
156}
157
158static int thunderx_gpio_get_direction(struct gpio_chip *chip, unsigned int line)
159{
160 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
161 u64 bit_cfg;
162
163 if (!thunderx_gpio_is_gpio_nowarn(txgpio, line))
164 /*
165 * Say it is input for now to avoid WARNing on
166 * gpiochip_add_data(). We will WARN if someone
167 * requests it or tries to use it.
168 */
169 return 1;
170
171 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
172
173 return !(bit_cfg & GPIO_BIT_CFG_TX_OE);
174}
175
176static int thunderx_gpio_set_config(struct gpio_chip *chip,
177 unsigned int line,
178 unsigned long cfg)
179{
180 bool orig_invert, orig_od, orig_dat, new_invert, new_od;
181 u32 arg, sel;
182 u64 bit_cfg;
183 int bank = line / 64;
184 int bank_bit = line % 64;
185 int ret = -ENOTSUPP;
186 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
187 void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET;
188
189 if (!thunderx_gpio_is_gpio(txgpio, line))
190 return -EIO;
191
192 raw_spin_lock(&txgpio->lock);
193 orig_invert = test_bit(line, txgpio->invert_mask);
194 new_invert = orig_invert;
195 orig_od = test_bit(line, txgpio->od_mask);
196 new_od = orig_od;
197 orig_dat = ((readq(reg) >> bank_bit) & 1) ^ orig_invert;
198 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
199 switch (pinconf_to_config_param(cfg)) {
200 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
201 /*
202 * Weird, setting open-drain mode causes signal
203 * inversion. Note this so we can compensate in the
204 * dir_out function.
205 */
206 set_bit(line, txgpio->invert_mask);
207 new_invert = true;
208 set_bit(line, txgpio->od_mask);
209 new_od = true;
210 ret = 0;
211 break;
212 case PIN_CONFIG_DRIVE_PUSH_PULL:
213 clear_bit(line, txgpio->invert_mask);
214 new_invert = false;
215 clear_bit(line, txgpio->od_mask);
216 new_od = false;
217 ret = 0;
218 break;
219 case PIN_CONFIG_INPUT_DEBOUNCE:
220 arg = pinconf_to_config_argument(cfg);
221 if (arg > 1228) { /* 15 * 2^15 * 2.5nS maximum */
222 ret = -EINVAL;
223 break;
224 }
225 arg *= 400; /* scale to 2.5nS clocks. */
226 sel = 0;
227 while (arg > 15) {
228 sel++;
229 arg++; /* always round up */
230 arg >>= 1;
231 }
232 txgpio->line_entries[line].fil_bits =
233 (sel << GPIO_BIT_CFG_FIL_SEL_SHIFT) |
234 (arg << GPIO_BIT_CFG_FIL_CNT_SHIFT);
235 bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK;
236 bit_cfg |= txgpio->line_entries[line].fil_bits;
237 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
238 ret = 0;
239 break;
240 default:
241 break;
242 }
243 raw_spin_unlock(&txgpio->lock);
244
245 /*
246 * If currently output and OPEN_DRAIN changed, install the new
247 * settings
248 */
249 if ((new_invert != orig_invert || new_od != orig_od) &&
250 (bit_cfg & GPIO_BIT_CFG_TX_OE))
251 ret = thunderx_gpio_dir_out(chip, line, orig_dat ^ new_invert);
252
253 return ret;
254}
255
256static int thunderx_gpio_get(struct gpio_chip *chip, unsigned int line)
257{
258 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
259 int bank = line / 64;
260 int bank_bit = line % 64;
261 u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT);
262 u64 masked_bits = read_bits & BIT_ULL(bank_bit);
263
264 if (test_bit(line, txgpio->invert_mask))
265 return masked_bits == 0;
266 else
267 return masked_bits != 0;
268}
269
270static void thunderx_gpio_set_multiple(struct gpio_chip *chip,
271 unsigned long *mask,
272 unsigned long *bits)
273{
274 int bank;
275 u64 set_bits, clear_bits;
276 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
277
278 for (bank = 0; bank <= chip->ngpio / 64; bank++) {
279 set_bits = bits[bank] & mask[bank];
280 clear_bits = ~bits[bank] & mask[bank];
281 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);
282 writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);
283 }
284}
285
286static void thunderx_gpio_irq_ack(struct irq_data *data)
287{
288 struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
289
290 writeq(GPIO_INTR_INTR,
291 txline->txgpio->register_base + intr_reg(txline->line));
292}
293
294static void thunderx_gpio_irq_mask(struct irq_data *data)
295{
296 struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
297
298 writeq(GPIO_INTR_ENA_W1C,
299 txline->txgpio->register_base + intr_reg(txline->line));
300}
301
302static void thunderx_gpio_irq_mask_ack(struct irq_data *data)
303{
304 struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
305
306 writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR,
307 txline->txgpio->register_base + intr_reg(txline->line));
308}
309
310static void thunderx_gpio_irq_unmask(struct irq_data *data)
311{
312 struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
313
314 writeq(GPIO_INTR_ENA_W1S,
315 txline->txgpio->register_base + intr_reg(txline->line));
316}
317
318static int thunderx_gpio_irq_set_type(struct irq_data *data,
319 unsigned int flow_type)
320{
321 struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
322 struct thunderx_gpio *txgpio = txline->txgpio;
323 u64 bit_cfg;
324
325 irqd_set_trigger_type(data, flow_type);
326
327 bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN;
328
329 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
330 irq_set_handler_locked(data, handle_fasteoi_ack_irq);
331 bit_cfg |= GPIO_BIT_CFG_INT_TYPE;
332 } else {
333 irq_set_handler_locked(data, handle_fasteoi_mask_irq);
334 }
335
336 raw_spin_lock(&txgpio->lock);
337 if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) {
338 bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
339 set_bit(txline->line, txgpio->invert_mask);
340 } else {
341 clear_bit(txline->line, txgpio->invert_mask);
342 }
343 clear_bit(txline->line, txgpio->od_mask);
344 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));
345 raw_spin_unlock(&txgpio->lock);
346
347 return IRQ_SET_MASK_OK;
348}
349
350static void thunderx_gpio_irq_enable(struct irq_data *data)
351{
352 irq_chip_enable_parent(data);
353 thunderx_gpio_irq_unmask(data);
354}
355
356static void thunderx_gpio_irq_disable(struct irq_data *data)
357{
358 thunderx_gpio_irq_mask(data);
359 irq_chip_disable_parent(data);
360}
361
362static int thunderx_gpio_irq_request_resources(struct irq_data *data)
363{
364 struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
365 struct thunderx_gpio *txgpio = txline->txgpio;
366 struct irq_data *parent_data = data->parent_data;
367 int r;
368
369 r = gpiochip_lock_as_irq(&txgpio->chip, txline->line);
370 if (r)
371 return r;
372
373 if (parent_data && parent_data->chip->irq_request_resources) {
374 r = parent_data->chip->irq_request_resources(parent_data);
375 if (r)
376 goto error;
377 }
378
379 return 0;
380error:
381 gpiochip_unlock_as_irq(&txgpio->chip, txline->line);
382 return r;
383}
384
385static void thunderx_gpio_irq_release_resources(struct irq_data *data)
386{
387 struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
388 struct thunderx_gpio *txgpio = txline->txgpio;
389 struct irq_data *parent_data = data->parent_data;
390
391 if (parent_data && parent_data->chip->irq_release_resources)
392 parent_data->chip->irq_release_resources(parent_data);
393
394 gpiochip_unlock_as_irq(&txgpio->chip, txline->line);
395}
396
397/*
398 * Interrupts are chained from underlying MSI-X vectors. We have
399 * these irq_chip functions to be able to handle level triggering
400 * semantics and other acknowledgment tasks associated with the GPIO
401 * mechanism.
402 */
403static struct irq_chip thunderx_gpio_irq_chip = {
404 .name = "GPIO",
405 .irq_enable = thunderx_gpio_irq_enable,
406 .irq_disable = thunderx_gpio_irq_disable,
407 .irq_ack = thunderx_gpio_irq_ack,
408 .irq_mask = thunderx_gpio_irq_mask,
409 .irq_mask_ack = thunderx_gpio_irq_mask_ack,
410 .irq_unmask = thunderx_gpio_irq_unmask,
411 .irq_eoi = irq_chip_eoi_parent,
412 .irq_set_affinity = irq_chip_set_affinity_parent,
413 .irq_request_resources = thunderx_gpio_irq_request_resources,
414 .irq_release_resources = thunderx_gpio_irq_release_resources,
415 .irq_set_type = thunderx_gpio_irq_set_type,
416
417 .flags = IRQCHIP_SET_TYPE_MASKED
418};
419
420static int thunderx_gpio_irq_map(struct irq_domain *d, unsigned int irq,
421 irq_hw_number_t hwirq)
422{
423 struct thunderx_gpio *txgpio = d->host_data;
424
425 if (hwirq >= txgpio->chip.ngpio)
426 return -EINVAL;
427 if (!thunderx_gpio_is_gpio_nowarn(txgpio, hwirq))
428 return -EPERM;
429 return 0;
430}
431
432static int thunderx_gpio_irq_translate(struct irq_domain *d,
433 struct irq_fwspec *fwspec,
434 irq_hw_number_t *hwirq,
435 unsigned int *type)
436{
437 struct thunderx_gpio *txgpio = d->host_data;
438
439 if (WARN_ON(fwspec->param_count < 2))
440 return -EINVAL;
441 if (fwspec->param[0] >= txgpio->chip.ngpio)
442 return -EINVAL;
443 *hwirq = fwspec->param[0];
444 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
445 return 0;
446}
447
448static int thunderx_gpio_irq_alloc(struct irq_domain *d, unsigned int virq,
449 unsigned int nr_irqs, void *arg)
450{
451 struct thunderx_line *txline = arg;
452
453 return irq_domain_set_hwirq_and_chip(d, virq, txline->line,
454 &thunderx_gpio_irq_chip, txline);
455}
456
457static const struct irq_domain_ops thunderx_gpio_irqd_ops = {
458 .map = thunderx_gpio_irq_map,
459 .alloc = thunderx_gpio_irq_alloc,
460 .translate = thunderx_gpio_irq_translate
461};
462
463static int thunderx_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
464{
465 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
466
467 return irq_find_mapping(txgpio->irqd, offset);
468}
469
470static int thunderx_gpio_probe(struct pci_dev *pdev,
471 const struct pci_device_id *id)
472{
473 void __iomem * const *tbl;
474 struct device *dev = &pdev->dev;
475 struct thunderx_gpio *txgpio;
476 struct gpio_chip *chip;
477 int ngpio, i;
478 int err = 0;
479
480 txgpio = devm_kzalloc(dev, sizeof(*txgpio), GFP_KERNEL);
481 if (!txgpio)
482 return -ENOMEM;
483
484 raw_spin_lock_init(&txgpio->lock);
485 chip = &txgpio->chip;
486
487 pci_set_drvdata(pdev, txgpio);
488
489 err = pcim_enable_device(pdev);
490 if (err) {
491 dev_err(dev, "Failed to enable PCI device: err %d\n", err);
492 goto out;
493 }
494
495 err = pcim_iomap_regions(pdev, 1 << 0, KBUILD_MODNAME);
496 if (err) {
497 dev_err(dev, "Failed to iomap PCI device: err %d\n", err);
498 goto out;
499 }
500
501 tbl = pcim_iomap_table(pdev);
502 txgpio->register_base = tbl[0];
503 if (!txgpio->register_base) {
504 dev_err(dev, "Cannot map PCI resource\n");
505 err = -ENOMEM;
506 goto out;
507 }
508
509 if (pdev->subsystem_device == 0xa10a) {
510 /* CN88XX has no GPIO_CONST register*/
511 ngpio = 50;
512 txgpio->base_msi = 48;
513 } else {
514 u64 c = readq(txgpio->register_base + GPIO_CONST);
515
516 ngpio = c & GPIO_CONST_GPIOS_MASK;
517 txgpio->base_msi = (c >> 8) & 0xff;
518 }
519
520 txgpio->msix_entries = devm_kzalloc(dev,
521 sizeof(struct msix_entry) * ngpio,
522 GFP_KERNEL);
523 if (!txgpio->msix_entries) {
524 err = -ENOMEM;
525 goto out;
526 }
527
528 txgpio->line_entries = devm_kzalloc(dev,
529 sizeof(struct thunderx_line) * ngpio,
530 GFP_KERNEL);
531 if (!txgpio->line_entries) {
532 err = -ENOMEM;
533 goto out;
534 }
535
536 for (i = 0; i < ngpio; i++) {
537 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i));
538
539 txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i);
540 txgpio->line_entries[i].line = i;
541 txgpio->line_entries[i].txgpio = txgpio;
542 /*
543 * If something has already programmed the pin, use
544 * the existing glitch filter settings, otherwise go
545 * to 400nS.
546 */
547 txgpio->line_entries[i].fil_bits = bit_cfg ?
548 (bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS;
549
550 if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD))
551 set_bit(i, txgpio->od_mask);
552 if (bit_cfg & GPIO_BIT_CFG_PIN_XOR)
553 set_bit(i, txgpio->invert_mask);
554 }
555
556
557 /* Enable all MSI-X for interrupts on all possible lines. */
558 err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio);
559 if (err < 0)
560 goto out;
561
562 /*
563 * Push GPIO specific irqdomain on hierarchy created as a side
564 * effect of the pci_enable_msix()
565 */
566 txgpio->irqd = irq_domain_create_hierarchy(irq_get_irq_data(txgpio->msix_entries[0].vector)->domain,
567 0, 0, of_node_to_fwnode(dev->of_node),
568 &thunderx_gpio_irqd_ops, txgpio);
569 if (!txgpio->irqd)
570 goto out;
571
572 /* Push on irq_data and the domain for each line. */
573 for (i = 0; i < ngpio; i++) {
574 err = irq_domain_push_irq(txgpio->irqd,
575 txgpio->msix_entries[i].vector,
576 &txgpio->line_entries[i]);
577 if (err < 0)
578 dev_err(dev, "irq_domain_push_irq: %d\n", err);
579 }
580
581 chip->label = KBUILD_MODNAME;
582 chip->parent = dev;
583 chip->owner = THIS_MODULE;
584 chip->request = thunderx_gpio_request;
585 chip->base = -1; /* System allocated */
586 chip->can_sleep = false;
587 chip->ngpio = ngpio;
588 chip->get_direction = thunderx_gpio_get_direction;
589 chip->direction_input = thunderx_gpio_dir_in;
590 chip->get = thunderx_gpio_get;
591 chip->direction_output = thunderx_gpio_dir_out;
592 chip->set = thunderx_gpio_set;
593 chip->set_multiple = thunderx_gpio_set_multiple;
594 chip->set_config = thunderx_gpio_set_config;
595 chip->to_irq = thunderx_gpio_to_irq;
596 err = devm_gpiochip_add_data(dev, chip, txgpio);
597 if (err)
598 goto out;
599
600 dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n",
601 ngpio, chip->base);
602 return 0;
603out:
604 pci_set_drvdata(pdev, NULL);
605 return err;
606}
607
608static void thunderx_gpio_remove(struct pci_dev *pdev)
609{
610 int i;
611 struct thunderx_gpio *txgpio = pci_get_drvdata(pdev);
612
613 for (i = 0; i < txgpio->chip.ngpio; i++)
614 irq_domain_pop_irq(txgpio->irqd,
615 txgpio->msix_entries[i].vector);
616
617 irq_domain_remove(txgpio->irqd);
618
619 pci_set_drvdata(pdev, NULL);
620}
621
622static const struct pci_device_id thunderx_gpio_id_table[] = {
623 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA00A) },
624 { 0, } /* end of table */
625};
626
627MODULE_DEVICE_TABLE(pci, thunderx_gpio_id_table);
628
629static struct pci_driver thunderx_gpio_driver = {
630 .name = KBUILD_MODNAME,
631 .id_table = thunderx_gpio_id_table,
632 .probe = thunderx_gpio_probe,
633 .remove = thunderx_gpio_remove,
634};
635
636module_pci_driver(thunderx_gpio_driver);
637
638MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver");
639MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-tps68470.c b/drivers/gpio/gpio-tps68470.c
new file mode 100644
index 000000000000..fa2662f8b026
--- /dev/null
+++ b/drivers/gpio/gpio-tps68470.c
@@ -0,0 +1,176 @@
1/*
2 * GPIO driver for TPS68470 PMIC
3 *
4 * Copyright (C) 2017 Intel Corporation
5 *
6 * Authors:
7 * Antti Laakso <antti.laakso@intel.com>
8 * Tianshu Qiu <tian.shu.qiu@intel.com>
9 * Jian Xu Zheng <jian.xu.zheng@intel.com>
10 * Yuning Pu <yuning.pu@intel.com>
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation version 2.
15 *
16 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
17 * kind, whether express or implied; without even the implied warranty
18 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/gpio/driver.h>
23#include <linux/mfd/tps68470.h>
24#include <linux/module.h>
25#include <linux/platform_device.h>
26#include <linux/regmap.h>
27
28#define TPS68470_N_LOGIC_OUTPUT 3
29#define TPS68470_N_REGULAR_GPIO 7
30#define TPS68470_N_GPIO (TPS68470_N_LOGIC_OUTPUT + TPS68470_N_REGULAR_GPIO)
31
32struct tps68470_gpio_data {
33 struct regmap *tps68470_regmap;
34 struct gpio_chip gc;
35};
36
37static int tps68470_gpio_get(struct gpio_chip *gc, unsigned int offset)
38{
39 struct tps68470_gpio_data *tps68470_gpio = gpiochip_get_data(gc);
40 struct regmap *regmap = tps68470_gpio->tps68470_regmap;
41 unsigned int reg = TPS68470_REG_GPDO;
42 int val, ret;
43
44 if (offset >= TPS68470_N_REGULAR_GPIO) {
45 offset -= TPS68470_N_REGULAR_GPIO;
46 reg = TPS68470_REG_SGPO;
47 }
48
49 ret = regmap_read(regmap, reg, &val);
50 if (ret) {
51 dev_err(tps68470_gpio->gc.parent, "reg 0x%x read failed\n",
52 TPS68470_REG_SGPO);
53 return ret;
54 }
55 return !!(val & BIT(offset));
56}
57
58/* Return 0 if output, 1 if input */
59static int tps68470_gpio_get_direction(struct gpio_chip *gc,
60 unsigned int offset)
61{
62 struct tps68470_gpio_data *tps68470_gpio = gpiochip_get_data(gc);
63 struct regmap *regmap = tps68470_gpio->tps68470_regmap;
64 int val, ret;
65
66 /* rest are always outputs */
67 if (offset >= TPS68470_N_REGULAR_GPIO)
68 return 0;
69
70 ret = regmap_read(regmap, TPS68470_GPIO_CTL_REG_A(offset), &val);
71 if (ret) {
72 dev_err(tps68470_gpio->gc.parent, "reg 0x%x read failed\n",
73 TPS68470_GPIO_CTL_REG_A(offset));
74 return ret;
75 }
76
77 val &= TPS68470_GPIO_MODE_MASK;
78 return val >= TPS68470_GPIO_MODE_OUT_CMOS ? 0 : 1;
79}
80
81static void tps68470_gpio_set(struct gpio_chip *gc, unsigned int offset,
82 int value)
83{
84 struct tps68470_gpio_data *tps68470_gpio = gpiochip_get_data(gc);
85 struct regmap *regmap = tps68470_gpio->tps68470_regmap;
86 unsigned int reg = TPS68470_REG_GPDO;
87
88 if (offset >= TPS68470_N_REGULAR_GPIO) {
89 reg = TPS68470_REG_SGPO;
90 offset -= TPS68470_N_REGULAR_GPIO;
91 }
92
93 regmap_update_bits(regmap, reg, BIT(offset), value ? BIT(offset) : 0);
94}
95
96static int tps68470_gpio_output(struct gpio_chip *gc, unsigned int offset,
97 int value)
98{
99 struct tps68470_gpio_data *tps68470_gpio = gpiochip_get_data(gc);
100 struct regmap *regmap = tps68470_gpio->tps68470_regmap;
101
102 /* rest are always outputs */
103 if (offset >= TPS68470_N_REGULAR_GPIO)
104 return 0;
105
106 /* Set the initial value */
107 tps68470_gpio_set(gc, offset, value);
108
109 return regmap_update_bits(regmap, TPS68470_GPIO_CTL_REG_A(offset),
110 TPS68470_GPIO_MODE_MASK,
111 TPS68470_GPIO_MODE_OUT_CMOS);
112}
113
114static int tps68470_gpio_input(struct gpio_chip *gc, unsigned int offset)
115{
116 struct tps68470_gpio_data *tps68470_gpio = gpiochip_get_data(gc);
117 struct regmap *regmap = tps68470_gpio->tps68470_regmap;
118
119 /* rest are always outputs */
120 if (offset >= TPS68470_N_REGULAR_GPIO)
121 return -EINVAL;
122
123 return regmap_update_bits(regmap, TPS68470_GPIO_CTL_REG_A(offset),
124 TPS68470_GPIO_MODE_MASK, 0x00);
125}
126
127static const char *tps68470_names[TPS68470_N_GPIO] = {
128 "gpio.0", "gpio.1", "gpio.2", "gpio.3",
129 "gpio.4", "gpio.5", "gpio.6",
130 "s_enable", "s_idle", "s_resetn",
131};
132
133static int tps68470_gpio_probe(struct platform_device *pdev)
134{
135 struct tps68470_gpio_data *tps68470_gpio;
136 int ret;
137
138 tps68470_gpio = devm_kzalloc(&pdev->dev, sizeof(*tps68470_gpio),
139 GFP_KERNEL);
140 if (!tps68470_gpio)
141 return -ENOMEM;
142
143 tps68470_gpio->tps68470_regmap = dev_get_drvdata(pdev->dev.parent);
144 tps68470_gpio->gc.label = "tps68470-gpio";
145 tps68470_gpio->gc.owner = THIS_MODULE;
146 tps68470_gpio->gc.direction_input = tps68470_gpio_input;
147 tps68470_gpio->gc.direction_output = tps68470_gpio_output;
148 tps68470_gpio->gc.get = tps68470_gpio_get;
149 tps68470_gpio->gc.get_direction = tps68470_gpio_get_direction;
150 tps68470_gpio->gc.set = tps68470_gpio_set;
151 tps68470_gpio->gc.can_sleep = true;
152 tps68470_gpio->gc.names = tps68470_names;
153 tps68470_gpio->gc.ngpio = TPS68470_N_GPIO;
154 tps68470_gpio->gc.base = -1;
155 tps68470_gpio->gc.parent = &pdev->dev;
156
157 ret = devm_gpiochip_add_data(&pdev->dev, &tps68470_gpio->gc,
158 tps68470_gpio);
159 if (ret < 0) {
160 dev_err(&pdev->dev, "Failed to register gpio_chip: %d\n", ret);
161 return ret;
162 }
163
164 platform_set_drvdata(pdev, tps68470_gpio);
165
166 return ret;
167}
168
169static struct platform_driver tps68470_gpio_driver = {
170 .driver = {
171 .name = "tps68470-gpio",
172 },
173 .probe = tps68470_gpio_probe,
174};
175
176builtin_platform_driver(tps68470_gpio_driver)
diff --git a/drivers/gpio/gpio-twl6040.c b/drivers/gpio/gpio-twl6040.c
index b780314cdfc9..dadeacf43e0c 100644
--- a/drivers/gpio/gpio-twl6040.c
+++ b/drivers/gpio/gpio-twl6040.c
@@ -32,8 +32,6 @@
32 32
33#include <linux/mfd/twl6040.h> 33#include <linux/mfd/twl6040.h>
34 34
35static struct gpio_chip twl6040gpo_chip;
36
37static int twl6040gpo_get(struct gpio_chip *chip, unsigned offset) 35static int twl6040gpo_get(struct gpio_chip *chip, unsigned offset)
38{ 36{
39 struct twl6040 *twl6040 = dev_get_drvdata(chip->parent->parent); 37 struct twl6040 *twl6040 = dev_get_drvdata(chip->parent->parent);
diff --git a/drivers/gpio/gpio-tz1090.c b/drivers/gpio/gpio-tz1090.c
index ca958e0f6909..22c5be65051f 100644
--- a/drivers/gpio/gpio-tz1090.c
+++ b/drivers/gpio/gpio-tz1090.c
@@ -527,13 +527,12 @@ static void tz1090_gpio_register_banks(struct tz1090_gpio *priv)
527 527
528 ret = of_property_read_u32(node, "reg", &addr); 528 ret = of_property_read_u32(node, "reg", &addr);
529 if (ret) { 529 if (ret) {
530 dev_err(priv->dev, "invalid reg on %s\n", 530 dev_err(priv->dev, "invalid reg on %pOF\n", node);
531 node->full_name);
532 continue; 531 continue;
533 } 532 }
534 if (addr >= 3) { 533 if (addr >= 3) {
535 dev_err(priv->dev, "index %u in %s out of range\n", 534 dev_err(priv->dev, "index %u in %pOF out of range\n",
536 addr, node->full_name); 535 addr, node);
537 continue; 536 continue;
538 } 537 }
539 538
@@ -543,8 +542,7 @@ static void tz1090_gpio_register_banks(struct tz1090_gpio *priv)
543 542
544 ret = tz1090_gpio_bank_probe(&info); 543 ret = tz1090_gpio_bank_probe(&info);
545 if (ret) { 544 if (ret) {
546 dev_err(priv->dev, "failure registering %s\n", 545 dev_err(priv->dev, "failure registering %pOF\n", node);
547 node->full_name);
548 of_node_put(node); 546 of_node_put(node);
549 continue; 547 continue;
550 } 548 }
diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
index 521fbe338589..cbe9e06861de 100644
--- a/drivers/gpio/gpio-vf610.c
+++ b/drivers/gpio/gpio-vf610.c
@@ -30,10 +30,16 @@
30 30
31#define VF610_GPIO_PER_PORT 32 31#define VF610_GPIO_PER_PORT 32
32 32
33struct fsl_gpio_soc_data {
34 /* SoCs has a Port Data Direction Register (PDDR) */
35 bool have_paddr;
36};
37
33struct vf610_gpio_port { 38struct vf610_gpio_port {
34 struct gpio_chip gc; 39 struct gpio_chip gc;
35 void __iomem *base; 40 void __iomem *base;
36 void __iomem *gpio_base; 41 void __iomem *gpio_base;
42 const struct fsl_gpio_soc_data *sdata;
37 u8 irqc[VF610_GPIO_PER_PORT]; 43 u8 irqc[VF610_GPIO_PER_PORT];
38 int irq; 44 int irq;
39}; 45};
@@ -43,6 +49,7 @@ struct vf610_gpio_port {
43#define GPIO_PCOR 0x08 49#define GPIO_PCOR 0x08
44#define GPIO_PTOR 0x0c 50#define GPIO_PTOR 0x0c
45#define GPIO_PDIR 0x10 51#define GPIO_PDIR 0x10
52#define GPIO_PDDR 0x14
46 53
47#define PORT_PCR(n) ((n) * 0x4) 54#define PORT_PCR(n) ((n) * 0x4)
48#define PORT_PCR_IRQC_OFFSET 16 55#define PORT_PCR_IRQC_OFFSET 16
@@ -61,8 +68,13 @@ struct vf610_gpio_port {
61 68
62static struct irq_chip vf610_gpio_irq_chip; 69static struct irq_chip vf610_gpio_irq_chip;
63 70
71static const struct fsl_gpio_soc_data imx_data = {
72 .have_paddr = true,
73};
74
64static const struct of_device_id vf610_gpio_dt_ids[] = { 75static const struct of_device_id vf610_gpio_dt_ids[] = {
65 { .compatible = "fsl,vf610-gpio" }, 76 { .compatible = "fsl,vf610-gpio", .data = NULL, },
77 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
66 { /* sentinel */ } 78 { /* sentinel */ }
67}; 79};
68 80
@@ -79,8 +91,18 @@ static inline u32 vf610_gpio_readl(void __iomem *reg)
79static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio) 91static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
80{ 92{
81 struct vf610_gpio_port *port = gpiochip_get_data(gc); 93 struct vf610_gpio_port *port = gpiochip_get_data(gc);
82 94 unsigned long mask = BIT(gpio);
83 return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDIR) & BIT(gpio)); 95 void __iomem *addr;
96
97 if (port->sdata && port->sdata->have_paddr) {
98 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
99 addr = mask ? port->gpio_base + GPIO_PDOR :
100 port->gpio_base + GPIO_PDIR;
101 return !!(vf610_gpio_readl(addr) & BIT(gpio));
102 } else {
103 return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDIR)
104 & BIT(gpio));
105 }
84} 106}
85 107
86static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 108static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
@@ -96,12 +118,28 @@ static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
96 118
97static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 119static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
98{ 120{
121 struct vf610_gpio_port *port = gpiochip_get_data(chip);
122 unsigned long mask = BIT(gpio);
123 u32 val;
124
125 if (port->sdata && port->sdata->have_paddr) {
126 val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
127 val &= ~mask;
128 vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
129 }
130
99 return pinctrl_gpio_direction_input(chip->base + gpio); 131 return pinctrl_gpio_direction_input(chip->base + gpio);
100} 132}
101 133
102static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 134static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
103 int value) 135 int value)
104{ 136{
137 struct vf610_gpio_port *port = gpiochip_get_data(chip);
138 unsigned long mask = BIT(gpio);
139
140 if (port->sdata && port->sdata->have_paddr)
141 vf610_gpio_writel(mask, port->gpio_base + GPIO_PDDR);
142
105 vf610_gpio_set(chip, gpio, value); 143 vf610_gpio_set(chip, gpio, value);
106 144
107 return pinctrl_gpio_direction_output(chip->base + gpio); 145 return pinctrl_gpio_direction_output(chip->base + gpio);
@@ -216,6 +254,8 @@ static struct irq_chip vf610_gpio_irq_chip = {
216 254
217static int vf610_gpio_probe(struct platform_device *pdev) 255static int vf610_gpio_probe(struct platform_device *pdev)
218{ 256{
257 const struct of_device_id *of_id = of_match_device(vf610_gpio_dt_ids,
258 &pdev->dev);
219 struct device *dev = &pdev->dev; 259 struct device *dev = &pdev->dev;
220 struct device_node *np = dev->of_node; 260 struct device_node *np = dev->of_node;
221 struct vf610_gpio_port *port; 261 struct vf610_gpio_port *port;
@@ -227,6 +267,7 @@ static int vf610_gpio_probe(struct platform_device *pdev)
227 if (!port) 267 if (!port)
228 return -ENOMEM; 268 return -ENOMEM;
229 269
270 port->sdata = of_id->data;
230 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 271 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
231 port->base = devm_ioremap_resource(dev, iores); 272 port->base = devm_ioremap_resource(dev, iores);
232 if (IS_ERR(port->base)) 273 if (IS_ERR(port->base))
diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c
index 14b2a62338ea..e8ec0e33a0a9 100644
--- a/drivers/gpio/gpio-xilinx.c
+++ b/drivers/gpio/gpio-xilinx.c
@@ -360,8 +360,8 @@ static int xgpio_probe(struct platform_device *pdev)
360 /* Call the OF gpio helper to setup and register the GPIO device */ 360 /* Call the OF gpio helper to setup and register the GPIO device */
361 status = of_mm_gpiochip_add_data(np, &chip->mmchip, chip); 361 status = of_mm_gpiochip_add_data(np, &chip->mmchip, chip);
362 if (status) { 362 if (status) {
363 pr_err("%s: error in probe function with status %d\n", 363 pr_err("%pOF: error in probe function with status %d\n",
364 np->full_name, status); 364 np, status);
365 return status; 365 return status;
366 } 366 }
367 367
diff --git a/drivers/gpio/gpio-zevio.c b/drivers/gpio/gpio-zevio.c
index e23ef7b9451d..3926ce9c2840 100644
--- a/drivers/gpio/gpio-zevio.c
+++ b/drivers/gpio/gpio-zevio.c
@@ -156,7 +156,7 @@ static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
156 return -ENXIO; 156 return -ENXIO;
157} 157}
158 158
159static struct gpio_chip zevio_gpio_chip = { 159static const struct gpio_chip zevio_gpio_chip = {
160 .direction_input = zevio_gpio_direction_input, 160 .direction_input = zevio_gpio_direction_input,
161 .direction_output = zevio_gpio_direction_output, 161 .direction_output = zevio_gpio_direction_output,
162 .set = zevio_gpio_set, 162 .set = zevio_gpio_set,
diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c
index df0851464006..b3cc948a2d8b 100644
--- a/drivers/gpio/gpio-zynq.c
+++ b/drivers/gpio/gpio-zynq.c
@@ -60,13 +60,13 @@
60#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \ 60#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1) 61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
62 62
63
64/* Register offsets for the GPIO device */ 63/* Register offsets for the GPIO device */
65/* LSW Mask & Data -WO */ 64/* LSW Mask & Data -WO */
66#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) 65#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
67/* MSW Mask & Data -WO */ 66/* MSW Mask & Data -WO */
68#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) 67#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
69/* Data Register-RW */ 68/* Data Register-RW */
69#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
70#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) 70#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
71/* Direction mode reg-RW */ 71/* Direction mode reg-RW */
72#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) 72#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
@@ -98,6 +98,19 @@
98 98
99/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */ 99/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
100#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0) 100#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
101#define GPIO_QUIRK_DATA_RO_BUG BIT(1)
102
103struct gpio_regs {
104 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
105 u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
106 u32 dirm[ZYNQMP_GPIO_MAX_BANK];
107 u32 outen[ZYNQMP_GPIO_MAX_BANK];
108 u32 int_en[ZYNQMP_GPIO_MAX_BANK];
109 u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
110 u32 int_type[ZYNQMP_GPIO_MAX_BANK];
111 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
112 u32 int_any[ZYNQMP_GPIO_MAX_BANK];
113};
101 114
102/** 115/**
103 * struct zynq_gpio - gpio device private data structure 116 * struct zynq_gpio - gpio device private data structure
@@ -106,6 +119,7 @@
106 * @clk: clock resource for this controller 119 * @clk: clock resource for this controller
107 * @irq: interrupt for the GPIO device 120 * @irq: interrupt for the GPIO device
108 * @p_data: pointer to platform data 121 * @p_data: pointer to platform data
122 * @context: context registers
109 */ 123 */
110struct zynq_gpio { 124struct zynq_gpio {
111 struct gpio_chip chip; 125 struct gpio_chip chip;
@@ -113,16 +127,18 @@ struct zynq_gpio {
113 struct clk *clk; 127 struct clk *clk;
114 int irq; 128 int irq;
115 const struct zynq_platform_data *p_data; 129 const struct zynq_platform_data *p_data;
130 struct gpio_regs context;
116}; 131};
117 132
118/** 133/**
119 * struct zynq_platform_data - zynq gpio platform data structure 134 * struct zynq_platform_data - zynq gpio platform data structure
120 * @label: string to store in gpio->label 135 * @label: string to store in gpio->label
136 * @quirks: Flags is used to identify the platform
121 * @ngpio: max number of gpio pins 137 * @ngpio: max number of gpio pins
122 * @max_bank: maximum number of gpio banks 138 * @max_bank: maximum number of gpio banks
123 * @bank_min: this array represents bank's min pin 139 * @bank_min: this array represents bank's min pin
124 * @bank_max: this array represents bank's max pin 140 * @bank_max: this array represents bank's max pin
125*/ 141 */
126struct zynq_platform_data { 142struct zynq_platform_data {
127 const char *label; 143 const char *label;
128 u32 quirks; 144 u32 quirks;
@@ -147,6 +163,17 @@ static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
147} 163}
148 164
149/** 165/**
166 * gpio_data_ro_bug - test if HW bug exists or not
167 * @gpio: Pointer to driver data struct
168 *
169 * Return: 0 if bug doesnot exist, 1 if bug exists.
170 */
171static int gpio_data_ro_bug(struct zynq_gpio *gpio)
172{
173 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
174}
175
176/**
150 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank 177 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
151 * for a given pin in the GPIO device 178 * for a given pin in the GPIO device
152 * @pin_num: gpio pin number within the device 179 * @pin_num: gpio pin number within the device
@@ -154,6 +181,7 @@ static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
154 * pin 181 * pin
155 * @bank_pin_num: an output parameter used to return pin number within a bank 182 * @bank_pin_num: an output parameter used to return pin number within a bank
156 * for the given gpio pin 183 * for the given gpio pin
184 * @gpio: gpio device data structure
157 * 185 *
158 * Returns the bank number and pin offset within the bank. 186 * Returns the bank number and pin offset within the bank.
159 */ 187 */
@@ -166,11 +194,11 @@ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
166 194
167 for (bank = 0; bank < gpio->p_data->max_bank; bank++) { 195 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
168 if ((pin_num >= gpio->p_data->bank_min[bank]) && 196 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
169 (pin_num <= gpio->p_data->bank_max[bank])) { 197 (pin_num <= gpio->p_data->bank_max[bank])) {
170 *bank_num = bank; 198 *bank_num = bank;
171 *bank_pin_num = pin_num - 199 *bank_pin_num = pin_num -
172 gpio->p_data->bank_min[bank]; 200 gpio->p_data->bank_min[bank];
173 return; 201 return;
174 } 202 }
175 } 203 }
176 204
@@ -197,9 +225,28 @@ static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
197 225
198 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 226 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
199 227
200 data = readl_relaxed(gpio->base_addr + 228 if (gpio_data_ro_bug(gpio)) {
201 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); 229 if (zynq_gpio_is_zynq(gpio)) {
202 230 if (bank_num <= 1) {
231 data = readl_relaxed(gpio->base_addr +
232 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
233 } else {
234 data = readl_relaxed(gpio->base_addr +
235 ZYNQ_GPIO_DATA_OFFSET(bank_num));
236 }
237 } else {
238 if (bank_num <= 2) {
239 data = readl_relaxed(gpio->base_addr +
240 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
241 } else {
242 data = readl_relaxed(gpio->base_addr +
243 ZYNQ_GPIO_DATA_OFFSET(bank_num));
244 }
245 }
246 } else {
247 data = readl_relaxed(gpio->base_addr +
248 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
249 }
203 return (data >> bank_pin_num) & 1; 250 return (data >> bank_pin_num) & 1;
204} 251}
205 252
@@ -263,7 +310,7 @@ static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
263 * as inputs. 310 * as inputs.
264 */ 311 */
265 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 && 312 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
266 (bank_pin_num == 7 || bank_pin_num == 8)) 313 (bank_pin_num == 7 || bank_pin_num == 8))
267 return -EINVAL; 314 return -EINVAL;
268 315
269 /* clear the bit in direction mode reg to set the pin as input */ 316 /* clear the bit in direction mode reg to set the pin as input */
@@ -464,13 +511,14 @@ static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
464 writel_relaxed(int_any, 511 writel_relaxed(int_any,
465 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); 512 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
466 513
467 if (type & IRQ_TYPE_LEVEL_MASK) { 514 if (type & IRQ_TYPE_LEVEL_MASK)
468 irq_set_chip_handler_name_locked(irq_data, 515 irq_set_chip_handler_name_locked(irq_data,
469 &zynq_gpio_level_irqchip, handle_fasteoi_irq, NULL); 516 &zynq_gpio_level_irqchip,
470 } else { 517 handle_fasteoi_irq, NULL);
518 else
471 irq_set_chip_handler_name_locked(irq_data, 519 irq_set_chip_handler_name_locked(irq_data,
472 &zynq_gpio_edge_irqchip, handle_level_irq, NULL); 520 &zynq_gpio_edge_irqchip,
473 } 521 handle_level_irq, NULL);
474 522
475 return 0; 523 return 0;
476} 524}
@@ -530,7 +578,6 @@ static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
530 578
531/** 579/**
532 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device 580 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
533 * @irq: irq number of the gpio bank where interrupt has occurred
534 * @desc: irq descriptor instance of the 'irq' 581 * @desc: irq descriptor instance of the 'irq'
535 * 582 *
536 * This function reads the Interrupt Status Register of each bank to get the 583 * This function reads the Interrupt Status Register of each bank to get the
@@ -560,14 +607,73 @@ static void zynq_gpio_irqhandler(struct irq_desc *desc)
560 chained_irq_exit(irqchip, desc); 607 chained_irq_exit(irqchip, desc);
561} 608}
562 609
610static void zynq_gpio_save_context(struct zynq_gpio *gpio)
611{
612 unsigned int bank_num;
613
614 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
615 gpio->context.datalsw[bank_num] =
616 readl_relaxed(gpio->base_addr +
617 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
618 gpio->context.datamsw[bank_num] =
619 readl_relaxed(gpio->base_addr +
620 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
621 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
622 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
623 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
624 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
625 gpio->context.int_type[bank_num] =
626 readl_relaxed(gpio->base_addr +
627 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
628 gpio->context.int_polarity[bank_num] =
629 readl_relaxed(gpio->base_addr +
630 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
631 gpio->context.int_any[bank_num] =
632 readl_relaxed(gpio->base_addr +
633 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
634 }
635}
636
637static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
638{
639 unsigned int bank_num;
640
641 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
642 writel_relaxed(gpio->context.datalsw[bank_num],
643 gpio->base_addr +
644 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
645 writel_relaxed(gpio->context.datamsw[bank_num],
646 gpio->base_addr +
647 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
648 writel_relaxed(gpio->context.dirm[bank_num],
649 gpio->base_addr +
650 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
651 writel_relaxed(gpio->context.int_en[bank_num],
652 gpio->base_addr +
653 ZYNQ_GPIO_INTEN_OFFSET(bank_num));
654 writel_relaxed(gpio->context.int_type[bank_num],
655 gpio->base_addr +
656 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
657 writel_relaxed(gpio->context.int_polarity[bank_num],
658 gpio->base_addr +
659 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
660 writel_relaxed(gpio->context.int_any[bank_num],
661 gpio->base_addr +
662 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
663 }
664}
665
563static int __maybe_unused zynq_gpio_suspend(struct device *dev) 666static int __maybe_unused zynq_gpio_suspend(struct device *dev)
564{ 667{
565 struct platform_device *pdev = to_platform_device(dev); 668 struct platform_device *pdev = to_platform_device(dev);
566 int irq = platform_get_irq(pdev, 0); 669 int irq = platform_get_irq(pdev, 0);
567 struct irq_data *data = irq_get_irq_data(irq); 670 struct irq_data *data = irq_get_irq_data(irq);
671 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
568 672
569 if (!irqd_is_wakeup_set(data)) 673 if (!irqd_is_wakeup_set(data)) {
674 zynq_gpio_save_context(gpio);
570 return pm_runtime_force_suspend(dev); 675 return pm_runtime_force_suspend(dev);
676 }
571 677
572 return 0; 678 return 0;
573} 679}
@@ -577,9 +683,14 @@ static int __maybe_unused zynq_gpio_resume(struct device *dev)
577 struct platform_device *pdev = to_platform_device(dev); 683 struct platform_device *pdev = to_platform_device(dev);
578 int irq = platform_get_irq(pdev, 0); 684 int irq = platform_get_irq(pdev, 0);
579 struct irq_data *data = irq_get_irq_data(irq); 685 struct irq_data *data = irq_get_irq_data(irq);
686 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
687 int ret;
580 688
581 if (!irqd_is_wakeup_set(data)) 689 if (!irqd_is_wakeup_set(data)) {
582 return pm_runtime_force_resume(dev); 690 ret = pm_runtime_force_resume(dev);
691 zynq_gpio_restore_context(gpio);
692 return ret;
693 }
583 694
584 return 0; 695 return 0;
585} 696}
@@ -602,7 +713,7 @@ static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
602 return clk_prepare_enable(gpio->clk); 713 return clk_prepare_enable(gpio->clk);
603} 714}
604 715
605static int zynq_gpio_request(struct gpio_chip *chip, unsigned offset) 716static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)
606{ 717{
607 int ret; 718 int ret;
608 719
@@ -615,7 +726,7 @@ static int zynq_gpio_request(struct gpio_chip *chip, unsigned offset)
615 return ret < 0 ? ret : 0; 726 return ret < 0 ? ret : 0;
616} 727}
617 728
618static void zynq_gpio_free(struct gpio_chip *chip, unsigned offset) 729static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
619{ 730{
620 pm_runtime_put(chip->parent); 731 pm_runtime_put(chip->parent);
621} 732}
@@ -623,11 +734,12 @@ static void zynq_gpio_free(struct gpio_chip *chip, unsigned offset)
623static const struct dev_pm_ops zynq_gpio_dev_pm_ops = { 734static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
624 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume) 735 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
625 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend, 736 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
626 zynq_gpio_runtime_resume, NULL) 737 zynq_gpio_runtime_resume, NULL)
627}; 738};
628 739
629static const struct zynq_platform_data zynqmp_gpio_def = { 740static const struct zynq_platform_data zynqmp_gpio_def = {
630 .label = "zynqmp_gpio", 741 .label = "zynqmp_gpio",
742 .quirks = GPIO_QUIRK_DATA_RO_BUG,
631 .ngpio = ZYNQMP_GPIO_NR_GPIOS, 743 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
632 .max_bank = ZYNQMP_GPIO_MAX_BANK, 744 .max_bank = ZYNQMP_GPIO_MAX_BANK,
633 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP), 745 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
@@ -646,7 +758,7 @@ static const struct zynq_platform_data zynqmp_gpio_def = {
646 758
647static const struct zynq_platform_data zynq_gpio_def = { 759static const struct zynq_platform_data zynq_gpio_def = {
648 .label = "zynq_gpio", 760 .label = "zynq_gpio",
649 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ, 761 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
650 .ngpio = ZYNQ_GPIO_NR_GPIOS, 762 .ngpio = ZYNQ_GPIO_NR_GPIOS,
651 .max_bank = ZYNQ_GPIO_MAX_BANK, 763 .max_bank = ZYNQ_GPIO_MAX_BANK,
652 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), 764 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
diff --git a/drivers/gpio/gpiolib-acpi.c b/drivers/gpio/gpiolib-acpi.c
index c9b42dd12dfa..4d2113530735 100644
--- a/drivers/gpio/gpiolib-acpi.c
+++ b/drivers/gpio/gpiolib-acpi.c
@@ -61,7 +61,7 @@ static int acpi_gpiochip_find(struct gpio_chip *gc, void *data)
61#ifdef CONFIG_PINCTRL 61#ifdef CONFIG_PINCTRL
62/** 62/**
63 * acpi_gpiochip_pin_to_gpio_offset() - translates ACPI GPIO to Linux GPIO 63 * acpi_gpiochip_pin_to_gpio_offset() - translates ACPI GPIO to Linux GPIO
64 * @chip: GPIO chip 64 * @gdev: GPIO device
65 * @pin: ACPI GPIO pin number from GpioIo/GpioInt resource 65 * @pin: ACPI GPIO pin number from GpioIo/GpioInt resource
66 * 66 *
67 * Function takes ACPI GpioIo/GpioInt pin number as a parameter and 67 * Function takes ACPI GpioIo/GpioInt pin number as a parameter and
@@ -763,7 +763,7 @@ struct gpio_desc *acpi_node_get_gpiod(struct fwnode_handle *fwnode,
763 * The function is idempotent, though each time it runs it will configure GPIO 763 * The function is idempotent, though each time it runs it will configure GPIO
764 * pin direction according to the flags in GpioInt resource. 764 * pin direction according to the flags in GpioInt resource.
765 * 765 *
766 * Return: Linux IRQ number (>%0) on success, negative errno on failure. 766 * Return: Linux IRQ number (> %0) on success, negative errno on failure.
767 */ 767 */
768int acpi_dev_gpio_irq_get(struct acpi_device *adev, int index) 768int acpi_dev_gpio_irq_get(struct acpi_device *adev, int index)
769{ 769{
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
index 54ce8dc58ad0..bfcd20699ec8 100644
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -78,8 +78,8 @@ struct gpio_desc *of_get_named_gpiod_flags(struct device_node *np,
78 ret = of_parse_phandle_with_args(np, propname, "#gpio-cells", index, 78 ret = of_parse_phandle_with_args(np, propname, "#gpio-cells", index,
79 &gpiospec); 79 &gpiospec);
80 if (ret) { 80 if (ret) {
81 pr_debug("%s: can't parse '%s' property of node '%s[%d]'\n", 81 pr_debug("%s: can't parse '%s' property of node '%pOF[%d]'\n",
82 __func__, propname, np->full_name, index); 82 __func__, propname, np, index);
83 return ERR_PTR(ret); 83 return ERR_PTR(ret);
84 } 84 }
85 85
@@ -93,8 +93,8 @@ struct gpio_desc *of_get_named_gpiod_flags(struct device_node *np,
93 if (IS_ERR(desc)) 93 if (IS_ERR(desc))
94 goto out; 94 goto out;
95 95
96 pr_debug("%s: parsed '%s' property of node '%s[%d]' - status (%d)\n", 96 pr_debug("%s: parsed '%s' property of node '%pOF[%d]' - status (%d)\n",
97 __func__, propname, np->full_name, index, 97 __func__, propname, np, index,
98 PTR_ERR_OR_ZERO(desc)); 98 PTR_ERR_OR_ZERO(desc));
99 99
100out: 100out:
@@ -273,14 +273,13 @@ static int of_gpiochip_scan_gpios(struct gpio_chip *chip)
273} 273}
274 274
275/** 275/**
276 * of_gpio_simple_xlate - translate gpio_spec to the GPIO number and flags 276 * of_gpio_simple_xlate - translate gpiospec to the GPIO number and flags
277 * @gc: pointer to the gpio_chip structure 277 * @gc: pointer to the gpio_chip structure
278 * @np: device node of the GPIO chip 278 * @gpiospec: GPIO specifier as found in the device tree
279 * @gpio_spec: gpio specifier as found in the device tree
280 * @flags: a flags pointer to fill in 279 * @flags: a flags pointer to fill in
281 * 280 *
282 * This is simple translation function, suitable for the most 1:1 mapped 281 * This is simple translation function, suitable for the most 1:1 mapped
283 * gpio chips. This function performs only one sanity check: whether gpio 282 * GPIO chips. This function performs only one sanity check: whether GPIO
284 * is less than ngpios (that is specified in the gpio_chip). 283 * is less than ngpios (that is specified in the gpio_chip).
285 */ 284 */
286int of_gpio_simple_xlate(struct gpio_chip *gc, 285int of_gpio_simple_xlate(struct gpio_chip *gc,
@@ -337,7 +336,7 @@ int of_mm_gpiochip_add_data(struct device_node *np,
337 int ret = -ENOMEM; 336 int ret = -ENOMEM;
338 struct gpio_chip *gc = &mm_gc->gc; 337 struct gpio_chip *gc = &mm_gc->gc;
339 338
340 gc->label = kstrdup(np->full_name, GFP_KERNEL); 339 gc->label = kasprintf(GFP_KERNEL, "%pOF", np);
341 if (!gc->label) 340 if (!gc->label)
342 goto err0; 341 goto err0;
343 342
@@ -362,8 +361,7 @@ err2:
362err1: 361err1:
363 kfree(gc->label); 362 kfree(gc->label);
364err0: 363err0:
365 pr_err("%s: GPIO chip registration failed with status %d\n", 364 pr_err("%pOF: GPIO chip registration failed with status %d\n", np, ret);
366 np->full_name, ret);
367 return ret; 365 return ret;
368} 366}
369EXPORT_SYMBOL(of_mm_gpiochip_add_data); 367EXPORT_SYMBOL(of_mm_gpiochip_add_data);
@@ -418,8 +416,8 @@ static int of_gpiochip_add_pin_range(struct gpio_chip *chip)
418 group_names_propname, 416 group_names_propname,
419 index, &name); 417 index, &name);
420 if (strlen(name)) { 418 if (strlen(name)) {
421 pr_err("%s: Group name of numeric GPIO ranges must be the empty string.\n", 419 pr_err("%pOF: Group name of numeric GPIO ranges must be the empty string.\n",
422 np->full_name); 420 np);
423 break; 421 break;
424 } 422 }
425 } 423 }
@@ -434,14 +432,14 @@ static int of_gpiochip_add_pin_range(struct gpio_chip *chip)
434 } else { 432 } else {
435 /* npins == 0: special range */ 433 /* npins == 0: special range */
436 if (pinspec.args[1]) { 434 if (pinspec.args[1]) {
437 pr_err("%s: Illegal gpio-range format.\n", 435 pr_err("%pOF: Illegal gpio-range format.\n",
438 np->full_name); 436 np);
439 break; 437 break;
440 } 438 }
441 439
442 if (!group_names) { 440 if (!group_names) {
443 pr_err("%s: GPIO group range requested but no %s property.\n", 441 pr_err("%pOF: GPIO group range requested but no %s property.\n",
444 np->full_name, group_names_propname); 442 np, group_names_propname);
445 break; 443 break;
446 } 444 }
447 445
@@ -452,8 +450,8 @@ static int of_gpiochip_add_pin_range(struct gpio_chip *chip)
452 break; 450 break;
453 451
454 if (!strlen(name)) { 452 if (!strlen(name)) {
455 pr_err("%s: Group name of GPIO group range cannot be the empty string.\n", 453 pr_err("%pOF: Group name of GPIO group range cannot be the empty string.\n",
456 np->full_name); 454 np);
457 break; 455 break;
458 } 456 }
459 457
diff --git a/drivers/gpio/gpiolib-sysfs.c b/drivers/gpio/gpiolib-sysfs.c
index fc80add5fedb..3f454eaf2101 100644
--- a/drivers/gpio/gpiolib-sysfs.c
+++ b/drivers/gpio/gpiolib-sysfs.c
@@ -540,8 +540,8 @@ static struct class gpio_class = {
540 540
541/** 541/**
542 * gpiod_export - export a GPIO through sysfs 542 * gpiod_export - export a GPIO through sysfs
543 * @gpio: gpio to make available, already requested 543 * @desc: GPIO to make available, already requested
544 * @direction_may_change: true if userspace may change gpio direction 544 * @direction_may_change: true if userspace may change GPIO direction
545 * Context: arch_initcall or later 545 * Context: arch_initcall or later
546 * 546 *
547 * When drivers want to make a GPIO accessible to userspace after they 547 * When drivers want to make a GPIO accessible to userspace after they
@@ -649,7 +649,7 @@ static int match_export(struct device *dev, const void *desc)
649 * gpiod_export_link - create a sysfs link to an exported GPIO node 649 * gpiod_export_link - create a sysfs link to an exported GPIO node
650 * @dev: device under which to create symlink 650 * @dev: device under which to create symlink
651 * @name: name of the symlink 651 * @name: name of the symlink
652 * @gpio: gpio to create symlink to, already exported 652 * @desc: GPIO to create symlink to, already exported
653 * 653 *
654 * Set up a symlink from /sys/.../dev/name to /sys/class/gpio/gpioN 654 * Set up a symlink from /sys/.../dev/name to /sys/class/gpio/gpioN
655 * node. Caller is responsible for unlinking. 655 * node. Caller is responsible for unlinking.
@@ -680,7 +680,7 @@ EXPORT_SYMBOL_GPL(gpiod_export_link);
680 680
681/** 681/**
682 * gpiod_unexport - reverse effect of gpiod_export() 682 * gpiod_unexport - reverse effect of gpiod_export()
683 * @gpio: gpio to make unavailable 683 * @desc: GPIO to make unavailable
684 * 684 *
685 * This is implicit on gpiod_free(). 685 * This is implicit on gpiod_free().
686 */ 686 */
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index cd003b74512f..eb80dac4e26a 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -84,7 +84,12 @@ static inline void desc_set_label(struct gpio_desc *d, const char *label)
84} 84}
85 85
86/** 86/**
87 * Convert a GPIO number to its descriptor 87 * gpio_to_desc - Convert a GPIO number to its descriptor
88 * @gpio: global GPIO number
89 *
90 * Returns:
91 * The GPIO descriptor associated with the given GPIO, or %NULL if no GPIO
92 * with the given number exists in the system.
88 */ 93 */
89struct gpio_desc *gpio_to_desc(unsigned gpio) 94struct gpio_desc *gpio_to_desc(unsigned gpio)
90{ 95{
@@ -111,7 +116,14 @@ struct gpio_desc *gpio_to_desc(unsigned gpio)
111EXPORT_SYMBOL_GPL(gpio_to_desc); 116EXPORT_SYMBOL_GPL(gpio_to_desc);
112 117
113/** 118/**
114 * Get the GPIO descriptor corresponding to the given hw number for this chip. 119 * gpiochip_get_desc - get the GPIO descriptor corresponding to the given
120 * hardware number for this chip
121 * @chip: GPIO chip
122 * @hwnum: hardware number of the GPIO for this chip
123 *
124 * Returns:
125 * A pointer to the GPIO descriptor or %ERR_PTR(-EINVAL) if no GPIO exists
126 * in the given chip for the specified hardware number.
115 */ 127 */
116struct gpio_desc *gpiochip_get_desc(struct gpio_chip *chip, 128struct gpio_desc *gpiochip_get_desc(struct gpio_chip *chip,
117 u16 hwnum) 129 u16 hwnum)
@@ -125,9 +137,14 @@ struct gpio_desc *gpiochip_get_desc(struct gpio_chip *chip,
125} 137}
126 138
127/** 139/**
128 * Convert a GPIO descriptor to the integer namespace. 140 * desc_to_gpio - convert a GPIO descriptor to the integer namespace
141 * @desc: GPIO descriptor
142 *
129 * This should disappear in the future but is needed since we still 143 * This should disappear in the future but is needed since we still
130 * use GPIO numbers for error messages and sysfs nodes 144 * use GPIO numbers for error messages and sysfs nodes.
145 *
146 * Returns:
147 * The global GPIO number for the GPIO specified by its descriptor.
131 */ 148 */
132int desc_to_gpio(const struct gpio_desc *desc) 149int desc_to_gpio(const struct gpio_desc *desc)
133{ 150{
@@ -254,7 +271,7 @@ static int gpiodev_add_to_list(struct gpio_device *gdev)
254 return -EBUSY; 271 return -EBUSY;
255} 272}
256 273
257/** 274/*
258 * Convert a GPIO name to its descriptor 275 * Convert a GPIO name to its descriptor
259 */ 276 */
260static struct gpio_desc *gpio_name_to_desc(const char * const name) 277static struct gpio_desc *gpio_name_to_desc(const char * const name)
@@ -878,7 +895,7 @@ out_free_le:
878 return ret; 895 return ret;
879} 896}
880 897
881/** 898/*
882 * gpio_ioctl() - ioctl handler for the GPIO chardev 899 * gpio_ioctl() - ioctl handler for the GPIO chardev
883 */ 900 */
884static long gpio_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 901static long gpio_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
@@ -1077,11 +1094,9 @@ static void gpiochip_setup_devs(void)
1077/** 1094/**
1078 * gpiochip_add_data() - register a gpio_chip 1095 * gpiochip_add_data() - register a gpio_chip
1079 * @chip: the chip to register, with chip->base initialized 1096 * @chip: the chip to register, with chip->base initialized
1080 * Context: potentially before irqs will work 1097 * @data: driver-private data associated with this chip
1081 * 1098 *
1082 * Returns a negative errno if the chip can't be registered, such as 1099 * Context: potentially before irqs will work
1083 * because the chip->base is invalid or already associated with a
1084 * different chip. Otherwise it returns zero as a success code.
1085 * 1100 *
1086 * When gpiochip_add_data() is called very early during boot, so that GPIOs 1101 * When gpiochip_add_data() is called very early during boot, so that GPIOs
1087 * can be freely used, the chip->parent device must be registered before 1102 * can be freely used, the chip->parent device must be registered before
@@ -1093,6 +1108,11 @@ static void gpiochip_setup_devs(void)
1093 * 1108 *
1094 * If chip->base is negative, this requests dynamic assignment of 1109 * If chip->base is negative, this requests dynamic assignment of
1095 * a range of valid GPIOs. 1110 * a range of valid GPIOs.
1111 *
1112 * Returns:
1113 * A negative errno if the chip can't be registered, such as because the
1114 * chip->base is invalid or already associated with a different chip.
1115 * Otherwise it returns zero as a success code.
1096 */ 1116 */
1097int gpiochip_add_data(struct gpio_chip *chip, void *data) 1117int gpiochip_add_data(struct gpio_chip *chip, void *data)
1098{ 1118{
@@ -1287,6 +1307,10 @@ EXPORT_SYMBOL_GPL(gpiochip_add_data);
1287 1307
1288/** 1308/**
1289 * gpiochip_get_data() - get per-subdriver data for the chip 1309 * gpiochip_get_data() - get per-subdriver data for the chip
1310 * @chip: GPIO chip
1311 *
1312 * Returns:
1313 * The per-subdriver data for the chip.
1290 */ 1314 */
1291void *gpiochip_get_data(struct gpio_chip *chip) 1315void *gpiochip_get_data(struct gpio_chip *chip)
1292{ 1316{
@@ -1370,13 +1394,16 @@ static int devm_gpio_chip_match(struct device *dev, void *res, void *data)
1370 * devm_gpiochip_add_data() - Resource manager piochip_add_data() 1394 * devm_gpiochip_add_data() - Resource manager piochip_add_data()
1371 * @dev: the device pointer on which irq_chip belongs to. 1395 * @dev: the device pointer on which irq_chip belongs to.
1372 * @chip: the chip to register, with chip->base initialized 1396 * @chip: the chip to register, with chip->base initialized
1373 * Context: potentially before irqs will work 1397 * @data: driver-private data associated with this chip
1374 * 1398 *
1375 * Returns a negative errno if the chip can't be registered, such as 1399 * Context: potentially before irqs will work
1376 * because the chip->base is invalid or already associated with a
1377 * different chip. Otherwise it returns zero as a success code.
1378 * 1400 *
1379 * The gpio chip automatically be released when the device is unbound. 1401 * The gpio chip automatically be released when the device is unbound.
1402 *
1403 * Returns:
1404 * A negative errno if the chip can't be registered, such as because the
1405 * chip->base is invalid or already associated with a different chip.
1406 * Otherwise it returns zero as a success code.
1380 */ 1407 */
1381int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip, 1408int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
1382 void *data) 1409 void *data)
@@ -1422,7 +1449,7 @@ EXPORT_SYMBOL_GPL(devm_gpiochip_remove);
1422/** 1449/**
1423 * gpiochip_find() - iterator for locating a specific gpio_chip 1450 * gpiochip_find() - iterator for locating a specific gpio_chip
1424 * @data: data to pass to match function 1451 * @data: data to pass to match function
1425 * @callback: Callback function to check gpio_chip 1452 * @match: Callback function to check gpio_chip
1426 * 1453 *
1427 * Similar to bus_find_device. It returns a reference to a gpio_chip as 1454 * Similar to bus_find_device. It returns a reference to a gpio_chip as
1428 * determined by a user supplied @match callback. The callback should return 1455 * determined by a user supplied @match callback. The callback should return
@@ -1604,6 +1631,9 @@ static int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
1604{ 1631{
1605 struct gpio_chip *chip = d->host_data; 1632 struct gpio_chip *chip = d->host_data;
1606 1633
1634 if (!gpiochip_irqchip_irq_valid(chip, hwirq))
1635 return -ENXIO;
1636
1607 irq_set_chip_data(irq, chip); 1637 irq_set_chip_data(irq, chip);
1608 /* 1638 /*
1609 * This lock class tells lockdep that GPIO irqs are in a different 1639 * This lock class tells lockdep that GPIO irqs are in a different
@@ -1670,7 +1700,9 @@ static void gpiochip_irq_relres(struct irq_data *d)
1670 1700
1671static int gpiochip_to_irq(struct gpio_chip *chip, unsigned offset) 1701static int gpiochip_to_irq(struct gpio_chip *chip, unsigned offset)
1672{ 1702{
1673 return irq_find_mapping(chip->irqdomain, offset); 1703 if (!gpiochip_irqchip_irq_valid(chip, offset))
1704 return -ENXIO;
1705 return irq_create_mapping(chip->irqdomain, offset);
1674} 1706}
1675 1707
1676/** 1708/**
@@ -1746,9 +1778,6 @@ int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
1746 struct lock_class_key *lock_key) 1778 struct lock_class_key *lock_key)
1747{ 1779{
1748 struct device_node *of_node; 1780 struct device_node *of_node;
1749 bool irq_base_set = false;
1750 unsigned int offset;
1751 unsigned irq_base = 0;
1752 1781
1753 if (!gpiochip || !irqchip) 1782 if (!gpiochip || !irqchip)
1754 return -EINVAL; 1783 return -EINVAL;
@@ -1774,7 +1803,7 @@ int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
1774 * conflicting triggers. Tell the user, and reset to NONE. 1803 * conflicting triggers. Tell the user, and reset to NONE.
1775 */ 1804 */
1776 if (WARN(of_node && type != IRQ_TYPE_NONE, 1805 if (WARN(of_node && type != IRQ_TYPE_NONE,
1777 "%s: Ignoring %d default trigger\n", of_node->full_name, type)) 1806 "%pOF: Ignoring %d default trigger\n", of_node, type))
1778 type = IRQ_TYPE_NONE; 1807 type = IRQ_TYPE_NONE;
1779 if (has_acpi_companion(gpiochip->parent) && type != IRQ_TYPE_NONE) { 1808 if (has_acpi_companion(gpiochip->parent) && type != IRQ_TYPE_NONE) {
1780 acpi_handle_warn(ACPI_HANDLE(gpiochip->parent), 1809 acpi_handle_warn(ACPI_HANDLE(gpiochip->parent),
@@ -1805,25 +1834,6 @@ int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
1805 irqchip->irq_release_resources = gpiochip_irq_relres; 1834 irqchip->irq_release_resources = gpiochip_irq_relres;
1806 } 1835 }
1807 1836
1808 /*
1809 * Prepare the mapping since the irqchip shall be orthogonal to
1810 * any gpiochip calls. If the first_irq was zero, this is
1811 * necessary to allocate descriptors for all IRQs.
1812 */
1813 for (offset = 0; offset < gpiochip->ngpio; offset++) {
1814 if (!gpiochip_irqchip_irq_valid(gpiochip, offset))
1815 continue;
1816 irq_base = irq_create_mapping(gpiochip->irqdomain, offset);
1817 if (!irq_base_set) {
1818 /*
1819 * Store the base into the gpiochip to be used when
1820 * unmapping the irqs.
1821 */
1822 gpiochip->irq_base = irq_base;
1823 irq_base_set = true;
1824 }
1825 }
1826
1827 acpi_gpiochip_request_interrupts(gpiochip); 1837 acpi_gpiochip_request_interrupts(gpiochip);
1828 1838
1829 return 0; 1839 return 0;
@@ -1930,11 +1940,14 @@ EXPORT_SYMBOL_GPL(gpiochip_add_pingroup_range);
1930/** 1940/**
1931 * gpiochip_add_pin_range() - add a range for GPIO <-> pin mapping 1941 * gpiochip_add_pin_range() - add a range for GPIO <-> pin mapping
1932 * @chip: the gpiochip to add the range for 1942 * @chip: the gpiochip to add the range for
1933 * @pinctrl_name: the dev_name() of the pin controller to map to 1943 * @pinctl_name: the dev_name() of the pin controller to map to
1934 * @gpio_offset: the start offset in the current gpio_chip number space 1944 * @gpio_offset: the start offset in the current gpio_chip number space
1935 * @pin_offset: the start offset in the pin controller number space 1945 * @pin_offset: the start offset in the pin controller number space
1936 * @npins: the number of pins from the offset of each pin space (GPIO and 1946 * @npins: the number of pins from the offset of each pin space (GPIO and
1937 * pin controller) to accumulate in this range 1947 * pin controller) to accumulate in this range
1948 *
1949 * Returns:
1950 * 0 on success, or a negative error-code on failure.
1938 */ 1951 */
1939int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, 1952int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
1940 unsigned int gpio_offset, unsigned int pin_offset, 1953 unsigned int gpio_offset, unsigned int pin_offset,
@@ -2179,7 +2192,8 @@ EXPORT_SYMBOL_GPL(gpiochip_is_requested);
2179 2192
2180/** 2193/**
2181 * gpiochip_request_own_desc - Allow GPIO chip to request its own descriptor 2194 * gpiochip_request_own_desc - Allow GPIO chip to request its own descriptor
2182 * @desc: GPIO descriptor to request 2195 * @chip: GPIO chip
2196 * @hwnum: hardware number of the GPIO for which to request the descriptor
2183 * @label: label for the GPIO 2197 * @label: label for the GPIO
2184 * 2198 *
2185 * Function allows GPIO chip drivers to request and use their own GPIO 2199 * Function allows GPIO chip drivers to request and use their own GPIO
@@ -2187,6 +2201,10 @@ EXPORT_SYMBOL_GPL(gpiochip_is_requested);
2187 * function will not increase reference count of the GPIO chip module. This 2201 * function will not increase reference count of the GPIO chip module. This
2188 * allows the GPIO chip module to be unloaded as needed (we assume that the 2202 * allows the GPIO chip module to be unloaded as needed (we assume that the
2189 * GPIO chip driver handles freeing the GPIOs it has requested). 2203 * GPIO chip driver handles freeing the GPIOs it has requested).
2204 *
2205 * Returns:
2206 * A pointer to the GPIO descriptor, or an ERR_PTR()-encoded negative error
2207 * code on failure.
2190 */ 2208 */
2191struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum, 2209struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
2192 const char *label) 2210 const char *label)
@@ -2368,12 +2386,13 @@ int gpiod_direction_output(struct gpio_desc *desc, int value)
2368EXPORT_SYMBOL_GPL(gpiod_direction_output); 2386EXPORT_SYMBOL_GPL(gpiod_direction_output);
2369 2387
2370/** 2388/**
2371 * gpiod_set_debounce - sets @debounce time for a @gpio 2389 * gpiod_set_debounce - sets @debounce time for a GPIO
2372 * @gpio: the gpio to set debounce time 2390 * @desc: descriptor of the GPIO for which to set debounce time
2373 * @debounce: debounce time is microseconds 2391 * @debounce: debounce time in microseconds
2374 * 2392 *
2375 * returns -ENOTSUPP if the controller does not support setting 2393 * Returns:
2376 * debounce. 2394 * 0 on success, %-ENOTSUPP if the controller doesn't support setting the
2395 * debounce time.
2377 */ 2396 */
2378int gpiod_set_debounce(struct gpio_desc *desc, unsigned debounce) 2397int gpiod_set_debounce(struct gpio_desc *desc, unsigned debounce)
2379{ 2398{
@@ -2981,6 +3000,23 @@ void gpiod_set_raw_array_value_cansleep(unsigned int array_size,
2981EXPORT_SYMBOL_GPL(gpiod_set_raw_array_value_cansleep); 3000EXPORT_SYMBOL_GPL(gpiod_set_raw_array_value_cansleep);
2982 3001
2983/** 3002/**
3003 * gpiod_add_lookup_tables() - register GPIO device consumers
3004 * @tables: list of tables of consumers to register
3005 * @n: number of tables in the list
3006 */
3007void gpiod_add_lookup_tables(struct gpiod_lookup_table **tables, size_t n)
3008{
3009 unsigned int i;
3010
3011 mutex_lock(&gpio_lookup_lock);
3012
3013 for (i = 0; i < n; i++)
3014 list_add_tail(&tables[i]->list, &gpio_lookup_list);
3015
3016 mutex_unlock(&gpio_lookup_lock);
3017}
3018
3019/**
2984 * gpiod_set_array_value_cansleep() - assign values to an array of GPIOs 3020 * gpiod_set_array_value_cansleep() - assign values to an array of GPIOs
2985 * @array_size: number of elements in the descriptor / value arrays 3021 * @array_size: number of elements in the descriptor / value arrays
2986 * @desc_array: array of GPIO descriptors whose values will be assigned 3022 * @desc_array: array of GPIO descriptors whose values will be assigned
@@ -3322,6 +3358,7 @@ EXPORT_SYMBOL_GPL(gpiod_get_index);
3322 * @propname: name of the firmware property representing the GPIO 3358 * @propname: name of the firmware property representing the GPIO
3323 * @index: index of the GPIO to obtain in the consumer 3359 * @index: index of the GPIO to obtain in the consumer
3324 * @dflags: GPIO initialization flags 3360 * @dflags: GPIO initialization flags
3361 * @label: label to attach to the requested GPIO
3325 * 3362 *
3326 * This function can be used for drivers that get their configuration 3363 * This function can be used for drivers that get their configuration
3327 * from firmware. 3364 * from firmware.
@@ -3330,6 +3367,7 @@ EXPORT_SYMBOL_GPL(gpiod_get_index);
3330 * underlying firmware interface and then makes sure that the GPIO 3367 * underlying firmware interface and then makes sure that the GPIO
3331 * descriptor is requested before it is returned to the caller. 3368 * descriptor is requested before it is returned to the caller.
3332 * 3369 *
3370 * Returns:
3333 * On successful request the GPIO pin is configured in accordance with 3371 * On successful request the GPIO pin is configured in accordance with
3334 * provided @dflags. 3372 * provided @dflags.
3335 * 3373 *
diff --git a/drivers/gpio/gpiolib.h b/drivers/gpio/gpiolib.h
index a8be286eff86..d003ccb12781 100644
--- a/drivers/gpio/gpiolib.h
+++ b/drivers/gpio/gpiolib.h
@@ -219,7 +219,7 @@ int gpiod_hog(struct gpio_desc *desc, const char *name,
219/* 219/*
220 * Return the GPIO number of the passed descriptor relative to its chip 220 * Return the GPIO number of the passed descriptor relative to its chip
221 */ 221 */
222static int __maybe_unused gpio_chip_hwgpio(const struct gpio_desc *desc) 222static inline int gpio_chip_hwgpio(const struct gpio_desc *desc)
223{ 223{
224 return desc - &desc->gdev->descs[0]; 224 return desc - &desc->gdev->descs[0];
225} 225}
diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h
index af20369ec8e7..c97f8325e8bf 100644
--- a/include/linux/gpio/driver.h
+++ b/include/linux/gpio/driver.h
@@ -180,8 +180,27 @@ struct gpio_chip {
180 * If CONFIG_OF is enabled, then all GPIO controllers described in the 180 * If CONFIG_OF is enabled, then all GPIO controllers described in the
181 * device tree automatically may have an OF translation 181 * device tree automatically may have an OF translation
182 */ 182 */
183
184 /**
185 * @of_node:
186 *
187 * Pointer to a device tree node representing this GPIO controller.
188 */
183 struct device_node *of_node; 189 struct device_node *of_node;
184 int of_gpio_n_cells; 190
191 /**
192 * @of_gpio_n_cells:
193 *
194 * Number of cells used to form the GPIO specifier.
195 */
196 unsigned int of_gpio_n_cells;
197
198 /**
199 * @of_xlate:
200 *
201 * Callback to translate a device tree GPIO specifier into a chip-
202 * relative GPIO number and flags.
203 */
185 int (*of_xlate)(struct gpio_chip *gc, 204 int (*of_xlate)(struct gpio_chip *gc,
186 const struct of_phandle_args *gpiospec, u32 *flags); 205 const struct of_phandle_args *gpiospec, u32 *flags);
187#endif 206#endif
@@ -327,11 +346,10 @@ int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset,
327 346
328/** 347/**
329 * struct gpio_pin_range - pin range controlled by a gpio chip 348 * struct gpio_pin_range - pin range controlled by a gpio chip
330 * @head: list for maintaining set of pin ranges, used internally 349 * @node: list for maintaining set of pin ranges, used internally
331 * @pctldev: pinctrl device which handles corresponding pins 350 * @pctldev: pinctrl device which handles corresponding pins
332 * @range: actual range of pins controlled by a gpio controller 351 * @range: actual range of pins controlled by a gpio controller
333 */ 352 */
334
335struct gpio_pin_range { 353struct gpio_pin_range {
336 struct list_head node; 354 struct list_head node;
337 struct pinctrl_dev *pctldev; 355 struct pinctrl_dev *pctldev;
diff --git a/include/linux/gpio/machine.h b/include/linux/gpio/machine.h
index 6e76b16fcade..ba4ccfd900f9 100644
--- a/include/linux/gpio/machine.h
+++ b/include/linux/gpio/machine.h
@@ -60,11 +60,14 @@ struct gpiod_lookup_table {
60 60
61#ifdef CONFIG_GPIOLIB 61#ifdef CONFIG_GPIOLIB
62void gpiod_add_lookup_table(struct gpiod_lookup_table *table); 62void gpiod_add_lookup_table(struct gpiod_lookup_table *table);
63void gpiod_add_lookup_tables(struct gpiod_lookup_table **tables, size_t n);
63void gpiod_remove_lookup_table(struct gpiod_lookup_table *table); 64void gpiod_remove_lookup_table(struct gpiod_lookup_table *table);
64#else 65#else
65static inline 66static inline
66void gpiod_add_lookup_table(struct gpiod_lookup_table *table) {} 67void gpiod_add_lookup_table(struct gpiod_lookup_table *table) {}
67static inline 68static inline
69void gpiod_add_lookup_tables(struct gpiod_lookup_table **tables, size_t n) {}
70static inline
68void gpiod_remove_lookup_table(struct gpiod_lookup_table *table) {} 71void gpiod_remove_lookup_table(struct gpiod_lookup_table *table) {}
69#endif 72#endif
70 73
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-29 19:48:41 -0400