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authorFugang Duan <b38611@freescale.com>2015-07-28 03:30:40 -0400
committerShawn Guo <shawnguo@kernel.org>2015-08-05 08:52:11 -0400
commit709bc0657fe6f9f55fdaab246135ff73ba7796e4 (patch)
treed4f41b70d964b4dd6e45b36b2c0322783ddcb4a1
parent9f55eb92441883a1afca48dc8d32bf62c4d8e833 (diff)
ARM: imx6ul: add fec MAC refrence clock and phy fixup init
Add FEC MAC refrence clock init. Add phy fixup init for i.MX6ul 14x14 evk board that installs KSZ8081 phy. For the phy, there needs extra phy fixup for MII and RMII mode. Signed-off-by: Fugang Duan <b38611@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm/mach-imx/mach-imx6ul.c43
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c
index f206506c8876..db74da5b46af 100644
--- a/arch/arm/mach-imx/mach-imx6ul.c
+++ b/arch/arm/mach-imx/mach-imx6ul.c
@@ -6,12 +6,54 @@
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8#include <linux/irqchip.h> 8#include <linux/irqchip.h>
9#include <linux/mfd/syscon.h>
10#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
11#include <linux/micrel_phy.h>
9#include <linux/of_platform.h> 12#include <linux/of_platform.h>
13#include <linux/phy.h>
14#include <linux/regmap.h>
10#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
11#include <asm/mach/map.h> 16#include <asm/mach/map.h>
12 17
13#include "common.h" 18#include "common.h"
14 19
20static void __init imx6ul_enet_clk_init(void)
21{
22 struct regmap *gpr;
23
24 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
25 if (!IS_ERR(gpr))
26 regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
27 IMX6UL_GPR1_ENET_CLK_OUTPUT);
28 else
29 pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
30
31}
32
33static int ksz8081_phy_fixup(struct phy_device *dev)
34{
35 if (dev && dev->interface == PHY_INTERFACE_MODE_MII) {
36 phy_write(dev, 0x1f, 0x8110);
37 phy_write(dev, 0x16, 0x201);
38 } else if (dev && dev->interface == PHY_INTERFACE_MODE_RMII) {
39 phy_write(dev, 0x1f, 0x8190);
40 phy_write(dev, 0x16, 0x202);
41 }
42
43 return 0;
44}
45
46static void __init imx6ul_enet_phy_init(void)
47{
48 phy_register_fixup_for_uid(PHY_ID_KSZ8081, 0xffffffff, ksz8081_phy_fixup);
49}
50
51static inline void imx6ul_enet_init(void)
52{
53 imx6ul_enet_clk_init();
54 imx6ul_enet_phy_init();
55}
56
15static void __init imx6ul_init_machine(void) 57static void __init imx6ul_init_machine(void)
16{ 58{
17 struct device *parent; 59 struct device *parent;
@@ -21,6 +63,7 @@ static void __init imx6ul_init_machine(void)
21 pr_warn("failed to initialize soc device\n"); 63 pr_warn("failed to initialize soc device\n");
22 64
23 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 65 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
66 imx6ul_enet_init();
24 imx_anatop_init(); 67 imx_anatop_init();
25} 68}
26 69