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authorLinus Torvalds <torvalds@linux-foundation.org>2017-02-25 17:21:18 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2017-02-25 17:21:18 -0500
commit7067739df23ffd641ca99c967830e0ed2ba39eab (patch)
treea29417bb61cc9802502b4ded00b4c706cf25fc10
parentac1820fb286b552b6885d40ab34f1e59b815f1f1 (diff)
parent4c21541d8da17fbe94ecadbfc913d6dff3be7ca2 (diff)
Merge branch 'i2c/for-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c updates from Wolfram Sang: "I2C has for you two new drivers (Tegra BPMP and STM32F4), interrupt support for pca954x muxes, and a bunch of driver bugfixes and improvements. Nothing really special this cycle. A few commits have been added to my tree just recently. Those are the Tegra BPMP driver and a few straightforward bugfixes or cleanups which I prefer to have upstream rather soonish. The rest had proper linux-next exposure" * 'i2c/for-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (25 commits) i2c: thunderx: Replace pci_enable_msix() i2c: exynos5: fix arbitration lost handling i2c: exynos5: disable fifo-almost-empty irq signal when necessary i2c: at91: ensure state is restored after suspending i2c: bcm2835: Avoid possible NULL ptr dereference i2c: Add Tegra BPMP I2C proxy driver dt-bindings: Add Tegra186 BPMP I2C binding misc: eeprom: at24: use device_property_*() functions instead of of_get_property() i2c: mux: pca954x: Add interrupt controller support dt: bindings: i2c-mux-pca954x: Add documentation for interrupt controller i2c: mux: pca954x: Add missing pca9542 definition to chip_desc i2c: riic: correctly finish transfers i2c: i801: Add support for Intel Gemini Lake i2c: mux: pca9541: Export OF device ID table as module aliases i2c: mux: pca954x: Export OF device ID table as module aliases i2c: mux: mlxcpld: remove unused including <linux/version.h> i2c: busses: constify i2c_algorithm structures i2c: i2c-mux-gpio: rename i2c-gpio-mux to i2c-mux-gpio i2c: sh_mobile: document support for r8a7796 (R-Car M3-W) i2c: i2c-cros-ec-tunnel: Reduce logging noise ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt14
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt1
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-stm32.txt33
-rw-r--r--Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt42
-rw-r--r--Documentation/i2c/busses/i2c-i8011
-rw-r--r--Documentation/i2c/muxes/i2c-mux-gpio20
-rw-r--r--drivers/i2c/busses/Kconfig22
-rw-r--r--drivers/i2c/busses/Makefile2
-rw-r--r--drivers/i2c/busses/i2c-at91.c5
-rw-r--r--drivers/i2c/busses/i2c-bcm2835.c4
-rw-r--r--drivers/i2c/busses/i2c-bfin-twi.c2
-rw-r--r--drivers/i2c/busses/i2c-cros-ec-tunnel.c8
-rw-r--r--drivers/i2c/busses/i2c-designware-core.c2
-rw-r--r--drivers/i2c/busses/i2c-eg20t.c2
-rw-r--r--drivers/i2c/busses/i2c-emev2.c2
-rw-r--r--drivers/i2c/busses/i2c-exynos5.c34
-rw-r--r--drivers/i2c/busses/i2c-i801.c3
-rw-r--r--drivers/i2c/busses/i2c-imx-lpi2c.c2
-rw-r--r--drivers/i2c/busses/i2c-imx.c2
-rw-r--r--drivers/i2c/busses/i2c-mv64xxx.c21
-rw-r--r--drivers/i2c/busses/i2c-nforce2.c2
-rw-r--r--drivers/i2c/busses/i2c-octeon-core.h4
-rw-r--r--drivers/i2c/busses/i2c-omap.c2
-rw-r--r--drivers/i2c/busses/i2c-riic.c30
-rw-r--r--drivers/i2c/busses/i2c-robotfuzz-osif.c2
-rw-r--r--drivers/i2c/busses/i2c-sh_mobile.c2
-rw-r--r--drivers/i2c/busses/i2c-st.c2
-rw-r--r--drivers/i2c/busses/i2c-stm32f4.c897
-rw-r--r--drivers/i2c/busses/i2c-tegra-bpmp.c346
-rw-r--r--drivers/i2c/busses/i2c-thunderx-pcidrv.c6
-rw-r--r--drivers/i2c/busses/i2c-xgene-slimpro.c2
-rw-r--r--drivers/i2c/busses/i2c-xlp9xx.c2
-rw-r--r--drivers/i2c/busses/i2c-xlr.c2
-rw-r--r--drivers/i2c/i2c-core.c33
-rw-r--r--drivers/i2c/muxes/i2c-mux-mlxcpld.c1
-rw-r--r--drivers/i2c/muxes/i2c-mux-pca9541.c1
-rw-r--r--drivers/i2c/muxes/i2c-mux-pca954x.c151
-rw-r--r--drivers/misc/eeprom/at24.c45
-rw-r--r--include/linux/i2c.h1
39 files changed, 1675 insertions, 78 deletions
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt
index cf53d5fba20a..aa097045a10e 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt
@@ -19,7 +19,14 @@ Optional Properties:
19 - i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all 19 - i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all
20 children in idle state. This is necessary for example, if there are several 20 children in idle state. This is necessary for example, if there are several
21 multiplexers on the bus and the devices behind them use same I2C addresses. 21 multiplexers on the bus and the devices behind them use same I2C addresses.
22 22 - interrupt-parent: Phandle for the interrupt controller that services
23 interrupts for this device.
24 - interrupts: Interrupt mapping for IRQ.
25 - interrupt-controller: Marks the device node as an interrupt controller.
26 - #interrupt-cells : Should be two.
27 - first cell is the pin number
28 - second cell is used to specify flags.
29 See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
23 30
24Example: 31Example:
25 32
@@ -29,6 +36,11 @@ Example:
29 #size-cells = <0>; 36 #size-cells = <0>;
30 reg = <0x74>; 37 reg = <0x74>;
31 38
39 interrupt-parent = <&ipic>;
40 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
41 interrupt-controller;
42 #interrupt-cells = <2>;
43
32 i2c@2 { 44 i2c@2 {
33 #address-cells = <1>; 45 #address-cells = <1>;
34 #size-cells = <0>; 46 #size-cells = <0>;
diff --git a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
index 7716acc55dec..ae9c2a735f39 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
@@ -10,6 +10,7 @@ Required properties:
10 - "renesas,iic-r8a7793" (R-Car M2-N) 10 - "renesas,iic-r8a7793" (R-Car M2-N)
11 - "renesas,iic-r8a7794" (R-Car E2) 11 - "renesas,iic-r8a7794" (R-Car E2)
12 - "renesas,iic-r8a7795" (R-Car H3) 12 - "renesas,iic-r8a7795" (R-Car H3)
13 - "renesas,iic-r8a7796" (R-Car M3-W)
13 - "renesas,iic-sh73a0" (SH-Mobile AG5) 14 - "renesas,iic-sh73a0" (SH-Mobile AG5)
14 - "renesas,rcar-gen2-iic" (generic R-Car Gen2 compatible device) 15 - "renesas,rcar-gen2-iic" (generic R-Car Gen2 compatible device)
15 - "renesas,rcar-gen3-iic" (generic R-Car Gen3 compatible device) 16 - "renesas,rcar-gen3-iic" (generic R-Car Gen3 compatible device)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-stm32.txt b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt
new file mode 100644
index 000000000000..78eaf7b718ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt
@@ -0,0 +1,33 @@
1* I2C controller embedded in STMicroelectronics STM32 I2C platform
2
3Required properties :
4- compatible : Must be "st,stm32f4-i2c"
5- reg : Offset and length of the register set for the device
6- interrupts : Must contain the interrupt id for I2C event and then the
7 interrupt id for I2C error.
8- resets: Must contain the phandle to the reset controller.
9- clocks: Must contain the input clock of the I2C instance.
10- A pinctrl state named "default" must be defined to set pins in mode of
11 operation for I2C transfer
12- #address-cells = <1>;
13- #size-cells = <0>;
14
15Optional properties :
16- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
17 the default 100 kHz frequency will be used. As only Normal and Fast modes
18 are supported, possible values are 100000 and 400000.
19
20Example :
21
22 i2c@40005400 {
23 compatible = "st,stm32f4-i2c";
24 #address-cells = <1>;
25 #size-cells = <0>;
26 reg = <0x40005400 0x400>;
27 interrupts = <31>,
28 <32>;
29 resets = <&rcc 277>;
30 clocks = <&rcc 0 149>;
31 pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
32 pinctrl-names = "default";
33 };
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
new file mode 100644
index 000000000000..ab240e10debc
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
@@ -0,0 +1,42 @@
1NVIDIA Tegra186 BPMP I2C controller
2
3In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
4devices, such as the I2C controller for the power management I2C bus. Software
5running on other CPUs must perform IPC to the BPMP in order to execute
6transactions on that I2C bus. This binding describes an I2C bus that is
7accessed in such a fashion.
8
9The BPMP I2C node must be located directly inside the main BPMP node. See
10../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
11
12This node represents an I2C controller. See ../i2c/i2c.txt for details of the
13core I2C binding.
14
15Required properties:
16- compatible:
17 Array of strings.
18 One of:
19 - "nvidia,tegra186-bpmp-i2c".
20- #address-cells: Address cells for I2C device address.
21 Single-cell integer.
22 Must be <1>.
23- #size-cells:
24 Single-cell integer.
25 Must be <0>.
26- nvidia,bpmp-bus-id:
27 Single-cell integer.
28 Indicates the I2C bus number this DT node represent, as defined by the
29 BPMP firmware.
30
31Example:
32
33bpmp {
34 ...
35
36 i2c {
37 compatible = "nvidia,tegra186-bpmp-i2c";
38 #address-cells = <1>;
39 #size-cells = <0>;
40 nvidia,bpmp-bus-id = <5>;
41 };
42};
diff --git a/Documentation/i2c/busses/i2c-i801 b/Documentation/i2c/busses/i2c-i801
index 1bba38dd2637..820d9040de16 100644
--- a/Documentation/i2c/busses/i2c-i801
+++ b/Documentation/i2c/busses/i2c-i801
@@ -33,6 +33,7 @@ Supported adapters:
33 * Intel DNV (SOC) 33 * Intel DNV (SOC)
34 * Intel Broxton (SOC) 34 * Intel Broxton (SOC)
35 * Intel Lewisburg (PCH) 35 * Intel Lewisburg (PCH)
36 * Intel Gemini Lake (SOC)
36 Datasheets: Publicly available at the Intel website 37 Datasheets: Publicly available at the Intel website
37 38
38On Intel Patsburg and later chipsets, both the normal host SMBus controller 39On Intel Patsburg and later chipsets, both the normal host SMBus controller
diff --git a/Documentation/i2c/muxes/i2c-mux-gpio b/Documentation/i2c/muxes/i2c-mux-gpio
index d4d91a53fc39..7a8d7d261632 100644
--- a/Documentation/i2c/muxes/i2c-mux-gpio
+++ b/Documentation/i2c/muxes/i2c-mux-gpio
@@ -1,11 +1,11 @@
1Kernel driver i2c-gpio-mux 1Kernel driver i2c-mux-gpio
2 2
3Author: Peter Korsgaard <peter.korsgaard@barco.com> 3Author: Peter Korsgaard <peter.korsgaard@barco.com>
4 4
5Description 5Description
6----------- 6-----------
7 7
8i2c-gpio-mux is an i2c mux driver providing access to I2C bus segments 8i2c-mux-gpio is an i2c mux driver providing access to I2C bus segments
9from a master I2C bus and a hardware MUX controlled through GPIO pins. 9from a master I2C bus and a hardware MUX controlled through GPIO pins.
10 10
11E.G.: 11E.G.:
@@ -26,16 +26,16 @@ according to the settings of the GPIO pins 1..N.
26Usage 26Usage
27----- 27-----
28 28
29i2c-gpio-mux uses the platform bus, so you need to provide a struct 29i2c-mux-gpio uses the platform bus, so you need to provide a struct
30platform_device with the platform_data pointing to a struct 30platform_device with the platform_data pointing to a struct
31gpio_i2cmux_platform_data with the I2C adapter number of the master 31i2c_mux_gpio_platform_data with the I2C adapter number of the master
32bus, the number of bus segments to create and the GPIO pins used 32bus, the number of bus segments to create and the GPIO pins used
33to control it. See include/linux/i2c-gpio-mux.h for details. 33to control it. See include/linux/i2c-mux-gpio.h for details.
34 34
35E.G. something like this for a MUX providing 4 bus segments 35E.G. something like this for a MUX providing 4 bus segments
36controlled through 3 GPIO pins: 36controlled through 3 GPIO pins:
37 37
38#include <linux/i2c-gpio-mux.h> 38#include <linux/i2c-mux-gpio.h>
39#include <linux/platform_device.h> 39#include <linux/platform_device.h>
40 40
41static const unsigned myboard_gpiomux_gpios[] = { 41static const unsigned myboard_gpiomux_gpios[] = {
@@ -46,7 +46,7 @@ static const unsigned myboard_gpiomux_values[] = {
46 0, 1, 2, 3 46 0, 1, 2, 3
47}; 47};
48 48
49static struct gpio_i2cmux_platform_data myboard_i2cmux_data = { 49static struct i2c_mux_gpio_platform_data myboard_i2cmux_data = {
50 .parent = 1, 50 .parent = 1,
51 .base_nr = 2, /* optional */ 51 .base_nr = 2, /* optional */
52 .values = myboard_gpiomux_values, 52 .values = myboard_gpiomux_values,
@@ -57,7 +57,7 @@ static struct gpio_i2cmux_platform_data myboard_i2cmux_data = {
57}; 57};
58 58
59static struct platform_device myboard_i2cmux = { 59static struct platform_device myboard_i2cmux = {
60 .name = "i2c-gpio-mux", 60 .name = "i2c-mux-gpio",
61 .id = 0, 61 .id = 0,
62 .dev = { 62 .dev = {
63 .platform_data = &myboard_i2cmux_data, 63 .platform_data = &myboard_i2cmux_data,
@@ -66,14 +66,14 @@ static struct platform_device myboard_i2cmux = {
66 66
67If you don't know the absolute GPIO pin numbers at registration time, 67If you don't know the absolute GPIO pin numbers at registration time,
68you can instead provide a chip name (.chip_name) and relative GPIO pin 68you can instead provide a chip name (.chip_name) and relative GPIO pin
69numbers, and the i2c-gpio-mux driver will do the work for you, 69numbers, and the i2c-mux-gpio driver will do the work for you,
70including deferred probing if the GPIO chip isn't immediately 70including deferred probing if the GPIO chip isn't immediately
71available. 71available.
72 72
73Device Registration 73Device Registration
74------------------- 74-------------------
75 75
76When registering your i2c-gpio-mux device, you should pass the number 76When registering your i2c-mux-gpio device, you should pass the number
77of any GPIO pin it uses as the device ID. This guarantees that every 77of any GPIO pin it uses as the device ID. This guarantees that every
78instance has a different ID. 78instance has a different ID.
79 79
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 0cdc8443deab..8adc0f1d7ad0 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -128,6 +128,7 @@ config I2C_I801
128 DNV (SOC) 128 DNV (SOC)
129 Broxton (SOC) 129 Broxton (SOC)
130 Lewisburg (PCH) 130 Lewisburg (PCH)
131 Gemini Lake (SOC)
131 132
132 This driver can also be built as a module. If so, the module 133 This driver can also be built as a module. If so, the module
133 will be called i2c-i801. 134 will be called i2c-i801.
@@ -886,6 +887,16 @@ config I2C_ST
886 This driver can also be built as module. If so, the module 887 This driver can also be built as module. If so, the module
887 will be called i2c-st. 888 will be called i2c-st.
888 889
890config I2C_STM32F4
891 tristate "STMicroelectronics STM32F4 I2C support"
892 depends on ARCH_STM32 || COMPILE_TEST
893 help
894 Enable this option to add support for STM32 I2C controller embedded
895 in STM32F4 SoCs.
896
897 This driver can also be built as module. If so, the module
898 will be called i2c-stm32f4.
899
889config I2C_STU300 900config I2C_STU300
890 tristate "ST Microelectronics DDC I2C interface" 901 tristate "ST Microelectronics DDC I2C interface"
891 depends on MACH_U300 902 depends on MACH_U300
@@ -919,6 +930,17 @@ config I2C_TEGRA
919 If you say yes to this option, support will be included for the 930 If you say yes to this option, support will be included for the
920 I2C controller embedded in NVIDIA Tegra SOCs 931 I2C controller embedded in NVIDIA Tegra SOCs
921 932
933config I2C_TEGRA_BPMP
934 tristate "NVIDIA Tegra BPMP I2C controller"
935 depends on TEGRA_BPMP
936 help
937 If you say yes to this option, support will be included for the I2C
938 controller embedded in NVIDIA Tegra SoCs accessed via the BPMP.
939
940 This I2C driver is a 'virtual' I2C driver. The real driver is part
941 of the BPMP firmware, and this driver merely communicates with that
942 real driver.
943
922config I2C_UNIPHIER 944config I2C_UNIPHIER
923 tristate "UniPhier FIFO-less I2C controller" 945 tristate "UniPhier FIFO-less I2C controller"
924 depends on ARCH_UNIPHIER || COMPILE_TEST 946 depends on ARCH_UNIPHIER || COMPILE_TEST
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 1c1bac87a9db..30b60855fbcd 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -85,9 +85,11 @@ obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o
85obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o 85obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o
86obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o 86obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o
87obj-$(CONFIG_I2C_ST) += i2c-st.o 87obj-$(CONFIG_I2C_ST) += i2c-st.o
88obj-$(CONFIG_I2C_STM32F4) += i2c-stm32f4.o
88obj-$(CONFIG_I2C_STU300) += i2c-stu300.o 89obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
89obj-$(CONFIG_I2C_SUN6I_P2WI) += i2c-sun6i-p2wi.o 90obj-$(CONFIG_I2C_SUN6I_P2WI) += i2c-sun6i-p2wi.o
90obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o 91obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o
92obj-$(CONFIG_I2C_TEGRA_BPMP) += i2c-tegra-bpmp.o
91obj-$(CONFIG_I2C_UNIPHIER) += i2c-uniphier.o 93obj-$(CONFIG_I2C_UNIPHIER) += i2c-uniphier.o
92obj-$(CONFIG_I2C_UNIPHIER_F) += i2c-uniphier-f.o 94obj-$(CONFIG_I2C_UNIPHIER_F) += i2c-uniphier-f.o
93obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o 95obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 0b86c6173e07..fabbb9e49161 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -820,7 +820,7 @@ static u32 at91_twi_func(struct i2c_adapter *adapter)
820 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 820 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
821} 821}
822 822
823static struct i2c_algorithm at91_twi_algorithm = { 823static const struct i2c_algorithm at91_twi_algorithm = {
824 .master_xfer = at91_twi_xfer, 824 .master_xfer = at91_twi_xfer,
825 .functionality = at91_twi_func, 825 .functionality = at91_twi_func,
826}; 826};
@@ -1180,6 +1180,7 @@ static int at91_twi_suspend_noirq(struct device *dev)
1180 1180
1181static int at91_twi_resume_noirq(struct device *dev) 1181static int at91_twi_resume_noirq(struct device *dev)
1182{ 1182{
1183 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1183 int ret; 1184 int ret;
1184 1185
1185 if (!pm_runtime_status_suspended(dev)) { 1186 if (!pm_runtime_status_suspended(dev)) {
@@ -1191,6 +1192,8 @@ static int at91_twi_resume_noirq(struct device *dev)
1191 pm_runtime_mark_last_busy(dev); 1192 pm_runtime_mark_last_busy(dev);
1192 pm_request_autosuspend(dev); 1193 pm_request_autosuspend(dev);
1193 1194
1195 at91_init_twi_bus(twi_dev);
1196
1194 return 0; 1197 return 0;
1195} 1198}
1196 1199
diff --git a/drivers/i2c/busses/i2c-bcm2835.c b/drivers/i2c/busses/i2c-bcm2835.c
index c3436f627028..cd07a69e2e93 100644
--- a/drivers/i2c/busses/i2c-bcm2835.c
+++ b/drivers/i2c/busses/i2c-bcm2835.c
@@ -195,7 +195,9 @@ static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data)
195 } 195 }
196 196
197 if (val & BCM2835_I2C_S_DONE) { 197 if (val & BCM2835_I2C_S_DONE) {
198 if (i2c_dev->curr_msg->flags & I2C_M_RD) { 198 if (!i2c_dev->curr_msg) {
199 dev_err(i2c_dev->dev, "Got unexpected interrupt (from firmware?)\n");
200 } else if (i2c_dev->curr_msg->flags & I2C_M_RD) {
199 bcm2835_drain_rxfifo(i2c_dev); 201 bcm2835_drain_rxfifo(i2c_dev);
200 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); 202 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
201 } 203 }
diff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-bfin-twi.c
index 29d00c4f7824..9fe942b8c610 100644
--- a/drivers/i2c/busses/i2c-bfin-twi.c
+++ b/drivers/i2c/busses/i2c-bfin-twi.c
@@ -563,7 +563,7 @@ static u32 bfin_twi_functionality(struct i2c_adapter *adap)
563 I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK; 563 I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
564} 564}
565 565
566static struct i2c_algorithm bfin_twi_algorithm = { 566static const struct i2c_algorithm bfin_twi_algorithm = {
567 .master_xfer = bfin_twi_master_xfer, 567 .master_xfer = bfin_twi_master_xfer,
568 .smbus_xfer = bfin_twi_smbus_xfer, 568 .smbus_xfer = bfin_twi_smbus_xfer,
569 .functionality = bfin_twi_functionality, 569 .functionality = bfin_twi_functionality,
diff --git a/drivers/i2c/busses/i2c-cros-ec-tunnel.c b/drivers/i2c/busses/i2c-cros-ec-tunnel.c
index 9b36a7b3befd..eb76b76f4754 100644
--- a/drivers/i2c/busses/i2c-cros-ec-tunnel.c
+++ b/drivers/i2c/busses/i2c-cros-ec-tunnel.c
@@ -154,8 +154,10 @@ static int ec_i2c_parse_response(const u8 *buf, struct i2c_msg i2c_msgs[],
154 resp = (const struct ec_response_i2c_passthru *)buf; 154 resp = (const struct ec_response_i2c_passthru *)buf;
155 if (resp->i2c_status & EC_I2C_STATUS_TIMEOUT) 155 if (resp->i2c_status & EC_I2C_STATUS_TIMEOUT)
156 return -ETIMEDOUT; 156 return -ETIMEDOUT;
157 else if (resp->i2c_status & EC_I2C_STATUS_NAK)
158 return -ENXIO;
157 else if (resp->i2c_status & EC_I2C_STATUS_ERROR) 159 else if (resp->i2c_status & EC_I2C_STATUS_ERROR)
158 return -EREMOTEIO; 160 return -EIO;
159 161
160 /* Other side could send us back fewer messages, but not more */ 162 /* Other side could send us back fewer messages, but not more */
161 if (resp->num_msgs > *num) 163 if (resp->num_msgs > *num)
@@ -222,10 +224,8 @@ static int ec_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg i2c_msgs[],
222 } 224 }
223 225
224 result = ec_i2c_parse_response(msg->data, i2c_msgs, &num); 226 result = ec_i2c_parse_response(msg->data, i2c_msgs, &num);
225 if (result < 0) { 227 if (result < 0)
226 dev_err(dev, "Error parsing EC i2c message %d\n", result);
227 goto exit; 228 goto exit;
228 }
229 229
230 /* Indicate success by saying how many messages were sent */ 230 /* Indicate success by saying how many messages were sent */
231 result = num; 231 result = num;
diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-core.c
index e9db857c6226..7a3faa551cf8 100644
--- a/drivers/i2c/busses/i2c-designware-core.c
+++ b/drivers/i2c/busses/i2c-designware-core.c
@@ -820,7 +820,7 @@ static u32 i2c_dw_func(struct i2c_adapter *adap)
820 return dev->functionality; 820 return dev->functionality;
821} 821}
822 822
823static struct i2c_algorithm i2c_dw_algo = { 823static const struct i2c_algorithm i2c_dw_algo = {
824 .master_xfer = i2c_dw_xfer, 824 .master_xfer = i2c_dw_xfer,
825 .functionality = i2c_dw_func, 825 .functionality = i2c_dw_func,
826}; 826};
diff --git a/drivers/i2c/busses/i2c-eg20t.c b/drivers/i2c/busses/i2c-eg20t.c
index 5ce71ce7b6c4..bdeab0174fec 100644
--- a/drivers/i2c/busses/i2c-eg20t.c
+++ b/drivers/i2c/busses/i2c-eg20t.c
@@ -715,7 +715,7 @@ static u32 pch_i2c_func(struct i2c_adapter *adap)
715 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; 715 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
716} 716}
717 717
718static struct i2c_algorithm pch_algorithm = { 718static const struct i2c_algorithm pch_algorithm = {
719 .master_xfer = pch_i2c_xfer, 719 .master_xfer = pch_i2c_xfer,
720 .functionality = pch_i2c_func 720 .functionality = pch_i2c_func
721}; 721};
diff --git a/drivers/i2c/busses/i2c-emev2.c b/drivers/i2c/busses/i2c-emev2.c
index 96bb4e749012..312912708854 100644
--- a/drivers/i2c/busses/i2c-emev2.c
+++ b/drivers/i2c/busses/i2c-emev2.c
@@ -347,7 +347,7 @@ static int em_i2c_unreg_slave(struct i2c_client *slave)
347 return 0; 347 return 0;
348} 348}
349 349
350static struct i2c_algorithm em_i2c_algo = { 350static const struct i2c_algorithm em_i2c_algo = {
351 .master_xfer = em_i2c_xfer, 351 .master_xfer = em_i2c_xfer,
352 .functionality = em_i2c_func, 352 .functionality = em_i2c_func,
353 .reg_slave = em_i2c_reg_slave, 353 .reg_slave = em_i2c_reg_slave,
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index bea607149972..cbd93ce0661f 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -130,12 +130,32 @@
130/* I2C_TRANS_STATUS register bits */ 130/* I2C_TRANS_STATUS register bits */
131#define HSI2C_MASTER_BUSY (1u << 17) 131#define HSI2C_MASTER_BUSY (1u << 17)
132#define HSI2C_SLAVE_BUSY (1u << 16) 132#define HSI2C_SLAVE_BUSY (1u << 16)
133
134/* I2C_TRANS_STATUS register bits for Exynos5 variant */
133#define HSI2C_TIMEOUT_AUTO (1u << 4) 135#define HSI2C_TIMEOUT_AUTO (1u << 4)
134#define HSI2C_NO_DEV (1u << 3) 136#define HSI2C_NO_DEV (1u << 3)
135#define HSI2C_NO_DEV_ACK (1u << 2) 137#define HSI2C_NO_DEV_ACK (1u << 2)
136#define HSI2C_TRANS_ABORT (1u << 1) 138#define HSI2C_TRANS_ABORT (1u << 1)
137#define HSI2C_TRANS_DONE (1u << 0) 139#define HSI2C_TRANS_DONE (1u << 0)
138 140
141/* I2C_TRANS_STATUS register bits for Exynos7 variant */
142#define HSI2C_MASTER_ST_MASK 0xf
143#define HSI2C_MASTER_ST_IDLE 0x0
144#define HSI2C_MASTER_ST_START 0x1
145#define HSI2C_MASTER_ST_RESTART 0x2
146#define HSI2C_MASTER_ST_STOP 0x3
147#define HSI2C_MASTER_ST_MASTER_ID 0x4
148#define HSI2C_MASTER_ST_ADDR0 0x5
149#define HSI2C_MASTER_ST_ADDR1 0x6
150#define HSI2C_MASTER_ST_ADDR2 0x7
151#define HSI2C_MASTER_ST_ADDR_SR 0x8
152#define HSI2C_MASTER_ST_READ 0x9
153#define HSI2C_MASTER_ST_WRITE 0xa
154#define HSI2C_MASTER_ST_NO_ACK 0xb
155#define HSI2C_MASTER_ST_LOSE 0xc
156#define HSI2C_MASTER_ST_WAIT 0xd
157#define HSI2C_MASTER_ST_WAIT_CMD 0xe
158
139/* I2C_ADDR register bits */ 159/* I2C_ADDR register bits */
140#define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0) 160#define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0)
141#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) 161#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
@@ -437,6 +457,7 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
437 457
438 int_status = readl(i2c->regs + HSI2C_INT_STATUS); 458 int_status = readl(i2c->regs + HSI2C_INT_STATUS);
439 writel(int_status, i2c->regs + HSI2C_INT_STATUS); 459 writel(int_status, i2c->regs + HSI2C_INT_STATUS);
460 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
440 461
441 /* handle interrupt related to the transfer status */ 462 /* handle interrupt related to the transfer status */
442 if (i2c->variant->hw == HSI2C_EXYNOS7) { 463 if (i2c->variant->hw == HSI2C_EXYNOS7) {
@@ -460,8 +481,12 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
460 i2c->state = -ETIMEDOUT; 481 i2c->state = -ETIMEDOUT;
461 goto stop; 482 goto stop;
462 } 483 }
484
485 if ((trans_status & HSI2C_MASTER_ST_MASK) == HSI2C_MASTER_ST_LOSE) {
486 i2c->state = -EAGAIN;
487 goto stop;
488 }
463 } else if (int_status & HSI2C_INT_I2C) { 489 } else if (int_status & HSI2C_INT_I2C) {
464 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
465 if (trans_status & HSI2C_NO_DEV_ACK) { 490 if (trans_status & HSI2C_NO_DEV_ACK) {
466 dev_dbg(i2c->dev, "No ACK from device\n"); 491 dev_dbg(i2c->dev, "No ACK from device\n");
467 i2c->state = -ENXIO; 492 i2c->state = -ENXIO;
@@ -502,8 +527,13 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
502 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status); 527 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
503 528
504 len = i2c->variant->fifo_depth - fifo_level; 529 len = i2c->variant->fifo_depth - fifo_level;
505 if (len > (i2c->msg->len - i2c->msg_ptr)) 530 if (len > (i2c->msg->len - i2c->msg_ptr)) {
531 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);
532
533 int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN;
534 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
506 len = i2c->msg->len - i2c->msg_ptr; 535 len = i2c->msg->len - i2c->msg_ptr;
536 }
507 537
508 while (len > 0) { 538 while (len > 0) {
509 byte = i2c->msg->buf[i2c->msg_ptr++]; 539 byte = i2c->msg->buf[i2c->msg_ptr++];
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index e242db43774b..6484fa6dbb84 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -65,6 +65,7 @@
65 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 65 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
66 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 66 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
67 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 67 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
68 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
68 * 69 *
69 * Features supported by this driver: 70 * Features supported by this driver:
70 * Software PEC no 71 * Software PEC no
@@ -213,6 +214,7 @@
213#define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 214#define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
214#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 215#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
215#define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 216#define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
217#define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
216#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 218#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
217#define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 219#define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
218#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 220#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
@@ -1012,6 +1014,7 @@ static const struct pci_device_id i801_ids[] = {
1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
diff --git a/drivers/i2c/busses/i2c-imx-lpi2c.c b/drivers/i2c/busses/i2c-imx-lpi2c.c
index 3310f2e0dbd3..e86801a63120 100644
--- a/drivers/i2c/busses/i2c-imx-lpi2c.c
+++ b/drivers/i2c/busses/i2c-imx-lpi2c.c
@@ -538,7 +538,7 @@ static u32 lpi2c_imx_func(struct i2c_adapter *adapter)
538 I2C_FUNC_SMBUS_READ_BLOCK_DATA; 538 I2C_FUNC_SMBUS_READ_BLOCK_DATA;
539} 539}
540 540
541static struct i2c_algorithm lpi2c_imx_algo = { 541static const struct i2c_algorithm lpi2c_imx_algo = {
542 .master_xfer = lpi2c_imx_xfer, 542 .master_xfer = lpi2c_imx_xfer,
543 .functionality = lpi2c_imx_func, 543 .functionality = lpi2c_imx_func,
544}; 544};
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 47fc1f1acff7..95ed17183e73 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -1037,7 +1037,7 @@ static u32 i2c_imx_func(struct i2c_adapter *adapter)
1037 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1037 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1038} 1038}
1039 1039
1040static struct i2c_algorithm i2c_imx_algo = { 1040static const struct i2c_algorithm i2c_imx_algo = {
1041 .master_xfer = i2c_imx_xfer, 1041 .master_xfer = i2c_imx_xfer,
1042 .functionality = i2c_imx_func, 1042 .functionality = i2c_imx_func,
1043}; 1043};
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index b4dec0841bc2..a50bd6891e27 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -977,11 +977,32 @@ mv64xxx_i2c_remove(struct platform_device *dev)
977 return 0; 977 return 0;
978} 978}
979 979
980#ifdef CONFIG_PM
981static int mv64xxx_i2c_resume(struct device *dev)
982{
983 struct platform_device *pdev = to_platform_device(dev);
984 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(pdev);
985
986 mv64xxx_i2c_hw_init(drv_data);
987
988 return 0;
989}
990
991static const struct dev_pm_ops mv64xxx_i2c_pm = {
992 .resume = mv64xxx_i2c_resume,
993};
994
995#define mv64xxx_i2c_pm_ops (&mv64xxx_i2c_pm)
996#else
997#define mv64xxx_i2c_pm_ops NULL
998#endif
999
980static struct platform_driver mv64xxx_i2c_driver = { 1000static struct platform_driver mv64xxx_i2c_driver = {
981 .probe = mv64xxx_i2c_probe, 1001 .probe = mv64xxx_i2c_probe,
982 .remove = mv64xxx_i2c_remove, 1002 .remove = mv64xxx_i2c_remove,
983 .driver = { 1003 .driver = {
984 .name = MV64XXX_I2C_CTLR_NAME, 1004 .name = MV64XXX_I2C_CTLR_NAME,
1005 .pm = mv64xxx_i2c_pm_ops,
985 .of_match_table = mv64xxx_i2c_of_match_table, 1006 .of_match_table = mv64xxx_i2c_of_match_table,
986 }, 1007 },
987}; 1008};
diff --git a/drivers/i2c/busses/i2c-nforce2.c b/drivers/i2c/busses/i2c-nforce2.c
index 374b35e7e450..3241bb9d6c18 100644
--- a/drivers/i2c/busses/i2c-nforce2.c
+++ b/drivers/i2c/busses/i2c-nforce2.c
@@ -296,7 +296,7 @@ static u32 nforce2_func(struct i2c_adapter *adapter)
296 I2C_FUNC_SMBUS_BLOCK_DATA : 0); 296 I2C_FUNC_SMBUS_BLOCK_DATA : 0);
297} 297}
298 298
299static struct i2c_algorithm smbus_algorithm = { 299static const struct i2c_algorithm smbus_algorithm = {
300 .smbus_xfer = nforce2_access, 300 .smbus_xfer = nforce2_access,
301 .functionality = nforce2_func, 301 .functionality = nforce2_func,
302}; 302};
diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-octeon-core.h
index e160f838c254..aa3c8f4771c1 100644
--- a/drivers/i2c/busses/i2c-octeon-core.h
+++ b/drivers/i2c/busses/i2c-octeon-core.h
@@ -6,7 +6,6 @@
6#include <linux/i2c-smbus.h> 6#include <linux/i2c-smbus.h>
7#include <linux/io.h> 7#include <linux/io.h>
8#include <linux/kernel.h> 8#include <linux/kernel.h>
9#include <linux/pci.h>
10 9
11/* Controller command patterns */ 10/* Controller command patterns */
12#define SW_TWSI_V BIT_ULL(63) /* Valid bit */ 11#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
@@ -118,9 +117,6 @@ struct octeon_i2c {
118 void (*hlc_int_disable)(struct octeon_i2c *); 117 void (*hlc_int_disable)(struct octeon_i2c *);
119 atomic_t int_enable_cnt; 118 atomic_t int_enable_cnt;
120 atomic_t hlc_int_enable_cnt; 119 atomic_t hlc_int_enable_cnt;
121#if IS_ENABLED(CONFIG_I2C_THUNDERX)
122 struct msix_entry i2c_msix;
123#endif
124 struct i2c_smbus_alert_setup alert_data; 120 struct i2c_smbus_alert_setup alert_data;
125 struct i2c_client *ara; 121 struct i2c_client *ara;
126}; 122};
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index c7da0c42baee..1ebb5e947e0b 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -1504,7 +1504,7 @@ static int omap_i2c_runtime_resume(struct device *dev)
1504 return 0; 1504 return 0;
1505} 1505}
1506 1506
1507static struct dev_pm_ops omap_i2c_pm_ops = { 1507static const struct dev_pm_ops omap_i2c_pm_ops = {
1508 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend, 1508 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1509 omap_i2c_runtime_resume, NULL) 1509 omap_i2c_runtime_resume, NULL)
1510}; 1510};
diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index 6263ea82d6ac..8f11d347b3ec 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -80,6 +80,7 @@
80#define ICIER_TEIE 0x40 80#define ICIER_TEIE 0x40
81#define ICIER_RIE 0x20 81#define ICIER_RIE 0x20
82#define ICIER_NAKIE 0x10 82#define ICIER_NAKIE 0x10
83#define ICIER_SPIE 0x08
83 84
84#define ICSR2_NACKF 0x10 85#define ICSR2_NACKF 0x10
85 86
@@ -216,11 +217,10 @@ static irqreturn_t riic_tend_isr(int irq, void *data)
216 return IRQ_NONE; 217 return IRQ_NONE;
217 } 218 }
218 219
219 if (riic->is_last || riic->err) 220 if (riic->is_last || riic->err) {
221 riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
220 writeb(ICCR2_SP, riic->base + RIIC_ICCR2); 222 writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
221 223 }
222 writeb(0, riic->base + RIIC_ICIER);
223 complete(&riic->msg_done);
224 224
225 return IRQ_HANDLED; 225 return IRQ_HANDLED;
226} 226}
@@ -240,13 +240,13 @@ static irqreturn_t riic_rdrf_isr(int irq, void *data)
240 240
241 if (riic->bytes_left == 1) { 241 if (riic->bytes_left == 1) {
242 /* STOP must come before we set ACKBT! */ 242 /* STOP must come before we set ACKBT! */
243 if (riic->is_last) 243 if (riic->is_last) {
244 riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
244 writeb(ICCR2_SP, riic->base + RIIC_ICCR2); 245 writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
246 }
245 247
246 riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3); 248 riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
247 249
248 writeb(0, riic->base + RIIC_ICIER);
249 complete(&riic->msg_done);
250 } else { 250 } else {
251 riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3); 251 riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
252 } 252 }
@@ -259,6 +259,21 @@ static irqreturn_t riic_rdrf_isr(int irq, void *data)
259 return IRQ_HANDLED; 259 return IRQ_HANDLED;
260} 260}
261 261
262static irqreturn_t riic_stop_isr(int irq, void *data)
263{
264 struct riic_dev *riic = data;
265
266 /* read back registers to confirm writes have fully propagated */
267 writeb(0, riic->base + RIIC_ICSR2);
268 readb(riic->base + RIIC_ICSR2);
269 writeb(0, riic->base + RIIC_ICIER);
270 readb(riic->base + RIIC_ICIER);
271
272 complete(&riic->msg_done);
273
274 return IRQ_HANDLED;
275}
276
262static u32 riic_func(struct i2c_adapter *adap) 277static u32 riic_func(struct i2c_adapter *adap)
263{ 278{
264 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 279 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
@@ -326,6 +341,7 @@ static struct riic_irq_desc riic_irqs[] = {
326 { .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" }, 341 { .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
327 { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" }, 342 { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
328 { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" }, 343 { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
344 { .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
329 { .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" }, 345 { .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
330}; 346};
331 347
diff --git a/drivers/i2c/busses/i2c-robotfuzz-osif.c b/drivers/i2c/busses/i2c-robotfuzz-osif.c
index 89d8b41b6668..9c0f52b7ff7e 100644
--- a/drivers/i2c/busses/i2c-robotfuzz-osif.c
+++ b/drivers/i2c/busses/i2c-robotfuzz-osif.c
@@ -117,7 +117,7 @@ static u32 osif_func(struct i2c_adapter *adapter)
117 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 117 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
118} 118}
119 119
120static struct i2c_algorithm osif_algorithm = { 120static const struct i2c_algorithm osif_algorithm = {
121 .master_xfer = osif_xfer, 121 .master_xfer = osif_xfer,
122 .functionality = osif_func, 122 .functionality = osif_func,
123}; 123};
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index 3d9ebe6e5716..3d7559348745 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -781,7 +781,7 @@ static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
781 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 781 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
782} 782}
783 783
784static struct i2c_algorithm sh_mobile_i2c_algorithm = { 784static const struct i2c_algorithm sh_mobile_i2c_algorithm = {
785 .functionality = sh_mobile_i2c_func, 785 .functionality = sh_mobile_i2c_func,
786 .master_xfer = sh_mobile_i2c_xfer, 786 .master_xfer = sh_mobile_i2c_xfer,
787}; 787};
diff --git a/drivers/i2c/busses/i2c-st.c b/drivers/i2c/busses/i2c-st.c
index 1371547ce1a3..1eb9fa82dcfd 100644
--- a/drivers/i2c/busses/i2c-st.c
+++ b/drivers/i2c/busses/i2c-st.c
@@ -776,7 +776,7 @@ static u32 st_i2c_func(struct i2c_adapter *adap)
776 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 776 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
777} 777}
778 778
779static struct i2c_algorithm st_i2c_algo = { 779static const struct i2c_algorithm st_i2c_algo = {
780 .master_xfer = st_i2c_xfer, 780 .master_xfer = st_i2c_xfer,
781 .functionality = st_i2c_func, 781 .functionality = st_i2c_func,
782}; 782};
diff --git a/drivers/i2c/busses/i2c-stm32f4.c b/drivers/i2c/busses/i2c-stm32f4.c
new file mode 100644
index 000000000000..f9dd7e86b861
--- /dev/null
+++ b/drivers/i2c/busses/i2c-stm32f4.c
@@ -0,0 +1,897 @@
1/*
2 * Driver for STMicroelectronics STM32 I2C controller
3 *
4 * This I2C controller is described in the STM32F429/439 Soc reference manual.
5 * Please see below a link to the documentation:
6 * http://www.st.com/resource/en/reference_manual/DM00031020.pdf
7 *
8 * Copyright (C) M'boumba Cedric Madianga 2016
9 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
10 *
11 * This driver is based on i2c-st.c
12 *
13 * License terms: GNU General Public License (GPL), version 2
14 */
15
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/err.h>
19#include <linux/i2c.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/iopoll.h>
23#include <linux/module.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
26#include <linux/of.h>
27#include <linux/platform_device.h>
28#include <linux/reset.h>
29
30/* STM32F4 I2C offset registers */
31#define STM32F4_I2C_CR1 0x00
32#define STM32F4_I2C_CR2 0x04
33#define STM32F4_I2C_DR 0x10
34#define STM32F4_I2C_SR1 0x14
35#define STM32F4_I2C_SR2 0x18
36#define STM32F4_I2C_CCR 0x1C
37#define STM32F4_I2C_TRISE 0x20
38#define STM32F4_I2C_FLTR 0x24
39
40/* STM32F4 I2C control 1*/
41#define STM32F4_I2C_CR1_POS BIT(11)
42#define STM32F4_I2C_CR1_ACK BIT(10)
43#define STM32F4_I2C_CR1_STOP BIT(9)
44#define STM32F4_I2C_CR1_START BIT(8)
45#define STM32F4_I2C_CR1_PE BIT(0)
46
47/* STM32F4 I2C control 2 */
48#define STM32F4_I2C_CR2_FREQ_MASK GENMASK(5, 0)
49#define STM32F4_I2C_CR2_FREQ(n) ((n) & STM32F4_I2C_CR2_FREQ_MASK)
50#define STM32F4_I2C_CR2_ITBUFEN BIT(10)
51#define STM32F4_I2C_CR2_ITEVTEN BIT(9)
52#define STM32F4_I2C_CR2_ITERREN BIT(8)
53#define STM32F4_I2C_CR2_IRQ_MASK (STM32F4_I2C_CR2_ITBUFEN | \
54 STM32F4_I2C_CR2_ITEVTEN | \
55 STM32F4_I2C_CR2_ITERREN)
56
57/* STM32F4 I2C Status 1 */
58#define STM32F4_I2C_SR1_AF BIT(10)
59#define STM32F4_I2C_SR1_ARLO BIT(9)
60#define STM32F4_I2C_SR1_BERR BIT(8)
61#define STM32F4_I2C_SR1_TXE BIT(7)
62#define STM32F4_I2C_SR1_RXNE BIT(6)
63#define STM32F4_I2C_SR1_BTF BIT(2)
64#define STM32F4_I2C_SR1_ADDR BIT(1)
65#define STM32F4_I2C_SR1_SB BIT(0)
66#define STM32F4_I2C_SR1_ITEVTEN_MASK (STM32F4_I2C_SR1_BTF | \
67 STM32F4_I2C_SR1_ADDR | \
68 STM32F4_I2C_SR1_SB)
69#define STM32F4_I2C_SR1_ITBUFEN_MASK (STM32F4_I2C_SR1_TXE | \
70 STM32F4_I2C_SR1_RXNE)
71#define STM32F4_I2C_SR1_ITERREN_MASK (STM32F4_I2C_SR1_AF | \
72 STM32F4_I2C_SR1_ARLO | \
73 STM32F4_I2C_SR1_BERR)
74
75/* STM32F4 I2C Status 2 */
76#define STM32F4_I2C_SR2_BUSY BIT(1)
77
78/* STM32F4 I2C Control Clock */
79#define STM32F4_I2C_CCR_CCR_MASK GENMASK(11, 0)
80#define STM32F4_I2C_CCR_CCR(n) ((n) & STM32F4_I2C_CCR_CCR_MASK)
81#define STM32F4_I2C_CCR_FS BIT(15)
82#define STM32F4_I2C_CCR_DUTY BIT(14)
83
84/* STM32F4 I2C Trise */
85#define STM32F4_I2C_TRISE_VALUE_MASK GENMASK(5, 0)
86#define STM32F4_I2C_TRISE_VALUE(n) ((n) & STM32F4_I2C_TRISE_VALUE_MASK)
87
88#define STM32F4_I2C_MIN_STANDARD_FREQ 2U
89#define STM32F4_I2C_MIN_FAST_FREQ 6U
90#define STM32F4_I2C_MAX_FREQ 46U
91#define HZ_TO_MHZ 1000000
92
93enum stm32f4_i2c_speed {
94 STM32F4_I2C_SPEED_STANDARD, /* 100 kHz */
95 STM32F4_I2C_SPEED_FAST, /* 400 kHz */
96 STM32F4_I2C_SPEED_END,
97};
98
99/**
100 * struct stm32f4_i2c_msg - client specific data
101 * @addr: 8-bit slave addr, including r/w bit
102 * @count: number of bytes to be transferred
103 * @buf: data buffer
104 * @result: result of the transfer
105 * @stop: last I2C msg to be sent, i.e. STOP to be generated
106 */
107struct stm32f4_i2c_msg {
108 u8 addr;
109 u32 count;
110 u8 *buf;
111 int result;
112 bool stop;
113};
114
115/**
116 * struct stm32f4_i2c_dev - private data of the controller
117 * @adap: I2C adapter for this controller
118 * @dev: device for this controller
119 * @base: virtual memory area
120 * @complete: completion of I2C message
121 * @clk: hw i2c clock
122 * @speed: I2C clock frequency of the controller. Standard or Fast are supported
123 * @parent_rate: I2C clock parent rate in MHz
124 * @msg: I2C transfer information
125 */
126struct stm32f4_i2c_dev {
127 struct i2c_adapter adap;
128 struct device *dev;
129 void __iomem *base;
130 struct completion complete;
131 struct clk *clk;
132 int speed;
133 int parent_rate;
134 struct stm32f4_i2c_msg msg;
135};
136
137static inline void stm32f4_i2c_set_bits(void __iomem *reg, u32 mask)
138{
139 writel_relaxed(readl_relaxed(reg) | mask, reg);
140}
141
142static inline void stm32f4_i2c_clr_bits(void __iomem *reg, u32 mask)
143{
144 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
145}
146
147static void stm32f4_i2c_disable_irq(struct stm32f4_i2c_dev *i2c_dev)
148{
149 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
150
151 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_IRQ_MASK);
152}
153
154static int stm32f4_i2c_set_periph_clk_freq(struct stm32f4_i2c_dev *i2c_dev)
155{
156 u32 freq;
157 u32 cr2 = 0;
158
159 i2c_dev->parent_rate = clk_get_rate(i2c_dev->clk);
160 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ);
161
162 if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD) {
163 /*
164 * To reach 100 kHz, the parent clk frequency should be between
165 * a minimum value of 2 MHz and a maximum value of 46 MHz due
166 * to hardware limitation
167 */
168 if (freq < STM32F4_I2C_MIN_STANDARD_FREQ ||
169 freq > STM32F4_I2C_MAX_FREQ) {
170 dev_err(i2c_dev->dev,
171 "bad parent clk freq for standard mode\n");
172 return -EINVAL;
173 }
174 } else {
175 /*
176 * To be as close as possible to 400 kHz, the parent clk
177 * frequency should be between a minimum value of 6 MHz and a
178 * maximum value of 46 MHz due to hardware limitation
179 */
180 if (freq < STM32F4_I2C_MIN_FAST_FREQ ||
181 freq > STM32F4_I2C_MAX_FREQ) {
182 dev_err(i2c_dev->dev,
183 "bad parent clk freq for fast mode\n");
184 return -EINVAL;
185 }
186 }
187
188 cr2 |= STM32F4_I2C_CR2_FREQ(freq);
189 writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2);
190
191 return 0;
192}
193
194static void stm32f4_i2c_set_rise_time(struct stm32f4_i2c_dev *i2c_dev)
195{
196 u32 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ);
197 u32 trise;
198
199 /*
200 * These bits must be programmed with the maximum SCL rise time given in
201 * the I2C bus specification, incremented by 1.
202 *
203 * In standard mode, the maximum allowed SCL rise time is 1000 ns.
204 * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to
205 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be
206 * programmed with 0x9. (1000 ns / 125 ns + 1)
207 * So, for I2C standard mode TRISE = FREQ[5:0] + 1
208 *
209 * In fast mode, the maximum allowed SCL rise time is 300 ns.
210 * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to
211 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be
212 * programmed with 0x3. (300 ns / 125 ns + 1)
213 * So, for I2C fast mode TRISE = FREQ[5:0] * 300 / 1000 + 1
214 *
215 * Function stm32f4_i2c_set_periph_clk_freq made sure that parent rate
216 * is not higher than 46 MHz . As a result trise is at most 4 bits wide
217 * and so fits into the TRISE bits [5:0].
218 */
219 if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD)
220 trise = freq + 1;
221 else
222 trise = freq * 3 / 10 + 1;
223
224 writel_relaxed(STM32F4_I2C_TRISE_VALUE(trise),
225 i2c_dev->base + STM32F4_I2C_TRISE);
226}
227
228static void stm32f4_i2c_set_speed_mode(struct stm32f4_i2c_dev *i2c_dev)
229{
230 u32 val;
231 u32 ccr = 0;
232
233 if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD) {
234 /*
235 * In standard mode:
236 * t_scl_high = t_scl_low = CCR * I2C parent clk period
237 * So to reach 100 kHz, we have:
238 * CCR = I2C parent rate / 100 kHz >> 1
239 *
240 * For example with parent rate = 2 MHz:
241 * CCR = 2000000 / (100000 << 1) = 10
242 * t_scl_high = t_scl_low = 10 * (1 / 2000000) = 5000 ns
243 * t_scl_high + t_scl_low = 10000 ns so 100 kHz is reached
244 *
245 * Function stm32f4_i2c_set_periph_clk_freq made sure that
246 * parent rate is not higher than 46 MHz . As a result val
247 * is at most 8 bits wide and so fits into the CCR bits [11:0].
248 */
249 val = i2c_dev->parent_rate / (100000 << 1);
250 } else {
251 /*
252 * In fast mode, we compute CCR with duty = 0 as with low
253 * frequencies we are not able to reach 400 kHz.
254 * In that case:
255 * t_scl_high = CCR * I2C parent clk period
256 * t_scl_low = 2 * CCR * I2C parent clk period
257 * So, CCR = I2C parent rate / (400 kHz * 3)
258 *
259 * For example with parent rate = 6 MHz:
260 * CCR = 6000000 / (400000 * 3) = 5
261 * t_scl_high = 5 * (1 / 6000000) = 833 ns > 600 ns
262 * t_scl_low = 2 * 5 * (1 / 6000000) = 1667 ns > 1300 ns
263 * t_scl_high + t_scl_low = 2500 ns so 400 kHz is reached
264 *
265 * Function stm32f4_i2c_set_periph_clk_freq made sure that
266 * parent rate is not higher than 46 MHz . As a result val
267 * is at most 6 bits wide and so fits into the CCR bits [11:0].
268 */
269 val = DIV_ROUND_UP(i2c_dev->parent_rate, 400000 * 3);
270
271 /* Select Fast mode */
272 ccr |= STM32F4_I2C_CCR_FS;
273 }
274
275 ccr |= STM32F4_I2C_CCR_CCR(val);
276 writel_relaxed(ccr, i2c_dev->base + STM32F4_I2C_CCR);
277}
278
279/**
280 * stm32f4_i2c_hw_config() - Prepare I2C block
281 * @i2c_dev: Controller's private data
282 */
283static int stm32f4_i2c_hw_config(struct stm32f4_i2c_dev *i2c_dev)
284{
285 int ret;
286
287 ret = stm32f4_i2c_set_periph_clk_freq(i2c_dev);
288 if (ret)
289 return ret;
290
291 stm32f4_i2c_set_rise_time(i2c_dev);
292
293 stm32f4_i2c_set_speed_mode(i2c_dev);
294
295 /* Enable I2C */
296 writel_relaxed(STM32F4_I2C_CR1_PE, i2c_dev->base + STM32F4_I2C_CR1);
297
298 return 0;
299}
300
301static int stm32f4_i2c_wait_free_bus(struct stm32f4_i2c_dev *i2c_dev)
302{
303 u32 status;
304 int ret;
305
306 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F4_I2C_SR2,
307 status,
308 !(status & STM32F4_I2C_SR2_BUSY),
309 10, 1000);
310 if (ret) {
311 dev_dbg(i2c_dev->dev, "bus not free\n");
312 ret = -EBUSY;
313 }
314
315 return ret;
316}
317
318/**
319 * stm32f4_i2c_write_ byte() - Write a byte in the data register
320 * @i2c_dev: Controller's private data
321 * @byte: Data to write in the register
322 */
323static void stm32f4_i2c_write_byte(struct stm32f4_i2c_dev *i2c_dev, u8 byte)
324{
325 writel_relaxed(byte, i2c_dev->base + STM32F4_I2C_DR);
326}
327
328/**
329 * stm32f4_i2c_write_msg() - Fill the data register in write mode
330 * @i2c_dev: Controller's private data
331 *
332 * This function fills the data register with I2C transfer buffer
333 */
334static void stm32f4_i2c_write_msg(struct stm32f4_i2c_dev *i2c_dev)
335{
336 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
337
338 stm32f4_i2c_write_byte(i2c_dev, *msg->buf++);
339 msg->count--;
340}
341
342static void stm32f4_i2c_read_msg(struct stm32f4_i2c_dev *i2c_dev)
343{
344 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
345 u32 rbuf;
346
347 rbuf = readl_relaxed(i2c_dev->base + STM32F4_I2C_DR);
348 *msg->buf++ = rbuf;
349 msg->count--;
350}
351
352static void stm32f4_i2c_terminate_xfer(struct stm32f4_i2c_dev *i2c_dev)
353{
354 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
355 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
356
357 stm32f4_i2c_disable_irq(i2c_dev);
358
359 reg = i2c_dev->base + STM32F4_I2C_CR1;
360 if (msg->stop)
361 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP);
362 else
363 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
364
365 complete(&i2c_dev->complete);
366}
367
368/**
369 * stm32f4_i2c_handle_write() - Handle FIFO empty interrupt in case of write
370 * @i2c_dev: Controller's private data
371 */
372static void stm32f4_i2c_handle_write(struct stm32f4_i2c_dev *i2c_dev)
373{
374 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
375 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
376
377 if (msg->count) {
378 stm32f4_i2c_write_msg(i2c_dev);
379 if (!msg->count) {
380 /*
381 * Disable buffer interrupts for RX not empty and TX
382 * empty events
383 */
384 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN);
385 }
386 } else {
387 stm32f4_i2c_terminate_xfer(i2c_dev);
388 }
389}
390
391/**
392 * stm32f4_i2c_handle_read() - Handle FIFO empty interrupt in case of read
393 * @i2c_dev: Controller's private data
394 *
395 * This function is called when a new data is received in data register
396 */
397static void stm32f4_i2c_handle_read(struct stm32f4_i2c_dev *i2c_dev)
398{
399 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
400 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
401
402 switch (msg->count) {
403 case 1:
404 stm32f4_i2c_disable_irq(i2c_dev);
405 stm32f4_i2c_read_msg(i2c_dev);
406 complete(&i2c_dev->complete);
407 break;
408 /*
409 * For 2-byte reception, 3-byte reception and for Data N-2, N-1 and N
410 * for N-byte reception with N > 3, we do not have to read the data
411 * register when RX not empty event occurs as we have to wait for byte
412 * transferred finished event before reading data.
413 * So, here we just disable buffer interrupt in order to avoid another
414 * system preemption due to RX not empty event.
415 */
416 case 2:
417 case 3:
418 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN);
419 break;
420 /*
421 * For N byte reception with N > 3 we directly read data register
422 * until N-2 data.
423 */
424 default:
425 stm32f4_i2c_read_msg(i2c_dev);
426 }
427}
428
429/**
430 * stm32f4_i2c_handle_rx_done() - Handle byte transfer finished interrupt
431 * in case of read
432 * @i2c_dev: Controller's private data
433 *
434 * This function is called when a new data is received in the shift register
435 * but data register has not been read yet.
436 */
437static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
438{
439 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
440 void __iomem *reg;
441 u32 mask;
442 int i;
443
444 switch (msg->count) {
445 case 2:
446 /*
447 * In order to correctly send the Stop or Repeated Start
448 * condition on the I2C bus, the STOP/START bit has to be set
449 * before reading the last two bytes (data N-1 and N).
450 * After that, we could read the last two bytes, disable
451 * remaining interrupts and notify the end of xfer to the
452 * client
453 */
454 reg = i2c_dev->base + STM32F4_I2C_CR1;
455 if (msg->stop)
456 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP);
457 else
458 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
459
460 for (i = 2; i > 0; i--)
461 stm32f4_i2c_read_msg(i2c_dev);
462
463 reg = i2c_dev->base + STM32F4_I2C_CR2;
464 mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN;
465 stm32f4_i2c_clr_bits(reg, mask);
466
467 complete(&i2c_dev->complete);
468 break;
469 case 3:
470 /*
471 * In order to correctly generate the NACK pulse after the last
472 * received data byte, we have to enable NACK before reading N-2
473 * data
474 */
475 reg = i2c_dev->base + STM32F4_I2C_CR1;
476 stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR1_ACK);
477 stm32f4_i2c_read_msg(i2c_dev);
478 break;
479 default:
480 stm32f4_i2c_read_msg(i2c_dev);
481 }
482}
483
484/**
485 * stm32f4_i2c_handle_rx_addr() - Handle address matched interrupt in case of
486 * master receiver
487 * @i2c_dev: Controller's private data
488 */
489static void stm32f4_i2c_handle_rx_addr(struct stm32f4_i2c_dev *i2c_dev)
490{
491 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
492 u32 cr1;
493
494 switch (msg->count) {
495 case 0:
496 stm32f4_i2c_terminate_xfer(i2c_dev);
497
498 /* Clear ADDR flag */
499 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
500 break;
501 case 1:
502 /*
503 * Single byte reception:
504 * Enable NACK and reset POS (Acknowledge position).
505 * Then, clear ADDR flag and set STOP or RepSTART.
506 * In that way, the NACK and STOP or RepStart pulses will be
507 * sent as soon as the byte will be received in shift register
508 */
509 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);
510 cr1 &= ~(STM32F4_I2C_CR1_ACK | STM32F4_I2C_CR1_POS);
511 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
512
513 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
514
515 if (msg->stop)
516 cr1 |= STM32F4_I2C_CR1_STOP;
517 else
518 cr1 |= STM32F4_I2C_CR1_START;
519 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
520 break;
521 case 2:
522 /*
523 * 2-byte reception:
524 * Enable NACK, set POS (NACK position) and clear ADDR flag.
525 * In that way, NACK will be sent for the next byte which will
526 * be received in the shift register instead of the current
527 * one.
528 */
529 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);
530 cr1 &= ~STM32F4_I2C_CR1_ACK;
531 cr1 |= STM32F4_I2C_CR1_POS;
532 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
533
534 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
535 break;
536
537 default:
538 /*
539 * N-byte reception:
540 * Enable ACK, reset POS (ACK postion) and clear ADDR flag.
541 * In that way, ACK will be sent as soon as the current byte
542 * will be received in the shift register
543 */
544 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);
545 cr1 |= STM32F4_I2C_CR1_ACK;
546 cr1 &= ~STM32F4_I2C_CR1_POS;
547 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
548
549 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
550 break;
551 }
552}
553
554/**
555 * stm32f4_i2c_isr_event() - Interrupt routine for I2C bus event
556 * @irq: interrupt number
557 * @data: Controller's private data
558 */
559static irqreturn_t stm32f4_i2c_isr_event(int irq, void *data)
560{
561 struct stm32f4_i2c_dev *i2c_dev = data;
562 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
563 u32 possible_status = STM32F4_I2C_SR1_ITEVTEN_MASK;
564 u32 status, ien, event, cr2;
565
566 cr2 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR2);
567 ien = cr2 & STM32F4_I2C_CR2_IRQ_MASK;
568
569 /* Update possible_status if buffer interrupt is enabled */
570 if (ien & STM32F4_I2C_CR2_ITBUFEN)
571 possible_status |= STM32F4_I2C_SR1_ITBUFEN_MASK;
572
573 status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1);
574 event = status & possible_status;
575 if (!event) {
576 dev_dbg(i2c_dev->dev,
577 "spurious evt irq (status=0x%08x, ien=0x%08x)\n",
578 status, ien);
579 return IRQ_NONE;
580 }
581
582 /* Start condition generated */
583 if (event & STM32F4_I2C_SR1_SB)
584 stm32f4_i2c_write_byte(i2c_dev, msg->addr);
585
586 /* I2C Address sent */
587 if (event & STM32F4_I2C_SR1_ADDR) {
588 if (msg->addr & I2C_M_RD)
589 stm32f4_i2c_handle_rx_addr(i2c_dev);
590 else
591 readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
592
593 /*
594 * Enable buffer interrupts for RX not empty and TX empty
595 * events
596 */
597 cr2 |= STM32F4_I2C_CR2_ITBUFEN;
598 writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2);
599 }
600
601 /* TX empty */
602 if ((event & STM32F4_I2C_SR1_TXE) && !(msg->addr & I2C_M_RD))
603 stm32f4_i2c_handle_write(i2c_dev);
604
605 /* RX not empty */
606 if ((event & STM32F4_I2C_SR1_RXNE) && (msg->addr & I2C_M_RD))
607 stm32f4_i2c_handle_read(i2c_dev);
608
609 /*
610 * The BTF (Byte Transfer finished) event occurs when:
611 * - in reception : a new byte is received in the shift register
612 * but the previous byte has not been read yet from data register
613 * - in transmission: a new byte should be sent but the data register
614 * has not been written yet
615 */
616 if (event & STM32F4_I2C_SR1_BTF) {
617 if (msg->addr & I2C_M_RD)
618 stm32f4_i2c_handle_rx_done(i2c_dev);
619 else
620 stm32f4_i2c_handle_write(i2c_dev);
621 }
622
623 return IRQ_HANDLED;
624}
625
626/**
627 * stm32f4_i2c_isr_error() - Interrupt routine for I2C bus error
628 * @irq: interrupt number
629 * @data: Controller's private data
630 */
631static irqreturn_t stm32f4_i2c_isr_error(int irq, void *data)
632{
633 struct stm32f4_i2c_dev *i2c_dev = data;
634 struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
635 void __iomem *reg;
636 u32 status;
637
638 status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1);
639
640 /* Arbitration lost */
641 if (status & STM32F4_I2C_SR1_ARLO) {
642 status &= ~STM32F4_I2C_SR1_ARLO;
643 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
644 msg->result = -EAGAIN;
645 }
646
647 /*
648 * Acknowledge failure:
649 * In master transmitter mode a Stop must be generated by software
650 */
651 if (status & STM32F4_I2C_SR1_AF) {
652 if (!(msg->addr & I2C_M_RD)) {
653 reg = i2c_dev->base + STM32F4_I2C_CR1;
654 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP);
655 }
656 status &= ~STM32F4_I2C_SR1_AF;
657 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
658 msg->result = -EIO;
659 }
660
661 /* Bus error */
662 if (status & STM32F4_I2C_SR1_BERR) {
663 status &= ~STM32F4_I2C_SR1_BERR;
664 writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
665 msg->result = -EIO;
666 }
667
668 stm32f4_i2c_disable_irq(i2c_dev);
669 complete(&i2c_dev->complete);
670
671 return IRQ_HANDLED;
672}
673
674/**
675 * stm32f4_i2c_xfer_msg() - Transfer a single I2C message
676 * @i2c_dev: Controller's private data
677 * @msg: I2C message to transfer
678 * @is_first: first message of the sequence
679 * @is_last: last message of the sequence
680 */
681static int stm32f4_i2c_xfer_msg(struct stm32f4_i2c_dev *i2c_dev,
682 struct i2c_msg *msg, bool is_first,
683 bool is_last)
684{
685 struct stm32f4_i2c_msg *f4_msg = &i2c_dev->msg;
686 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR1;
687 unsigned long timeout;
688 u32 mask;
689 int ret;
690
691 f4_msg->addr = i2c_8bit_addr_from_msg(msg);
692 f4_msg->buf = msg->buf;
693 f4_msg->count = msg->len;
694 f4_msg->result = 0;
695 f4_msg->stop = is_last;
696
697 reinit_completion(&i2c_dev->complete);
698
699 /* Enable events and errors interrupts */
700 mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN;
701 stm32f4_i2c_set_bits(i2c_dev->base + STM32F4_I2C_CR2, mask);
702
703 if (is_first) {
704 ret = stm32f4_i2c_wait_free_bus(i2c_dev);
705 if (ret)
706 return ret;
707
708 /* START generation */
709 stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
710 }
711
712 timeout = wait_for_completion_timeout(&i2c_dev->complete,
713 i2c_dev->adap.timeout);
714 ret = f4_msg->result;
715
716 if (!timeout)
717 ret = -ETIMEDOUT;
718
719 return ret;
720}
721
722/**
723 * stm32f4_i2c_xfer() - Transfer combined I2C message
724 * @i2c_adap: Adapter pointer to the controller
725 * @msgs: Pointer to data to be written.
726 * @num: Number of messages to be executed
727 */
728static int stm32f4_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[],
729 int num)
730{
731 struct stm32f4_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
732 int ret, i;
733
734 ret = clk_enable(i2c_dev->clk);
735 if (ret) {
736 dev_err(i2c_dev->dev, "Failed to enable clock\n");
737 return ret;
738 }
739
740 for (i = 0; i < num && !ret; i++)
741 ret = stm32f4_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0,
742 i == num - 1);
743
744 clk_disable(i2c_dev->clk);
745
746 return (ret < 0) ? ret : num;
747}
748
749static u32 stm32f4_i2c_func(struct i2c_adapter *adap)
750{
751 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
752}
753
754static struct i2c_algorithm stm32f4_i2c_algo = {
755 .master_xfer = stm32f4_i2c_xfer,
756 .functionality = stm32f4_i2c_func,
757};
758
759static int stm32f4_i2c_probe(struct platform_device *pdev)
760{
761 struct device_node *np = pdev->dev.of_node;
762 struct stm32f4_i2c_dev *i2c_dev;
763 struct resource *res;
764 u32 irq_event, irq_error, clk_rate;
765 struct i2c_adapter *adap;
766 struct reset_control *rst;
767 int ret;
768
769 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
770 if (!i2c_dev)
771 return -ENOMEM;
772
773 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
774 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
775 if (IS_ERR(i2c_dev->base))
776 return PTR_ERR(i2c_dev->base);
777
778 irq_event = irq_of_parse_and_map(np, 0);
779 if (!irq_event) {
780 dev_err(&pdev->dev, "IRQ event missing or invalid\n");
781 return -EINVAL;
782 }
783
784 irq_error = irq_of_parse_and_map(np, 1);
785 if (!irq_error) {
786 dev_err(&pdev->dev, "IRQ error missing or invalid\n");
787 return -EINVAL;
788 }
789
790 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
791 if (IS_ERR(i2c_dev->clk)) {
792 dev_err(&pdev->dev, "Error: Missing controller clock\n");
793 return PTR_ERR(i2c_dev->clk);
794 }
795 ret = clk_prepare_enable(i2c_dev->clk);
796 if (ret) {
797 dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n");
798 return ret;
799 }
800
801 rst = devm_reset_control_get(&pdev->dev, NULL);
802 if (IS_ERR(rst)) {
803 dev_err(&pdev->dev, "Error: Missing controller reset\n");
804 ret = PTR_ERR(rst);
805 goto clk_free;
806 }
807 reset_control_assert(rst);
808 udelay(2);
809 reset_control_deassert(rst);
810
811 i2c_dev->speed = STM32F4_I2C_SPEED_STANDARD;
812 ret = of_property_read_u32(np, "clock-frequency", &clk_rate);
813 if (!ret && clk_rate >= 400000)
814 i2c_dev->speed = STM32F4_I2C_SPEED_FAST;
815
816 i2c_dev->dev = &pdev->dev;
817
818 ret = devm_request_irq(&pdev->dev, irq_event, stm32f4_i2c_isr_event, 0,
819 pdev->name, i2c_dev);
820 if (ret) {
821 dev_err(&pdev->dev, "Failed to request irq event %i\n",
822 irq_event);
823 goto clk_free;
824 }
825
826 ret = devm_request_irq(&pdev->dev, irq_error, stm32f4_i2c_isr_error, 0,
827 pdev->name, i2c_dev);
828 if (ret) {
829 dev_err(&pdev->dev, "Failed to request irq error %i\n",
830 irq_error);
831 goto clk_free;
832 }
833
834 ret = stm32f4_i2c_hw_config(i2c_dev);
835 if (ret)
836 goto clk_free;
837
838 adap = &i2c_dev->adap;
839 i2c_set_adapdata(adap, i2c_dev);
840 snprintf(adap->name, sizeof(adap->name), "STM32 I2C(%pa)", &res->start);
841 adap->owner = THIS_MODULE;
842 adap->timeout = 2 * HZ;
843 adap->retries = 0;
844 adap->algo = &stm32f4_i2c_algo;
845 adap->dev.parent = &pdev->dev;
846 adap->dev.of_node = pdev->dev.of_node;
847
848 init_completion(&i2c_dev->complete);
849
850 ret = i2c_add_adapter(adap);
851 if (ret)
852 goto clk_free;
853
854 platform_set_drvdata(pdev, i2c_dev);
855
856 clk_disable(i2c_dev->clk);
857
858 dev_info(i2c_dev->dev, "STM32F4 I2C driver registered\n");
859
860 return 0;
861
862clk_free:
863 clk_disable_unprepare(i2c_dev->clk);
864 return ret;
865}
866
867static int stm32f4_i2c_remove(struct platform_device *pdev)
868{
869 struct stm32f4_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
870
871 i2c_del_adapter(&i2c_dev->adap);
872
873 clk_unprepare(i2c_dev->clk);
874
875 return 0;
876}
877
878static const struct of_device_id stm32f4_i2c_match[] = {
879 { .compatible = "st,stm32f4-i2c", },
880 {},
881};
882MODULE_DEVICE_TABLE(of, stm32f4_i2c_match);
883
884static struct platform_driver stm32f4_i2c_driver = {
885 .driver = {
886 .name = "stm32f4-i2c",
887 .of_match_table = stm32f4_i2c_match,
888 },
889 .probe = stm32f4_i2c_probe,
890 .remove = stm32f4_i2c_remove,
891};
892
893module_platform_driver(stm32f4_i2c_driver);
894
895MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
896MODULE_DESCRIPTION("STMicroelectronics STM32F4 I2C driver");
897MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-tegra-bpmp.c b/drivers/i2c/busses/i2c-tegra-bpmp.c
new file mode 100644
index 000000000000..9eed69d5e17e
--- /dev/null
+++ b/drivers/i2c/busses/i2c-tegra-bpmp.c
@@ -0,0 +1,346 @@
1/*
2 * drivers/i2c/busses/i2c-tegra-bpmp.c
3 *
4 * Copyright (c) 2016 NVIDIA Corporation. All rights reserved.
5 *
6 * Author: Shardar Shariff Md <smohammed@nvidia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/err.h>
22#include <linux/i2c.h>
23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/of_device.h>
27#include <linux/platform_device.h>
28#include <linux/pm_runtime.h>
29
30#include <soc/tegra/bpmp-abi.h>
31#include <soc/tegra/bpmp.h>
32
33/*
34 * Serialized I2C message header size is 6 bytes and includes address, flags
35 * and length
36 */
37#define SERIALI2C_HDR_SIZE 6
38
39struct tegra_bpmp_i2c {
40 struct i2c_adapter adapter;
41 struct device *dev;
42
43 struct tegra_bpmp *bpmp;
44 unsigned int bus;
45};
46
47/*
48 * Linux flags are translated to BPMP defined I2C flags that are used in BPMP
49 * firmware I2C driver to avoid any issues in future if Linux I2C flags are
50 * changed.
51 */
52static int tegra_bpmp_xlate_flags(u16 flags, u16 *out)
53{
54 if (flags & I2C_M_TEN) {
55 *out |= SERIALI2C_TEN;
56 flags &= ~I2C_M_TEN;
57 }
58
59 if (flags & I2C_M_RD) {
60 *out |= SERIALI2C_RD;
61 flags &= ~I2C_M_RD;
62 }
63
64 if (flags & I2C_M_STOP) {
65 *out |= SERIALI2C_STOP;
66 flags &= ~I2C_M_STOP;
67 }
68
69 if (flags & I2C_M_NOSTART) {
70 *out |= SERIALI2C_NOSTART;
71 flags &= ~I2C_M_NOSTART;
72 }
73
74 if (flags & I2C_M_REV_DIR_ADDR) {
75 *out |= SERIALI2C_REV_DIR_ADDR;
76 flags &= ~I2C_M_REV_DIR_ADDR;
77 }
78
79 if (flags & I2C_M_IGNORE_NAK) {
80 *out |= SERIALI2C_IGNORE_NAK;
81 flags &= ~I2C_M_IGNORE_NAK;
82 }
83
84 if (flags & I2C_M_NO_RD_ACK) {
85 *out |= SERIALI2C_NO_RD_ACK;
86 flags &= ~I2C_M_NO_RD_ACK;
87 }
88
89 if (flags & I2C_M_RECV_LEN) {
90 *out |= SERIALI2C_RECV_LEN;
91 flags &= ~I2C_M_RECV_LEN;
92 }
93
94 return (flags != 0) ? -EINVAL : 0;
95}
96
97/**
98 * The serialized I2C format is simply the following:
99 * [addr little-endian][flags little-endian][len little-endian][data if write]
100 * [addr little-endian][flags little-endian][len little-endian][data if write]
101 * ...
102 *
103 * The flags are translated from Linux kernel representation to seriali2c
104 * representation. Any undefined flag being set causes an error.
105 *
106 * The data is there only for writes. Reads have the data transferred in the
107 * other direction, and thus data is not present.
108 *
109 * See deserialize_i2c documentation for the data format in the other direction.
110 */
111static int tegra_bpmp_serialize_i2c_msg(struct tegra_bpmp_i2c *i2c,
112 struct mrq_i2c_request *request,
113 struct i2c_msg *msgs,
114 unsigned int num)
115{
116 char *buf = request->xfer.data_buf;
117 unsigned int i, j, pos = 0;
118 int err;
119
120 for (i = 0; i < num; i++) {
121 struct i2c_msg *msg = &msgs[i];
122 u16 flags = 0;
123
124 err = tegra_bpmp_xlate_flags(msg->flags, &flags);
125 if (err < 0)
126 return err;
127
128 buf[pos++] = msg->addr & 0xff;
129 buf[pos++] = (msg->addr & 0xff00) >> 8;
130 buf[pos++] = flags & 0xff;
131 buf[pos++] = (flags & 0xff00) >> 8;
132 buf[pos++] = msg->len & 0xff;
133 buf[pos++] = (msg->len & 0xff00) >> 8;
134
135 if ((flags & SERIALI2C_RD) == 0) {
136 for (j = 0; j < msg->len; j++)
137 buf[pos++] = msg->buf[j];
138 }
139 }
140
141 request->xfer.data_size = pos;
142
143 return 0;
144}
145
146/**
147 * The data in the BPMP -> CPU direction is composed of sequential blocks for
148 * those messages that have I2C_M_RD. So, for example, if you have:
149 *
150 * - !I2C_M_RD, len == 5, data == a0 01 02 03 04
151 * - !I2C_M_RD, len == 1, data == a0
152 * - I2C_M_RD, len == 2, data == [uninitialized buffer 1]
153 * - !I2C_M_RD, len == 1, data == a2
154 * - I2C_M_RD, len == 2, data == [uninitialized buffer 2]
155 *
156 * ...then the data in the BPMP -> CPU direction would be 4 bytes total, and
157 * would contain 2 bytes that will go to uninitialized buffer 1, and 2 bytes
158 * that will go to uninitialized buffer 2.
159 */
160static int tegra_bpmp_i2c_deserialize(struct tegra_bpmp_i2c *i2c,
161 struct mrq_i2c_response *response,
162 struct i2c_msg *msgs,
163 unsigned int num)
164{
165 size_t size = response->xfer.data_size, len = 0, pos = 0;
166 char *buf = response->xfer.data_buf;
167 unsigned int i;
168
169 for (i = 0; i < num; i++)
170 if (msgs[i].flags & I2C_M_RD)
171 len += msgs[i].len;
172
173 if (len != size)
174 return -EINVAL;
175
176 for (i = 0; i < num; i++) {
177 if (msgs[i].flags & I2C_M_RD) {
178 memcpy(msgs[i].buf, buf + pos, msgs[i].len);
179 pos += msgs[i].len;
180 }
181 }
182
183 return 0;
184}
185
186static int tegra_bpmp_i2c_msg_len_check(struct i2c_msg *msgs, unsigned int num)
187{
188 size_t tx_len = 0, rx_len = 0;
189 unsigned int i;
190
191 for (i = 0; i < num; i++)
192 if (!(msgs[i].flags & I2C_M_RD))
193 tx_len += SERIALI2C_HDR_SIZE + msgs[i].len;
194
195 if (tx_len > TEGRA_I2C_IPC_MAX_IN_BUF_SIZE)
196 return -EINVAL;
197
198 for (i = 0; i < num; i++)
199 if ((msgs[i].flags & I2C_M_RD))
200 rx_len += msgs[i].len;
201
202 if (rx_len > TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE)
203 return -EINVAL;
204
205 return 0;
206}
207
208static int tegra_bpmp_i2c_msg_xfer(struct tegra_bpmp_i2c *i2c,
209 struct mrq_i2c_request *request,
210 struct mrq_i2c_response *response)
211{
212 struct tegra_bpmp_message msg;
213 int err;
214
215 request->cmd = CMD_I2C_XFER;
216 request->xfer.bus_id = i2c->bus;
217
218 memset(&msg, 0, sizeof(msg));
219 msg.mrq = MRQ_I2C;
220 msg.tx.data = request;
221 msg.tx.size = sizeof(*request);
222 msg.rx.data = response;
223 msg.rx.size = sizeof(*response);
224
225 if (irqs_disabled())
226 err = tegra_bpmp_transfer_atomic(i2c->bpmp, &msg);
227 else
228 err = tegra_bpmp_transfer(i2c->bpmp, &msg);
229
230 return err;
231}
232
233static int tegra_bpmp_i2c_xfer(struct i2c_adapter *adapter,
234 struct i2c_msg *msgs, int num)
235{
236 struct tegra_bpmp_i2c *i2c = i2c_get_adapdata(adapter);
237 struct mrq_i2c_response response;
238 struct mrq_i2c_request request;
239 int err;
240
241 err = tegra_bpmp_i2c_msg_len_check(msgs, num);
242 if (err < 0) {
243 dev_err(i2c->dev, "unsupported message length\n");
244 return err;
245 }
246
247 memset(&request, 0, sizeof(request));
248 memset(&response, 0, sizeof(response));
249
250 err = tegra_bpmp_serialize_i2c_msg(i2c, &request, msgs, num);
251 if (err < 0) {
252 dev_err(i2c->dev, "failed to serialize message: %d\n", err);
253 return err;
254 }
255
256 err = tegra_bpmp_i2c_msg_xfer(i2c, &request, &response);
257 if (err < 0) {
258 dev_err(i2c->dev, "failed to transfer message: %d\n", err);
259 return err;
260 }
261
262 err = tegra_bpmp_i2c_deserialize(i2c, &response, msgs, num);
263 if (err < 0) {
264 dev_err(i2c->dev, "failed to deserialize message: %d\n", err);
265 return err;
266 }
267
268 return num;
269}
270
271static u32 tegra_bpmp_i2c_func(struct i2c_adapter *adapter)
272{
273 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
274 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
275}
276
277static const struct i2c_algorithm tegra_bpmp_i2c_algo = {
278 .master_xfer = tegra_bpmp_i2c_xfer,
279 .functionality = tegra_bpmp_i2c_func,
280};
281
282static int tegra_bpmp_i2c_probe(struct platform_device *pdev)
283{
284 struct tegra_bpmp_i2c *i2c;
285 u32 value;
286 int err;
287
288 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
289 if (!i2c)
290 return -ENOMEM;
291
292 i2c->dev = &pdev->dev;
293
294 i2c->bpmp = dev_get_drvdata(pdev->dev.parent);
295 if (!i2c->bpmp)
296 return -ENODEV;
297
298 err = of_property_read_u32(pdev->dev.of_node, "nvidia,bpmp-bus-id",
299 &value);
300 if (err < 0)
301 return err;
302
303 i2c->bus = value;
304
305 i2c_set_adapdata(&i2c->adapter, i2c);
306 i2c->adapter.owner = THIS_MODULE;
307 strlcpy(i2c->adapter.name, "Tegra BPMP I2C adapter",
308 sizeof(i2c->adapter.name));
309 i2c->adapter.algo = &tegra_bpmp_i2c_algo;
310 i2c->adapter.dev.parent = &pdev->dev;
311 i2c->adapter.dev.of_node = pdev->dev.of_node;
312
313 platform_set_drvdata(pdev, i2c);
314
315 return i2c_add_adapter(&i2c->adapter);
316}
317
318static int tegra_bpmp_i2c_remove(struct platform_device *pdev)
319{
320 struct tegra_bpmp_i2c *i2c = platform_get_drvdata(pdev);
321
322 i2c_del_adapter(&i2c->adapter);
323
324 return 0;
325}
326
327static const struct of_device_id tegra_bpmp_i2c_of_match[] = {
328 { .compatible = "nvidia,tegra186-bpmp-i2c", },
329 { }
330};
331MODULE_DEVICE_TABLE(of, tegra_bpmp_i2c_of_match);
332
333static struct platform_driver tegra_bpmp_i2c_driver = {
334 .driver = {
335 .name = "tegra-bpmp-i2c",
336 .of_match_table = tegra_bpmp_i2c_of_match,
337 },
338 .probe = tegra_bpmp_i2c_probe,
339 .remove = tegra_bpmp_i2c_remove,
340};
341module_platform_driver(tegra_bpmp_i2c_driver);
342
343MODULE_DESCRIPTION("NVIDIA Tegra BPMP I2C bus contoller driver");
344MODULE_AUTHOR("Shardar Shariff Md <smohammed@nvidia.com>");
345MODULE_AUTHOR("Juha-Matti Tilli");
346MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/i2c-thunderx-pcidrv.c
index bba5b429f69c..1d4c2beacf2e 100644
--- a/drivers/i2c/busses/i2c-thunderx-pcidrv.c
+++ b/drivers/i2c/busses/i2c-thunderx-pcidrv.c
@@ -188,11 +188,11 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev,
188 i2c->hlc_int_enable = thunder_i2c_hlc_int_enable; 188 i2c->hlc_int_enable = thunder_i2c_hlc_int_enable;
189 i2c->hlc_int_disable = thunder_i2c_hlc_int_disable; 189 i2c->hlc_int_disable = thunder_i2c_hlc_int_disable;
190 190
191 ret = pci_enable_msix(pdev, &i2c->i2c_msix, 1); 191 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
192 if (ret) 192 if (ret < 0)
193 goto error; 193 goto error;
194 194
195 ret = devm_request_irq(dev, i2c->i2c_msix.vector, octeon_i2c_isr, 0, 195 ret = devm_request_irq(dev, pci_irq_vector(pdev, 0), octeon_i2c_isr, 0,
196 DRV_NAME, i2c); 196 DRV_NAME, i2c);
197 if (ret) 197 if (ret)
198 goto error; 198 goto error;
diff --git a/drivers/i2c/busses/i2c-xgene-slimpro.c b/drivers/i2c/busses/i2c-xgene-slimpro.c
index 0ab1e55558bc..dbe7e44c9321 100644
--- a/drivers/i2c/busses/i2c-xgene-slimpro.c
+++ b/drivers/i2c/busses/i2c-xgene-slimpro.c
@@ -372,7 +372,7 @@ static u32 xgene_slimpro_i2c_func(struct i2c_adapter *adapter)
372 I2C_FUNC_SMBUS_I2C_BLOCK; 372 I2C_FUNC_SMBUS_I2C_BLOCK;
373} 373}
374 374
375static struct i2c_algorithm xgene_slimpro_i2c_algorithm = { 375static const struct i2c_algorithm xgene_slimpro_i2c_algorithm = {
376 .smbus_xfer = xgene_slimpro_i2c_xfer, 376 .smbus_xfer = xgene_slimpro_i2c_xfer,
377 .functionality = xgene_slimpro_i2c_func, 377 .functionality = xgene_slimpro_i2c_func,
378}; 378};
diff --git a/drivers/i2c/busses/i2c-xlp9xx.c b/drivers/i2c/busses/i2c-xlp9xx.c
index 84a8b2eccffb..66b464d52c9c 100644
--- a/drivers/i2c/busses/i2c-xlp9xx.c
+++ b/drivers/i2c/busses/i2c-xlp9xx.c
@@ -334,7 +334,7 @@ static u32 xlp9xx_i2c_functionality(struct i2c_adapter *adapter)
334 I2C_FUNC_10BIT_ADDR; 334 I2C_FUNC_10BIT_ADDR;
335} 335}
336 336
337static struct i2c_algorithm xlp9xx_i2c_algo = { 337static const struct i2c_algorithm xlp9xx_i2c_algo = {
338 .master_xfer = xlp9xx_i2c_xfer, 338 .master_xfer = xlp9xx_i2c_xfer,
339 .functionality = xlp9xx_i2c_functionality, 339 .functionality = xlp9xx_i2c_functionality,
340}; 340};
diff --git a/drivers/i2c/busses/i2c-xlr.c b/drivers/i2c/busses/i2c-xlr.c
index ad17d88d8573..484bfa15d58e 100644
--- a/drivers/i2c/busses/i2c-xlr.c
+++ b/drivers/i2c/busses/i2c-xlr.c
@@ -335,7 +335,7 @@ static u32 xlr_func(struct i2c_adapter *adap)
335 return (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | I2C_FUNC_I2C; 335 return (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | I2C_FUNC_I2C;
336} 336}
337 337
338static struct i2c_algorithm xlr_i2c_algo = { 338static const struct i2c_algorithm xlr_i2c_algo = {
339 .master_xfer = xlr_i2c_xfer, 339 .master_xfer = xlr_i2c_xfer,
340 .functionality = xlr_func, 340 .functionality = xlr_func,
341}; 341};
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index bfb6ba7cac00..d2402bbf6729 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -3705,6 +3705,39 @@ int i2c_slave_unregister(struct i2c_client *client)
3705 return ret; 3705 return ret;
3706} 3706}
3707EXPORT_SYMBOL_GPL(i2c_slave_unregister); 3707EXPORT_SYMBOL_GPL(i2c_slave_unregister);
3708
3709/**
3710 * i2c_detect_slave_mode - detect operation mode
3711 * @dev: The device owning the bus
3712 *
3713 * This checks the device nodes for an I2C slave by checking the address
3714 * used in the reg property. If the address match the I2C_OWN_SLAVE_ADDRESS
3715 * flag this means the device is configured to act as a I2C slave and it will
3716 * be listening at that address.
3717 *
3718 * Returns true if an I2C own slave address is detected, otherwise returns
3719 * false.
3720 */
3721bool i2c_detect_slave_mode(struct device *dev)
3722{
3723 if (IS_BUILTIN(CONFIG_OF) && dev->of_node) {
3724 struct device_node *child;
3725 u32 reg;
3726
3727 for_each_child_of_node(dev->of_node, child) {
3728 of_property_read_u32(child, "reg", &reg);
3729 if (reg & I2C_OWN_SLAVE_ADDRESS) {
3730 of_node_put(child);
3731 return true;
3732 }
3733 }
3734 } else if (IS_BUILTIN(CONFIG_ACPI) && ACPI_HANDLE(dev)) {
3735 dev_dbg(dev, "ACPI slave is not supported yet\n");
3736 }
3737 return false;
3738}
3739EXPORT_SYMBOL_GPL(i2c_detect_slave_mode);
3740
3708#endif 3741#endif
3709 3742
3710MODULE_AUTHOR("Simon G. Vogl <simon@tk.uni-linz.ac.at>"); 3743MODULE_AUTHOR("Simon G. Vogl <simon@tk.uni-linz.ac.at>");
diff --git a/drivers/i2c/muxes/i2c-mux-mlxcpld.c b/drivers/i2c/muxes/i2c-mux-mlxcpld.c
index b7ca249ec9c3..e53f2abd1350 100644
--- a/drivers/i2c/muxes/i2c-mux-mlxcpld.c
+++ b/drivers/i2c/muxes/i2c-mux-mlxcpld.c
@@ -40,7 +40,6 @@
40#include <linux/module.h> 40#include <linux/module.h>
41#include <linux/platform_device.h> 41#include <linux/platform_device.h>
42#include <linux/slab.h> 42#include <linux/slab.h>
43#include <linux/version.h>
44#include <linux/i2c/mlxcpld.h> 43#include <linux/i2c/mlxcpld.h>
45 44
46#define CPLD_MUX_MAX_NCHANS 8 45#define CPLD_MUX_MAX_NCHANS 8
diff --git a/drivers/i2c/muxes/i2c-mux-pca9541.c b/drivers/i2c/muxes/i2c-mux-pca9541.c
index 4ea7e691afc7..77840f7845a1 100644
--- a/drivers/i2c/muxes/i2c-mux-pca9541.c
+++ b/drivers/i2c/muxes/i2c-mux-pca9541.c
@@ -90,6 +90,7 @@ static const struct of_device_id pca9541_of_match[] = {
90 { .compatible = "nxp,pca9541" }, 90 { .compatible = "nxp,pca9541" },
91 {} 91 {}
92}; 92};
93MODULE_DEVICE_TABLE(of, pca9541_of_match);
93#endif 94#endif
94 95
95/* 96/*
diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c
index dd18b9ccb1f4..dfc1c0e37c40 100644
--- a/drivers/i2c/muxes/i2c-mux-pca954x.c
+++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
@@ -41,14 +41,20 @@
41#include <linux/i2c.h> 41#include <linux/i2c.h>
42#include <linux/i2c-mux.h> 42#include <linux/i2c-mux.h>
43#include <linux/i2c/pca954x.h> 43#include <linux/i2c/pca954x.h>
44#include <linux/interrupt.h>
45#include <linux/irq.h>
44#include <linux/module.h> 46#include <linux/module.h>
45#include <linux/of.h> 47#include <linux/of.h>
46#include <linux/of_device.h> 48#include <linux/of_device.h>
49#include <linux/of_irq.h>
47#include <linux/pm.h> 50#include <linux/pm.h>
48#include <linux/slab.h> 51#include <linux/slab.h>
52#include <linux/spinlock.h>
49 53
50#define PCA954X_MAX_NCHANS 8 54#define PCA954X_MAX_NCHANS 8
51 55
56#define PCA954X_IRQ_OFFSET 4
57
52enum pca_type { 58enum pca_type {
53 pca_9540, 59 pca_9540,
54 pca_9542, 60 pca_9542,
@@ -63,6 +69,7 @@ enum pca_type {
63struct chip_desc { 69struct chip_desc {
64 u8 nchans; 70 u8 nchans;
65 u8 enable; /* used for muxes only */ 71 u8 enable; /* used for muxes only */
72 u8 has_irq;
66 enum muxtype { 73 enum muxtype {
67 pca954x_ismux = 0, 74 pca954x_ismux = 0,
68 pca954x_isswi 75 pca954x_isswi
@@ -75,6 +82,10 @@ struct pca954x {
75 u8 last_chan; /* last register value */ 82 u8 last_chan; /* last register value */
76 u8 deselect; 83 u8 deselect;
77 struct i2c_client *client; 84 struct i2c_client *client;
85
86 struct irq_domain *irq;
87 unsigned int irq_mask;
88 spinlock_t lock;
78}; 89};
79 90
80/* Provide specs for the PCA954x types we know about */ 91/* Provide specs for the PCA954x types we know about */
@@ -84,17 +95,26 @@ static const struct chip_desc chips[] = {
84 .enable = 0x4, 95 .enable = 0x4,
85 .muxtype = pca954x_ismux, 96 .muxtype = pca954x_ismux,
86 }, 97 },
98 [pca_9542] = {
99 .nchans = 2,
100 .enable = 0x4,
101 .has_irq = 1,
102 .muxtype = pca954x_ismux,
103 },
87 [pca_9543] = { 104 [pca_9543] = {
88 .nchans = 2, 105 .nchans = 2,
106 .has_irq = 1,
89 .muxtype = pca954x_isswi, 107 .muxtype = pca954x_isswi,
90 }, 108 },
91 [pca_9544] = { 109 [pca_9544] = {
92 .nchans = 4, 110 .nchans = 4,
93 .enable = 0x4, 111 .enable = 0x4,
112 .has_irq = 1,
94 .muxtype = pca954x_ismux, 113 .muxtype = pca954x_ismux,
95 }, 114 },
96 [pca_9545] = { 115 [pca_9545] = {
97 .nchans = 4, 116 .nchans = 4,
117 .has_irq = 1,
98 .muxtype = pca954x_isswi, 118 .muxtype = pca954x_isswi,
99 }, 119 },
100 [pca_9547] = { 120 [pca_9547] = {
@@ -110,7 +130,7 @@ static const struct chip_desc chips[] = {
110 130
111static const struct i2c_device_id pca954x_id[] = { 131static const struct i2c_device_id pca954x_id[] = {
112 { "pca9540", pca_9540 }, 132 { "pca9540", pca_9540 },
113 { "pca9542", pca_9540 }, 133 { "pca9542", pca_9542 },
114 { "pca9543", pca_9543 }, 134 { "pca9543", pca_9543 },
115 { "pca9544", pca_9544 }, 135 { "pca9544", pca_9544 },
116 { "pca9545", pca_9545 }, 136 { "pca9545", pca_9545 },
@@ -124,7 +144,7 @@ MODULE_DEVICE_TABLE(i2c, pca954x_id);
124#ifdef CONFIG_ACPI 144#ifdef CONFIG_ACPI
125static const struct acpi_device_id pca954x_acpi_ids[] = { 145static const struct acpi_device_id pca954x_acpi_ids[] = {
126 { .id = "PCA9540", .driver_data = pca_9540 }, 146 { .id = "PCA9540", .driver_data = pca_9540 },
127 { .id = "PCA9542", .driver_data = pca_9540 }, 147 { .id = "PCA9542", .driver_data = pca_9542 },
128 { .id = "PCA9543", .driver_data = pca_9543 }, 148 { .id = "PCA9543", .driver_data = pca_9543 },
129 { .id = "PCA9544", .driver_data = pca_9544 }, 149 { .id = "PCA9544", .driver_data = pca_9544 },
130 { .id = "PCA9545", .driver_data = pca_9545 }, 150 { .id = "PCA9545", .driver_data = pca_9545 },
@@ -148,6 +168,7 @@ static const struct of_device_id pca954x_of_match[] = {
148 { .compatible = "nxp,pca9548", .data = &chips[pca_9548] }, 168 { .compatible = "nxp,pca9548", .data = &chips[pca_9548] },
149 {} 169 {}
150}; 170};
171MODULE_DEVICE_TABLE(of, pca954x_of_match);
151#endif 172#endif
152 173
153/* Write to mux register. Don't use i2c_transfer()/i2c_smbus_xfer() 174/* Write to mux register. Don't use i2c_transfer()/i2c_smbus_xfer()
@@ -217,6 +238,114 @@ static int pca954x_deselect_mux(struct i2c_mux_core *muxc, u32 chan)
217 return pca954x_reg_write(muxc->parent, client, data->last_chan); 238 return pca954x_reg_write(muxc->parent, client, data->last_chan);
218} 239}
219 240
241static irqreturn_t pca954x_irq_handler(int irq, void *dev_id)
242{
243 struct pca954x *data = dev_id;
244 unsigned int child_irq;
245 int ret, i, handled = 0;
246
247 ret = i2c_smbus_read_byte(data->client);
248 if (ret < 0)
249 return IRQ_NONE;
250
251 for (i = 0; i < data->chip->nchans; i++) {
252 if (ret & BIT(PCA954X_IRQ_OFFSET + i)) {
253 child_irq = irq_linear_revmap(data->irq, i);
254 handle_nested_irq(child_irq);
255 handled++;
256 }
257 }
258 return handled ? IRQ_HANDLED : IRQ_NONE;
259}
260
261static void pca954x_irq_mask(struct irq_data *idata)
262{
263 struct pca954x *data = irq_data_get_irq_chip_data(idata);
264 unsigned int pos = idata->hwirq;
265 unsigned long flags;
266
267 spin_lock_irqsave(&data->lock, flags);
268
269 data->irq_mask &= ~BIT(pos);
270 if (!data->irq_mask)
271 disable_irq(data->client->irq);
272
273 spin_unlock_irqrestore(&data->lock, flags);
274}
275
276static void pca954x_irq_unmask(struct irq_data *idata)
277{
278 struct pca954x *data = irq_data_get_irq_chip_data(idata);
279 unsigned int pos = idata->hwirq;
280 unsigned long flags;
281
282 spin_lock_irqsave(&data->lock, flags);
283
284 if (!data->irq_mask)
285 enable_irq(data->client->irq);
286 data->irq_mask |= BIT(pos);
287
288 spin_unlock_irqrestore(&data->lock, flags);
289}
290
291static int pca954x_irq_set_type(struct irq_data *idata, unsigned int type)
292{
293 if ((type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_LOW)
294 return -EINVAL;
295 return 0;
296}
297
298static struct irq_chip pca954x_irq_chip = {
299 .name = "i2c-mux-pca954x",
300 .irq_mask = pca954x_irq_mask,
301 .irq_unmask = pca954x_irq_unmask,
302 .irq_set_type = pca954x_irq_set_type,
303};
304
305static int pca954x_irq_setup(struct i2c_mux_core *muxc)
306{
307 struct pca954x *data = i2c_mux_priv(muxc);
308 struct i2c_client *client = data->client;
309 int c, err, irq;
310
311 if (!data->chip->has_irq || client->irq <= 0)
312 return 0;
313
314 spin_lock_init(&data->lock);
315
316 data->irq = irq_domain_add_linear(client->dev.of_node,
317 data->chip->nchans,
318 &irq_domain_simple_ops, data);
319 if (!data->irq)
320 return -ENODEV;
321
322 for (c = 0; c < data->chip->nchans; c++) {
323 irq = irq_create_mapping(data->irq, c);
324 irq_set_chip_data(irq, data);
325 irq_set_chip_and_handler(irq, &pca954x_irq_chip,
326 handle_simple_irq);
327 }
328
329 err = devm_request_threaded_irq(&client->dev, data->client->irq, NULL,
330 pca954x_irq_handler,
331 IRQF_ONESHOT | IRQF_SHARED,
332 "pca954x", data);
333 if (err)
334 goto err_req_irq;
335
336 disable_irq(data->client->irq);
337
338 return 0;
339err_req_irq:
340 for (c = 0; c < data->chip->nchans; c++) {
341 irq = irq_find_mapping(data->irq, c);
342 irq_dispose_mapping(irq);
343 }
344 irq_domain_remove(data->irq);
345
346 return err;
347}
348
220/* 349/*
221 * I2C init/probing/exit functions 350 * I2C init/probing/exit functions
222 */ 351 */
@@ -281,6 +410,10 @@ static int pca954x_probe(struct i2c_client *client,
281 idle_disconnect_dt = of_node && 410 idle_disconnect_dt = of_node &&
282 of_property_read_bool(of_node, "i2c-mux-idle-disconnect"); 411 of_property_read_bool(of_node, "i2c-mux-idle-disconnect");
283 412
413 ret = pca954x_irq_setup(muxc);
414 if (ret)
415 goto fail_del_adapters;
416
284 /* Now create an adapter for each channel */ 417 /* Now create an adapter for each channel */
285 for (num = 0; num < data->chip->nchans; num++) { 418 for (num = 0; num < data->chip->nchans; num++) {
286 bool idle_disconnect_pd = false; 419 bool idle_disconnect_pd = false;
@@ -306,7 +439,7 @@ static int pca954x_probe(struct i2c_client *client,
306 dev_err(&client->dev, 439 dev_err(&client->dev,
307 "failed to register multiplexed adapter" 440 "failed to register multiplexed adapter"
308 " %d as bus %d\n", num, force); 441 " %d as bus %d\n", num, force);
309 goto virt_reg_failed; 442 goto fail_del_adapters;
310 } 443 }
311 } 444 }
312 445
@@ -317,7 +450,7 @@ static int pca954x_probe(struct i2c_client *client,
317 450
318 return 0; 451 return 0;
319 452
320virt_reg_failed: 453fail_del_adapters:
321 i2c_mux_del_adapters(muxc); 454 i2c_mux_del_adapters(muxc);
322 return ret; 455 return ret;
323} 456}
@@ -325,6 +458,16 @@ virt_reg_failed:
325static int pca954x_remove(struct i2c_client *client) 458static int pca954x_remove(struct i2c_client *client)
326{ 459{
327 struct i2c_mux_core *muxc = i2c_get_clientdata(client); 460 struct i2c_mux_core *muxc = i2c_get_clientdata(client);
461 struct pca954x *data = i2c_mux_priv(muxc);
462 int c, irq;
463
464 if (data->irq) {
465 for (c = 0; c < data->chip->nchans; c++) {
466 irq = irq_find_mapping(data->irq, c);
467 irq_dispose_mapping(irq);
468 }
469 irq_domain_remove(data->irq);
470 }
328 471
329 i2c_mux_del_adapters(muxc); 472 i2c_mux_del_adapters(muxc);
330 return 0; 473 return 0;
diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
index 051b14766ef9..764ff5df0dbc 100644
--- a/drivers/misc/eeprom/at24.c
+++ b/drivers/misc/eeprom/at24.c
@@ -19,7 +19,7 @@
19#include <linux/log2.h> 19#include <linux/log2.h>
20#include <linux/bitops.h> 20#include <linux/bitops.h>
21#include <linux/jiffies.h> 21#include <linux/jiffies.h>
22#include <linux/of.h> 22#include <linux/property.h>
23#include <linux/acpi.h> 23#include <linux/acpi.h>
24#include <linux/i2c.h> 24#include <linux/i2c.h>
25#include <linux/nvmem-provider.h> 25#include <linux/nvmem-provider.h>
@@ -562,26 +562,26 @@ static int at24_write(void *priv, unsigned int off, void *val, size_t count)
562 return 0; 562 return 0;
563} 563}
564 564
565#ifdef CONFIG_OF 565static void at24_get_pdata(struct device *dev, struct at24_platform_data *chip)
566static void at24_get_ofdata(struct i2c_client *client,
567 struct at24_platform_data *chip)
568{ 566{
569 const __be32 *val; 567 int err;
570 struct device_node *node = client->dev.of_node; 568 u32 val;
571 569
572 if (node) { 570 if (device_property_present(dev, "read-only"))
573 if (of_get_property(node, "read-only", NULL)) 571 chip->flags |= AT24_FLAG_READONLY;
574 chip->flags |= AT24_FLAG_READONLY; 572
575 val = of_get_property(node, "pagesize", NULL); 573 err = device_property_read_u32(dev, "pagesize", &val);
576 if (val) 574 if (!err) {
577 chip->page_size = be32_to_cpup(val); 575 chip->page_size = val;
576 } else {
577 /*
578 * This is slow, but we can't know all eeproms, so we better
579 * play safe. Specifying custom eeprom-types via platform_data
580 * is recommended anyhow.
581 */
582 chip->page_size = 1;
578 } 583 }
579} 584}
580#else
581static void at24_get_ofdata(struct i2c_client *client,
582 struct at24_platform_data *chip)
583{ }
584#endif /* CONFIG_OF */
585 585
586static int at24_probe(struct i2c_client *client, const struct i2c_device_id *id) 586static int at24_probe(struct i2c_client *client, const struct i2c_device_id *id)
587{ 587{
@@ -613,15 +613,8 @@ static int at24_probe(struct i2c_client *client, const struct i2c_device_id *id)
613 chip.byte_len = BIT(magic & AT24_BITMASK(AT24_SIZE_BYTELEN)); 613 chip.byte_len = BIT(magic & AT24_BITMASK(AT24_SIZE_BYTELEN));
614 magic >>= AT24_SIZE_BYTELEN; 614 magic >>= AT24_SIZE_BYTELEN;
615 chip.flags = magic & AT24_BITMASK(AT24_SIZE_FLAGS); 615 chip.flags = magic & AT24_BITMASK(AT24_SIZE_FLAGS);
616 /*
617 * This is slow, but we can't know all eeproms, so we better
618 * play safe. Specifying custom eeprom-types via platform_data
619 * is recommended anyhow.
620 */
621 chip.page_size = 1;
622 616
623 /* update chipdata if OF is present */ 617 at24_get_pdata(&client->dev, &chip);
624 at24_get_ofdata(client, &chip);
625 618
626 chip.setup = NULL; 619 chip.setup = NULL;
627 chip.context = NULL; 620 chip.context = NULL;
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 7b23a3316dcb..bed8fbb45f31 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -283,6 +283,7 @@ enum i2c_slave_event {
283 283
284extern int i2c_slave_register(struct i2c_client *client, i2c_slave_cb_t slave_cb); 284extern int i2c_slave_register(struct i2c_client *client, i2c_slave_cb_t slave_cb);
285extern int i2c_slave_unregister(struct i2c_client *client); 285extern int i2c_slave_unregister(struct i2c_client *client);
286extern bool i2c_detect_slave_mode(struct device *dev);
286 287
287static inline int i2c_slave_event(struct i2c_client *client, 288static inline int i2c_slave_event(struct i2c_client *client,
288 enum i2c_slave_event event, u8 *val) 289 enum i2c_slave_event event, u8 *val)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-25 17:08:18 -0400