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authorAlexander Kochetkov <al.kochet@gmail.com>2014-11-12 20:26:20 -0500
committerDavid S. Miller <davem@davemloft.net>2014-11-13 14:37:53 -0500
commit6ff53fd37175e35dc4f70b0e8f48b28338fbee29 (patch)
tree0e322b0185bec1710b17092092de85d3ebe19b3f
parent242bcd5ba1dcea802c0ad03344f626a727212399 (diff)
net/smsc911x: Fix delays in the PHY enable/disable routines
Increased delay in the smsc911x_phy_disable_energy_detect (from 1ms to 2ms). Dropped delays in the smsc911x_phy_enable_energy_detect (100ms and 1ms). The patch affect SMSC LAN generation 4 chips with integrated PHY (LAN9221). I saw problems with soft reset due to wrong udelay timings. After I fixed udelay, I measured the time needed to bring integrated PHY from power-down to operational mode (the time beetween clearing EDPWRDOWN bit and soft reset complete event). I got 1ms (measured using ktime_get). The value is equal to the current value (1ms) used in the smsc911x_phy_disable_energy_detect. It is near the upper bound and in order to avoid rare soft reset faults it is doubled (2ms). I don't know official timing for bringing up integrated PHY as specs doesn't clarify this (or may be I didn't found). It looks safe to drop delays before and after setting EDPWRDOWN bit (enable PHY power-down mode). I didn't saw any regressions with the patch. The patch was reviewed by Steve Glendinning and Microchip Team. Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Acked-by: Steve Glendinning <steve.glendinning@shawell.net> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/smsc/smsc911x.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/drivers/net/ethernet/smsc/smsc911x.c b/drivers/net/ethernet/smsc/smsc911x.c
index 1e1f6194cb37..c3bf17f89b05 100644
--- a/drivers/net/ethernet/smsc/smsc911x.c
+++ b/drivers/net/ethernet/smsc/smsc911x.c
@@ -1366,8 +1366,8 @@ static int smsc911x_phy_disable_energy_detect(struct smsc911x_data *pdata)
1366 SMSC_WARN(pdata, drv, "Failed writing PHY control reg"); 1366 SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
1367 return rc; 1367 return rc;
1368 } 1368 }
1369 1369 /* Allow PHY to wakeup */
1370 mdelay(1); 1370 mdelay(2);
1371 } 1371 }
1372 1372
1373 return 0; 1373 return 0;
@@ -1389,7 +1389,6 @@ static int smsc911x_phy_enable_energy_detect(struct smsc911x_data *pdata)
1389 1389
1390 /* Only enable if energy detect mode is already disabled */ 1390 /* Only enable if energy detect mode is already disabled */
1391 if (!(rc & MII_LAN83C185_EDPWRDOWN)) { 1391 if (!(rc & MII_LAN83C185_EDPWRDOWN)) {
1392 mdelay(100);
1393 /* Enable energy detect mode for this SMSC Transceivers */ 1392 /* Enable energy detect mode for this SMSC Transceivers */
1394 rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS, 1393 rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS,
1395 rc | MII_LAN83C185_EDPWRDOWN); 1394 rc | MII_LAN83C185_EDPWRDOWN);
@@ -1398,8 +1397,6 @@ static int smsc911x_phy_enable_energy_detect(struct smsc911x_data *pdata)
1398 SMSC_WARN(pdata, drv, "Failed writing PHY control reg"); 1397 SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
1399 return rc; 1398 return rc;
1400 } 1399 }
1401
1402 mdelay(1);
1403 } 1400 }
1404 return 0; 1401 return 0;
1405} 1402}