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authorJubin John <jubin.john@intel.com>2015-09-02 10:43:24 -0400
committerDoug Ledford <dledford@redhat.com>2015-09-03 15:27:45 -0400
commit6fd8edabc2b03203e6bc44e77d1dfff415e706cc (patch)
tree800762a0b0d7fe491ce5eebe7a7d71bb93962d7a
parentb636401f0ec9bbf7931774e00f3adf7ee9214cce (diff)
IB/hfi1: Add CSRs for CONFIG_SDMA_VERBOSITY
3 CSRs needed by the CONFIG_SDMA_VERBOSITY code were removed during the CSR clean up. Adding these CSRs back to resolve 0-day build failure: https://lists.01.org/pipermail/kbuild-all/2015-August/011919.html Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Jubin John <jubin.john@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
-rw-r--r--drivers/staging/rdma/hfi1/chip_registers.h3
-rw-r--r--drivers/staging/rdma/hfi1/sdma.c4
2 files changed, 5 insertions, 2 deletions
diff --git a/drivers/staging/rdma/hfi1/chip_registers.h b/drivers/staging/rdma/hfi1/chip_registers.h
index 6521030018d8..bf45de29d8bd 100644
--- a/drivers/staging/rdma/hfi1/chip_registers.h
+++ b/drivers/staging/rdma/hfi1/chip_registers.h
@@ -1285,5 +1285,8 @@
1285#define PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT 8 1285#define PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT 8
1286#define PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK 0x20ull 1286#define PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK 0x20ull
1287#define PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK 0x10ull 1287#define PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK 0x10ull
1288#define CCE_INT_BLOCKED (CCE + 0x000000110C00)
1289#define SEND_DMA_IDLE_CNT (TXE + 0x000000200040)
1290#define SEND_DMA_DESC_FETCHED_CNT (TXE + 0x000000200058)
1288 1291
1289#endif /* DEF_CHIP_REG */ 1292#endif /* DEF_CHIP_REG */
diff --git a/drivers/staging/rdma/hfi1/sdma.c b/drivers/staging/rdma/hfi1/sdma.c
index 37bd767d6bc0..a8c903caecce 100644
--- a/drivers/staging/rdma/hfi1/sdma.c
+++ b/drivers/staging/rdma/hfi1/sdma.c
@@ -1769,7 +1769,7 @@ void sdma_dumpstate(struct sdma_engine *sde)
1769 sdma_dumpstate_helper(SD(ENG_ERR_MASK)); 1769 sdma_dumpstate_helper(SD(ENG_ERR_MASK));
1770 1770
1771 for (i = 0; i < CCE_NUM_INT_CSRS; ++i) { 1771 for (i = 0; i < CCE_NUM_INT_CSRS; ++i) {
1772 sdma_dumpstate_helper2(CCE_INT_STATUS)); 1772 sdma_dumpstate_helper2(CCE_INT_STATUS);
1773 sdma_dumpstate_helper2(CCE_INT_MASK); 1773 sdma_dumpstate_helper2(CCE_INT_MASK);
1774 sdma_dumpstate_helper2(CCE_INT_BLOCKED); 1774 sdma_dumpstate_helper2(CCE_INT_BLOCKED);
1775 } 1775 }
@@ -1777,7 +1777,7 @@ void sdma_dumpstate(struct sdma_engine *sde)
1777 sdma_dumpstate_helper(SD(TAIL)); 1777 sdma_dumpstate_helper(SD(TAIL));
1778 sdma_dumpstate_helper(SD(HEAD)); 1778 sdma_dumpstate_helper(SD(HEAD));
1779 sdma_dumpstate_helper(SD(PRIORITY_THLD)); 1779 sdma_dumpstate_helper(SD(PRIORITY_THLD));
1780 sdma_dumpstate_helper(SD(IDLE_CNT); 1780 sdma_dumpstate_helper(SD(IDLE_CNT));
1781 sdma_dumpstate_helper(SD(RELOAD_CNT)); 1781 sdma_dumpstate_helper(SD(RELOAD_CNT));
1782 sdma_dumpstate_helper(SD(DESC_CNT)); 1782 sdma_dumpstate_helper(SD(DESC_CNT));
1783 sdma_dumpstate_helper(SD(DESC_FETCHED_CNT)); 1783 sdma_dumpstate_helper(SD(DESC_FETCHED_CNT));