diff options
author | Marc Kleine-Budde <mkl@pengutronix.de> | 2014-09-23 05:03:01 -0400 |
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committer | Marc Kleine-Budde <mkl@pengutronix.de> | 2015-05-06 16:57:27 -0400 |
commit | 6f75fce1ea81b1d91f6f1a8e3dd00b0ce8e83982 (patch) | |
tree | 2dd34fc11be1c386af4ca9083167ac66d8d1894d | |
parent | 66a6ef02294f066b5e059373e798b700b4b73b3b (diff) |
can: flexcan: rename struct flexcan_regs::crl2 -> ctrl2
This is done to mach the abbreviationin of the register in the datasheets.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
-rw-r--r-- | drivers/net/can/flexcan.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c index eb3ebfb47442..69333416d661 100644 --- a/drivers/net/can/flexcan.c +++ b/drivers/net/can/flexcan.c | |||
@@ -93,13 +93,13 @@ | |||
93 | (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) | 93 | (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) |
94 | 94 | ||
95 | /* FLEXCAN control register 2 (CTRL2) bits */ | 95 | /* FLEXCAN control register 2 (CTRL2) bits */ |
96 | #define FLEXCAN_CRL2_ECRWRE BIT(29) | 96 | #define FLEXCAN_CTRL2_ECRWRE BIT(29) |
97 | #define FLEXCAN_CRL2_WRMFRZ BIT(28) | 97 | #define FLEXCAN_CTRL2_WRMFRZ BIT(28) |
98 | #define FLEXCAN_CRL2_RFFN(x) (((x) & 0x0f) << 24) | 98 | #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24) |
99 | #define FLEXCAN_CRL2_TASD(x) (((x) & 0x1f) << 19) | 99 | #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19) |
100 | #define FLEXCAN_CRL2_MRP BIT(18) | 100 | #define FLEXCAN_CTRL2_MRP BIT(18) |
101 | #define FLEXCAN_CRL2_RRS BIT(17) | 101 | #define FLEXCAN_CTRL2_RRS BIT(17) |
102 | #define FLEXCAN_CRL2_EACEN BIT(16) | 102 | #define FLEXCAN_CTRL2_EACEN BIT(16) |
103 | 103 | ||
104 | /* FLEXCAN memory error control register (MECR) bits */ | 104 | /* FLEXCAN memory error control register (MECR) bits */ |
105 | #define FLEXCAN_MECR_ECRWRDIS BIT(31) | 105 | #define FLEXCAN_MECR_ECRWRDIS BIT(31) |
@@ -221,7 +221,7 @@ struct flexcan_regs { | |||
221 | u32 imask1; /* 0x28 */ | 221 | u32 imask1; /* 0x28 */ |
222 | u32 iflag2; /* 0x2c */ | 222 | u32 iflag2; /* 0x2c */ |
223 | u32 iflag1; /* 0x30 */ | 223 | u32 iflag1; /* 0x30 */ |
224 | u32 crl2; /* 0x34 */ | 224 | u32 ctrl2; /* 0x34 */ |
225 | u32 esr2; /* 0x38 */ | 225 | u32 esr2; /* 0x38 */ |
226 | u32 imeur; /* 0x3c */ | 226 | u32 imeur; /* 0x3c */ |
227 | u32 lrfr; /* 0x40 */ | 227 | u32 lrfr; /* 0x40 */ |
@@ -825,7 +825,7 @@ static int flexcan_chip_start(struct net_device *dev) | |||
825 | { | 825 | { |
826 | struct flexcan_priv *priv = netdev_priv(dev); | 826 | struct flexcan_priv *priv = netdev_priv(dev); |
827 | struct flexcan_regs __iomem *regs = priv->base; | 827 | struct flexcan_regs __iomem *regs = priv->base; |
828 | u32 reg_mcr, reg_ctrl, reg_crl2, reg_mecr; | 828 | u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr; |
829 | int err, i; | 829 | int err, i; |
830 | 830 | ||
831 | /* enable module */ | 831 | /* enable module */ |
@@ -928,9 +928,9 @@ static int flexcan_chip_start(struct net_device *dev) | |||
928 | * and Correction of Memory Errors" to write to | 928 | * and Correction of Memory Errors" to write to |
929 | * MECR register | 929 | * MECR register |
930 | */ | 930 | */ |
931 | reg_crl2 = flexcan_read(®s->crl2); | 931 | reg_ctrl2 = flexcan_read(®s->ctrl2); |
932 | reg_crl2 |= FLEXCAN_CRL2_ECRWRE; | 932 | reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE; |
933 | flexcan_write(reg_crl2, ®s->crl2); | 933 | flexcan_write(reg_ctrl2, ®s->ctrl2); |
934 | 934 | ||
935 | reg_mecr = flexcan_read(®s->mecr); | 935 | reg_mecr = flexcan_read(®s->mecr); |
936 | reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS; | 936 | reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS; |