diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-05-27 12:28:34 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-05-27 12:28:34 -0400 |
commit | 6f68a6ae1f0ea2fd87e26dc345866e928b5850a8 (patch) | |
tree | c0e26127ab1236432b99eee29bac640896dbacb0 | |
parent | 38e6bf238daa2514a543f76ec8d1cc0f488ac422 (diff) | |
parent | a4700a26107241cc7b9ac8528b2c6714ff99983d (diff) |
Merge tag 'powerpc-4.12-4' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc fixes from Michael Ellerman:
"Fix running SPU programs on Cell, and a few other minor fixes.
Thanks to Alistair Popple, Jeremy Kerr, Michael Neuling, Nicholas
Piggin"
* tag 'powerpc-4.12-4' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
powerpc: Add PPC_FEATURE userspace bits for SCV and DARN instructions
powerpc/spufs: Fix hash faults for kernel regions
powerpc: Fix booting P9 hash with CONFIG_PPC_RADIX_MMU=N
powerpc/powernv/npu-dma.c: Fix opal_npu_destroy_context() call
selftests/powerpc: Fix TM resched DSCR test with some compilers
-rw-r--r-- | arch/powerpc/include/uapi/asm/cputable.h | 2 | ||||
-rw-r--r-- | arch/powerpc/kernel/cputable.c | 3 | ||||
-rw-r--r-- | arch/powerpc/kernel/prom.c | 2 | ||||
-rw-r--r-- | arch/powerpc/platforms/cell/spu_base.c | 4 | ||||
-rw-r--r-- | arch/powerpc/platforms/powernv/npu-dma.c | 5 | ||||
-rw-r--r-- | tools/testing/selftests/powerpc/tm/tm-resched-dscr.c | 2 |
6 files changed, 12 insertions, 6 deletions
diff --git a/arch/powerpc/include/uapi/asm/cputable.h b/arch/powerpc/include/uapi/asm/cputable.h index 3e7ce86d5c13..4d877144f377 100644 --- a/arch/powerpc/include/uapi/asm/cputable.h +++ b/arch/powerpc/include/uapi/asm/cputable.h | |||
@@ -46,6 +46,8 @@ | |||
46 | #define PPC_FEATURE2_HTM_NOSC 0x01000000 | 46 | #define PPC_FEATURE2_HTM_NOSC 0x01000000 |
47 | #define PPC_FEATURE2_ARCH_3_00 0x00800000 /* ISA 3.00 */ | 47 | #define PPC_FEATURE2_ARCH_3_00 0x00800000 /* ISA 3.00 */ |
48 | #define PPC_FEATURE2_HAS_IEEE128 0x00400000 /* VSX IEEE Binary Float 128-bit */ | 48 | #define PPC_FEATURE2_HAS_IEEE128 0x00400000 /* VSX IEEE Binary Float 128-bit */ |
49 | #define PPC_FEATURE2_DARN 0x00200000 /* darn random number insn */ | ||
50 | #define PPC_FEATURE2_SCV 0x00100000 /* scv syscall */ | ||
49 | 51 | ||
50 | /* | 52 | /* |
51 | * IMPORTANT! | 53 | * IMPORTANT! |
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 9b3e88b1a9c8..6f849832a669 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c | |||
@@ -124,7 +124,8 @@ extern void __restore_cpu_e6500(void); | |||
124 | #define COMMON_USER_POWER9 COMMON_USER_POWER8 | 124 | #define COMMON_USER_POWER9 COMMON_USER_POWER8 |
125 | #define COMMON_USER2_POWER9 (COMMON_USER2_POWER8 | \ | 125 | #define COMMON_USER2_POWER9 (COMMON_USER2_POWER8 | \ |
126 | PPC_FEATURE2_ARCH_3_00 | \ | 126 | PPC_FEATURE2_ARCH_3_00 | \ |
127 | PPC_FEATURE2_HAS_IEEE128) | 127 | PPC_FEATURE2_HAS_IEEE128 | \ |
128 | PPC_FEATURE2_DARN ) | ||
128 | 129 | ||
129 | #ifdef CONFIG_PPC_BOOK3E_64 | 130 | #ifdef CONFIG_PPC_BOOK3E_64 |
130 | #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE) | 131 | #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE) |
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 40c4887c27b6..f83056297441 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c | |||
@@ -161,7 +161,9 @@ static struct ibm_pa_feature { | |||
161 | { .pabyte = 0, .pabit = 3, .cpu_features = CPU_FTR_CTRL }, | 161 | { .pabyte = 0, .pabit = 3, .cpu_features = CPU_FTR_CTRL }, |
162 | { .pabyte = 0, .pabit = 6, .cpu_features = CPU_FTR_NOEXECUTE }, | 162 | { .pabyte = 0, .pabit = 6, .cpu_features = CPU_FTR_NOEXECUTE }, |
163 | { .pabyte = 1, .pabit = 2, .mmu_features = MMU_FTR_CI_LARGE_PAGE }, | 163 | { .pabyte = 1, .pabit = 2, .mmu_features = MMU_FTR_CI_LARGE_PAGE }, |
164 | #ifdef CONFIG_PPC_RADIX_MMU | ||
164 | { .pabyte = 40, .pabit = 0, .mmu_features = MMU_FTR_TYPE_RADIX }, | 165 | { .pabyte = 40, .pabit = 0, .mmu_features = MMU_FTR_TYPE_RADIX }, |
166 | #endif | ||
165 | { .pabyte = 1, .pabit = 1, .invert = 1, .cpu_features = CPU_FTR_NODSISRALIGN }, | 167 | { .pabyte = 1, .pabit = 1, .invert = 1, .cpu_features = CPU_FTR_NODSISRALIGN }, |
166 | { .pabyte = 5, .pabit = 0, .cpu_features = CPU_FTR_REAL_LE, | 168 | { .pabyte = 5, .pabit = 0, .cpu_features = CPU_FTR_REAL_LE, |
167 | .cpu_user_ftrs = PPC_FEATURE_TRUE_LE }, | 169 | .cpu_user_ftrs = PPC_FEATURE_TRUE_LE }, |
diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c index 96c2b8a40630..0c45cdbac4cf 100644 --- a/arch/powerpc/platforms/cell/spu_base.c +++ b/arch/powerpc/platforms/cell/spu_base.c | |||
@@ -197,7 +197,9 @@ static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr) | |||
197 | (REGION_ID(ea) != USER_REGION_ID)) { | 197 | (REGION_ID(ea) != USER_REGION_ID)) { |
198 | 198 | ||
199 | spin_unlock(&spu->register_lock); | 199 | spin_unlock(&spu->register_lock); |
200 | ret = hash_page(ea, _PAGE_PRESENT | _PAGE_READ, 0x300, dsisr); | 200 | ret = hash_page(ea, |
201 | _PAGE_PRESENT | _PAGE_READ | _PAGE_PRIVILEGED, | ||
202 | 0x300, dsisr); | ||
201 | spin_lock(&spu->register_lock); | 203 | spin_lock(&spu->register_lock); |
202 | 204 | ||
203 | if (!ret) { | 205 | if (!ret) { |
diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c index 067defeea691..78fa9395b8c5 100644 --- a/arch/powerpc/platforms/powernv/npu-dma.c +++ b/arch/powerpc/platforms/powernv/npu-dma.c | |||
@@ -714,7 +714,7 @@ static void pnv_npu2_release_context(struct kref *kref) | |||
714 | void pnv_npu2_destroy_context(struct npu_context *npu_context, | 714 | void pnv_npu2_destroy_context(struct npu_context *npu_context, |
715 | struct pci_dev *gpdev) | 715 | struct pci_dev *gpdev) |
716 | { | 716 | { |
717 | struct pnv_phb *nphb, *phb; | 717 | struct pnv_phb *nphb; |
718 | struct npu *npu; | 718 | struct npu *npu; |
719 | struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0); | 719 | struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0); |
720 | struct device_node *nvlink_dn; | 720 | struct device_node *nvlink_dn; |
@@ -728,13 +728,12 @@ void pnv_npu2_destroy_context(struct npu_context *npu_context, | |||
728 | 728 | ||
729 | nphb = pci_bus_to_host(npdev->bus)->private_data; | 729 | nphb = pci_bus_to_host(npdev->bus)->private_data; |
730 | npu = &nphb->npu; | 730 | npu = &nphb->npu; |
731 | phb = pci_bus_to_host(gpdev->bus)->private_data; | ||
732 | nvlink_dn = of_parse_phandle(npdev->dev.of_node, "ibm,nvlink", 0); | 731 | nvlink_dn = of_parse_phandle(npdev->dev.of_node, "ibm,nvlink", 0); |
733 | if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index", | 732 | if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index", |
734 | &nvlink_index))) | 733 | &nvlink_index))) |
735 | return; | 734 | return; |
736 | npu_context->npdev[npu->index][nvlink_index] = NULL; | 735 | npu_context->npdev[npu->index][nvlink_index] = NULL; |
737 | opal_npu_destroy_context(phb->opal_id, npu_context->mm->context.id, | 736 | opal_npu_destroy_context(nphb->opal_id, npu_context->mm->context.id, |
738 | PCI_DEVID(gpdev->bus->number, gpdev->devfn)); | 737 | PCI_DEVID(gpdev->bus->number, gpdev->devfn)); |
739 | kref_put(&npu_context->kref, pnv_npu2_release_context); | 738 | kref_put(&npu_context->kref, pnv_npu2_release_context); |
740 | } | 739 | } |
diff --git a/tools/testing/selftests/powerpc/tm/tm-resched-dscr.c b/tools/testing/selftests/powerpc/tm/tm-resched-dscr.c index d9c49f41515e..e79ccd6aada1 100644 --- a/tools/testing/selftests/powerpc/tm/tm-resched-dscr.c +++ b/tools/testing/selftests/powerpc/tm/tm-resched-dscr.c | |||
@@ -42,12 +42,12 @@ int test_body(void) | |||
42 | printf("Check DSCR TM context switch: "); | 42 | printf("Check DSCR TM context switch: "); |
43 | fflush(stdout); | 43 | fflush(stdout); |
44 | for (;;) { | 44 | for (;;) { |
45 | rv = 1; | ||
46 | asm __volatile__ ( | 45 | asm __volatile__ ( |
47 | /* set a known value into the DSCR */ | 46 | /* set a known value into the DSCR */ |
48 | "ld 3, %[dscr1];" | 47 | "ld 3, %[dscr1];" |
49 | "mtspr %[sprn_dscr], 3;" | 48 | "mtspr %[sprn_dscr], 3;" |
50 | 49 | ||
50 | "li %[rv], 1;" | ||
51 | /* start and suspend a transaction */ | 51 | /* start and suspend a transaction */ |
52 | "tbegin.;" | 52 | "tbegin.;" |
53 | "beq 1f;" | 53 | "beq 1f;" |