diff options
author | Rex Zhu <Rex.Zhu@amd.com> | 2016-12-28 06:50:58 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-01-27 11:12:59 -0500 |
commit | 6f4dc24a88a015ca31c8dbb79f9ad3bcc34f386e (patch) | |
tree | bdcf13f8f084b8c0b9ac7454af13468e9f62ae82 | |
parent | 1c86380248467b99a0d9a9f7fdd0834fa0c6c5aa (diff) |
drm/amd/powerplay: not use module parameter in powerplay.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 |
2 files changed, 3 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index 6bc63f26623d..f4358740a104 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | |||
@@ -66,6 +66,7 @@ int hwmgr_early_init(struct pp_instance *handle) | |||
66 | hwmgr->device = handle->device; | 66 | hwmgr->device = handle->device; |
67 | hwmgr->chip_family = handle->chip_family; | 67 | hwmgr->chip_family = handle->chip_family; |
68 | hwmgr->chip_id = handle->chip_id; | 68 | hwmgr->chip_id = handle->chip_id; |
69 | hwmgr->feature_mask = handle->feature_mask; | ||
69 | hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT; | 70 | hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT; |
70 | hwmgr->power_source = PP_PowerSource_AC; | 71 | hwmgr->power_source = PP_PowerSource_AC; |
71 | hwmgr->pp_table_version = PP_TABLE_V1; | 72 | hwmgr->pp_table_version = PP_TABLE_V1; |
@@ -738,14 +739,14 @@ void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr) | |||
738 | 739 | ||
739 | int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr) | 740 | int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr) |
740 | { | 741 | { |
741 | if (amdgpu_pp_feature_mask & PP_SCLK_DEEP_SLEEP_MASK) | 742 | if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK) |
742 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | 743 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
743 | PHM_PlatformCaps_SclkDeepSleep); | 744 | PHM_PlatformCaps_SclkDeepSleep); |
744 | else | 745 | else |
745 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | 746 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
746 | PHM_PlatformCaps_SclkDeepSleep); | 747 | PHM_PlatformCaps_SclkDeepSleep); |
747 | 748 | ||
748 | if (amdgpu_pp_feature_mask & PP_POWER_CONTAINMENT_MASK) { | 749 | if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { |
749 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | 750 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
750 | PHM_PlatformCaps_PowerContainment); | 751 | PHM_PlatformCaps_PowerContainment); |
751 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, | 752 | phm_cap_set(hwmgr->platform_descriptor.platformCaps, |
@@ -756,7 +757,6 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr) | |||
756 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, | 757 | phm_cap_unset(hwmgr->platform_descriptor.platformCaps, |
757 | PHM_PlatformCaps_CAC); | 758 | PHM_PlatformCaps_CAC); |
758 | } | 759 | } |
759 | hwmgr->feature_mask = amdgpu_pp_feature_mask; | ||
760 | 760 | ||
761 | return 0; | 761 | return 0; |
762 | } | 762 | } |
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index 0d93801f21ea..072350b1e408 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | |||
@@ -38,8 +38,6 @@ struct pp_hwmgr; | |||
38 | struct phm_fan_speed_info; | 38 | struct phm_fan_speed_info; |
39 | struct pp_atomctrl_voltage_table; | 39 | struct pp_atomctrl_voltage_table; |
40 | 40 | ||
41 | extern unsigned amdgpu_pp_feature_mask; | ||
42 | |||
43 | #define VOLTAGE_SCALE 4 | 41 | #define VOLTAGE_SCALE 4 |
44 | 42 | ||
45 | uint8_t convert_to_vid(uint16_t vddc); | 43 | uint8_t convert_to_vid(uint16_t vddc); |