diff options
author | Dave Airlie <airlied@redhat.com> | 2017-03-08 22:45:52 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2017-06-16 16:58:31 -0400 |
commit | 6f0308ebc196f18607f45cc753521eb8448dfdfd (patch) | |
tree | b7e120c9dac34f70fcafea9dd84abb3b43206d93 | |
parent | 64dab074fe5e8852b0c981564dc146f39535a81a (diff) |
amdgpu/cs: split out fence dependency checking (v2)
This just splits out the fence depenency checking into it's
own function to make it easier to add semaphore dependencies.
v2: rebase onto other changes.
v1-Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 93 |
1 files changed, 51 insertions, 42 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index a37bdf4f8e9b..29469e6b58b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | |||
@@ -923,59 +923,68 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, | |||
923 | return 0; | 923 | return 0; |
924 | } | 924 | } |
925 | 925 | ||
926 | static int amdgpu_cs_dependencies(struct amdgpu_device *adev, | 926 | static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p, |
927 | struct amdgpu_cs_parser *p) | 927 | struct amdgpu_cs_chunk *chunk) |
928 | { | 928 | { |
929 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | 929 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
930 | int i, j, r; | 930 | unsigned num_deps; |
931 | int i, r; | ||
932 | struct drm_amdgpu_cs_chunk_dep *deps; | ||
931 | 933 | ||
932 | for (i = 0; i < p->nchunks; ++i) { | 934 | deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; |
933 | struct drm_amdgpu_cs_chunk_dep *deps; | 935 | num_deps = chunk->length_dw * 4 / |
934 | struct amdgpu_cs_chunk *chunk; | 936 | sizeof(struct drm_amdgpu_cs_chunk_dep); |
935 | unsigned num_deps; | ||
936 | 937 | ||
937 | chunk = &p->chunks[i]; | 938 | for (i = 0; i < num_deps; ++i) { |
939 | struct amdgpu_ring *ring; | ||
940 | struct amdgpu_ctx *ctx; | ||
941 | struct dma_fence *fence; | ||
938 | 942 | ||
939 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES) | 943 | ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id); |
940 | continue; | 944 | if (ctx == NULL) |
945 | return -EINVAL; | ||
941 | 946 | ||
942 | deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; | 947 | r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr, |
943 | num_deps = chunk->length_dw * 4 / | 948 | deps[i].ip_type, |
944 | sizeof(struct drm_amdgpu_cs_chunk_dep); | 949 | deps[i].ip_instance, |
950 | deps[i].ring, &ring); | ||
951 | if (r) { | ||
952 | amdgpu_ctx_put(ctx); | ||
953 | return r; | ||
954 | } | ||
945 | 955 | ||
946 | for (j = 0; j < num_deps; ++j) { | 956 | fence = amdgpu_ctx_get_fence(ctx, ring, |
947 | struct amdgpu_ring *ring; | 957 | deps[i].handle); |
948 | struct amdgpu_ctx *ctx; | 958 | if (IS_ERR(fence)) { |
949 | struct dma_fence *fence; | 959 | r = PTR_ERR(fence); |
960 | amdgpu_ctx_put(ctx); | ||
961 | return r; | ||
962 | } else if (fence) { | ||
963 | r = amdgpu_sync_fence(p->adev, &p->job->sync, | ||
964 | fence); | ||
965 | dma_fence_put(fence); | ||
966 | amdgpu_ctx_put(ctx); | ||
967 | if (r) | ||
968 | return r; | ||
969 | } | ||
970 | } | ||
971 | return 0; | ||
972 | } | ||
950 | 973 | ||
951 | ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id); | 974 | static int amdgpu_cs_dependencies(struct amdgpu_device *adev, |
952 | if (ctx == NULL) | 975 | struct amdgpu_cs_parser *p) |
953 | return -EINVAL; | 976 | { |
977 | int i, r; | ||
954 | 978 | ||
955 | r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, | 979 | for (i = 0; i < p->nchunks; ++i) { |
956 | deps[j].ip_type, | 980 | struct amdgpu_cs_chunk *chunk; |
957 | deps[j].ip_instance, | ||
958 | deps[j].ring, &ring); | ||
959 | if (r) { | ||
960 | amdgpu_ctx_put(ctx); | ||
961 | return r; | ||
962 | } | ||
963 | 981 | ||
964 | fence = amdgpu_ctx_get_fence(ctx, ring, | 982 | chunk = &p->chunks[i]; |
965 | deps[j].handle); | ||
966 | if (IS_ERR(fence)) { | ||
967 | r = PTR_ERR(fence); | ||
968 | amdgpu_ctx_put(ctx); | ||
969 | return r; | ||
970 | 983 | ||
971 | } else if (fence) { | 984 | if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) { |
972 | r = amdgpu_sync_fence(adev, &p->job->sync, | 985 | r = amdgpu_cs_process_fence_dep(p, chunk); |
973 | fence); | 986 | if (r) |
974 | dma_fence_put(fence); | 987 | return r; |
975 | amdgpu_ctx_put(ctx); | ||
976 | if (r) | ||
977 | return r; | ||
978 | } | ||
979 | } | 988 | } |
980 | } | 989 | } |
981 | 990 | ||