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authorBen Skeggs <bskeggs@redhat.com>2015-03-25 23:26:20 -0400
committerBen Skeggs <bskeggs@redhat.com>2015-04-14 03:00:54 -0400
commit6eb70826215f3f3ac04b4749ac0de1ac06047e4f (patch)
treeb2c141b92efa37abb4d1b83548e8ba1943d98b66
parent3740c82590d87714b41b8b48bd3062178cbe0b17 (diff)
drm/nouveau/gr/gk104-: correct crop/zrop num_active_fbps setting
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c16
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c8
3 files changed, 11 insertions, 14 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
index 1166b1aa1525..e9852764ac1d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
@@ -88,6 +88,7 @@ void gk104_grctx_generate_bundle(struct gf100_grctx *);
88void gk104_grctx_generate_pagepool(struct gf100_grctx *); 88void gk104_grctx_generate_pagepool(struct gf100_grctx *);
89void gk104_grctx_generate_unkn(struct gf100_gr_priv *); 89void gk104_grctx_generate_unkn(struct gf100_gr_priv *);
90void gk104_grctx_generate_r418bb8(struct gf100_gr_priv *); 90void gk104_grctx_generate_r418bb8(struct gf100_gr_priv *);
91void gk104_grctx_generate_rop_active_fbps(struct gf100_gr_priv *);
91 92
92extern struct nvkm_oclass *gk110_grctx_oclass; 93extern struct nvkm_oclass *gk110_grctx_oclass;
93extern struct nvkm_oclass *gk110b_grctx_oclass; 94extern struct nvkm_oclass *gk110b_grctx_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
index 5e9454ba158f..b12f6a9fd926 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
@@ -941,6 +941,14 @@ gk104_grctx_generate_r418bb8(struct gf100_gr_priv *priv)
941} 941}
942 942
943void 943void
944gk104_grctx_generate_rop_active_fbps(struct gf100_gr_priv *priv)
945{
946 const u32 fbp_count = nv_rd32(priv, 0x120074);
947 nv_mask(priv, 0x408850, 0x0000000f, fbp_count); /* zrop */
948 nv_mask(priv, 0x408958, 0x0000000f, fbp_count); /* crop */
949}
950
951void
944gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) 952gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
945{ 953{
946 struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; 954 struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
@@ -970,13 +978,7 @@ gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
970 nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); 978 nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
971 979
972 nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); 980 nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
973 if (priv->gpc_nr == 1) { 981 gk104_grctx_generate_rop_active_fbps(priv);
974 nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]);
975 nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]);
976 } else {
977 nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr);
978 nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
979 }
980 nv_mask(priv, 0x419f78, 0x00000001, 0x00000000); 982 nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
981 983
982 gf100_gr_icmd(priv, oclass->icmd); 984 gf100_gr_icmd(priv, oclass->icmd);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
index b2fae6e389e2..206f8caafe1c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
@@ -982,13 +982,7 @@ gm107_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
982 982
983 nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); 983 nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
984 984
985 if (priv->gpc_nr == 1) { 985 gk104_grctx_generate_rop_active_fbps(priv);
986 nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]);
987 nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]);
988 } else {
989 nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr);
990 nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
991 }
992 986
993 gf100_gr_icmd(priv, oclass->icmd); 987 gf100_gr_icmd(priv, oclass->icmd);
994 nv_wr32(priv, 0x404154, 0x00000400); 988 nv_wr32(priv, 0x404154, 0x00000400);