serial: imx: ensure UCR3 and UFCR are setup correctly

Commit e61c38d85b73 ("serial: imx: setup DCEDTE early and ensure DCD and
RI irqs to be off") has a flaw: While UCR3 and UFCR were modified using
read-modify-write before it switched to write register values
independent of the previous state. That's a good idea in principle (and
that's why I did it) but needs more care.

This patch reinstates read-modify-write for UFCR and for UCR3 ensures
that RXDMUXSEL and ADNIMP are set for post imx1.

Fixes: e61c38d85b73 ("serial: imx: setup DCEDTE early and ensure DCD and RI irqs to be off")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Mika Penttilä <mika.penttila@nextfour.com>
Tested-by: Mika Penttilä <mika.penttila@nextfour.com>
Acked-by: Steve Twiss <stwiss.opensource@diasemi.com>
Tested-by: Steve Twiss <stwiss.opensource@diasemi.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

1 files changed, 12 insertions, 2 deletions

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 33509b4beaec..bbefddd92bfe 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -2184,7 +2184,9 @@ static int serial_imx_probe(struct platform_device *pdev)
                  * and DCD (when they are outputs) or enables the respective
                  * irqs. So set this bit early, i.e. before requesting irqs.
                  */
-                writel(UFCR_DCEDTE, sport->port.membase + UFCR);
+                reg = readl(sport->port.membase + UFCR);
+                if (!(reg & UFCR_DCEDTE))
+                        writel(reg | UFCR_DCEDTE, sport->port.membase + UFCR);
 
                 /*
                  * Disable UCR3_RI and UCR3_DCD irqs. They are also not
@@ -2195,7 +2197,15 @@ static int serial_imx_probe(struct platform_device *pdev)
                        sport->port.membase + UCR3);
 
         } else {
-                writel(0, sport->port.membase + UFCR);
+                unsigned long ucr3 = UCR3_DSR;
+
+                reg = readl(sport->port.membase + UFCR);
+                if (reg & UFCR_DCEDTE)
+                        writel(reg & ~UFCR_DCEDTE, sport->port.membase + UFCR);
+
+                if (!is_imx1_uart(sport))
+                        ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
+                writel(ucr3, sport->port.membase + UCR3);
         }
 
         clk_disable_unprepare(sport->clk_ipg);