ARM: zynq: DT: Add missing interrupt for L2 pl310

Add pl310 interrupt to the Zynq devicetree.

Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index d373b3860333..ac0a6a09b652 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -139,6 +139,7 @@
                 L2: cache-controller@f8f02000 {
                         compatible = "arm,pl310-cache";
                         reg = <0xF8F02000 0x1000>;
+                        interrupts = <0 2 4>;
                         arm,data-latency = <3 2 2>;
                         arm,tag-latency = <2 2 2>;
                         cache-unified;