diff options
author | Chris Brandt <chris.brandt@renesas.com> | 2016-09-15 15:34:02 -0400 |
---|---|---|
committer | Simon Horman <horms+renesas@verge.net.au> | 2016-10-17 02:20:02 -0400 |
commit | 6c35a666566cf48faaa95699b0d79c6b8cad824c (patch) | |
tree | c498608b51e3f0b4154be3a1bb3ee7bb04ba7e2f | |
parent | 1001354ca34179f3db924eb66672442a173147dc (diff) |
ARM: dts: r7s72100: add mmcif clock to device tree
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r-- | arch/arm/boot/dts/r7s72100.dtsi | 9 | ||||
-rw-r--r-- | include/dt-bindings/clock/r7s72100-clock.h | 3 |
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index fb9ef9ca120e..e18d4e645d6e 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi | |||
@@ -117,6 +117,15 @@ | |||
117 | clock-output-names = "ether"; | 117 | clock-output-names = "ether"; |
118 | }; | 118 | }; |
119 | 119 | ||
120 | mstp8_clks: mstp8_clks@fcfe0434 { | ||
121 | #clock-cells = <1>; | ||
122 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | ||
123 | reg = <0xfcfe0434 4>; | ||
124 | clocks = <&p1_clk>; | ||
125 | clock-indices = <R7S72100_CLK_MMCIF>; | ||
126 | clock-output-names = "mmcif"; | ||
127 | }; | ||
128 | |||
120 | mstp9_clks: mstp9_clks@fcfe0438 { | 129 | mstp9_clks: mstp9_clks@fcfe0438 { |
121 | #clock-cells = <1>; | 130 | #clock-cells = <1>; |
122 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | 131 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; |
diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h index 3cd813896d08..5eaf0fb469c2 100644 --- a/include/dt-bindings/clock/r7s72100-clock.h +++ b/include/dt-bindings/clock/r7s72100-clock.h | |||
@@ -28,6 +28,9 @@ | |||
28 | /* MSTP7 */ | 28 | /* MSTP7 */ |
29 | #define R7S72100_CLK_ETHER 4 | 29 | #define R7S72100_CLK_ETHER 4 |
30 | 30 | ||
31 | /* MSTP8 */ | ||
32 | #define R7S72100_CLK_MMCIF 4 | ||
33 | |||
31 | /* MSTP9 */ | 34 | /* MSTP9 */ |
32 | #define R7S72100_CLK_I2C0 7 | 35 | #define R7S72100_CLK_I2C0 7 |
33 | #define R7S72100_CLK_I2C1 6 | 36 | #define R7S72100_CLK_I2C1 6 |