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authorBoris Brezillon <boris.brezillon@bootlin.com>2018-03-26 05:53:01 -0400
committerBoris Brezillon <boris.brezillon@bootlin.com>2018-03-29 03:38:21 -0400
commit6b6de6543dd5040727afc56a69c7ba6698dd3090 (patch)
tree212003e5d4442abf8800e5eafefc66e8d7b54d7c
parentbb00ff2f4a746db95a44758d45bd3f715169ef6f (diff)
mtd: rawnand: marvell: Rename ->ecc_clk into ->core_clk
The core clock field was badly named ->ecc_clk which might lead to some confusion. Rename it ->core_clk. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
-rw-r--r--drivers/mtd/nand/raw/marvell_nand.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c
index 3d84f4252af4..10e953218948 100644
--- a/drivers/mtd/nand/raw/marvell_nand.c
+++ b/drivers/mtd/nand/raw/marvell_nand.c
@@ -307,7 +307,7 @@ struct marvell_nfc_caps {
307 * @controller: Base controller structure 307 * @controller: Base controller structure
308 * @dev: Parent device (used to print error messages) 308 * @dev: Parent device (used to print error messages)
309 * @regs: NAND controller registers 309 * @regs: NAND controller registers
310 * @ecc_clk: ECC block clock, two times the NAND controller clock 310 * @core_clk: Core clock
311 * @reg_clk: Regiters clock 311 * @reg_clk: Regiters clock
312 * @complete: Completion object to wait for NAND controller events 312 * @complete: Completion object to wait for NAND controller events
313 * @assigned_cs: Bitmask describing already assigned CS lines 313 * @assigned_cs: Bitmask describing already assigned CS lines
@@ -321,7 +321,7 @@ struct marvell_nfc {
321 struct nand_hw_control controller; 321 struct nand_hw_control controller;
322 struct device *dev; 322 struct device *dev;
323 void __iomem *regs; 323 void __iomem *regs;
324 struct clk *ecc_clk; 324 struct clk *core_clk;
325 struct clk *reg_clk; 325 struct clk *reg_clk;
326 struct completion complete; 326 struct completion complete;
327 unsigned long assigned_cs; 327 unsigned long assigned_cs;
@@ -2193,7 +2193,7 @@ static int marvell_nfc_setup_data_interface(struct mtd_info *mtd, int chipnr,
2193 struct nand_chip *chip = mtd_to_nand(mtd); 2193 struct nand_chip *chip = mtd_to_nand(mtd);
2194 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 2194 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
2195 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 2195 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2196 unsigned int period_ns = 1000000000 / clk_get_rate(nfc->ecc_clk) * 2; 2196 unsigned int period_ns = 1000000000 / clk_get_rate(nfc->core_clk) * 2;
2197 const struct nand_sdr_timings *sdr; 2197 const struct nand_sdr_timings *sdr;
2198 struct marvell_nfc_timings nfc_tmg; 2198 struct marvell_nfc_timings nfc_tmg;
2199 int read_delay; 2199 int read_delay;
@@ -2759,16 +2759,16 @@ static int marvell_nfc_probe(struct platform_device *pdev)
2759 return irq; 2759 return irq;
2760 } 2760 }
2761 2761
2762 nfc->ecc_clk = devm_clk_get(&pdev->dev, "core"); 2762 nfc->core_clk = devm_clk_get(&pdev->dev, "core");
2763 2763
2764 /* Managed the legacy case (when the first clock was not named) */ 2764 /* Managed the legacy case (when the first clock was not named) */
2765 if (nfc->ecc_clk == ERR_PTR(-ENOENT)) 2765 if (nfc->core_clk == ERR_PTR(-ENOENT))
2766 nfc->ecc_clk = devm_clk_get(&pdev->dev, NULL); 2766 nfc->core_clk = devm_clk_get(&pdev->dev, NULL);
2767 2767
2768 if (IS_ERR(nfc->ecc_clk)) 2768 if (IS_ERR(nfc->core_clk))
2769 return PTR_ERR(nfc->ecc_clk); 2769 return PTR_ERR(nfc->core_clk);
2770 2770
2771 ret = clk_prepare_enable(nfc->ecc_clk); 2771 ret = clk_prepare_enable(nfc->core_clk);
2772 if (ret) 2772 if (ret)
2773 return ret; 2773 return ret;
2774 2774
@@ -2777,10 +2777,10 @@ static int marvell_nfc_probe(struct platform_device *pdev)
2777 if (!IS_ERR(nfc->reg_clk)) { 2777 if (!IS_ERR(nfc->reg_clk)) {
2778 ret = clk_prepare_enable(nfc->reg_clk); 2778 ret = clk_prepare_enable(nfc->reg_clk);
2779 if (ret) 2779 if (ret)
2780 goto unprepare_ecc_clk; 2780 goto unprepare_core_clk;
2781 } else { 2781 } else {
2782 ret = PTR_ERR(nfc->reg_clk); 2782 ret = PTR_ERR(nfc->reg_clk);
2783 goto unprepare_ecc_clk; 2783 goto unprepare_core_clk;
2784 } 2784 }
2785 } 2785 }
2786 2786
@@ -2818,8 +2818,8 @@ static int marvell_nfc_probe(struct platform_device *pdev)
2818 2818
2819unprepare_reg_clk: 2819unprepare_reg_clk:
2820 clk_disable_unprepare(nfc->reg_clk); 2820 clk_disable_unprepare(nfc->reg_clk);
2821unprepare_ecc_clk: 2821unprepare_core_clk:
2822 clk_disable_unprepare(nfc->ecc_clk); 2822 clk_disable_unprepare(nfc->core_clk);
2823 2823
2824 return ret; 2824 return ret;
2825} 2825}
@@ -2836,7 +2836,7 @@ static int marvell_nfc_remove(struct platform_device *pdev)
2836 } 2836 }
2837 2837
2838 clk_disable_unprepare(nfc->reg_clk); 2838 clk_disable_unprepare(nfc->reg_clk);
2839 clk_disable_unprepare(nfc->ecc_clk); 2839 clk_disable_unprepare(nfc->core_clk);
2840 2840
2841 return 0; 2841 return 0;
2842} 2842}