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authorMaxime Ripard <maxime.ripard@free-electrons.com>2016-10-16 12:54:26 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-01-23 05:45:36 -0500
commit6b48644b1d29d78c146bc94814afe01625dd0f0d (patch)
tree2635dad6a1e4090e1a19485333fa6b009d9c32fe
parent98a59a0fbf80ec6a00c43fd0c62b8bcfe6e1ac24 (diff)
ARM: gr8: Convert to CCU
Now that we have a driver for the GR8, we can convert our DT to it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/sun5i-gr8.dtsi520
1 files changed, 56 insertions, 464 deletions
diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi
index ea86d4d58db6..5165092deffa 100644
--- a/arch/arm/boot/dts/sun5i-gr8.dtsi
+++ b/arch/arm/boot/dts/sun5i-gr8.dtsi
@@ -42,9 +42,10 @@
42 * OTHER DEALINGS IN THE SOFTWARE. 42 * OTHER DEALINGS IN THE SOFTWARE.
43 */ 43 */
44 44
45#include <dt-bindings/clock/sun4i-a10-pll2.h> 45#include <dt-bindings/clock/sun5i-ccu.h>
46#include <dt-bindings/dma/sun4i-a10.h> 46#include <dt-bindings/dma/sun4i-a10.h>
47#include <dt-bindings/pinctrl/sun4i-a10.h> 47#include <dt-bindings/pinctrl/sun4i-a10.h>
48#include <dt-bindings/reset/sun5i-ccu.h>
48 49
49/ { 50/ {
50 interrupt-parent = <&intc>; 51 interrupt-parent = <&intc>;
@@ -59,7 +60,7 @@
59 device_type = "cpu"; 60 device_type = "cpu";
60 compatible = "arm,cortex-a8"; 61 compatible = "arm,cortex-a8";
61 reg = <0x0>; 62 reg = <0x0>;
62 clocks = <&cpu>; 63 clocks = <&ccu CLK_CPU>;
63 }; 64 };
64 }; 65 };
65 66
@@ -68,419 +69,19 @@
68 #size-cells = <1>; 69 #size-cells = <1>;
69 ranges; 70 ranges;
70 71
71 /*
72 * This is a dummy clock, to be used as placeholder on
73 * other mux clocks when a specific parent clock is not
74 * yet implemented. It should be dropped when the driver
75 * is complete.
76 */
77 dummy: dummy {
78 #clock-cells = <0>;
79 compatible = "fixed-clock";
80 clock-frequency = <0>;
81 };
82
83 osc24M: clk@01c20050 { 72 osc24M: clk@01c20050 {
84 #clock-cells = <0>; 73 #clock-cells = <0>;
85 compatible = "allwinner,sun4i-a10-osc-clk"; 74 compatible = "fixed-clock";
86 reg = <0x01c20050 0x4>;
87 clock-frequency = <24000000>; 75 clock-frequency = <24000000>;
88 clock-output-names = "osc24M"; 76 clock-output-names = "osc24M";
89 }; 77 };
90 78
91 osc3M: osc3M-clk {
92 compatible = "fixed-factor-clock";
93 #clock-cells = <0>;
94 clock-div = <8>;
95 clock-mult = <1>;
96 clocks = <&osc24M>;
97 clock-output-names = "osc3M";
98 };
99
100 osc32k: clk@0 { 79 osc32k: clk@0 {
101 #clock-cells = <0>; 80 #clock-cells = <0>;
102 compatible = "fixed-clock"; 81 compatible = "fixed-clock";
103 clock-frequency = <32768>; 82 clock-frequency = <32768>;
104 clock-output-names = "osc32k"; 83 clock-output-names = "osc32k";
105 }; 84 };
106
107 pll1: clk@01c20000 {
108 #clock-cells = <0>;
109 compatible = "allwinner,sun4i-a10-pll1-clk";
110 reg = <0x01c20000 0x4>;
111 clocks = <&osc24M>;
112 clock-output-names = "pll1";
113 };
114
115 pll2: clk@01c20008 {
116 #clock-cells = <1>;
117 compatible = "allwinner,sun5i-a13-pll2-clk";
118 reg = <0x01c20008 0x8>;
119 clocks = <&osc24M>;
120 clock-output-names = "pll2-1x", "pll2-2x",
121 "pll2-4x", "pll2-8x";
122 };
123
124 pll3: clk@01c20010 {
125 #clock-cells = <0>;
126 compatible = "allwinner,sun4i-a10-pll3-clk";
127 reg = <0x01c20010 0x4>;
128 clocks = <&osc3M>;
129 clock-output-names = "pll3";
130 };
131
132 pll3x2: pll3x2-clk {
133 compatible = "allwinner,sun4i-a10-pll3-2x-clk";
134 #clock-cells = <0>;
135 clock-div = <1>;
136 clock-mult = <2>;
137 clocks = <&pll3>;
138 clock-output-names = "pll3-2x";
139 };
140
141 pll4: clk@01c20018 {
142 #clock-cells = <0>;
143 compatible = "allwinner,sun4i-a10-pll1-clk";
144 reg = <0x01c20018 0x4>;
145 clocks = <&osc24M>;
146 clock-output-names = "pll4";
147 };
148
149 pll5: clk@01c20020 {
150 #clock-cells = <1>;
151 compatible = "allwinner,sun4i-a10-pll5-clk";
152 reg = <0x01c20020 0x4>;
153 clocks = <&osc24M>;
154 clock-output-names = "pll5_ddr", "pll5_other";
155 };
156
157 pll6: clk@01c20028 {
158 #clock-cells = <1>;
159 compatible = "allwinner,sun4i-a10-pll6-clk";
160 reg = <0x01c20028 0x4>;
161 clocks = <&osc24M>;
162 clock-output-names = "pll6_sata", "pll6_other", "pll6";
163 };
164
165 pll7: clk@01c20030 {
166 #clock-cells = <0>;
167 compatible = "allwinner,sun4i-a10-pll3-clk";
168 reg = <0x01c20030 0x4>;
169 clocks = <&osc3M>;
170 clock-output-names = "pll7";
171 };
172
173 pll7x2: pll7x2-clk {
174 compatible = "allwinner,sun4i-a10-pll3-2x-clk";
175 #clock-cells = <0>;
176 clock-div = <1>;
177 clock-mult = <2>;
178 clocks = <&pll7>;
179 clock-output-names = "pll7-2x";
180 };
181
182 /* dummy is 200M */
183 cpu: cpu@01c20054 {
184 #clock-cells = <0>;
185 compatible = "allwinner,sun4i-a10-cpu-clk";
186 reg = <0x01c20054 0x4>;
187 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
188 clock-output-names = "cpu";
189 };
190
191 axi: axi@01c20054 {
192 #clock-cells = <0>;
193 compatible = "allwinner,sun4i-a10-axi-clk";
194 reg = <0x01c20054 0x4>;
195 clocks = <&cpu>;
196 clock-output-names = "axi";
197 };
198
199 ahb: ahb@01c20054 {
200 #clock-cells = <0>;
201 compatible = "allwinner,sun5i-a13-ahb-clk";
202 reg = <0x01c20054 0x4>;
203 clocks = <&axi>, <&cpu>, <&pll6 1>;
204 clock-output-names = "ahb";
205 /*
206 * Use PLL6 as parent, instead of CPU/AXI
207 * which has rate changes due to cpufreq
208 */
209 assigned-clocks = <&ahb>;
210 assigned-clock-parents = <&pll6 1>;
211 };
212
213 apb0: apb0@01c20054 {
214 #clock-cells = <0>;
215 compatible = "allwinner,sun4i-a10-apb0-clk";
216 reg = <0x01c20054 0x4>;
217 clocks = <&ahb>;
218 clock-output-names = "apb0";
219 };
220
221 apb1: clk@01c20058 {
222 #clock-cells = <0>;
223 compatible = "allwinner,sun4i-a10-apb1-clk";
224 reg = <0x01c20058 0x4>;
225 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
226 clock-output-names = "apb1";
227 };
228
229 axi_gates: clk@01c2005c {
230 #clock-cells = <1>;
231 compatible = "allwinner,sun4i-a10-gates-clk";
232 reg = <0x01c2005c 0x4>;
233 clocks = <&axi>;
234 clock-indices = <0>;
235 clock-output-names = "axi_dram";
236 };
237
238 ahb_gates: clk@01c20060 {
239 #clock-cells = <1>;
240 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
241 reg = <0x01c20060 0x8>;
242 clocks = <&ahb>;
243 clock-indices = <0>, <1>,
244 <2>, <5>, <6>,
245 <7>, <8>, <9>,
246 <10>, <13>,
247 <14>, <17>, <20>,
248 <21>, <22>,
249 <28>, <32>, <34>,
250 <36>, <40>, <44>,
251 <46>, <51>,
252 <52>;
253 clock-output-names = "ahb_usbotg", "ahb_ehci",
254 "ahb_ohci", "ahb_ss", "ahb_dma",
255 "ahb_bist", "ahb_mmc0", "ahb_mmc1",
256 "ahb_mmc2", "ahb_nand",
257 "ahb_sdram", "ahb_emac", "ahb_spi0",
258 "ahb_spi1", "ahb_spi2",
259 "ahb_hstimer", "ahb_ve", "ahb_tve",
260 "ahb_lcd", "ahb_csi", "ahb_de_be",
261 "ahb_de_fe", "ahb_iep",
262 "ahb_mali400";
263 };
264
265 apb0_gates: clk@01c20068 {
266 #clock-cells = <1>;
267 compatible = "allwinner,sun4i-a10-gates-clk";
268 reg = <0x01c20068 0x4>;
269 clocks = <&apb0>;
270 clock-indices = <0>, <3>,
271 <5>, <6>;
272 clock-output-names = "apb0_codec", "apb0_i2s0",
273 "apb0_pio", "apb0_ir";
274 };
275
276 apb1_gates: clk@01c2006c {
277 #clock-cells = <1>;
278 compatible = "allwinner,sun4i-a10-gates-clk";
279 reg = <0x01c2006c 0x4>;
280 clocks = <&apb1>;
281 clock-indices = <0>, <1>,
282 <2>, <17>,
283 <18>, <19>;
284 clock-output-names = "apb1_i2c0", "apb1_i2c1",
285 "apb1_i2c2", "apb1_uart1",
286 "apb1_uart2", "apb1_uart3";
287 };
288
289 nand_clk: clk@01c20080 {
290 #clock-cells = <0>;
291 compatible = "allwinner,sun4i-a10-mod0-clk";
292 reg = <0x01c20080 0x4>;
293 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
294 clock-output-names = "nand";
295 };
296
297 ms_clk: clk@01c20084 {
298 #clock-cells = <0>;
299 compatible = "allwinner,sun4i-a10-mod0-clk";
300 reg = <0x01c20084 0x4>;
301 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
302 clock-output-names = "ms";
303 };
304
305 mmc0_clk: clk@01c20088 {
306 #clock-cells = <1>;
307 compatible = "allwinner,sun4i-a10-mmc-clk";
308 reg = <0x01c20088 0x4>;
309 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
310 clock-output-names = "mmc0",
311 "mmc0_output",
312 "mmc0_sample";
313 };
314
315 mmc1_clk: clk@01c2008c {
316 #clock-cells = <1>;
317 compatible = "allwinner,sun4i-a10-mmc-clk";
318 reg = <0x01c2008c 0x4>;
319 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
320 clock-output-names = "mmc1",
321 "mmc1_output",
322 "mmc1_sample";
323 };
324
325 mmc2_clk: clk@01c20090 {
326 #clock-cells = <1>;
327 compatible = "allwinner,sun4i-a10-mmc-clk";
328 reg = <0x01c20090 0x4>;
329 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
330 clock-output-names = "mmc2",
331 "mmc2_output",
332 "mmc2_sample";
333 };
334
335 ts_clk: clk@01c20098 {
336 #clock-cells = <0>;
337 compatible = "allwinner,sun4i-a10-mod0-clk";
338 reg = <0x01c20098 0x4>;
339 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
340 clock-output-names = "ts";
341 };
342
343 ss_clk: clk@01c2009c {
344 #clock-cells = <0>;
345 compatible = "allwinner,sun4i-a10-mod0-clk";
346 reg = <0x01c2009c 0x4>;
347 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
348 clock-output-names = "ss";
349 };
350
351 spi0_clk: clk@01c200a0 {
352 #clock-cells = <0>;
353 compatible = "allwinner,sun4i-a10-mod0-clk";
354 reg = <0x01c200a0 0x4>;
355 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
356 clock-output-names = "spi0";
357 };
358
359 spi1_clk: clk@01c200a4 {
360 #clock-cells = <0>;
361 compatible = "allwinner,sun4i-a10-mod0-clk";
362 reg = <0x01c200a4 0x4>;
363 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
364 clock-output-names = "spi1";
365 };
366
367 spi2_clk: clk@01c200a8 {
368 #clock-cells = <0>;
369 compatible = "allwinner,sun4i-a10-mod0-clk";
370 reg = <0x01c200a8 0x4>;
371 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
372 clock-output-names = "spi2";
373 };
374
375 ir0_clk: clk@01c200b0 {
376 #clock-cells = <0>;
377 compatible = "allwinner,sun4i-a10-mod0-clk";
378 reg = <0x01c200b0 0x4>;
379 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
380 clock-output-names = "ir0";
381 };
382
383 i2s0_clk: clk@01c200b8 {
384 #clock-cells = <0>;
385 compatible = "allwinner,sun4i-a10-mod1-clk";
386 reg = <0x01c200b8 0x4>;
387 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
388 <&pll2 SUN4I_A10_PLL2_4X>,
389 <&pll2 SUN4I_A10_PLL2_2X>,
390 <&pll2 SUN4I_A10_PLL2_1X>;
391 clock-output-names = "i2s0";
392 };
393
394 spdif_clk: clk@01c200c0 {
395 #clock-cells = <0>;
396 compatible = "allwinner,sun4i-a10-mod1-clk";
397 reg = <0x01c200c0 0x4>;
398 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
399 <&pll2 SUN4I_A10_PLL2_4X>,
400 <&pll2 SUN4I_A10_PLL2_2X>,
401 <&pll2 SUN4I_A10_PLL2_1X>;
402 clock-output-names = "spdif";
403 };
404
405 usb_clk: clk@01c200cc {
406 #clock-cells = <1>;
407 #reset-cells = <1>;
408 compatible = "allwinner,sun5i-a13-usb-clk";
409 reg = <0x01c200cc 0x4>;
410 clocks = <&pll6 1>;
411 clock-output-names = "usb_ohci0", "usb_phy";
412 };
413
414 dram_gates: clk@01c20100 {
415 #clock-cells = <1>;
416 compatible = "nextthing,gr8-dram-gates-clk",
417 "allwinner,sun4i-a10-gates-clk";
418 reg = <0x01c20100 0x4>;
419 clocks = <&pll5 0>;
420 clock-indices = <0>,
421 <1>,
422 <25>,
423 <26>,
424 <29>,
425 <31>;
426 clock-output-names = "dram_ve",
427 "dram_csi",
428 "dram_de_fe",
429 "dram_de_be",
430 "dram_ace",
431 "dram_iep";
432 };
433
434 de_be_clk: clk@01c20104 {
435 #clock-cells = <0>;
436 #reset-cells = <0>;
437 compatible = "allwinner,sun4i-a10-display-clk";
438 reg = <0x01c20104 0x4>;
439 clocks = <&pll3>, <&pll7>, <&pll5 1>;
440 clock-output-names = "de-be";
441 };
442
443 de_fe_clk: clk@01c2010c {
444 #clock-cells = <0>;
445 #reset-cells = <0>;
446 compatible = "allwinner,sun4i-a10-display-clk";
447 reg = <0x01c2010c 0x4>;
448 clocks = <&pll3>, <&pll7>, <&pll5 1>;
449 clock-output-names = "de-fe";
450 };
451
452 tcon_ch0_clk: clk@01c20118 {
453 #clock-cells = <0>;
454 #reset-cells = <1>;
455 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
456 reg = <0x01c20118 0x4>;
457 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
458 clock-output-names = "tcon-ch0-sclk";
459 };
460
461 tcon_ch1_clk: clk@01c2012c {
462 #clock-cells = <0>;
463 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
464 reg = <0x01c2012c 0x4>;
465 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
466 clock-output-names = "tcon-ch1-sclk";
467 };
468
469 codec_clk: clk@01c20140 {
470 #clock-cells = <0>;
471 compatible = "allwinner,sun4i-a10-codec-clk";
472 reg = <0x01c20140 0x4>;
473 clocks = <&pll2 SUN4I_A10_PLL2_1X>;
474 clock-output-names = "codec";
475 };
476
477 mbus_clk: clk@01c2015c {
478 #clock-cells = <0>;
479 compatible = "allwinner,sun5i-a13-mbus-clk";
480 reg = <0x01c2015c 0x4>;
481 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
482 clock-output-names = "mbus";
483 };
484 }; 85 };
485 86
486 display-engine { 87 display-engine {
@@ -528,7 +129,7 @@
528 compatible = "allwinner,sun4i-a10-dma"; 129 compatible = "allwinner,sun4i-a10-dma";
529 reg = <0x01c02000 0x1000>; 130 reg = <0x01c02000 0x1000>;
530 interrupts = <27>; 131 interrupts = <27>;
531 clocks = <&ahb_gates 6>; 132 clocks = <&ccu CLK_AHB_DMA>;
532 #dma-cells = <2>; 133 #dma-cells = <2>;
533 }; 134 };
534 135
@@ -536,7 +137,7 @@
536 compatible = "allwinner,sun4i-a10-nand"; 137 compatible = "allwinner,sun4i-a10-nand";
537 reg = <0x01c03000 0x1000>; 138 reg = <0x01c03000 0x1000>;
538 interrupts = <37>; 139 interrupts = <37>;
539 clocks = <&ahb_gates 13>, <&nand_clk>; 140 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
540 clock-names = "ahb", "mod"; 141 clock-names = "ahb", "mod";
541 dmas = <&dma SUN4I_DMA_DEDICATED 3>; 142 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
542 dma-names = "rxtx"; 143 dma-names = "rxtx";
@@ -549,7 +150,7 @@
549 compatible = "allwinner,sun4i-a10-spi"; 150 compatible = "allwinner,sun4i-a10-spi";
550 reg = <0x01c05000 0x1000>; 151 reg = <0x01c05000 0x1000>;
551 interrupts = <10>; 152 interrupts = <10>;
552 clocks = <&ahb_gates 20>, <&spi0_clk>; 153 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
553 clock-names = "ahb", "mod"; 154 clock-names = "ahb", "mod";
554 dmas = <&dma SUN4I_DMA_DEDICATED 27>, 155 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
555 <&dma SUN4I_DMA_DEDICATED 26>; 156 <&dma SUN4I_DMA_DEDICATED 26>;
@@ -563,7 +164,7 @@
563 compatible = "allwinner,sun4i-a10-spi"; 164 compatible = "allwinner,sun4i-a10-spi";
564 reg = <0x01c06000 0x1000>; 165 reg = <0x01c06000 0x1000>;
565 interrupts = <11>; 166 interrupts = <11>;
566 clocks = <&ahb_gates 21>, <&spi1_clk>; 167 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
567 clock-names = "ahb", "mod"; 168 clock-names = "ahb", "mod";
568 dmas = <&dma SUN4I_DMA_DEDICATED 9>, 169 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
569 <&dma SUN4I_DMA_DEDICATED 8>; 170 <&dma SUN4I_DMA_DEDICATED 8>;
@@ -576,8 +177,8 @@
576 tve0: tv-encoder@01c0a000 { 177 tve0: tv-encoder@01c0a000 {
577 compatible = "allwinner,sun4i-a10-tv-encoder"; 178 compatible = "allwinner,sun4i-a10-tv-encoder";
578 reg = <0x01c0a000 0x1000>; 179 reg = <0x01c0a000 0x1000>;
579 clocks = <&ahb_gates 34>; 180 clocks = <&ccu CLK_AHB_TVE>;
580 resets = <&tcon_ch0_clk 0>; 181 resets = <&ccu RST_TVE>;
581 status = "disabled"; 182 status = "disabled";
582 183
583 port { 184 port {
@@ -595,11 +196,11 @@
595 compatible = "allwinner,sun5i-a13-tcon"; 196 compatible = "allwinner,sun5i-a13-tcon";
596 reg = <0x01c0c000 0x1000>; 197 reg = <0x01c0c000 0x1000>;
597 interrupts = <44>; 198 interrupts = <44>;
598 resets = <&tcon_ch0_clk 1>; 199 resets = <&ccu RST_LCD>;
599 reset-names = "lcd"; 200 reset-names = "lcd";
600 clocks = <&ahb_gates 36>, 201 clocks = <&ccu CLK_AHB_LCD>,
601 <&tcon_ch0_clk>, 202 <&ccu CLK_TCON_CH0>,
602 <&tcon_ch1_clk>; 203 <&ccu CLK_TCON_CH1>;
603 clock-names = "ahb", 204 clock-names = "ahb",
604 "tcon-ch0", 205 "tcon-ch0",
605 "tcon-ch1"; 206 "tcon-ch1";
@@ -637,14 +238,8 @@
637 mmc0: mmc@01c0f000 { 238 mmc0: mmc@01c0f000 {
638 compatible = "allwinner,sun5i-a13-mmc"; 239 compatible = "allwinner,sun5i-a13-mmc";
639 reg = <0x01c0f000 0x1000>; 240 reg = <0x01c0f000 0x1000>;
640 clocks = <&ahb_gates 8>, 241 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
641 <&mmc0_clk 0>, 242 clock-names = "ahb", "mmc";
642 <&mmc0_clk 1>,
643 <&mmc0_clk 2>;
644 clock-names = "ahb",
645 "mmc",
646 "output",
647 "sample";
648 interrupts = <32>; 243 interrupts = <32>;
649 status = "disabled"; 244 status = "disabled";
650 #address-cells = <1>; 245 #address-cells = <1>;
@@ -654,14 +249,8 @@
654 mmc1: mmc@01c10000 { 249 mmc1: mmc@01c10000 {
655 compatible = "allwinner,sun5i-a13-mmc"; 250 compatible = "allwinner,sun5i-a13-mmc";
656 reg = <0x01c10000 0x1000>; 251 reg = <0x01c10000 0x1000>;
657 clocks = <&ahb_gates 9>, 252 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
658 <&mmc1_clk 0>, 253 clock-names = "ahb", "mmc";
659 <&mmc1_clk 1>,
660 <&mmc1_clk 2>;
661 clock-names = "ahb",
662 "mmc",
663 "output",
664 "sample";
665 interrupts = <33>; 254 interrupts = <33>;
666 status = "disabled"; 255 status = "disabled";
667 #address-cells = <1>; 256 #address-cells = <1>;
@@ -671,14 +260,8 @@
671 mmc2: mmc@01c11000 { 260 mmc2: mmc@01c11000 {
672 compatible = "allwinner,sun5i-a13-mmc"; 261 compatible = "allwinner,sun5i-a13-mmc";
673 reg = <0x01c11000 0x1000>; 262 reg = <0x01c11000 0x1000>;
674 clocks = <&ahb_gates 10>, 263 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
675 <&mmc2_clk 0>, 264 clock-names = "ahb", "mmc";
676 <&mmc2_clk 1>,
677 <&mmc2_clk 2>;
678 clock-names = "ahb",
679 "mmc",
680 "output",
681 "sample";
682 interrupts = <34>; 265 interrupts = <34>;
683 status = "disabled"; 266 status = "disabled";
684 #address-cells = <1>; 267 #address-cells = <1>;
@@ -688,7 +271,7 @@
688 usb_otg: usb@01c13000 { 271 usb_otg: usb@01c13000 {
689 compatible = "allwinner,sun4i-a10-musb"; 272 compatible = "allwinner,sun4i-a10-musb";
690 reg = <0x01c13000 0x0400>; 273 reg = <0x01c13000 0x0400>;
691 clocks = <&ahb_gates 0>; 274 clocks = <&ccu CLK_AHB_OTG>;
692 interrupts = <38>; 275 interrupts = <38>;
693 interrupt-names = "mc"; 276 interrupt-names = "mc";
694 phys = <&usbphy 0>; 277 phys = <&usbphy 0>;
@@ -705,9 +288,9 @@
705 compatible = "allwinner,sun5i-a13-usb-phy"; 288 compatible = "allwinner,sun5i-a13-usb-phy";
706 reg = <0x01c13400 0x10 0x01c14800 0x4>; 289 reg = <0x01c13400 0x10 0x01c14800 0x4>;
707 reg-names = "phy_ctrl", "pmu1"; 290 reg-names = "phy_ctrl", "pmu1";
708 clocks = <&usb_clk 8>; 291 clocks = <&ccu CLK_USB_PHY0>;
709 clock-names = "usb_phy"; 292 clock-names = "usb_phy";
710 resets = <&usb_clk 0>, <&usb_clk 1>; 293 resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
711 reset-names = "usb0_reset", "usb1_reset"; 294 reset-names = "usb0_reset", "usb1_reset";
712 status = "disabled"; 295 status = "disabled";
713 }; 296 };
@@ -716,7 +299,7 @@
716 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; 299 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
717 reg = <0x01c14000 0x100>; 300 reg = <0x01c14000 0x100>;
718 interrupts = <39>; 301 interrupts = <39>;
719 clocks = <&ahb_gates 1>; 302 clocks = <&ccu CLK_AHB_EHCI>;
720 phys = <&usbphy 1>; 303 phys = <&usbphy 1>;
721 phy-names = "usb"; 304 phy-names = "usb";
722 status = "disabled"; 305 status = "disabled";
@@ -726,7 +309,7 @@
726 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; 309 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
727 reg = <0x01c14400 0x100>; 310 reg = <0x01c14400 0x100>;
728 interrupts = <40>; 311 interrupts = <40>;
729 clocks = <&usb_clk 6>, <&ahb_gates 2>; 312 clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
730 phys = <&usbphy 1>; 313 phys = <&usbphy 1>;
731 phy-names = "usb"; 314 phy-names = "usb";
732 status = "disabled"; 315 status = "disabled";
@@ -736,7 +319,7 @@
736 compatible = "allwinner,sun4i-a10-spi"; 319 compatible = "allwinner,sun4i-a10-spi";
737 reg = <0x01c17000 0x1000>; 320 reg = <0x01c17000 0x1000>;
738 interrupts = <12>; 321 interrupts = <12>;
739 clocks = <&ahb_gates 22>, <&spi2_clk>; 322 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
740 clock-names = "ahb", "mod"; 323 clock-names = "ahb", "mod";
741 dmas = <&dma SUN4I_DMA_DEDICATED 29>, 324 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
742 <&dma SUN4I_DMA_DEDICATED 28>; 325 <&dma SUN4I_DMA_DEDICATED 28>;
@@ -746,6 +329,15 @@
746 #size-cells = <0>; 329 #size-cells = <0>;
747 }; 330 };
748 331
332 ccu: clock@01c20000 {
333 compatible = "nextthing,gr8-ccu";
334 reg = <0x01c20000 0x400>;
335 clocks = <&osc24M>, <&osc32k>;
336 clock-names = "hosc", "losc";
337 #clock-cells = <1>;
338 #reset-cells = <1>;
339 };
340
749 intc: interrupt-controller@01c20400 { 341 intc: interrupt-controller@01c20400 {
750 compatible = "allwinner,sun4i-a10-ic"; 342 compatible = "allwinner,sun4i-a10-ic";
751 reg = <0x01c20400 0x400>; 343 reg = <0x01c20400 0x400>;
@@ -757,7 +349,7 @@
757 compatible = "nextthing,gr8-pinctrl"; 349 compatible = "nextthing,gr8-pinctrl";
758 reg = <0x01c20800 0x400>; 350 reg = <0x01c20800 0x400>;
759 interrupts = <28>; 351 interrupts = <28>;
760 clocks = <&apb0_gates 5>; 352 clocks = <&ccu CLK_APB0_PIO>;
761 gpio-controller; 353 gpio-controller;
762 interrupt-controller; 354 interrupt-controller;
763 #interrupt-cells = <3>; 355 #interrupt-cells = <3>;
@@ -914,7 +506,7 @@
914 pwm: pwm@01c20e00 { 506 pwm: pwm@01c20e00 {
915 compatible = "allwinner,sun5i-a10s-pwm"; 507 compatible = "allwinner,sun5i-a10s-pwm";
916 reg = <0x01c20e00 0xc>; 508 reg = <0x01c20e00 0xc>;
917 clocks = <&osc24M>; 509 clocks = <&ccu CLK_HOSC>;
918 #pwm-cells = <3>; 510 #pwm-cells = <3>;
919 status = "disabled"; 511 status = "disabled";
920 }; 512 };
@@ -923,7 +515,7 @@
923 compatible = "allwinner,sun4i-a10-timer"; 515 compatible = "allwinner,sun4i-a10-timer";
924 reg = <0x01c20c00 0x90>; 516 reg = <0x01c20c00 0x90>;
925 interrupts = <22>; 517 interrupts = <22>;
926 clocks = <&osc24M>; 518 clocks = <&ccu CLK_HOSC>;
927 }; 519 };
928 520
929 wdt: watchdog@01c20c90 { 521 wdt: watchdog@01c20c90 {
@@ -936,7 +528,7 @@
936 compatible = "allwinner,sun4i-a10-spdif"; 528 compatible = "allwinner,sun4i-a10-spdif";
937 reg = <0x01c21000 0x400>; 529 reg = <0x01c21000 0x400>;
938 interrupts = <13>; 530 interrupts = <13>;
939 clocks = <&apb0_gates 1>, <&spdif_clk>; 531 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
940 clock-names = "apb", "spdif"; 532 clock-names = "apb", "spdif";
941 dmas = <&dma SUN4I_DMA_NORMAL 2>, 533 dmas = <&dma SUN4I_DMA_NORMAL 2>,
942 <&dma SUN4I_DMA_NORMAL 2>; 534 <&dma SUN4I_DMA_NORMAL 2>;
@@ -946,7 +538,7 @@
946 538
947 ir0: ir@01c21800 { 539 ir0: ir@01c21800 {
948 compatible = "allwinner,sun4i-a10-ir"; 540 compatible = "allwinner,sun4i-a10-ir";
949 clocks = <&apb0_gates 6>, <&ir0_clk>; 541 clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
950 clock-names = "apb", "ir"; 542 clock-names = "apb", "ir";
951 interrupts = <5>; 543 interrupts = <5>;
952 reg = <0x01c21800 0x40>; 544 reg = <0x01c21800 0x40>;
@@ -958,7 +550,7 @@
958 compatible = "allwinner,sun4i-a10-i2s"; 550 compatible = "allwinner,sun4i-a10-i2s";
959 reg = <0x01c22400 0x400>; 551 reg = <0x01c22400 0x400>;
960 interrupts = <16>; 552 interrupts = <16>;
961 clocks = <&apb0_gates 3>, <&i2s0_clk>; 553 clocks = <&ccu CLK_APB0_I2S>, <&ccu CLK_I2S>;
962 clock-names = "apb", "mod"; 554 clock-names = "apb", "mod";
963 dmas = <&dma SUN4I_DMA_NORMAL 3>, 555 dmas = <&dma SUN4I_DMA_NORMAL 3>,
964 <&dma SUN4I_DMA_NORMAL 3>; 556 <&dma SUN4I_DMA_NORMAL 3>;
@@ -978,7 +570,7 @@
978 compatible = "allwinner,sun4i-a10-codec"; 570 compatible = "allwinner,sun4i-a10-codec";
979 reg = <0x01c22c00 0x40>; 571 reg = <0x01c22c00 0x40>;
980 interrupts = <30>; 572 interrupts = <30>;
981 clocks = <&apb0_gates 0>, <&codec_clk>; 573 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
982 clock-names = "apb", "codec"; 574 clock-names = "apb", "codec";
983 dmas = <&dma SUN4I_DMA_NORMAL 19>, 575 dmas = <&dma SUN4I_DMA_NORMAL 19>,
984 <&dma SUN4I_DMA_NORMAL 19>; 576 <&dma SUN4I_DMA_NORMAL 19>;
@@ -999,7 +591,7 @@
999 interrupts = <2>; 591 interrupts = <2>;
1000 reg-shift = <2>; 592 reg-shift = <2>;
1001 reg-io-width = <4>; 593 reg-io-width = <4>;
1002 clocks = <&apb1_gates 17>; 594 clocks = <&ccu CLK_APB1_UART1>;
1003 status = "disabled"; 595 status = "disabled";
1004 }; 596 };
1005 597
@@ -1009,7 +601,7 @@
1009 interrupts = <3>; 601 interrupts = <3>;
1010 reg-shift = <2>; 602 reg-shift = <2>;
1011 reg-io-width = <4>; 603 reg-io-width = <4>;
1012 clocks = <&apb1_gates 18>; 604 clocks = <&ccu CLK_APB1_UART2>;
1013 status = "disabled"; 605 status = "disabled";
1014 }; 606 };
1015 607
@@ -1019,7 +611,7 @@
1019 interrupts = <4>; 611 interrupts = <4>;
1020 reg-shift = <2>; 612 reg-shift = <2>;
1021 reg-io-width = <4>; 613 reg-io-width = <4>;
1022 clocks = <&apb1_gates 19>; 614 clocks = <&ccu CLK_APB1_UART3>;
1023 status = "disabled"; 615 status = "disabled";
1024 }; 616 };
1025 617
@@ -1027,7 +619,7 @@
1027 compatible = "allwinner,sun4i-a10-i2c"; 619 compatible = "allwinner,sun4i-a10-i2c";
1028 reg = <0x01c2ac00 0x400>; 620 reg = <0x01c2ac00 0x400>;
1029 interrupts = <7>; 621 interrupts = <7>;
1030 clocks = <&apb1_gates 0>; 622 clocks = <&ccu CLK_APB1_I2C0>;
1031 status = "disabled"; 623 status = "disabled";
1032 #address-cells = <1>; 624 #address-cells = <1>;
1033 #size-cells = <0>; 625 #size-cells = <0>;
@@ -1037,7 +629,7 @@
1037 compatible = "allwinner,sun4i-a10-i2c"; 629 compatible = "allwinner,sun4i-a10-i2c";
1038 reg = <0x01c2b000 0x400>; 630 reg = <0x01c2b000 0x400>;
1039 interrupts = <8>; 631 interrupts = <8>;
1040 clocks = <&apb1_gates 1>; 632 clocks = <&ccu CLK_APB1_I2C1>;
1041 status = "disabled"; 633 status = "disabled";
1042 #address-cells = <1>; 634 #address-cells = <1>;
1043 #size-cells = <0>; 635 #size-cells = <0>;
@@ -1047,7 +639,7 @@
1047 compatible = "allwinner,sun4i-a10-i2c"; 639 compatible = "allwinner,sun4i-a10-i2c";
1048 reg = <0x01c2b400 0x400>; 640 reg = <0x01c2b400 0x400>;
1049 interrupts = <9>; 641 interrupts = <9>;
1050 clocks = <&apb1_gates 2>; 642 clocks = <&ccu CLK_APB1_I2C2>;
1051 status = "disabled"; 643 status = "disabled";
1052 #address-cells = <1>; 644 #address-cells = <1>;
1053 #size-cells = <0>; 645 #size-cells = <0>;
@@ -1057,18 +649,18 @@
1057 compatible = "allwinner,sun5i-a13-hstimer"; 649 compatible = "allwinner,sun5i-a13-hstimer";
1058 reg = <0x01c60000 0x1000>; 650 reg = <0x01c60000 0x1000>;
1059 interrupts = <82>, <83>; 651 interrupts = <82>, <83>;
1060 clocks = <&ahb_gates 28>; 652 clocks = <&ccu CLK_AHB_HSTIMER>;
1061 }; 653 };
1062 654
1063 fe0: display-frontend@01e00000 { 655 fe0: display-frontend@01e00000 {
1064 compatible = "allwinner,sun5i-a13-display-frontend"; 656 compatible = "allwinner,sun5i-a13-display-frontend";
1065 reg = <0x01e00000 0x20000>; 657 reg = <0x01e00000 0x20000>;
1066 interrupts = <47>; 658 interrupts = <47>;
1067 clocks = <&ahb_gates 46>, <&de_fe_clk>, 659 clocks = <&ccu CLK_AHB_DE_FE>, <&ccu CLK_DE_FE>,
1068 <&dram_gates 25>; 660 <&ccu CLK_DRAM_DE_FE>;
1069 clock-names = "ahb", "mod", 661 clock-names = "ahb", "mod",
1070 "ram"; 662 "ram";
1071 resets = <&de_fe_clk>; 663 resets = <&ccu RST_DE_FE>;
1072 status = "disabled"; 664 status = "disabled";
1073 665
1074 ports { 666 ports {
@@ -1091,14 +683,14 @@
1091 be0: display-backend@01e60000 { 683 be0: display-backend@01e60000 {
1092 compatible = "allwinner,sun5i-a13-display-backend"; 684 compatible = "allwinner,sun5i-a13-display-backend";
1093 reg = <0x01e60000 0x10000>; 685 reg = <0x01e60000 0x10000>;
1094 clocks = <&ahb_gates 44>, <&de_be_clk>, 686 clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
1095 <&dram_gates 26>; 687 <&ccu CLK_DRAM_DE_BE>;
1096 clock-names = "ahb", "mod", 688 clock-names = "ahb", "mod",
1097 "ram"; 689 "ram";
1098 resets = <&de_be_clk>; 690 resets = <&ccu RST_DE_BE>;
1099 status = "disabled"; 691 status = "disabled";
1100 692
1101 assigned-clocks = <&de_be_clk>; 693 assigned-clocks = <&ccu CLK_DE_BE>;
1102 assigned-clock-rates = <300000000>; 694 assigned-clock-rates = <300000000>;
1103 695
1104 ports { 696 ports {
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 09:33:56 -0400