Merge branch 'clocksource/physical-timers' into next/drivers

* clocksource/physical-timers:
  clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers
  clocksource: arch_timer: Fix code to use physical timers when requested

4 files changed, 38 insertions, 1 deletions

diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index 37b2cafa4e52..256b4d8bab7b 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -22,6 +22,14 @@ to deliver its interrupts via SPIs.
 - always-on : a boolean property. If present, the timer is powered through an
   always-on power domain, therefore it never loses context.
 
+** Optional properties:
+
+- arm,cpu-registers-not-fw-configured : Firmware does not initialize
+  any of the generic timer CPU registers, which contain their
+  architecturally-defined reset values. Only supported for 32-bit
+  systems which follow the ARMv7 architected reset values.
+
+
 Example:
 
         timer {
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 92793ba69c40..d4ebf5679f1f 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -78,6 +78,15 @@ static inline u32 arch_timer_get_cntfrq(void)
         return val;
 }
 
+static inline u64 arch_counter_get_cntpct(void)
+{
+        u64 cval;
+
+        isb();
+        asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
+        return cval;
+}
+
 static inline u64 arch_counter_get_cntvct(void)
 {
         u64 cval;
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index f19097134b02..b1fa4e614718 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -104,6 +104,15 @@ static inline void arch_timer_set_cntkctl(u32 cntkctl)
         asm volatile("msr       cntkctl_el1, %0" : : "r" (cntkctl));
 }
 
+static inline u64 arch_counter_get_cntpct(void)
+{
+        /*
+         * AArch64 kernel and user space mandate the use of CNTVCT.
+         */
+        BUG();
+        return 0;
+}
+
 static inline u64 arch_counter_get_cntvct(void)
 {
         u64 cval;
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 43005d4d3348..6a79fc4f900c 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -462,7 +462,10 @@ static void __init arch_counter_register(unsigned type)
 
         /* Register the CP15 based counter if we have one */
         if (type & ARCH_CP15_TIMER) {
-                arch_timer_read_counter = arch_counter_get_cntvct;
+                if (arch_timer_use_virtual)
+                        arch_timer_read_counter = arch_counter_get_cntvct;
+                else
+                        arch_timer_read_counter = arch_counter_get_cntpct;
         } else {
                 arch_timer_read_counter = arch_counter_get_cntvct_mem;
 
@@ -702,6 +705,14 @@ static void __init arch_timer_init(struct device_node *np)
         arch_timer_detect_rate(NULL, np);
 
         /*
+         * If we cannot rely on firmware initializing the timer registers then
+         * we should use the physical timers instead.
+         */
+        if (IS_ENABLED(CONFIG_ARM) &&
+            of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
+                        arch_timer_use_virtual = false;
+
+        /*
          * If HYP mode is available, we know that the physical timer
          * has been configured to be accessible from PL1. Use it, so
          * that a guest can use the virtual timer instead.