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authorArnd Bergmann <arnd@arndb.de>2017-10-30 07:02:31 -0400
committerArnd Bergmann <arnd@arndb.de>2017-10-30 07:02:31 -0400
commit6ac5482ee67d7b959eeae081e2b514d125598113 (patch)
treea9413186a9e8f102b85719326ea270fb9a59489f
parentc0dec1ec33d74ac7b07caf32506a84495e0a062f (diff)
parentb6d3b649441936621c87b79bff8dd436e2397e3c (diff)
Merge tag 'renesas-dt2-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Pull "Second Round of Renesas ARM Based SoC DT Updates for v4.15" from Simon Horman: * r8a77430 (RZ/G1M) SoC - Add XHCI support to SoC DT. Boards may enable this as appropriate * All Renesas ARM based SoCs - Add missing clocks for ARM CPU cores Geert Uytterhoeven says "This series improves DT hardware descriptions for Renesas arm32 SoCs by adding missing clocks properties to the device nodes corresponding to ARM CPU cores." * R-Car Gen 1 and 2, and RZ/G SoCs - Use R-Car Fallback compat strings for GPIO Simon Horman says "Use newly added R-Car GPIO Gen 1, 2 and 3 fallback compat strings in peace of now deprecated non-generation specific R-Car GPIO fallback compat string in the DT of Renesas ARM and arm64 based SoCs. As noted in the changelogs for the r8a777[89] changes, this introduces an incompatibility with pre-v4.14 kernels used with new DTBs. There is no run-time effect for other SoCs updated by this changeset." * r7s72100 (RZ/A1H) GR-Peach board - Add pin configuration subnode for ETHER pin group. This avoids relying on boot-loader configuration of these pins. - Enable ostm0 and ostm1 timers Jacopo Mondi says these are "to be used as clock source and clockevent source. The timers provides greater accuracy than the already enabled mtu2 one." - Correct leds node name indent - Enable MTU2 timer pulse unit Jacopo Mondi says "MTU2 multi-function/multi-channel timer/counter is not enabled for GR-Peach board. The timer is used as clock event source to schedule wake-ups, and without this enabled all sleeps not performed through busy waiting hang the board." * r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven SoM - Add USB function support * r8a7745 (RZ/G1E) iW-RainboW-G22D development platform - Add USB2.0 Host support * r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven development platform - Rework DT architecture and add DT for camera DB Fabrizio Castro says "Some of the serial interfaces are exposed on the camera daughter board. The camera daughter board can be connected to the carrier board by means of expansion connectors 1, 2 and 3. The carrier board may host an RZ/G1M or an RZ/G1N based SoM. While adding support for the serial interfaces on the camera daughter board we faced the dilemma of how to properly describe all of the possible HW configurations and how to maximize code reuse. The best option would be to use device tree overlays, however there is still some work to be done on that front before actually using them, therefore for the time being we decided to provide .dtsi files to describe the carrier board and the camera daughter board, and provide .dts files to describe the HW configurations we need to support." * r8a779[0-4] R-Car Gen2 SoCs - Use generic node name for VSP1 nodes Geert Uytterhoeven says "This patch series replaces the specific node names used for the VSP1 nodes by the preferred generic node names, cfr. commit 0e1bfb72b076b07d ("v4l: vsp1: Use generic node name")." * tag 'renesas-dt2-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (42 commits) ARM: dts: r8a7743: Add xhci support to SoC dtsi ARM: dts: r7s72100: Add clock for CA9 CPU core dt-bindings: clk: r7s72100: Add missing I and G clocks ARM: dts: sh73a0: Add clocks for CA9 CPU cores ARM: dts: r8a7794: Add missing clock for secondary CA7 CPU core ARM: dts: r8a7793: Add missing clock for secondary CA15 CPU core ARM: dts: r8a7792: Add missing clock for secondary CA15 CPU core ARM: dts: r8a7791: Add missing clock for secondary CA15 CPU core ARM: dts: r8a7790: Add clocks for CA7 CPU cores ARM: dts: r8a7790: Add missing clocks for secondary CA15 CPU cores ARM: dts: r8a7779: Add clocks for CA9 CPU cores ARM: dts: r8a7778: Add clock for CA9 CPU core ARM: dts: r8a7743: Add missing clock for secondary CA15 CPU core ARM: dts: r8a73a4: Add clock for CA15 CPU0 core ARM: dts: r8a7794: Use R-Car GPIO Gen2 fallback compat string ARM: dts: r8a7793: Use R-Car GPIO Gen2 fallback compat string ARM: dts: r8a7792: Use R-Car GPIO Gen2 fallback compat string ARM: dts: r8a7791: Use R-Car GPIO Gen2 fallback compat string ARM: dts: r8a7790: Use R-Car GPIO Gen2 fallback compat string ARM: dts: r8a7743: Use R-Car GPIO Gen2 fallback compat string ...
Diffstat
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/iwg20d-q7-common.dtsi152
-rw-r--r--arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi43
-rw-r--r--arch/arm/boot/dts/r7s72100-gr-peach.dts53
-rw-r--r--arch/arm/boot/dts/r7s72100.dtsi1
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi1
-rw-r--r--arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts19
-rw-r--r--arch/arm/boot/dts/r8a7743-iwg20d-q7.dts139
-rw-r--r--arch/arm/boot/dts/r8a7743.dtsi82
-rw-r--r--arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts15
-rw-r--r--arch/arm/boot/dts/r8a7745.dtsi92
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi11
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi18
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi35
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi23
-rw-r--r--arch/arm/boot/dts/r8a7792.dtsi31
-rw-r--r--arch/arm/boot/dts/r8a7793.dtsi17
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi19
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi2
-rw-r--r--include/dt-bindings/clock/r7s72100-clock.h2
20 files changed, 545 insertions, 211 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b53d1a5104d3..cffb7f686996 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -727,6 +727,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
727 r8a73a4-ape6evm.dtb \ 727 r8a73a4-ape6evm.dtb \
728 r8a7740-armadillo800eva.dtb \ 728 r8a7740-armadillo800eva.dtb \
729 r8a7743-iwg20d-q7.dtb \ 729 r8a7743-iwg20d-q7.dtb \
730 r8a7743-iwg20d-q7-dbcm-ca.dtb \
730 r8a7743-sk-rzg1m.dtb \ 731 r8a7743-sk-rzg1m.dtb \
731 r8a7745-iwg22d-sodimm.dtb \ 732 r8a7745-iwg22d-sodimm.dtb \
732 r8a7745-sk-rzg1e.dtb \ 733 r8a7745-sk-rzg1e.dtb \
diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
new file mode 100644
index 000000000000..efd8af9242d1
--- /dev/null
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -0,0 +1,152 @@
1/*
2 * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board
3 *
4 * Copyright (C) 2017 Renesas Electronics Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/ {
12 aliases {
13 serial0 = &scif0;
14 ethernet0 = &avb;
15 };
16
17 chosen {
18 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
19 stdout-path = "serial0:115200n8";
20 };
21
22 vcc_sdhi1: regulator-vcc-sdhi1 {
23 compatible = "regulator-fixed";
24
25 regulator-name = "SDHI1 Vcc";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
28
29 gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
30 };
31
32 vccq_sdhi1: regulator-vccq-sdhi1 {
33 compatible = "regulator-gpio";
34
35 regulator-name = "SDHI1 VccQ";
36 regulator-min-microvolt = <1800000>;
37 regulator-max-microvolt = <3300000>;
38
39 gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
40 gpios-states = <1>;
41 states = <3300000 1
42 1800000 0>;
43 };
44};
45
46&avb {
47 pinctrl-0 = <&avb_pins>;
48 pinctrl-names = "default";
49
50 phy-handle = <&phy3>;
51 phy-mode = "gmii";
52 renesas,no-ether-link;
53 status = "okay";
54
55 phy3: ethernet-phy@3 {
56 reg = <3>;
57 micrel,led-mode = <1>;
58 };
59};
60
61&hsusb {
62 status = "okay";
63 pinctrl-0 = <&usb0_pins>;
64 pinctrl-names = "default";
65};
66
67&i2c2 {
68 pinctrl-0 = <&i2c2_pins>;
69 pinctrl-names = "default";
70
71 status = "okay";
72 clock-frequency = <400000>;
73
74 rtc@68 {
75 compatible = "ti,bq32000";
76 reg = <0x68>;
77 };
78};
79
80&pci0 {
81 pinctrl-0 = <&usb0_pins>;
82 pinctrl-names = "default";
83};
84
85&pci1 {
86 status = "okay";
87 pinctrl-0 = <&usb1_pins>;
88 pinctrl-names = "default";
89};
90
91&pfc {
92 avb_pins: avb {
93 groups = "avb_mdio", "avb_gmii";
94 function = "avb";
95 };
96
97 i2c2_pins: i2c2 {
98 groups = "i2c2";
99 function = "i2c2";
100 };
101
102 scif0_pins: scif0 {
103 groups = "scif0_data_d";
104 function = "scif0";
105 };
106
107 sdhi1_pins: sd1 {
108 groups = "sdhi1_data4", "sdhi1_ctrl";
109 function = "sdhi1";
110 power-source = <3300>;
111 };
112
113 sdhi1_pins_uhs: sd1_uhs {
114 groups = "sdhi1_data4", "sdhi1_ctrl";
115 function = "sdhi1";
116 power-source = <1800>;
117 };
118
119 usb0_pins: usb0 {
120 groups = "usb0";
121 function = "usb0";
122 };
123
124 usb1_pins: usb1 {
125 groups = "usb1";
126 function = "usb1";
127 };
128};
129
130&scif0 {
131 pinctrl-0 = <&scif0_pins>;
132 pinctrl-names = "default";
133
134 status = "okay";
135};
136
137&sdhi1 {
138 pinctrl-0 = <&sdhi1_pins>;
139 pinctrl-1 = <&sdhi1_pins_uhs>;
140 pinctrl-names = "default", "state_uhs";
141
142 vmmc-supply = <&vcc_sdhi1>;
143 vqmmc-supply = <&vccq_sdhi1>;
144 cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
145 wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
146 sd-uhs-sdr50;
147 status = "okay";
148};
149
150&usbphy {
151 status = "okay";
152};
diff --git a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
new file mode 100644
index 000000000000..31fab5f183a9
--- /dev/null
+++ b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
@@ -0,0 +1,43 @@
1/*
2 * Device Tree Source for the iWave-RZ-G1M/N Daughter Board Camera Module
3 *
4 * Copyright (C) 2017 Renesas Electronics Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/ {
12 aliases {
13 serial1 = &scif1;
14 serial4 = &hscif1;
15 };
16};
17
18&hscif1 {
19 pinctrl-0 = <&hscif1_pins>;
20 pinctrl-names = "default";
21
22 uart-has-rtscts;
23 status = "okay";
24};
25
26&pfc {
27 hscif1_pins: hscif1 {
28 groups = "hscif1_data_c", "hscif1_ctrl_c";
29 function = "hscif1";
30 };
31
32 scif1_pins: scif1 {
33 groups = "scif1_data_d";
34 function = "scif1";
35 };
36};
37
38&scif1 {
39 pinctrl-0 = <&scif1_pins>;
40 pinctrl-names = "default";
41
42 status = "okay";
43};
diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts
index 13d745bb56a5..779f724b4531 100644
--- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
+++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
@@ -53,7 +53,7 @@
53 }; 53 };
54 }; 54 };
55 55
56leds { 56 leds {
57 status = "okay"; 57 status = "okay";
58 compatible = "gpio-leds"; 58 compatible = "gpio-leds";
59 59
@@ -68,6 +68,28 @@ leds {
68 /* P6_2 as RxD2; P6_3 as TxD2 */ 68 /* P6_2 as RxD2; P6_3 as TxD2 */
69 pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>; 69 pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
70 }; 70 };
71
72 ether_pins: ether {
73 /* Ethernet on Ports 1,3,5,10 */
74 pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */
75 <RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */
76 <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
77 <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
78 <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
79 <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
80 <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
81 <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */
82 <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */
83 <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */
84 <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */
85 <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */
86 <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */
87 <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */
88 <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */
89 <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */
90 <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
91 <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
92 };
71}; 93};
72 94
73&extal_clk { 95&extal_clk {
@@ -78,9 +100,38 @@ leds {
78 clock-frequency = <48000000>; 100 clock-frequency = <48000000>;
79}; 101};
80 102
103&mtu2 {
104 status = "okay";
105};
106
107&ostm0 {
108 status = "okay";
109};
110
111&ostm1 {
112 status = "okay";
113};
114
81&scif2 { 115&scif2 {
82 pinctrl-names = "default"; 116 pinctrl-names = "default";
83 pinctrl-0 = <&scif2_pins>; 117 pinctrl-0 = <&scif2_pins>;
84 118
85 status = "okay"; 119 status = "okay";
86}; 120};
121
122&ether {
123 pinctrl-names = "default";
124 pinctrl-0 = <&ether_pins>;
125
126 status = "okay";
127
128 renesas,no-ether-link;
129 phy-handle = <&phy0>;
130
131 phy0: ethernet-phy@0 {
132 reg = <0>;
133
134 reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
135 reset-delay-us = <5>;
136 };
137};
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 4ed12a4d9d51..ab9645a42eca 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -203,6 +203,7 @@
203 compatible = "arm,cortex-a9"; 203 compatible = "arm,cortex-a9";
204 reg = <0>; 204 reg = <0>;
205 clock-frequency = <400000000>; 205 clock-frequency = <400000000>;
206 clocks = <&cpg_clocks R7S72100_CLK_I>;
206 next-level-cache = <&L2>; 207 next-level-cache = <&L2>;
207 }; 208 };
208 }; 209 };
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 310222634570..dd4d09712a2a 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -27,6 +27,7 @@
27 device_type = "cpu"; 27 device_type = "cpu";
28 compatible = "arm,cortex-a15"; 28 compatible = "arm,cortex-a15";
29 reg = <0>; 29 reg = <0>;
30 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
30 clock-frequency = <1500000000>; 31 clock-frequency = <1500000000>;
31 power-domains = <&pd_a2sl>; 32 power-domains = <&pd_a2sl>;
32 next-level-cache = <&L2_CA15>; 33 next-level-cache = <&L2_CA15>;
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
new file mode 100644
index 000000000000..d90eb8464222
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
@@ -0,0 +1,19 @@
1/*
2 * Device Tree Source for the iWave-RZ/G1M Qseven board + camera daughter board
3 *
4 * Copyright (C) 2017 Renesas Electronics Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "r8a7743-iwg20m.dtsi"
13#include "iwg20d-q7-common.dtsi"
14#include "iwg20d-q7-dbcm-ca.dtsi"
15
16/ {
17 model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board";
18 compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
19};
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
index 0136864bc595..6aa6b7467704 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for the iWave-RZG1M Qseven carrier board 2 * Device Tree Source for the iWave-RZ/G1M Qseven board
3 * 3 *
4 * Copyright (C) 2017 Renesas Electronics Corp. 4 * Copyright (C) 2017 Renesas Electronics Corp.
5 * 5 *
@@ -10,144 +10,9 @@
10 10
11/dts-v1/; 11/dts-v1/;
12#include "r8a7743-iwg20m.dtsi" 12#include "r8a7743-iwg20m.dtsi"
13#include "iwg20d-q7-common.dtsi"
13 14
14/ { 15/ {
15 model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M"; 16 model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M";
16 compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; 17 compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
17
18 aliases {
19 serial0 = &scif0;
20 ethernet0 = &avb;
21 };
22
23 chosen {
24 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
25 stdout-path = "serial0:115200n8";
26 };
27
28 vcc_sdhi1: regulator-vcc-sdhi1 {
29 compatible = "regulator-fixed";
30
31 regulator-name = "SDHI1 Vcc";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34
35 gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
36 };
37
38 vccq_sdhi1: regulator-vccq-sdhi1 {
39 compatible = "regulator-gpio";
40
41 regulator-name = "SDHI1 VccQ";
42 regulator-min-microvolt = <1800000>;
43 regulator-max-microvolt = <3300000>;
44
45 gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
46 gpios-states = <1>;
47 states = <3300000 1
48 1800000 0>;
49 };
50};
51
52&pfc {
53 i2c2_pins: i2c2 {
54 groups = "i2c2";
55 function = "i2c2";
56 };
57
58 scif0_pins: scif0 {
59 groups = "scif0_data_d";
60 function = "scif0";
61 };
62
63 avb_pins: avb {
64 groups = "avb_mdio", "avb_gmii";
65 function = "avb";
66 };
67
68 sdhi1_pins: sd1 {
69 groups = "sdhi1_data4", "sdhi1_ctrl";
70 function = "sdhi1";
71 power-source = <3300>;
72 };
73
74 sdhi1_pins_uhs: sd1_uhs {
75 groups = "sdhi1_data4", "sdhi1_ctrl";
76 function = "sdhi1";
77 power-source = <1800>;
78 };
79
80 usb0_pins: usb0 {
81 groups = "usb0";
82 function = "usb0";
83 };
84
85 usb1_pins: usb1 {
86 groups = "usb1";
87 function = "usb1";
88 };
89};
90
91&scif0 {
92 pinctrl-0 = <&scif0_pins>;
93 pinctrl-names = "default";
94
95 status = "okay";
96};
97
98&avb {
99 pinctrl-0 = <&avb_pins>;
100 pinctrl-names = "default";
101
102 phy-handle = <&phy3>;
103 phy-mode = "gmii";
104 renesas,no-ether-link;
105 status = "okay";
106
107 phy3: ethernet-phy@3 {
108 reg = <3>;
109 micrel,led-mode = <1>;
110 };
111};
112
113&sdhi1 {
114 pinctrl-0 = <&sdhi1_pins>;
115 pinctrl-1 = <&sdhi1_pins_uhs>;
116 pinctrl-names = "default", "state_uhs";
117
118 vmmc-supply = <&vcc_sdhi1>;
119 vqmmc-supply = <&vccq_sdhi1>;
120 cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
121 wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
122 sd-uhs-sdr50;
123 status = "okay";
124};
125
126&i2c2 {
127 pinctrl-0 = <&i2c2_pins>;
128 pinctrl-names = "default";
129
130 status = "okay";
131 clock-frequency = <400000>;
132
133 rtc@68 {
134 compatible = "ti,bq32000";
135 reg = <0x68>;
136 };
137};
138
139&pci0 {
140 status = "okay";
141 pinctrl-0 = <&usb0_pins>;
142 pinctrl-names = "default";
143};
144
145&pci1 {
146 status = "okay";
147 pinctrl-0 = <&usb1_pins>;
148 pinctrl-names = "default";
149};
150
151&usbphy {
152 status = "okay";
153}; 18};
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index d541fd9ffafb..7bbba4a36f31 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -63,6 +63,7 @@
63 compatible = "arm,cortex-a15"; 63 compatible = "arm,cortex-a15";
64 reg = <1>; 64 reg = <1>;
65 clock-frequency = <1500000000>; 65 clock-frequency = <1500000000>;
66 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
66 power-domains = <&sysc R8A7743_PD_CA15_CPU1>; 67 power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
67 next-level-cache = <&L2_CA15>; 68 next-level-cache = <&L2_CA15>;
68 }; 69 };
@@ -108,7 +109,7 @@
108 109
109 gpio0: gpio@e6050000 { 110 gpio0: gpio@e6050000 {
110 compatible = "renesas,gpio-r8a7743", 111 compatible = "renesas,gpio-r8a7743",
111 "renesas,gpio-rcar"; 112 "renesas,rcar-gen2-gpio";
112 reg = <0 0xe6050000 0 0x50>; 113 reg = <0 0xe6050000 0 0x50>;
113 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 114 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
114 #gpio-cells = <2>; 115 #gpio-cells = <2>;
@@ -123,7 +124,7 @@
123 124
124 gpio1: gpio@e6051000 { 125 gpio1: gpio@e6051000 {
125 compatible = "renesas,gpio-r8a7743", 126 compatible = "renesas,gpio-r8a7743",
126 "renesas,gpio-rcar"; 127 "renesas,rcar-gen2-gpio";
127 reg = <0 0xe6051000 0 0x50>; 128 reg = <0 0xe6051000 0 0x50>;
128 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 129 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
129 #gpio-cells = <2>; 130 #gpio-cells = <2>;
@@ -138,7 +139,7 @@
138 139
139 gpio2: gpio@e6052000 { 140 gpio2: gpio@e6052000 {
140 compatible = "renesas,gpio-r8a7743", 141 compatible = "renesas,gpio-r8a7743",
141 "renesas,gpio-rcar"; 142 "renesas,rcar-gen2-gpio";
142 reg = <0 0xe6052000 0 0x50>; 143 reg = <0 0xe6052000 0 0x50>;
143 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 144 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
144 #gpio-cells = <2>; 145 #gpio-cells = <2>;
@@ -153,7 +154,7 @@
153 154
154 gpio3: gpio@e6053000 { 155 gpio3: gpio@e6053000 {
155 compatible = "renesas,gpio-r8a7743", 156 compatible = "renesas,gpio-r8a7743",
156 "renesas,gpio-rcar"; 157 "renesas,rcar-gen2-gpio";
157 reg = <0 0xe6053000 0 0x50>; 158 reg = <0 0xe6053000 0 0x50>;
158 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 159 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
159 #gpio-cells = <2>; 160 #gpio-cells = <2>;
@@ -168,7 +169,7 @@
168 169
169 gpio4: gpio@e6054000 { 170 gpio4: gpio@e6054000 {
170 compatible = "renesas,gpio-r8a7743", 171 compatible = "renesas,gpio-r8a7743",
171 "renesas,gpio-rcar"; 172 "renesas,rcar-gen2-gpio";
172 reg = <0 0xe6054000 0 0x50>; 173 reg = <0 0xe6054000 0 0x50>;
173 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 174 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
174 #gpio-cells = <2>; 175 #gpio-cells = <2>;
@@ -183,7 +184,7 @@
183 184
184 gpio5: gpio@e6055000 { 185 gpio5: gpio@e6055000 {
185 compatible = "renesas,gpio-r8a7743", 186 compatible = "renesas,gpio-r8a7743",
186 "renesas,gpio-rcar"; 187 "renesas,rcar-gen2-gpio";
187 reg = <0 0xe6055000 0 0x50>; 188 reg = <0 0xe6055000 0 0x50>;
188 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 189 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
189 #gpio-cells = <2>; 190 #gpio-cells = <2>;
@@ -198,7 +199,7 @@
198 199
199 gpio6: gpio@e6055400 { 200 gpio6: gpio@e6055400 {
200 compatible = "renesas,gpio-r8a7743", 201 compatible = "renesas,gpio-r8a7743",
201 "renesas,gpio-rcar"; 202 "renesas,rcar-gen2-gpio";
202 reg = <0 0xe6055400 0 0x50>; 203 reg = <0 0xe6055400 0 0x50>;
203 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 204 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
204 #gpio-cells = <2>; 205 #gpio-cells = <2>;
@@ -213,7 +214,7 @@
213 214
214 gpio7: gpio@e6055800 { 215 gpio7: gpio@e6055800 {
215 compatible = "renesas,gpio-r8a7743", 216 compatible = "renesas,gpio-r8a7743",
216 "renesas,gpio-rcar"; 217 "renesas,rcar-gen2-gpio";
217 reg = <0 0xe6055800 0 0x50>; 218 reg = <0 0xe6055800 0 0x50>;
218 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 219 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
219 #gpio-cells = <2>; 220 #gpio-cells = <2>;
@@ -355,6 +356,34 @@
355 dma-channels = <15>; 356 dma-channels = <15>;
356 }; 357 };
357 358
359 usb_dmac0: dma-controller@e65a0000 {
360 compatible = "renesas,r8a7743-usb-dmac",
361 "renesas,usb-dmac";
362 reg = <0 0xe65a0000 0 0x100>;
363 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
364 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
365 interrupt-names = "ch0", "ch1";
366 clocks = <&cpg CPG_MOD 330>;
367 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
368 resets = <&cpg 330>;
369 #dma-cells = <1>;
370 dma-channels = <2>;
371 };
372
373 usb_dmac1: dma-controller@e65b0000 {
374 compatible = "renesas,r8a7743-usb-dmac",
375 "renesas,usb-dmac";
376 reg = <0 0xe65b0000 0 0x100>;
377 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
379 interrupt-names = "ch0", "ch1";
380 clocks = <&cpg CPG_MOD 331>;
381 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
382 resets = <&cpg 331>;
383 #dma-cells = <1>;
384 dma-channels = <2>;
385 };
386
358 /* The memory map in the User's Manual maps the cores to bus 387 /* The memory map in the User's Manual maps the cores to bus
359 * numbers 388 * numbers
360 */ 389 */
@@ -903,6 +932,26 @@
903 status = "disabled"; 932 status = "disabled";
904 }; 933 };
905 934
935 /*
936 * pci1 and xhci share the same phy, therefore only one of them
937 * can be active at any one time. If both of them are enabled,
938 * a race condition will determine who'll control the phy.
939 * A firmware file is needed by the xhci driver in order for
940 * USB 3.0 to work properly.
941 */
942 xhci: usb@ee000000 {
943 compatible = "renesas,xhci-r8a7743",
944 "renesas,rcar-gen2-xhci";
945 reg = <0 0xee000000 0 0xc00>;
946 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&cpg CPG_MOD 328>;
948 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
949 resets = <&cpg 328>;
950 phys = <&usb2 1>;
951 phy-names = "usb";
952 status = "disabled";
953 };
954
906 sdhi0: sd@ee100000 { 955 sdhi0: sd@ee100000 {
907 compatible = "renesas,sdhi-r8a7743"; 956 compatible = "renesas,sdhi-r8a7743";
908 reg = <0 0xee100000 0 0x328>; 957 reg = <0 0xee100000 0 0x328>;
@@ -945,6 +994,23 @@
945 status = "disabled"; 994 status = "disabled";
946 }; 995 };
947 996
997 hsusb: usb@e6590000 {
998 compatible = "renesas,usbhs-r8a7743",
999 "renesas,rcar-gen2-usbhs";
1000 reg = <0 0xe6590000 0 0x100>;
1001 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&cpg CPG_MOD 704>;
1003 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
1004 <&usb_dmac1 0>, <&usb_dmac1 1>;
1005 dma-names = "ch0", "ch1", "ch2", "ch3";
1006 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
1007 resets = <&cpg 704>;
1008 renesas,buswait = <4>;
1009 phys = <&usb0 1>;
1010 phy-names = "usb";
1011 status = "disabled";
1012 };
1013
948 usbphy: usb-phy@e6590100 { 1014 usbphy: usb-phy@e6590100 {
949 compatible = "renesas,usb-phy-r8a7743", 1015 compatible = "renesas,usb-phy-r8a7743",
950 "renesas,rcar-gen2-usb-phy"; 1016 "renesas,rcar-gen2-usb-phy";
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index 8772c561e3a8..52153ec3638c 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -55,6 +55,11 @@
55 function = "sdhi0"; 55 function = "sdhi0";
56 power-source = <3300>; 56 power-source = <3300>;
57 }; 57 };
58
59 usb1_pins: usb1 {
60 groups = "usb1";
61 function = "usb1";
62 };
58}; 63};
59 64
60&scif4 { 65&scif4 {
@@ -92,3 +97,13 @@
92 cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; 97 cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
93 status = "okay"; 98 status = "okay";
94}; 99};
100
101&pci1 {
102 status = "okay";
103 pinctrl-0 = <&usb1_pins>;
104 pinctrl-names = "default";
105};
106
107&usbphy {
108 status = "okay";
109};
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 6ba3b8b04edb..3a50f703601c 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -845,6 +845,98 @@
845 resets = <&cpg 311>; 845 resets = <&cpg 311>;
846 status = "disabled"; 846 status = "disabled";
847 }; 847 };
848
849 pci0: pci@ee090000 {
850 compatible = "renesas,pci-r8a7745",
851 "renesas,pci-rcar-gen2";
852 device_type = "pci";
853 reg = <0 0xee090000 0 0xc00>,
854 <0 0xee080000 0 0x1100>;
855 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&cpg CPG_MOD 703>;
857 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
858 resets = <&cpg 703>;
859 status = "disabled";
860
861 bus-range = <0 0>;
862 #address-cells = <3>;
863 #size-cells = <2>;
864 #interrupt-cells = <1>;
865 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
866 interrupt-map-mask = <0xff00 0 0 0x7>;
867 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
868 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
869 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
870
871 usb@1,0 {
872 reg = <0x800 0 0 0 0>;
873 phys = <&usb0 0>;
874 phy-names = "usb";
875 };
876
877 usb@2,0 {
878 reg = <0x1000 0 0 0 0>;
879 phys = <&usb0 0>;
880 phy-names = "usb";
881 };
882 };
883
884 pci1: pci@ee0d0000 {
885 compatible = "renesas,pci-r8a7745",
886 "renesas,pci-rcar-gen2";
887 device_type = "pci";
888 reg = <0 0xee0d0000 0 0xc00>,
889 <0 0xee0c0000 0 0x1100>;
890 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
891 clocks = <&cpg CPG_MOD 703>;
892 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
893 resets = <&cpg 703>;
894 status = "disabled";
895
896 bus-range = <1 1>;
897 #address-cells = <3>;
898 #size-cells = <2>;
899 #interrupt-cells = <1>;
900 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
901 interrupt-map-mask = <0xff00 0 0 0x7>;
902 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
903 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
904 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
905
906 usb@1,0 {
907 reg = <0x10800 0 0 0 0>;
908 phys = <&usb2 0>;
909 phy-names = "usb";
910 };
911
912 usb@2,0 {
913 reg = <0x11000 0 0 0 0>;
914 phys = <&usb2 0>;
915 phy-names = "usb";
916 };
917 };
918
919 usbphy: usb-phy@e6590100 {
920 compatible = "renesas,usb-phy-r8a7745",
921 "renesas,rcar-gen2-usb-phy";
922 reg = <0 0xe6590100 0 0x100>;
923 #address-cells = <1>;
924 #size-cells = <0>;
925 clocks = <&cpg CPG_MOD 704>;
926 clock-names = "usbhs";
927 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
928 resets = <&cpg 704>;
929 status = "disabled";
930
931 usb0: usb-channel@0 {
932 reg = <0>;
933 #phy-cells = <1>;
934 };
935 usb2: usb-channel@2 {
936 reg = <2>;
937 #phy-cells = <1>;
938 };
939 };
848 }; 940 };
849 941
850 /* External root clock */ 942 /* External root clock */
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 8f3156c0e575..a39472aab867 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -33,6 +33,7 @@
33 compatible = "arm,cortex-a9"; 33 compatible = "arm,cortex-a9";
34 reg = <0>; 34 reg = <0>;
35 clock-frequency = <800000000>; 35 clock-frequency = <800000000>;
36 clocks = <&z_clk>;
36 }; 37 };
37 }; 38 };
38 39
@@ -88,7 +89,7 @@
88 }; 89 };
89 90
90 gpio0: gpio@ffc40000 { 91 gpio0: gpio@ffc40000 {
91 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 92 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
92 reg = <0xffc40000 0x2c>; 93 reg = <0xffc40000 0x2c>;
93 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 94 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
94 #gpio-cells = <2>; 95 #gpio-cells = <2>;
@@ -99,7 +100,7 @@
99 }; 100 };
100 101
101 gpio1: gpio@ffc41000 { 102 gpio1: gpio@ffc41000 {
102 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 103 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
103 reg = <0xffc41000 0x2c>; 104 reg = <0xffc41000 0x2c>;
104 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 105 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
105 #gpio-cells = <2>; 106 #gpio-cells = <2>;
@@ -110,7 +111,7 @@
110 }; 111 };
111 112
112 gpio2: gpio@ffc42000 { 113 gpio2: gpio@ffc42000 {
113 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 114 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
114 reg = <0xffc42000 0x2c>; 115 reg = <0xffc42000 0x2c>;
115 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 116 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
116 #gpio-cells = <2>; 117 #gpio-cells = <2>;
@@ -121,7 +122,7 @@
121 }; 122 };
122 123
123 gpio3: gpio@ffc43000 { 124 gpio3: gpio@ffc43000 {
124 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 125 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
125 reg = <0xffc43000 0x2c>; 126 reg = <0xffc43000 0x2c>;
126 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 127 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
127 #gpio-cells = <2>; 128 #gpio-cells = <2>;
@@ -132,7 +133,7 @@
132 }; 133 };
133 134
134 gpio4: gpio@ffc44000 { 135 gpio4: gpio@ffc44000 {
135 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 136 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
136 reg = <0xffc44000 0x2c>; 137 reg = <0xffc44000 0x2c>;
137 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 138 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
138 #gpio-cells = <2>; 139 #gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 8ee0b2ca5d39..e8eb94748b27 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -29,12 +29,14 @@
29 compatible = "arm,cortex-a9"; 29 compatible = "arm,cortex-a9";
30 reg = <0>; 30 reg = <0>;
31 clock-frequency = <1000000000>; 31 clock-frequency = <1000000000>;
32 clocks = <&cpg_clocks R8A7779_CLK_Z>;
32 }; 33 };
33 cpu@1 { 34 cpu@1 {
34 device_type = "cpu"; 35 device_type = "cpu";
35 compatible = "arm,cortex-a9"; 36 compatible = "arm,cortex-a9";
36 reg = <1>; 37 reg = <1>;
37 clock-frequency = <1000000000>; 38 clock-frequency = <1000000000>;
39 clocks = <&cpg_clocks R8A7779_CLK_Z>;
38 power-domains = <&sysc R8A7779_PD_ARM1>; 40 power-domains = <&sysc R8A7779_PD_ARM1>;
39 }; 41 };
40 cpu@2 { 42 cpu@2 {
@@ -42,6 +44,7 @@
42 compatible = "arm,cortex-a9"; 44 compatible = "arm,cortex-a9";
43 reg = <2>; 45 reg = <2>;
44 clock-frequency = <1000000000>; 46 clock-frequency = <1000000000>;
47 clocks = <&cpg_clocks R8A7779_CLK_Z>;
45 power-domains = <&sysc R8A7779_PD_ARM2>; 48 power-domains = <&sysc R8A7779_PD_ARM2>;
46 }; 49 };
47 cpu@3 { 50 cpu@3 {
@@ -49,6 +52,7 @@
49 compatible = "arm,cortex-a9"; 52 compatible = "arm,cortex-a9";
50 reg = <3>; 53 reg = <3>;
51 clock-frequency = <1000000000>; 54 clock-frequency = <1000000000>;
55 clocks = <&cpg_clocks R8A7779_CLK_Z>;
52 power-domains = <&sysc R8A7779_PD_ARM3>; 56 power-domains = <&sysc R8A7779_PD_ARM3>;
53 }; 57 };
54 }; 58 };
@@ -76,7 +80,7 @@
76 }; 80 };
77 81
78 gpio0: gpio@ffc40000 { 82 gpio0: gpio@ffc40000 {
79 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 83 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
80 reg = <0xffc40000 0x2c>; 84 reg = <0xffc40000 0x2c>;
81 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 85 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
82 #gpio-cells = <2>; 86 #gpio-cells = <2>;
@@ -87,7 +91,7 @@
87 }; 91 };
88 92
89 gpio1: gpio@ffc41000 { 93 gpio1: gpio@ffc41000 {
90 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 94 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
91 reg = <0xffc41000 0x2c>; 95 reg = <0xffc41000 0x2c>;
92 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 96 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
93 #gpio-cells = <2>; 97 #gpio-cells = <2>;
@@ -98,7 +102,7 @@
98 }; 102 };
99 103
100 gpio2: gpio@ffc42000 { 104 gpio2: gpio@ffc42000 {
101 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 105 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
102 reg = <0xffc42000 0x2c>; 106 reg = <0xffc42000 0x2c>;
103 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 107 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
104 #gpio-cells = <2>; 108 #gpio-cells = <2>;
@@ -109,7 +113,7 @@
109 }; 113 };
110 114
111 gpio3: gpio@ffc43000 { 115 gpio3: gpio@ffc43000 {
112 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 116 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
113 reg = <0xffc43000 0x2c>; 117 reg = <0xffc43000 0x2c>;
114 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 118 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
115 #gpio-cells = <2>; 119 #gpio-cells = <2>;
@@ -120,7 +124,7 @@
120 }; 124 };
121 125
122 gpio4: gpio@ffc44000 { 126 gpio4: gpio@ffc44000 {
123 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 127 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
124 reg = <0xffc44000 0x2c>; 128 reg = <0xffc44000 0x2c>;
125 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 129 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
126 #gpio-cells = <2>; 130 #gpio-cells = <2>;
@@ -131,7 +135,7 @@
131 }; 135 };
132 136
133 gpio5: gpio@ffc45000 { 137 gpio5: gpio@ffc45000 {
134 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 138 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
135 reg = <0xffc45000 0x2c>; 139 reg = <0xffc45000 0x2c>;
136 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 140 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
137 #gpio-cells = <2>; 141 #gpio-cells = <2>;
@@ -142,7 +146,7 @@
142 }; 146 };
143 147
144 gpio6: gpio@ffc46000 { 148 gpio6: gpio@ffc46000 {
145 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 149 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
146 reg = <0xffc46000 0x2c>; 150 reg = <0xffc46000 0x2c>;
147 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 151 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
148 #gpio-cells = <2>; 152 #gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 081cf5cdb13b..2f017fee4009 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -56,6 +56,7 @@
56 clock-latency = <300000>; /* 300 us */ 56 clock-latency = <300000>; /* 300 us */
57 power-domains = <&sysc R8A7790_PD_CA15_CPU0>; 57 power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
58 next-level-cache = <&L2_CA15>; 58 next-level-cache = <&L2_CA15>;
59 capacity-dmips-mhz = <1024>;
59 60
60 /* kHz - uV - OPPs unknown yet */ 61 /* kHz - uV - OPPs unknown yet */
61 operating-points = <1400000 1000000>, 62 operating-points = <1400000 1000000>,
@@ -71,8 +72,10 @@
71 compatible = "arm,cortex-a15"; 72 compatible = "arm,cortex-a15";
72 reg = <1>; 73 reg = <1>;
73 clock-frequency = <1300000000>; 74 clock-frequency = <1300000000>;
75 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
74 power-domains = <&sysc R8A7790_PD_CA15_CPU1>; 76 power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
75 next-level-cache = <&L2_CA15>; 77 next-level-cache = <&L2_CA15>;
78 capacity-dmips-mhz = <1024>;
76 }; 79 };
77 80
78 cpu2: cpu@2 { 81 cpu2: cpu@2 {
@@ -80,8 +83,10 @@
80 compatible = "arm,cortex-a15"; 83 compatible = "arm,cortex-a15";
81 reg = <2>; 84 reg = <2>;
82 clock-frequency = <1300000000>; 85 clock-frequency = <1300000000>;
86 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
83 power-domains = <&sysc R8A7790_PD_CA15_CPU2>; 87 power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
84 next-level-cache = <&L2_CA15>; 88 next-level-cache = <&L2_CA15>;
89 capacity-dmips-mhz = <1024>;
85 }; 90 };
86 91
87 cpu3: cpu@3 { 92 cpu3: cpu@3 {
@@ -89,8 +94,10 @@
89 compatible = "arm,cortex-a15"; 94 compatible = "arm,cortex-a15";
90 reg = <3>; 95 reg = <3>;
91 clock-frequency = <1300000000>; 96 clock-frequency = <1300000000>;
97 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
92 power-domains = <&sysc R8A7790_PD_CA15_CPU3>; 98 power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
93 next-level-cache = <&L2_CA15>; 99 next-level-cache = <&L2_CA15>;
100 capacity-dmips-mhz = <1024>;
94 }; 101 };
95 102
96 cpu4: cpu@100 { 103 cpu4: cpu@100 {
@@ -98,8 +105,10 @@
98 compatible = "arm,cortex-a7"; 105 compatible = "arm,cortex-a7";
99 reg = <0x100>; 106 reg = <0x100>;
100 clock-frequency = <780000000>; 107 clock-frequency = <780000000>;
108 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
101 power-domains = <&sysc R8A7790_PD_CA7_CPU0>; 109 power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
102 next-level-cache = <&L2_CA7>; 110 next-level-cache = <&L2_CA7>;
111 capacity-dmips-mhz = <539>;
103 }; 112 };
104 113
105 cpu5: cpu@101 { 114 cpu5: cpu@101 {
@@ -107,8 +116,10 @@
107 compatible = "arm,cortex-a7"; 116 compatible = "arm,cortex-a7";
108 reg = <0x101>; 117 reg = <0x101>;
109 clock-frequency = <780000000>; 118 clock-frequency = <780000000>;
119 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
110 power-domains = <&sysc R8A7790_PD_CA7_CPU1>; 120 power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
111 next-level-cache = <&L2_CA7>; 121 next-level-cache = <&L2_CA7>;
122 capacity-dmips-mhz = <539>;
112 }; 123 };
113 124
114 cpu6: cpu@102 { 125 cpu6: cpu@102 {
@@ -116,8 +127,10 @@
116 compatible = "arm,cortex-a7"; 127 compatible = "arm,cortex-a7";
117 reg = <0x102>; 128 reg = <0x102>;
118 clock-frequency = <780000000>; 129 clock-frequency = <780000000>;
130 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
119 power-domains = <&sysc R8A7790_PD_CA7_CPU2>; 131 power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
120 next-level-cache = <&L2_CA7>; 132 next-level-cache = <&L2_CA7>;
133 capacity-dmips-mhz = <539>;
121 }; 134 };
122 135
123 cpu7: cpu@103 { 136 cpu7: cpu@103 {
@@ -125,8 +138,10 @@
125 compatible = "arm,cortex-a7"; 138 compatible = "arm,cortex-a7";
126 reg = <0x103>; 139 reg = <0x103>;
127 clock-frequency = <780000000>; 140 clock-frequency = <780000000>;
141 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
128 power-domains = <&sysc R8A7790_PD_CA7_CPU3>; 142 power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
129 next-level-cache = <&L2_CA7>; 143 next-level-cache = <&L2_CA7>;
144 capacity-dmips-mhz = <539>;
130 }; 145 };
131 146
132 L2_CA15: cache-controller-0 { 147 L2_CA15: cache-controller-0 {
@@ -192,7 +207,7 @@
192 }; 207 };
193 208
194 gpio0: gpio@e6050000 { 209 gpio0: gpio@e6050000 {
195 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 210 compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
196 reg = <0 0xe6050000 0 0x50>; 211 reg = <0 0xe6050000 0 0x50>;
197 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 212 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
198 #gpio-cells = <2>; 213 #gpio-cells = <2>;
@@ -206,7 +221,7 @@
206 }; 221 };
207 222
208 gpio1: gpio@e6051000 { 223 gpio1: gpio@e6051000 {
209 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 224 compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
210 reg = <0 0xe6051000 0 0x50>; 225 reg = <0 0xe6051000 0 0x50>;
211 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 226 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
212 #gpio-cells = <2>; 227 #gpio-cells = <2>;
@@ -220,7 +235,7 @@
220 }; 235 };
221 236
222 gpio2: gpio@e6052000 { 237 gpio2: gpio@e6052000 {
223 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 238 compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
224 reg = <0 0xe6052000 0 0x50>; 239 reg = <0 0xe6052000 0 0x50>;
225 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 240 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
226 #gpio-cells = <2>; 241 #gpio-cells = <2>;
@@ -234,7 +249,7 @@
234 }; 249 };
235 250
236 gpio3: gpio@e6053000 { 251 gpio3: gpio@e6053000 {
237 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 252 compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
238 reg = <0 0xe6053000 0 0x50>; 253 reg = <0 0xe6053000 0 0x50>;
239 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 254 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
240 #gpio-cells = <2>; 255 #gpio-cells = <2>;
@@ -248,7 +263,7 @@
248 }; 263 };
249 264
250 gpio4: gpio@e6054000 { 265 gpio4: gpio@e6054000 {
251 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 266 compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
252 reg = <0 0xe6054000 0 0x50>; 267 reg = <0 0xe6054000 0 0x50>;
253 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 268 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
254 #gpio-cells = <2>; 269 #gpio-cells = <2>;
@@ -262,7 +277,7 @@
262 }; 277 };
263 278
264 gpio5: gpio@e6055000 { 279 gpio5: gpio@e6055000 {
265 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 280 compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
266 reg = <0 0xe6055000 0 0x50>; 281 reg = <0 0xe6055000 0 0x50>;
267 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 282 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
268 #gpio-cells = <2>; 283 #gpio-cells = <2>;
@@ -1014,7 +1029,7 @@
1014 status = "disabled"; 1029 status = "disabled";
1015 }; 1030 };
1016 1031
1017 vsp1@fe920000 { 1032 vsp@fe920000 {
1018 compatible = "renesas,vsp1"; 1033 compatible = "renesas,vsp1";
1019 reg = <0 0xfe920000 0 0x8000>; 1034 reg = <0 0xfe920000 0 0x8000>;
1020 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1035 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
@@ -1023,7 +1038,7 @@
1023 resets = <&cpg 130>; 1038 resets = <&cpg 130>;
1024 }; 1039 };
1025 1040
1026 vsp1@fe928000 { 1041 vsp@fe928000 {
1027 compatible = "renesas,vsp1"; 1042 compatible = "renesas,vsp1";
1028 reg = <0 0xfe928000 0 0x8000>; 1043 reg = <0 0xfe928000 0 0x8000>;
1029 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 1044 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
@@ -1032,7 +1047,7 @@
1032 resets = <&cpg 131>; 1047 resets = <&cpg 131>;
1033 }; 1048 };
1034 1049
1035 vsp1@fe930000 { 1050 vsp@fe930000 {
1036 compatible = "renesas,vsp1"; 1051 compatible = "renesas,vsp1";
1037 reg = <0 0xfe930000 0 0x8000>; 1052 reg = <0 0xfe930000 0 0x8000>;
1038 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1053 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
@@ -1041,7 +1056,7 @@
1041 resets = <&cpg 128>; 1056 resets = <&cpg 128>;
1042 }; 1057 };
1043 1058
1044 vsp1@fe938000 { 1059 vsp@fe938000 {
1045 compatible = "renesas,vsp1"; 1060 compatible = "renesas,vsp1";
1046 reg = <0 0xfe938000 0 0x8000>; 1061 reg = <0 0xfe938000 0 0x8000>;
1047 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 1062 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 5a8a15847076..67831d0405f3 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -70,6 +70,7 @@
70 compatible = "arm,cortex-a15"; 70 compatible = "arm,cortex-a15";
71 reg = <1>; 71 reg = <1>;
72 clock-frequency = <1500000000>; 72 clock-frequency = <1500000000>;
73 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
73 power-domains = <&sysc R8A7791_PD_CA15_CPU1>; 74 power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
74 next-level-cache = <&L2_CA15>; 75 next-level-cache = <&L2_CA15>;
75 }; 76 };
@@ -124,7 +125,7 @@
124 }; 125 };
125 126
126 gpio0: gpio@e6050000 { 127 gpio0: gpio@e6050000 {
127 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 128 compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
128 reg = <0 0xe6050000 0 0x50>; 129 reg = <0 0xe6050000 0 0x50>;
129 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 130 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
130 #gpio-cells = <2>; 131 #gpio-cells = <2>;
@@ -138,7 +139,7 @@
138 }; 139 };
139 140
140 gpio1: gpio@e6051000 { 141 gpio1: gpio@e6051000 {
141 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 142 compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
142 reg = <0 0xe6051000 0 0x50>; 143 reg = <0 0xe6051000 0 0x50>;
143 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 144 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
144 #gpio-cells = <2>; 145 #gpio-cells = <2>;
@@ -152,7 +153,7 @@
152 }; 153 };
153 154
154 gpio2: gpio@e6052000 { 155 gpio2: gpio@e6052000 {
155 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 156 compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
156 reg = <0 0xe6052000 0 0x50>; 157 reg = <0 0xe6052000 0 0x50>;
157 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 158 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
158 #gpio-cells = <2>; 159 #gpio-cells = <2>;
@@ -166,7 +167,7 @@
166 }; 167 };
167 168
168 gpio3: gpio@e6053000 { 169 gpio3: gpio@e6053000 {
169 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 170 compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
170 reg = <0 0xe6053000 0 0x50>; 171 reg = <0 0xe6053000 0 0x50>;
171 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 172 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>; 173 #gpio-cells = <2>;
@@ -180,7 +181,7 @@
180 }; 181 };
181 182
182 gpio4: gpio@e6054000 { 183 gpio4: gpio@e6054000 {
183 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 184 compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
184 reg = <0 0xe6054000 0 0x50>; 185 reg = <0 0xe6054000 0 0x50>;
185 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 186 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
186 #gpio-cells = <2>; 187 #gpio-cells = <2>;
@@ -194,7 +195,7 @@
194 }; 195 };
195 196
196 gpio5: gpio@e6055000 { 197 gpio5: gpio@e6055000 {
197 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 198 compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
198 reg = <0 0xe6055000 0 0x50>; 199 reg = <0 0xe6055000 0 0x50>;
199 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 200 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
200 #gpio-cells = <2>; 201 #gpio-cells = <2>;
@@ -208,7 +209,7 @@
208 }; 209 };
209 210
210 gpio6: gpio@e6055400 { 211 gpio6: gpio@e6055400 {
211 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 212 compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
212 reg = <0 0xe6055400 0 0x50>; 213 reg = <0 0xe6055400 0 0x50>;
213 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 214 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
214 #gpio-cells = <2>; 215 #gpio-cells = <2>;
@@ -222,7 +223,7 @@
222 }; 223 };
223 224
224 gpio7: gpio@e6055800 { 225 gpio7: gpio@e6055800 {
225 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 226 compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
226 reg = <0 0xe6055800 0 0x50>; 227 reg = <0 0xe6055800 0 0x50>;
227 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 228 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
228 #gpio-cells = <2>; 229 #gpio-cells = <2>;
@@ -1073,7 +1074,7 @@
1073 status = "disabled"; 1074 status = "disabled";
1074 }; 1075 };
1075 1076
1076 vsp1@fe928000 { 1077 vsp@fe928000 {
1077 compatible = "renesas,vsp1"; 1078 compatible = "renesas,vsp1";
1078 reg = <0 0xfe928000 0 0x8000>; 1079 reg = <0 0xfe928000 0 0x8000>;
1079 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 1080 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
@@ -1082,7 +1083,7 @@
1082 resets = <&cpg 131>; 1083 resets = <&cpg 131>;
1083 }; 1084 };
1084 1085
1085 vsp1@fe930000 { 1086 vsp@fe930000 {
1086 compatible = "renesas,vsp1"; 1087 compatible = "renesas,vsp1";
1087 reg = <0 0xfe930000 0 0x8000>; 1088 reg = <0 0xfe930000 0 0x8000>;
1088 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1089 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
@@ -1091,7 +1092,7 @@
1091 resets = <&cpg 128>; 1092 resets = <&cpg 128>;
1092 }; 1093 };
1093 1094
1094 vsp1@fe938000 { 1095 vsp@fe938000 {
1095 compatible = "renesas,vsp1"; 1096 compatible = "renesas,vsp1";
1096 reg = <0 0xfe938000 0 0x8000>; 1097 reg = <0 0xfe938000 0 0x8000>;
1097 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 1098 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index c332f77ebb6b..131f65b0426e 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -56,6 +56,7 @@
56 compatible = "arm,cortex-a15"; 56 compatible = "arm,cortex-a15";
57 reg = <1>; 57 reg = <1>;
58 clock-frequency = <1000000000>; 58 clock-frequency = <1000000000>;
59 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
59 power-domains = <&sysc R8A7792_PD_CA15_CPU1>; 60 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
60 next-level-cache = <&L2_CA15>; 61 next-level-cache = <&L2_CA15>;
61 }; 62 };
@@ -147,7 +148,7 @@
147 148
148 gpio0: gpio@e6050000 { 149 gpio0: gpio@e6050000 {
149 compatible = "renesas,gpio-r8a7792", 150 compatible = "renesas,gpio-r8a7792",
150 "renesas,gpio-rcar"; 151 "renesas,rcar-gen2-gpio";
151 reg = <0 0xe6050000 0 0x50>; 152 reg = <0 0xe6050000 0 0x50>;
152 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 153 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
153 #gpio-cells = <2>; 154 #gpio-cells = <2>;
@@ -162,7 +163,7 @@
162 163
163 gpio1: gpio@e6051000 { 164 gpio1: gpio@e6051000 {
164 compatible = "renesas,gpio-r8a7792", 165 compatible = "renesas,gpio-r8a7792",
165 "renesas,gpio-rcar"; 166 "renesas,rcar-gen2-gpio";
166 reg = <0 0xe6051000 0 0x50>; 167 reg = <0 0xe6051000 0 0x50>;
167 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 168 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
168 #gpio-cells = <2>; 169 #gpio-cells = <2>;
@@ -177,7 +178,7 @@
177 178
178 gpio2: gpio@e6052000 { 179 gpio2: gpio@e6052000 {
179 compatible = "renesas,gpio-r8a7792", 180 compatible = "renesas,gpio-r8a7792",
180 "renesas,gpio-rcar"; 181 "renesas,rcar-gen2-gpio";
181 reg = <0 0xe6052000 0 0x50>; 182 reg = <0 0xe6052000 0 0x50>;
182 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 183 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
183 #gpio-cells = <2>; 184 #gpio-cells = <2>;
@@ -192,7 +193,7 @@
192 193
193 gpio3: gpio@e6053000 { 194 gpio3: gpio@e6053000 {
194 compatible = "renesas,gpio-r8a7792", 195 compatible = "renesas,gpio-r8a7792",
195 "renesas,gpio-rcar"; 196 "renesas,rcar-gen2-gpio";
196 reg = <0 0xe6053000 0 0x50>; 197 reg = <0 0xe6053000 0 0x50>;
197 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 198 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
198 #gpio-cells = <2>; 199 #gpio-cells = <2>;
@@ -207,7 +208,7 @@
207 208
208 gpio4: gpio@e6054000 { 209 gpio4: gpio@e6054000 {
209 compatible = "renesas,gpio-r8a7792", 210 compatible = "renesas,gpio-r8a7792",
210 "renesas,gpio-rcar"; 211 "renesas,rcar-gen2-gpio";
211 reg = <0 0xe6054000 0 0x50>; 212 reg = <0 0xe6054000 0 0x50>;
212 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 213 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
213 #gpio-cells = <2>; 214 #gpio-cells = <2>;
@@ -222,7 +223,7 @@
222 223
223 gpio5: gpio@e6055000 { 224 gpio5: gpio@e6055000 {
224 compatible = "renesas,gpio-r8a7792", 225 compatible = "renesas,gpio-r8a7792",
225 "renesas,gpio-rcar"; 226 "renesas,rcar-gen2-gpio";
226 reg = <0 0xe6055000 0 0x50>; 227 reg = <0 0xe6055000 0 0x50>;
227 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 228 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
228 #gpio-cells = <2>; 229 #gpio-cells = <2>;
@@ -237,7 +238,7 @@
237 238
238 gpio6: gpio@e6055100 { 239 gpio6: gpio@e6055100 {
239 compatible = "renesas,gpio-r8a7792", 240 compatible = "renesas,gpio-r8a7792",
240 "renesas,gpio-rcar"; 241 "renesas,rcar-gen2-gpio";
241 reg = <0 0xe6055100 0 0x50>; 242 reg = <0 0xe6055100 0 0x50>;
242 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 243 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
243 #gpio-cells = <2>; 244 #gpio-cells = <2>;
@@ -252,7 +253,7 @@
252 253
253 gpio7: gpio@e6055200 { 254 gpio7: gpio@e6055200 {
254 compatible = "renesas,gpio-r8a7792", 255 compatible = "renesas,gpio-r8a7792",
255 "renesas,gpio-rcar"; 256 "renesas,rcar-gen2-gpio";
256 reg = <0 0xe6055200 0 0x50>; 257 reg = <0 0xe6055200 0 0x50>;
257 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 258 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
258 #gpio-cells = <2>; 259 #gpio-cells = <2>;
@@ -267,7 +268,7 @@
267 268
268 gpio8: gpio@e6055300 { 269 gpio8: gpio@e6055300 {
269 compatible = "renesas,gpio-r8a7792", 270 compatible = "renesas,gpio-r8a7792",
270 "renesas,gpio-rcar"; 271 "renesas,rcar-gen2-gpio";
271 reg = <0 0xe6055300 0 0x50>; 272 reg = <0 0xe6055300 0 0x50>;
272 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 273 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
273 #gpio-cells = <2>; 274 #gpio-cells = <2>;
@@ -282,7 +283,7 @@
282 283
283 gpio9: gpio@e6055400 { 284 gpio9: gpio@e6055400 {
284 compatible = "renesas,gpio-r8a7792", 285 compatible = "renesas,gpio-r8a7792",
285 "renesas,gpio-rcar"; 286 "renesas,rcar-gen2-gpio";
286 reg = <0 0xe6055400 0 0x50>; 287 reg = <0 0xe6055400 0 0x50>;
287 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 288 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
288 #gpio-cells = <2>; 289 #gpio-cells = <2>;
@@ -297,7 +298,7 @@
297 298
298 gpio10: gpio@e6055500 { 299 gpio10: gpio@e6055500 {
299 compatible = "renesas,gpio-r8a7792", 300 compatible = "renesas,gpio-r8a7792",
300 "renesas,gpio-rcar"; 301 "renesas,rcar-gen2-gpio";
301 reg = <0 0xe6055500 0 0x50>; 302 reg = <0 0xe6055500 0 0x50>;
302 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 303 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
303 #gpio-cells = <2>; 304 #gpio-cells = <2>;
@@ -312,7 +313,7 @@
312 313
313 gpio11: gpio@e6055600 { 314 gpio11: gpio@e6055600 {
314 compatible = "renesas,gpio-r8a7792", 315 compatible = "renesas,gpio-r8a7792",
315 "renesas,gpio-rcar"; 316 "renesas,rcar-gen2-gpio";
316 reg = <0 0xe6055600 0 0x50>; 317 reg = <0 0xe6055600 0 0x50>;
317 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 318 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
318 #gpio-cells = <2>; 319 #gpio-cells = <2>;
@@ -794,7 +795,7 @@
794 status = "disabled"; 795 status = "disabled";
795 }; 796 };
796 797
797 vsp1@fe928000 { 798 vsp@fe928000 {
798 compatible = "renesas,vsp1"; 799 compatible = "renesas,vsp1";
799 reg = <0 0xfe928000 0 0x8000>; 800 reg = <0 0xfe928000 0 0x8000>;
800 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 801 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
@@ -803,7 +804,7 @@
803 resets = <&cpg 131>; 804 resets = <&cpg 131>;
804 }; 805 };
805 806
806 vsp1@fe930000 { 807 vsp@fe930000 {
807 compatible = "renesas,vsp1"; 808 compatible = "renesas,vsp1";
808 reg = <0 0xfe930000 0 0x8000>; 809 reg = <0 0xfe930000 0 0x8000>;
809 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 810 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
@@ -812,7 +813,7 @@
812 resets = <&cpg 128>; 813 resets = <&cpg 128>;
813 }; 814 };
814 815
815 vsp1@fe938000 { 816 vsp@fe938000 {
816 compatible = "renesas,vsp1"; 817 compatible = "renesas,vsp1";
817 reg = <0 0xfe938000 0 0x8000>; 818 reg = <0 0xfe938000 0 0x8000>;
818 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 819 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index aa19b93494bf..58eae569b4e0 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -62,6 +62,7 @@
62 compatible = "arm,cortex-a15"; 62 compatible = "arm,cortex-a15";
63 reg = <1>; 63 reg = <1>;
64 clock-frequency = <1500000000>; 64 clock-frequency = <1500000000>;
65 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
65 power-domains = <&sysc R8A7793_PD_CA15_CPU1>; 66 power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
66 }; 67 };
67 68
@@ -115,7 +116,7 @@
115 }; 116 };
116 117
117 gpio0: gpio@e6050000 { 118 gpio0: gpio@e6050000 {
118 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 119 compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
119 reg = <0 0xe6050000 0 0x50>; 120 reg = <0 0xe6050000 0 0x50>;
120 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 121 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
121 #gpio-cells = <2>; 122 #gpio-cells = <2>;
@@ -129,7 +130,7 @@
129 }; 130 };
130 131
131 gpio1: gpio@e6051000 { 132 gpio1: gpio@e6051000 {
132 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 133 compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
133 reg = <0 0xe6051000 0 0x50>; 134 reg = <0 0xe6051000 0 0x50>;
134 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 135 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
135 #gpio-cells = <2>; 136 #gpio-cells = <2>;
@@ -143,7 +144,7 @@
143 }; 144 };
144 145
145 gpio2: gpio@e6052000 { 146 gpio2: gpio@e6052000 {
146 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 147 compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
147 reg = <0 0xe6052000 0 0x50>; 148 reg = <0 0xe6052000 0 0x50>;
148 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 149 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
149 #gpio-cells = <2>; 150 #gpio-cells = <2>;
@@ -157,7 +158,7 @@
157 }; 158 };
158 159
159 gpio3: gpio@e6053000 { 160 gpio3: gpio@e6053000 {
160 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 161 compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
161 reg = <0 0xe6053000 0 0x50>; 162 reg = <0 0xe6053000 0 0x50>;
162 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 163 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
163 #gpio-cells = <2>; 164 #gpio-cells = <2>;
@@ -171,7 +172,7 @@
171 }; 172 };
172 173
173 gpio4: gpio@e6054000 { 174 gpio4: gpio@e6054000 {
174 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 175 compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
175 reg = <0 0xe6054000 0 0x50>; 176 reg = <0 0xe6054000 0 0x50>;
176 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 177 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
177 #gpio-cells = <2>; 178 #gpio-cells = <2>;
@@ -185,7 +186,7 @@
185 }; 186 };
186 187
187 gpio5: gpio@e6055000 { 188 gpio5: gpio@e6055000 {
188 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 189 compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
189 reg = <0 0xe6055000 0 0x50>; 190 reg = <0 0xe6055000 0 0x50>;
190 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 191 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
191 #gpio-cells = <2>; 192 #gpio-cells = <2>;
@@ -199,7 +200,7 @@
199 }; 200 };
200 201
201 gpio6: gpio@e6055400 { 202 gpio6: gpio@e6055400 {
202 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 203 compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
203 reg = <0 0xe6055400 0 0x50>; 204 reg = <0 0xe6055400 0 0x50>;
204 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 205 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
205 #gpio-cells = <2>; 206 #gpio-cells = <2>;
@@ -213,7 +214,7 @@
213 }; 214 };
214 215
215 gpio7: gpio@e6055800 { 216 gpio7: gpio@e6055800 {
216 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; 217 compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
217 reg = <0 0xe6055800 0 0x50>; 218 reg = <0 0xe6055800 0 0x50>;
218 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 219 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
219 #gpio-cells = <2>; 220 #gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 035c33715b65..905e50c9b524 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -53,6 +53,7 @@
53 compatible = "arm,cortex-a7"; 53 compatible = "arm,cortex-a7";
54 reg = <1>; 54 reg = <1>;
55 clock-frequency = <1000000000>; 55 clock-frequency = <1000000000>;
56 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
56 power-domains = <&sysc R8A7794_PD_CA7_CPU1>; 57 power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
57 next-level-cache = <&L2_CA7>; 58 next-level-cache = <&L2_CA7>;
58 }; 59 };
@@ -82,7 +83,7 @@
82 }; 83 };
83 84
84 gpio0: gpio@e6050000 { 85 gpio0: gpio@e6050000 {
85 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; 86 compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
86 reg = <0 0xe6050000 0 0x50>; 87 reg = <0 0xe6050000 0 0x50>;
87 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 88 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
88 #gpio-cells = <2>; 89 #gpio-cells = <2>;
@@ -96,7 +97,7 @@
96 }; 97 };
97 98
98 gpio1: gpio@e6051000 { 99 gpio1: gpio@e6051000 {
99 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; 100 compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
100 reg = <0 0xe6051000 0 0x50>; 101 reg = <0 0xe6051000 0 0x50>;
101 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 102 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
102 #gpio-cells = <2>; 103 #gpio-cells = <2>;
@@ -110,7 +111,7 @@
110 }; 111 };
111 112
112 gpio2: gpio@e6052000 { 113 gpio2: gpio@e6052000 {
113 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; 114 compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
114 reg = <0 0xe6052000 0 0x50>; 115 reg = <0 0xe6052000 0 0x50>;
115 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 116 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
116 #gpio-cells = <2>; 117 #gpio-cells = <2>;
@@ -124,7 +125,7 @@
124 }; 125 };
125 126
126 gpio3: gpio@e6053000 { 127 gpio3: gpio@e6053000 {
127 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; 128 compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
128 reg = <0 0xe6053000 0 0x50>; 129 reg = <0 0xe6053000 0 0x50>;
129 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 130 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
130 #gpio-cells = <2>; 131 #gpio-cells = <2>;
@@ -138,7 +139,7 @@
138 }; 139 };
139 140
140 gpio4: gpio@e6054000 { 141 gpio4: gpio@e6054000 {
141 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; 142 compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
142 reg = <0 0xe6054000 0 0x50>; 143 reg = <0 0xe6054000 0 0x50>;
143 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 144 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
144 #gpio-cells = <2>; 145 #gpio-cells = <2>;
@@ -152,7 +153,7 @@
152 }; 153 };
153 154
154 gpio5: gpio@e6055000 { 155 gpio5: gpio@e6055000 {
155 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; 156 compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
156 reg = <0 0xe6055000 0 0x50>; 157 reg = <0 0xe6055000 0 0x50>;
157 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 158 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
158 #gpio-cells = <2>; 159 #gpio-cells = <2>;
@@ -166,7 +167,7 @@
166 }; 167 };
167 168
168 gpio6: gpio@e6055400 { 169 gpio6: gpio@e6055400 {
169 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar"; 170 compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
170 reg = <0 0xe6055400 0 0x50>; 171 reg = <0 0xe6055400 0 0x50>;
171 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 172 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>; 173 #gpio-cells = <2>;
@@ -970,7 +971,7 @@
970 }; 971 };
971 }; 972 };
972 973
973 vsp1@fe928000 { 974 vsp@fe928000 {
974 compatible = "renesas,vsp1"; 975 compatible = "renesas,vsp1";
975 reg = <0 0xfe928000 0 0x8000>; 976 reg = <0 0xfe928000 0 0x8000>;
976 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 977 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
@@ -979,7 +980,7 @@
979 resets = <&cpg 131>; 980 resets = <&cpg 131>;
980 }; 981 };
981 982
982 vsp1@fe930000 { 983 vsp@fe930000 {
983 compatible = "renesas,vsp1"; 984 compatible = "renesas,vsp1";
984 reg = <0 0xfe930000 0 0x8000>; 985 reg = <0 0xfe930000 0 0x8000>;
985 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 986 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 4ea5c5a16c57..88d7e5631d34 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -27,6 +27,7 @@
27 compatible = "arm,cortex-a9"; 27 compatible = "arm,cortex-a9";
28 reg = <0>; 28 reg = <0>;
29 clock-frequency = <1196000000>; 29 clock-frequency = <1196000000>;
30 clocks = <&cpg_clocks SH73A0_CLK_Z>;
30 power-domains = <&pd_a2sl>; 31 power-domains = <&pd_a2sl>;
31 next-level-cache = <&L2>; 32 next-level-cache = <&L2>;
32 }; 33 };
@@ -35,6 +36,7 @@
35 compatible = "arm,cortex-a9"; 36 compatible = "arm,cortex-a9";
36 reg = <1>; 37 reg = <1>;
37 clock-frequency = <1196000000>; 38 clock-frequency = <1196000000>;
39 clocks = <&cpg_clocks SH73A0_CLK_Z>;
38 power-domains = <&pd_a2sl>; 40 power-domains = <&pd_a2sl>;
39 next-level-cache = <&L2>; 41 next-level-cache = <&L2>;
40 }; 42 };
diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h
index 7dd8bc0c3cd0..0dcb3e87d44c 100644
--- a/include/dt-bindings/clock/r7s72100-clock.h
+++ b/include/dt-bindings/clock/r7s72100-clock.h
@@ -11,6 +11,8 @@
11#define __DT_BINDINGS_CLOCK_R7S72100_H__ 11#define __DT_BINDINGS_CLOCK_R7S72100_H__
12 12
13#define R7S72100_CLK_PLL 0 13#define R7S72100_CLK_PLL 0
14#define R7S72100_CLK_I 1
15#define R7S72100_CLK_G 2
14 16
15/* MSTP2 */ 17/* MSTP2 */
16#define R7S72100_CLK_CORESIGHT 0 18#define R7S72100_CLK_CORESIGHT 0
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 07:49:47 -0400