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authorGeert Uytterhoeven <geert+renesas@glider.be>2019-03-01 06:07:15 -0500
committerGeert Uytterhoeven <geert+renesas@glider.be>2019-03-18 12:03:57 -0400
commit6a82559f745bc26d2e4974c1d26014ef7fa14794 (patch)
tree922dc1124ce2bfba27be5e2ef24c9fd10d0d3efb
parent9e98c678c2d6ae3a17cb2de55d17f69dddaa231b (diff)
clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register()
Explicitly pass the clock's name and register offset to cpg_sd_clk_register(), so the latter doesn't have to extract them from the cpg_core_clk object. This keeps all cpg_core_clk parsing and unmarshalling contained in a single function (rcar_gen3_cpg_clk_register()). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 9a8071a8114d..dcd4ac389326 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -369,8 +369,8 @@ static u32 cpg_quirks __initdata;
369#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ 369#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
370#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */ 370#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
371 371
372static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, 372static struct clk * __init cpg_sd_clk_register(const char *name,
373 void __iomem *base, const char *parent_name, 373 void __iomem *base, unsigned int offset, const char *parent_name,
374 struct raw_notifier_head *notifiers) 374 struct raw_notifier_head *notifiers)
375{ 375{
376 struct clk_init_data init; 376 struct clk_init_data init;
@@ -383,13 +383,13 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
383 if (!clock) 383 if (!clock)
384 return ERR_PTR(-ENOMEM); 384 return ERR_PTR(-ENOMEM);
385 385
386 init.name = core->name; 386 init.name = name;
387 init.ops = &cpg_sd_clock_ops; 387 init.ops = &cpg_sd_clock_ops;
388 init.flags = CLK_SET_RATE_PARENT; 388 init.flags = CLK_SET_RATE_PARENT;
389 init.parent_names = &parent_name; 389 init.parent_names = &parent_name;
390 init.num_parents = 1; 390 init.num_parents = 1;
391 391
392 clock->csn.reg = base + core->offset; 392 clock->csn.reg = base + offset;
393 clock->hw.init = &init; 393 clock->hw.init = &init;
394 clock->div_table = cpg_sd_div_table; 394 clock->div_table = cpg_sd_div_table;
395 clock->div_num = ARRAY_SIZE(cpg_sd_div_table); 395 clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
@@ -606,8 +606,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
606 break; 606 break;
607 607
608 case CLK_TYPE_GEN3_SD: 608 case CLK_TYPE_GEN3_SD:
609 return cpg_sd_clk_register(core, base, __clk_get_name(parent), 609 return cpg_sd_clk_register(core->name, base, core->offset,
610 notifiers); 610 __clk_get_name(parent), notifiers);
611 611
612 case CLK_TYPE_GEN3_R: 612 case CLK_TYPE_GEN3_R:
613 if (cpg_quirks & RCKCR_CKSEL) { 613 if (cpg_quirks & RCKCR_CKSEL) {