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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2018-06-11 19:55:04 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2018-07-23 01:22:52 -0400
commit6a794a27daca9c5a39de13c03b0748bb2d4a7a70 (patch)
treea1d3f7354c7c142fdaea5fc721f538fbd756b69d
parent2be5263c5df45bbd5ad49ea8c394aca6e709d204 (diff)
fsi: master-ast-cf: Add new FSI master using Aspeed ColdFire
The Aspeed AST2x00 can contain a ColdFire v1 coprocessor which is currently unused on OpenPower systems. This adds an alternative to the fsi-master-gpio driver that uses that coprocessor instead of bit banging from the ARM core itself. The end result is about 4 times faster. The firmware for the coprocessor and its source code can be found at https://github.com/ozbenh/cf-fsi and is system specific. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat
-rw-r--r--drivers/fsi/Kconfig9
-rw-r--r--drivers/fsi/Makefile1
-rw-r--r--drivers/fsi/cf-fsi-fw.h157
-rw-r--r--drivers/fsi/fsi-master-ast-cf.c1438
-rw-r--r--include/trace/events/fsi_master_ast_cf.h150
5 files changed, 1755 insertions, 0 deletions
diff --git a/drivers/fsi/Kconfig b/drivers/fsi/Kconfig
index 9c08f467a7bb..8d82b1e60514 100644
--- a/drivers/fsi/Kconfig
+++ b/drivers/fsi/Kconfig
@@ -27,6 +27,15 @@ config FSI_MASTER_HUB
27 allow chaining of FSI links to an arbitrary depth. This allows for 27 allow chaining of FSI links to an arbitrary depth. This allows for
28 a high target device fanout. 28 a high target device fanout.
29 29
30config FSI_MASTER_AST_CF
31 tristate "FSI master based on Aspeed ColdFire coprocessor"
32 depends on GPIOLIB
33 depends on GPIO_ASPEED
34 ---help---
35 This option enables a FSI master using the AST2400 and AST2500 GPIO
36 lines driven by the internal ColdFire coprocessor. This requires
37 the corresponding machine specific ColdFire firmware to be available.
38
30config FSI_SCOM 39config FSI_SCOM
31 tristate "SCOM FSI client device driver" 40 tristate "SCOM FSI client device driver"
32 ---help--- 41 ---help---
diff --git a/drivers/fsi/Makefile b/drivers/fsi/Makefile
index 851182e1cd9e..a50d6ce22fb3 100644
--- a/drivers/fsi/Makefile
+++ b/drivers/fsi/Makefile
@@ -2,5 +2,6 @@
2obj-$(CONFIG_FSI) += fsi-core.o 2obj-$(CONFIG_FSI) += fsi-core.o
3obj-$(CONFIG_FSI_MASTER_HUB) += fsi-master-hub.o 3obj-$(CONFIG_FSI_MASTER_HUB) += fsi-master-hub.o
4obj-$(CONFIG_FSI_MASTER_GPIO) += fsi-master-gpio.o 4obj-$(CONFIG_FSI_MASTER_GPIO) += fsi-master-gpio.o
5obj-$(CONFIG_FSI_MASTER_AST_CF) += fsi-master-ast-cf.o
5obj-$(CONFIG_FSI_SCOM) += fsi-scom.o 6obj-$(CONFIG_FSI_SCOM) += fsi-scom.o
6obj-$(CONFIG_FSI_SBEFIFO) += fsi-sbefifo.o 7obj-$(CONFIG_FSI_SBEFIFO) += fsi-sbefifo.o
diff --git a/drivers/fsi/cf-fsi-fw.h b/drivers/fsi/cf-fsi-fw.h
new file mode 100644
index 000000000000..712df0461911
--- /dev/null
+++ b/drivers/fsi/cf-fsi-fw.h
@@ -0,0 +1,157 @@
1// SPDX-License-Identifier: GPL-2.0+
2#ifndef __CF_FSI_FW_H
3#define __CF_FSI_FW_H
4
5/*
6 * uCode file layout
7 *
8 * 0000...03ff : m68k exception vectors
9 * 0400...04ff : Header info & boot config block
10 * 0500....... : Code & stack
11 */
12
13/*
14 * Header info & boot config area
15 *
16 * The Header info is built into the ucode and provide version and
17 * platform information.
18 *
19 * the Boot config needs to be adjusted by the ARM prior to starting
20 * the ucode if the Command/Status area isn't at 0x320000 in CF space
21 * (ie. beginning of SRAM).
22 */
23
24#define HDR_OFFSET 0x400
25
26/* Info: Signature & version */
27#define HDR_SYS_SIG 0x00 /* 2 bytes system signature */
28#define SYS_SIG_SHARED 0x5348
29#define SYS_SIG_SPLIT 0x5350
30#define HDR_FW_VERS 0x02 /* 2 bytes Major.Minor */
31#define HDR_API_VERS 0x04 /* 2 bytes Major.Minor */
32#define API_VERSION_MAJ 2 /* Current version */
33#define API_VERSION_MIN 1
34#define HDR_FW_OPTIONS 0x08 /* 4 bytes option flags */
35#define FW_OPTION_TRACE_EN 0x00000001 /* FW tracing enabled */
36#define FW_OPTION_CONT_CLOCK 0x00000002 /* Continuous clocking supported */
37#define HDR_FW_SIZE 0x10 /* 4 bytes size for combo image */
38
39/* Boot Config: Address of Command/Status area */
40#define HDR_CMD_STAT_AREA 0x80 /* 4 bytes CF address */
41#define HDR_FW_CONTROL 0x84 /* 4 bytes control flags */
42#define FW_CONTROL_CONT_CLOCK 0x00000002 /* Continuous clocking enabled */
43#define FW_CONTROL_DUMMY_RD 0x00000004 /* Extra dummy read (AST2400) */
44#define FW_CONTROL_USE_STOP 0x00000008 /* Use STOP instructions */
45#define HDR_CLOCK_GPIO_VADDR 0x90 /* 2 bytes offset from GPIO base */
46#define HDR_CLOCK_GPIO_DADDR 0x92 /* 2 bytes offset from GPIO base */
47#define HDR_DATA_GPIO_VADDR 0x94 /* 2 bytes offset from GPIO base */
48#define HDR_DATA_GPIO_DADDR 0x96 /* 2 bytes offset from GPIO base */
49#define HDR_TRANS_GPIO_VADDR 0x98 /* 2 bytes offset from GPIO base */
50#define HDR_TRANS_GPIO_DADDR 0x9a /* 2 bytes offset from GPIO base */
51#define HDR_CLOCK_GPIO_BIT 0x9c /* 1 byte bit number */
52#define HDR_DATA_GPIO_BIT 0x9d /* 1 byte bit number */
53#define HDR_TRANS_GPIO_BIT 0x9e /* 1 byte bit number */
54
55/*
56 * Command/Status area layout: Main part
57 */
58
59/* Command/Status register:
60 *
61 * +---------------------------+
62 * | STAT | RLEN | CLEN | CMD |
63 * | 8 | 8 | 8 | 8 |
64 * +---------------------------+
65 * | | | |
66 * status | | |
67 * Response len | |
68 * (in bits) | |
69 * | |
70 * Command len |
71 * (in bits) |
72 * |
73 * Command code
74 *
75 * Due to the big endian layout, that means that a byte read will
76 * return the status byte
77 */
78#define CMD_STAT_REG 0x00
79#define CMD_REG_CMD_MASK 0x000000ff
80#define CMD_REG_CMD_SHIFT 0
81#define CMD_NONE 0x00
82#define CMD_COMMAND 0x01
83#define CMD_BREAK 0x02
84#define CMD_IDLE_CLOCKS 0x03 /* clen = #clocks */
85#define CMD_INVALID 0xff
86#define CMD_REG_CLEN_MASK 0x0000ff00
87#define CMD_REG_CLEN_SHIFT 8
88#define CMD_REG_RLEN_MASK 0x00ff0000
89#define CMD_REG_RLEN_SHIFT 16
90#define CMD_REG_STAT_MASK 0xff000000
91#define CMD_REG_STAT_SHIFT 24
92#define STAT_WORKING 0x00
93#define STAT_COMPLETE 0x01
94#define STAT_ERR_INVAL_CMD 0x80
95#define STAT_ERR_INVAL_IRQ 0x81
96#define STAT_ERR_MTOE 0x82
97
98/* Response tag & CRC */
99#define STAT_RTAG 0x04
100
101/* Response CRC */
102#define STAT_RCRC 0x05
103
104/* Echo and Send delay */
105#define ECHO_DLY_REG 0x08
106#define SEND_DLY_REG 0x09
107
108/* Command data area
109 *
110 * Last byte of message must be left aligned
111 */
112#define CMD_DATA 0x10 /* 64 bit of data */
113
114/* Response data area, right aligned, unused top bits are 1 */
115#define RSP_DATA 0x20 /* 32 bit of data */
116
117/* Misc */
118#define INT_CNT 0x30 /* 32-bit interrupt count */
119#define BAD_INT_VEC 0x34 /* 32-bit bad interrupt vector # */
120#define CF_STARTED 0x38 /* byte, set to -1 when copro started */
121#define CLK_CNT 0x3c /* 32-bit, clock count (debug only) */
122
123/*
124 * SRAM layout: GPIO arbitration part
125 */
126#define ARB_REG 0x40
127#define ARB_ARM_REQ 0x01
128#define ARB_ARM_ACK 0x02
129
130/* Misc2 */
131#define CF_RESET_D0 0x50
132#define CF_RESET_D1 0x54
133#define BAD_INT_S0 0x58
134#define BAD_INT_S1 0x5c
135#define STOP_CNT 0x60
136
137/* Internal */
138
139/*
140 * SRAM layout: Trace buffer (debug builds only)
141 */
142#define TRACEBUF 0x100
143#define TR_CLKOBIT0 0xc0
144#define TR_CLKOBIT1 0xc1
145#define TR_CLKOSTART 0x82
146#define TR_OLEN 0x83 /* + len */
147#define TR_CLKZ 0x84 /* + count */
148#define TR_CLKWSTART 0x85
149#define TR_CLKTAG 0x86 /* + tag */
150#define TR_CLKDATA 0x87 /* + len */
151#define TR_CLKCRC 0x88 /* + raw crc */
152#define TR_CLKIBIT0 0x90
153#define TR_CLKIBIT1 0x91
154#define TR_END 0xff
155
156#endif /* __CF_FSI_FW_H */
157
diff --git a/drivers/fsi/fsi-master-ast-cf.c b/drivers/fsi/fsi-master-ast-cf.c
new file mode 100644
index 000000000000..57afaae0b691
--- /dev/null
+++ b/drivers/fsi/fsi-master-ast-cf.c
@@ -0,0 +1,1438 @@
1// SPDX-License-Identifier: GPL-2.0+
2// Copyright 2018 IBM Corp
3/*
4 * A FSI master controller, using a simple GPIO bit-banging interface
5 */
6
7#include <linux/crc4.h>
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/fsi.h>
11#include <linux/gpio/consumer.h>
12#include <linux/io.h>
13#include <linux/irqflags.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/slab.h>
18#include <linux/regmap.h>
19#include <linux/firmware.h>
20#include <linux/gpio/aspeed.h>
21#include <linux/mfd/syscon.h>
22#include <linux/of_address.h>
23#include <linux/genalloc.h>
24
25#include "fsi-master.h"
26#include "cf-fsi-fw.h"
27
28#define FW_FILE_NAME "cf-fsi-fw.bin"
29
30/* Common SCU based coprocessor control registers */
31#define SCU_COPRO_CTRL 0x100
32#define SCU_COPRO_RESET 0x00000002
33#define SCU_COPRO_CLK_EN 0x00000001
34
35/* AST2500 specific ones */
36#define SCU_2500_COPRO_SEG0 0x104
37#define SCU_2500_COPRO_SEG1 0x108
38#define SCU_2500_COPRO_SEG2 0x10c
39#define SCU_2500_COPRO_SEG3 0x110
40#define SCU_2500_COPRO_SEG4 0x114
41#define SCU_2500_COPRO_SEG5 0x118
42#define SCU_2500_COPRO_SEG6 0x11c
43#define SCU_2500_COPRO_SEG7 0x120
44#define SCU_2500_COPRO_SEG8 0x124
45#define SCU_2500_COPRO_SEG_SWAP 0x00000001
46#define SCU_2500_COPRO_CACHE_CTL 0x128
47#define SCU_2500_COPRO_CACHE_EN 0x00000001
48#define SCU_2500_COPRO_SEG0_CACHE_EN 0x00000002
49#define SCU_2500_COPRO_SEG1_CACHE_EN 0x00000004
50#define SCU_2500_COPRO_SEG2_CACHE_EN 0x00000008
51#define SCU_2500_COPRO_SEG3_CACHE_EN 0x00000010
52#define SCU_2500_COPRO_SEG4_CACHE_EN 0x00000020
53#define SCU_2500_COPRO_SEG5_CACHE_EN 0x00000040
54#define SCU_2500_COPRO_SEG6_CACHE_EN 0x00000080
55#define SCU_2500_COPRO_SEG7_CACHE_EN 0x00000100
56#define SCU_2500_COPRO_SEG8_CACHE_EN 0x00000200
57
58#define SCU_2400_COPRO_SEG0 0x104
59#define SCU_2400_COPRO_SEG2 0x108
60#define SCU_2400_COPRO_SEG4 0x10c
61#define SCU_2400_COPRO_SEG6 0x110
62#define SCU_2400_COPRO_SEG8 0x114
63#define SCU_2400_COPRO_SEG_SWAP 0x80000000
64#define SCU_2400_COPRO_CACHE_CTL 0x118
65#define SCU_2400_COPRO_CACHE_EN 0x00000001
66#define SCU_2400_COPRO_SEG0_CACHE_EN 0x00000002
67#define SCU_2400_COPRO_SEG2_CACHE_EN 0x00000004
68#define SCU_2400_COPRO_SEG4_CACHE_EN 0x00000008
69#define SCU_2400_COPRO_SEG6_CACHE_EN 0x00000010
70#define SCU_2400_COPRO_SEG8_CACHE_EN 0x00000020
71
72/* CVIC registers */
73#define CVIC_EN_REG 0x10
74#define CVIC_TRIG_REG 0x18
75
76/*
77 * System register base address (needed for configuring the
78 * coldfire maps)
79 */
80#define SYSREG_BASE 0x1e600000
81
82/* Amount of SRAM required */
83#define SRAM_SIZE 0x1000
84
85#define LAST_ADDR_INVALID 0x1
86
87struct fsi_master_acf {
88 struct fsi_master master;
89 struct device *dev;
90 struct regmap *scu;
91 struct mutex lock; /* mutex for command ordering */
92 struct gpio_desc *gpio_clk;
93 struct gpio_desc *gpio_data;
94 struct gpio_desc *gpio_trans; /* Voltage translator */
95 struct gpio_desc *gpio_enable; /* FSI enable */
96 struct gpio_desc *gpio_mux; /* Mux control */
97 uint16_t gpio_clk_vreg;
98 uint16_t gpio_clk_dreg;
99 uint16_t gpio_dat_vreg;
100 uint16_t gpio_dat_dreg;
101 uint16_t gpio_tra_vreg;
102 uint16_t gpio_tra_dreg;
103 uint8_t gpio_clk_bit;
104 uint8_t gpio_dat_bit;
105 uint8_t gpio_tra_bit;
106 uint32_t cf_mem_addr;
107 size_t cf_mem_size;
108 void __iomem *cf_mem;
109 void __iomem *cvic;
110 struct gen_pool *sram_pool;
111 void __iomem *sram;
112 bool is_ast2500;
113 bool external_mode;
114 bool trace_enabled;
115 uint32_t last_addr;
116 uint8_t t_send_delay;
117 uint8_t t_echo_delay;
118 uint32_t cvic_sw_irq;
119};
120#define to_fsi_master_acf(m) container_of(m, struct fsi_master_acf, master)
121
122struct fsi_msg {
123 uint64_t msg;
124 uint8_t bits;
125};
126
127#define CREATE_TRACE_POINTS
128#include <trace/events/fsi_master_ast_cf.h>
129
130static void msg_push_bits(struct fsi_msg *msg, uint64_t data, int bits)
131{
132 msg->msg <<= bits;
133 msg->msg |= data & ((1ull << bits) - 1);
134 msg->bits += bits;
135}
136
137static void msg_push_crc(struct fsi_msg *msg)
138{
139 uint8_t crc;
140 int top;
141
142 top = msg->bits & 0x3;
143
144 /* start bit, and any non-aligned top bits */
145 crc = crc4(0, 1 << top | msg->msg >> (msg->bits - top), top + 1);
146
147 /* aligned bits */
148 crc = crc4(crc, msg->msg, msg->bits - top);
149
150 msg_push_bits(msg, crc, 4);
151}
152
153static void msg_finish_cmd(struct fsi_msg *cmd)
154{
155 /* Left align message */
156 cmd->msg <<= (64 - cmd->bits);
157}
158
159static bool check_same_address(struct fsi_master_acf *master, int id,
160 uint32_t addr)
161{
162 /* this will also handle LAST_ADDR_INVALID */
163 return master->last_addr == (((id & 0x3) << 21) | (addr & ~0x3));
164}
165
166static bool check_relative_address(struct fsi_master_acf *master, int id,
167 uint32_t addr, uint32_t *rel_addrp)
168{
169 uint32_t last_addr = master->last_addr;
170 int32_t rel_addr;
171
172 if (last_addr == LAST_ADDR_INVALID)
173 return false;
174
175 /* We may be in 23-bit addressing mode, which uses the id as the
176 * top two address bits. So, if we're referencing a different ID,
177 * use absolute addresses.
178 */
179 if (((last_addr >> 21) & 0x3) != id)
180 return false;
181
182 /* remove the top two bits from any 23-bit addressing */
183 last_addr &= (1 << 21) - 1;
184
185 /* We know that the addresses are limited to 21 bits, so this won't
186 * overflow the signed rel_addr */
187 rel_addr = addr - last_addr;
188 if (rel_addr > 255 || rel_addr < -256)
189 return false;
190
191 *rel_addrp = (uint32_t)rel_addr;
192
193 return true;
194}
195
196static void last_address_update(struct fsi_master_acf *master,
197 int id, bool valid, uint32_t addr)
198{
199 if (!valid)
200 master->last_addr = LAST_ADDR_INVALID;
201 else
202 master->last_addr = ((id & 0x3) << 21) | (addr & ~0x3);
203}
204
205/*
206 * Encode an Absolute/Relative/Same Address command
207 */
208static void build_ar_command(struct fsi_master_acf *master,
209 struct fsi_msg *cmd, uint8_t id,
210 uint32_t addr, size_t size,
211 const void *data)
212{
213 int i, addr_bits, opcode_bits;
214 bool write = !!data;
215 uint8_t ds, opcode;
216 uint32_t rel_addr;
217
218 cmd->bits = 0;
219 cmd->msg = 0;
220
221 /* we have 21 bits of address max */
222 addr &= ((1 << 21) - 1);
223
224 /* cmd opcodes are variable length - SAME_AR is only two bits */
225 opcode_bits = 3;
226
227 if (check_same_address(master, id, addr)) {
228 /* we still address the byte offset within the word */
229 addr_bits = 2;
230 opcode_bits = 2;
231 opcode = FSI_CMD_SAME_AR;
232 trace_fsi_master_acf_cmd_same_addr(master);
233
234 } else if (check_relative_address(master, id, addr, &rel_addr)) {
235 /* 8 bits plus sign */
236 addr_bits = 9;
237 addr = rel_addr;
238 opcode = FSI_CMD_REL_AR;
239 trace_fsi_master_acf_cmd_rel_addr(master, rel_addr);
240
241 } else {
242 addr_bits = 21;
243 opcode = FSI_CMD_ABS_AR;
244 trace_fsi_master_acf_cmd_abs_addr(master, addr);
245 }
246
247 /*
248 * The read/write size is encoded in the lower bits of the address
249 * (as it must be naturally-aligned), and the following ds bit.
250 *
251 * size addr:1 addr:0 ds
252 * 1 x x 0
253 * 2 x 0 1
254 * 4 0 1 1
255 *
256 */
257 ds = size > 1 ? 1 : 0;
258 addr &= ~(size - 1);
259 if (size == 4)
260 addr |= 1;
261
262 msg_push_bits(cmd, id, 2);
263 msg_push_bits(cmd, opcode, opcode_bits);
264 msg_push_bits(cmd, write ? 0 : 1, 1);
265 msg_push_bits(cmd, addr, addr_bits);
266 msg_push_bits(cmd, ds, 1);
267 for (i = 0; write && i < size; i++)
268 msg_push_bits(cmd, ((uint8_t *)data)[i], 8);
269
270 msg_push_crc(cmd);
271 msg_finish_cmd(cmd);
272}
273
274static void build_dpoll_command(struct fsi_msg *cmd, uint8_t slave_id)
275{
276 cmd->bits = 0;
277 cmd->msg = 0;
278
279 msg_push_bits(cmd, slave_id, 2);
280 msg_push_bits(cmd, FSI_CMD_DPOLL, 3);
281 msg_push_crc(cmd);
282 msg_finish_cmd(cmd);
283}
284
285static void build_epoll_command(struct fsi_msg *cmd, uint8_t slave_id)
286{
287 cmd->bits = 0;
288 cmd->msg = 0;
289
290 msg_push_bits(cmd, slave_id, 2);
291 msg_push_bits(cmd, FSI_CMD_EPOLL, 3);
292 msg_push_crc(cmd);
293 msg_finish_cmd(cmd);
294}
295
296static void build_term_command(struct fsi_msg *cmd, uint8_t slave_id)
297{
298 cmd->bits = 0;
299 cmd->msg = 0;
300
301 msg_push_bits(cmd, slave_id, 2);
302 msg_push_bits(cmd, FSI_CMD_TERM, 6);
303 msg_push_crc(cmd);
304 msg_finish_cmd(cmd);
305}
306
307static int do_copro_command(struct fsi_master_acf *master, uint32_t op)
308{
309 uint32_t timeout = 10000000;
310 uint8_t stat;
311
312 trace_fsi_master_acf_copro_command(master, op);
313
314 /* Send command */
315 iowrite32be(op, master->sram + CMD_STAT_REG);
316
317 /* Ring doorbell if any */
318 if (master->cvic)
319 iowrite32(0x2, master->cvic + CVIC_TRIG_REG);
320
321 /* Wait for status to indicate completion (or error) */
322 do {
323 if (timeout-- == 0) {
324 dev_warn(master->dev,
325 "Timeout waiting for coprocessor completion\n");
326 return -ETIMEDOUT;
327 }
328 stat = ioread8(master->sram + CMD_STAT_REG);
329 } while(stat < STAT_COMPLETE || stat == 0xff);
330
331 if (stat == STAT_COMPLETE)
332 return 0;
333 switch(stat) {
334 case STAT_ERR_INVAL_CMD:
335 return -EINVAL;
336 case STAT_ERR_INVAL_IRQ:
337 return -EIO;
338 case STAT_ERR_MTOE:
339 return -ESHUTDOWN;
340 }
341 return -ENXIO;
342}
343
344static int clock_zeros(struct fsi_master_acf *master, int count)
345{
346 while (count) {
347 int rc, lcnt = min(count, 255);
348
349 rc = do_copro_command(master,
350 CMD_IDLE_CLOCKS | (lcnt << CMD_REG_CLEN_SHIFT));
351 if (rc)
352 return rc;
353 count -= lcnt;
354 }
355 return 0;
356}
357
358static int send_request(struct fsi_master_acf *master, struct fsi_msg *cmd,
359 unsigned int resp_bits)
360{
361 uint32_t op;
362
363 trace_fsi_master_acf_send_request(master, cmd, resp_bits);
364
365 /* Store message into SRAM */
366 iowrite32be((cmd->msg >> 32), master->sram + CMD_DATA);
367 iowrite32be((cmd->msg & 0xffffffff), master->sram + CMD_DATA + 4);
368
369 op = CMD_COMMAND;
370 op |= cmd->bits << CMD_REG_CLEN_SHIFT;
371 if (resp_bits)
372 op |= resp_bits << CMD_REG_RLEN_SHIFT;
373
374 return do_copro_command(master, op);
375}
376
377static int read_copro_response(struct fsi_master_acf *master, uint8_t size,
378 uint32_t *response, u8 *tag)
379{
380 uint8_t rtag = ioread8(master->sram + STAT_RTAG);
381 uint8_t rcrc = ioread8(master->sram + STAT_RCRC);
382 uint32_t rdata = 0;
383 uint32_t crc;
384 uint8_t ack;
385
386 *tag = ack = rtag & 3;
387
388 /* we have a whole message now; check CRC */
389 crc = crc4(0, 1, 1);
390 crc = crc4(crc, rtag, 4);
391 if (ack == FSI_RESP_ACK && size) {
392 rdata = ioread32be(master->sram + RSP_DATA);
393 crc = crc4(crc, rdata, size);
394 if (response)
395 *response = rdata;
396 }
397 crc = crc4(crc, rcrc, 4);
398
399 trace_fsi_master_acf_copro_response(master, rtag, rcrc, rdata, crc == 0);
400
401 if (crc) {
402 /*
403 * Check if it's all 1's or all 0's, that probably means
404 * the host is off
405 */
406 if ((rtag == 0xf && rcrc == 0xf) || (rtag == 0 && rcrc == 0))
407 return -ENODEV;
408 dev_dbg(master->dev, "Bad response CRC !\n");
409 return -EAGAIN;
410 }
411 return 0;
412}
413
414static int send_term(struct fsi_master_acf *master, uint8_t slave)
415{
416 struct fsi_msg cmd;
417 uint8_t tag;
418 int rc;
419
420 build_term_command(&cmd, slave);
421
422 rc = send_request(master, &cmd, 0);
423 if (rc) {
424 dev_warn(master->dev, "Error %d sending term\n", rc);
425 return rc;
426 }
427
428 rc = read_copro_response(master, 0, NULL, &tag);
429 if (rc < 0) {
430 dev_err(master->dev,
431 "TERM failed; lost communication with slave\n");
432 return -EIO;
433 } else if (tag != FSI_RESP_ACK) {
434 dev_err(master->dev, "TERM failed; response %d\n", tag);
435 return -EIO;
436 }
437 return 0;
438}
439
440static void dump_trace(struct fsi_master_acf *master)
441{
442 char trbuf[52];
443 char *p;
444 int i;
445
446 dev_dbg(master->dev,
447 "CMDSTAT:%08x RTAG=%02x RCRC=%02x RDATA=%02x #INT=%08x\n",
448 ioread32be(master->sram + CMD_STAT_REG),
449 ioread8(master->sram + STAT_RTAG),
450 ioread8(master->sram + STAT_RCRC),
451 ioread32be(master->sram + RSP_DATA),
452 ioread32be(master->sram + INT_CNT));
453
454 for (i = 0; i < 512; i++) {
455 uint8_t v;
456 if ((i % 16) == 0)
457 p = trbuf;
458 v = ioread8(master->sram + TRACEBUF + i);
459 p += sprintf(p, "%02x ", v);
460 if (((i % 16) == 15) || v == TR_END)
461 dev_dbg(master->dev, "%s\n", trbuf);
462 if (v == TR_END)
463 break;
464 }
465}
466
467static int handle_response(struct fsi_master_acf *master,
468 uint8_t slave, uint8_t size, void *data)
469{
470 int busy_count = 0, rc;
471 int crc_err_retries = 0;
472 struct fsi_msg cmd;
473 uint32_t response;
474 uint8_t tag;
475retry:
476 rc = read_copro_response(master, size, &response, &tag);
477
478 /* Handle retries on CRC errors */
479 if (rc == -EAGAIN) {
480 /* Too many retries ? */
481 if (crc_err_retries++ > FSI_CRC_ERR_RETRIES) {
482 /*
483 * Pass it up as a -EIO otherwise upper level will retry
484 * the whole command which isn't what we want here.
485 */
486 rc = -EIO;
487 goto bail;
488 }
489 trace_fsi_master_acf_crc_rsp_error(master, crc_err_retries);
490 if (master->trace_enabled)
491 dump_trace(master);
492 rc = clock_zeros(master, FSI_MASTER_EPOLL_CLOCKS);
493 if (rc) {
494 dev_warn(master->dev,
495 "Error %d clocking zeros for E_POLL\n", rc);
496 return rc;
497 }
498 build_epoll_command(&cmd, slave);
499 rc = send_request(master, &cmd, size);
500 if (rc) {
501 dev_warn(master->dev, "Error %d sending E_POLL\n", rc);
502 return -EIO;
503 }
504 goto retry;
505 }
506 if (rc)
507 return rc;
508
509 switch (tag) {
510 case FSI_RESP_ACK:
511 if (size && data) {
512 if (size == 32)
513 *(__be32 *)data = cpu_to_be32(response);
514 else if (size == 16)
515 *(__be16 *)data = cpu_to_be16(response);
516 else
517 *(u8 *)data = response;
518 }
519 break;
520 case FSI_RESP_BUSY:
521 /*
522 * Its necessary to clock slave before issuing
523 * d-poll, not indicated in the hardware protocol
524 * spec. < 20 clocks causes slave to hang, 21 ok.
525 */
526 dev_dbg(master->dev, "Busy, retrying...\n");
527 if (master->trace_enabled)
528 dump_trace(master);
529 rc = clock_zeros(master, FSI_MASTER_DPOLL_CLOCKS);
530 if (rc) {
531 dev_warn(master->dev,
532 "Error %d clocking zeros for D_POLL\n", rc);
533 break;
534 }
535 if (busy_count++ < FSI_MASTER_MAX_BUSY) {
536 build_dpoll_command(&cmd, slave);
537 rc = send_request(master, &cmd, size);
538 if (rc) {
539 dev_warn(master->dev, "Error %d sending D_POLL\n", rc);
540 break;
541 }
542 goto retry;
543 }
544 dev_dbg(master->dev,
545 "ERR slave is stuck in busy state, issuing TERM\n");
546 send_term(master, slave);
547 rc = -EIO;
548 break;
549
550 case FSI_RESP_ERRA:
551 dev_dbg(master->dev, "ERRA received\n");
552 if (master->trace_enabled)
553 dump_trace(master);
554 rc = -EIO;
555 break;
556 case FSI_RESP_ERRC:
557 dev_dbg(master->dev, "ERRC received\n");
558 if (master->trace_enabled)
559 dump_trace(master);
560 rc = -EAGAIN;
561 break;
562 }
563 bail:
564 if (busy_count > 0) {
565 trace_fsi_master_acf_poll_response_busy(master, busy_count);
566 }
567
568 return rc;
569}
570
571static int fsi_master_acf_xfer(struct fsi_master_acf *master, uint8_t slave,
572 struct fsi_msg *cmd, size_t resp_len, void *resp)
573{
574 int rc = -EAGAIN, retries = 0;
575
576 resp_len <<= 3;
577 while ((retries++) < FSI_CRC_ERR_RETRIES) {
578 rc = send_request(master, cmd, resp_len);
579 if (rc) {
580 if (rc != -ESHUTDOWN)
581 dev_warn(master->dev, "Error %d sending command\n", rc);
582 break;
583 }
584 rc = handle_response(master, slave, resp_len, resp);
585 if (rc != -EAGAIN)
586 break;
587 rc = -EIO;
588 dev_dbg(master->dev, "ECRC retry %d\n", retries);
589
590 /* Pace it a bit before retry */
591 msleep(1);
592 }
593
594 return rc;
595}
596
597static int fsi_master_acf_read(struct fsi_master *_master, int link,
598 uint8_t id, uint32_t addr, void *val,
599 size_t size)
600{
601 struct fsi_master_acf *master = to_fsi_master_acf(_master);
602 struct fsi_msg cmd;
603 int rc;
604
605 if (link != 0)
606 return -ENODEV;
607
608 mutex_lock(&master->lock);
609 dev_dbg(master->dev, "read id %d addr %x size %ud\n", id, addr, size);
610 build_ar_command(master, &cmd, id, addr, size, NULL);
611 rc = fsi_master_acf_xfer(master, id, &cmd, size, val);
612 last_address_update(master, id, rc == 0, addr);
613 if (rc)
614 dev_dbg(master->dev, "read id %d addr 0x%08x err: %d\n",
615 id, addr, rc);
616 mutex_unlock(&master->lock);
617
618 return rc;
619}
620
621static int fsi_master_acf_write(struct fsi_master *_master, int link,
622 uint8_t id, uint32_t addr, const void *val,
623 size_t size)
624{
625 struct fsi_master_acf *master = to_fsi_master_acf(_master);
626 struct fsi_msg cmd;
627 int rc;
628
629 if (link != 0)
630 return -ENODEV;
631
632 mutex_lock(&master->lock);
633 build_ar_command(master, &cmd, id, addr, size, val);
634 dev_dbg(master->dev, "write id %d addr %x size %ud raw_data: %08x\n",
635 id, addr, size, *(uint32_t *)val);
636 rc = fsi_master_acf_xfer(master, id, &cmd, 0, NULL);
637 last_address_update(master, id, rc == 0, addr);
638 if (rc)
639 dev_dbg(master->dev, "write id %d addr 0x%08x err: %d\n",
640 id, addr, rc);
641 mutex_unlock(&master->lock);
642
643 return rc;
644}
645
646static int fsi_master_acf_term(struct fsi_master *_master,
647 int link, uint8_t id)
648{
649 struct fsi_master_acf *master = to_fsi_master_acf(_master);
650 struct fsi_msg cmd;
651 int rc;
652
653 if (link != 0)
654 return -ENODEV;
655
656 mutex_lock(&master->lock);
657 build_term_command(&cmd, id);
658 dev_dbg(master->dev, "term id %d\n", id);
659 rc = fsi_master_acf_xfer(master, id, &cmd, 0, NULL);
660 last_address_update(master, id, false, 0);
661 mutex_unlock(&master->lock);
662
663 return rc;
664}
665
666static int fsi_master_acf_break(struct fsi_master *_master, int link)
667{
668 struct fsi_master_acf *master = to_fsi_master_acf(_master);
669 int rc;
670
671 if (link != 0)
672 return -ENODEV;
673
674 mutex_lock(&master->lock);
675 if (master->external_mode) {
676 mutex_unlock(&master->lock);
677 return -EBUSY;
678 }
679 dev_dbg(master->dev, "sending BREAK\n");
680 rc = do_copro_command(master, CMD_BREAK);
681 last_address_update(master, 0, false, 0);
682 mutex_unlock(&master->lock);
683
684 /* Wait for logic reset to take effect */
685 udelay(200);
686
687 return rc;
688}
689
690static void reset_cf(struct fsi_master_acf *master)
691{
692 regmap_write(master->scu, SCU_COPRO_CTRL, SCU_COPRO_RESET);
693 usleep_range(20,20);
694 regmap_write(master->scu, SCU_COPRO_CTRL, 0);
695 usleep_range(20,20);
696}
697
698static void start_cf(struct fsi_master_acf *master)
699{
700 regmap_write(master->scu, SCU_COPRO_CTRL, SCU_COPRO_CLK_EN);
701}
702
703static void setup_ast2500_cf_maps(struct fsi_master_acf *master)
704{
705 /*
706 * Note about byteswap setting: the bus is wired backwards,
707 * so setting the byteswap bit actually makes the ColdFire
708 * work "normally" for a BE processor, ie, put the MSB in
709 * the lowest address byte.
710 *
711 * We thus need to set the bit for our main memory which
712 * contains our program code. We create two mappings for
713 * the register, one with each setting.
714 *
715 * Segments 2 and 3 has a "swapped" mapping (BE)
716 * and 6 and 7 have a non-swapped mapping (LE) which allows
717 * us to avoid byteswapping register accesses since the
718 * registers are all LE.
719 */
720
721 /* Setup segment 0 to our memory region */
722 regmap_write(master->scu, SCU_2500_COPRO_SEG0, master->cf_mem_addr |
723 SCU_2500_COPRO_SEG_SWAP);
724
725 /* Segments 2 and 3 to sysregs with byteswap (for SRAM) */
726 regmap_write(master->scu, SCU_2500_COPRO_SEG2, SYSREG_BASE |
727 SCU_2500_COPRO_SEG_SWAP);
728 regmap_write(master->scu, SCU_2500_COPRO_SEG3, SYSREG_BASE | 0x100000 |
729 SCU_2500_COPRO_SEG_SWAP);
730
731 /* And segment 6 and 7 to sysregs no byteswap */
732 regmap_write(master->scu, SCU_2500_COPRO_SEG6, SYSREG_BASE);
733 regmap_write(master->scu, SCU_2500_COPRO_SEG7, SYSREG_BASE | 0x100000);
734
735 /* Memory cachable, regs and SRAM not cachable */
736 regmap_write(master->scu, SCU_2500_COPRO_CACHE_CTL,
737 SCU_2500_COPRO_SEG0_CACHE_EN | SCU_2500_COPRO_CACHE_EN);
738}
739
740static void setup_ast2400_cf_maps(struct fsi_master_acf *master)
741{
742 /* Setup segment 0 to our memory region */
743 regmap_write(master->scu, SCU_2400_COPRO_SEG0, master->cf_mem_addr |
744 SCU_2400_COPRO_SEG_SWAP);
745
746 /* Segments 2 to sysregs with byteswap (for SRAM) */
747 regmap_write(master->scu, SCU_2400_COPRO_SEG2, SYSREG_BASE |
748 SCU_2400_COPRO_SEG_SWAP);
749
750 /* And segment 6 to sysregs no byteswap */
751 regmap_write(master->scu, SCU_2400_COPRO_SEG6, SYSREG_BASE);
752
753 /* Memory cachable, regs and SRAM not cachable */
754 regmap_write(master->scu, SCU_2400_COPRO_CACHE_CTL,
755 SCU_2400_COPRO_SEG0_CACHE_EN | SCU_2400_COPRO_CACHE_EN);
756}
757
758static void setup_common_fw_config(struct fsi_master_acf *master,
759 void __iomem *base)
760{
761 iowrite16be(master->gpio_clk_vreg, base + HDR_CLOCK_GPIO_VADDR);
762 iowrite16be(master->gpio_clk_dreg, base + HDR_CLOCK_GPIO_DADDR);
763 iowrite16be(master->gpio_dat_vreg, base + HDR_DATA_GPIO_VADDR);
764 iowrite16be(master->gpio_dat_dreg, base + HDR_DATA_GPIO_DADDR);
765 iowrite16be(master->gpio_tra_vreg, base + HDR_TRANS_GPIO_VADDR);
766 iowrite16be(master->gpio_tra_dreg, base + HDR_TRANS_GPIO_DADDR);
767 iowrite8(master->gpio_clk_bit, base + HDR_CLOCK_GPIO_BIT);
768 iowrite8(master->gpio_dat_bit, base + HDR_DATA_GPIO_BIT);
769 iowrite8(master->gpio_tra_bit, base + HDR_TRANS_GPIO_BIT);
770}
771
772static void setup_ast2500_fw_config(struct fsi_master_acf *master)
773{
774 void __iomem *base = master->cf_mem + HDR_OFFSET;
775
776 setup_common_fw_config(master, base);
777 iowrite32be(FW_CONTROL_USE_STOP, base + HDR_FW_CONTROL);
778}
779
780static void setup_ast2400_fw_config(struct fsi_master_acf *master)
781{
782 void __iomem *base = master->cf_mem + HDR_OFFSET;
783
784 setup_common_fw_config(master, base);
785 iowrite32be(FW_CONTROL_CONT_CLOCK|FW_CONTROL_DUMMY_RD, base + HDR_FW_CONTROL);
786}
787
788static int setup_gpios_for_copro(struct fsi_master_acf *master)
789{
790
791 int rc;
792
793 /* This aren't under ColdFire control, just set them up appropriately */
794 gpiod_direction_output(master->gpio_mux, 1);
795 gpiod_direction_output(master->gpio_enable, 1);
796
797 /* Those are under ColdFire control, let it configure them */
798 rc = aspeed_gpio_copro_grab_gpio(master->gpio_clk, &master->gpio_clk_vreg,
799 &master->gpio_clk_dreg, &master->gpio_clk_bit);
800 if (rc) {
801 dev_err(master->dev, "failed to assign clock gpio to coprocessor\n");
802 return rc;
803 }
804 rc = aspeed_gpio_copro_grab_gpio(master->gpio_data, &master->gpio_dat_vreg,
805 &master->gpio_dat_dreg, &master->gpio_dat_bit);
806 if (rc) {
807 dev_err(master->dev, "failed to assign data gpio to coprocessor\n");
808 aspeed_gpio_copro_release_gpio(master->gpio_clk);
809 return rc;
810 }
811 rc = aspeed_gpio_copro_grab_gpio(master->gpio_trans, &master->gpio_tra_vreg,
812 &master->gpio_tra_dreg, &master->gpio_tra_bit);
813 if (rc) {
814 dev_err(master->dev, "failed to assign trans gpio to coprocessor\n");
815 aspeed_gpio_copro_release_gpio(master->gpio_clk);
816 aspeed_gpio_copro_release_gpio(master->gpio_data);
817 return rc;
818 }
819 return 0;
820}
821
822static void release_copro_gpios(struct fsi_master_acf *master)
823{
824 aspeed_gpio_copro_release_gpio(master->gpio_clk);
825 aspeed_gpio_copro_release_gpio(master->gpio_data);
826 aspeed_gpio_copro_release_gpio(master->gpio_trans);
827}
828
829static int load_copro_firmware(struct fsi_master_acf *master)
830{
831 const struct firmware *fw;
832 uint16_t sig = 0, wanted_sig;
833 const u8 *data;
834 size_t size = 0;
835 int rc;
836
837 /* Get the binary */
838 rc = request_firmware(&fw, FW_FILE_NAME, master->dev);
839 if (rc) {
840 dev_err(
841 master->dev, "Error %d to load firwmare '%s' !\n",
842 rc, FW_FILE_NAME);
843 return rc;
844 }
845
846 /* Which image do we want ? (shared vs. split clock/data GPIOs) */
847 if (master->gpio_clk_vreg == master->gpio_dat_vreg)
848 wanted_sig = SYS_SIG_SHARED;
849 else
850 wanted_sig = SYS_SIG_SPLIT;
851 dev_dbg(master->dev, "Looking for image sig %04x\n", wanted_sig);
852
853 /* Try to find it */
854 for (data = fw->data; data < (fw->data + fw->size);) {
855 sig = be16_to_cpup((__be16 *)(data + HDR_OFFSET + HDR_SYS_SIG));
856 size = be32_to_cpup((__be32 *)(data + HDR_OFFSET + HDR_FW_SIZE));
857 if (sig == wanted_sig)
858 break;
859 data += size;
860 }
861 if (sig != wanted_sig) {
862 dev_err(master->dev, "Failed to locate image sig %04x in FW blob\n",
863 wanted_sig);
864 return -ENODEV;
865 }
866 if (size > master->cf_mem_size) {
867 dev_err(master->dev, "FW size (%zd) bigger than memory reserve (%zd)\n",
868 fw->size, master->cf_mem_size);
869 rc = -ENOMEM;
870 } else {
871 memcpy_toio(master->cf_mem, data, size);
872 }
873 release_firmware(fw);
874
875 return rc;
876}
877
878static int check_firmware_image(struct fsi_master_acf *master)
879{
880 uint32_t fw_vers, fw_api, fw_options;
881
882 fw_vers = ioread16be(master->cf_mem + HDR_OFFSET + HDR_FW_VERS);
883 fw_api = ioread16be(master->cf_mem + HDR_OFFSET + HDR_API_VERS);
884 fw_options = ioread32be(master->cf_mem + HDR_OFFSET + HDR_FW_OPTIONS);
885 master->trace_enabled = !!(fw_options & FW_OPTION_TRACE_EN);
886
887 /* Check version and signature */
888 dev_info(master->dev, "ColdFire initialized, firmware v%d API v%d.%d (trace %s)\n",
889 fw_vers, fw_api >> 8, fw_api & 0xff,
890 master->trace_enabled ? "enabled" : "disabled");
891
892 if ((fw_api >> 8) != API_VERSION_MAJ) {
893 dev_err(master->dev, "Unsupported coprocessor API version !\n");
894 return -ENODEV;
895 }
896
897 return 0;
898}
899
900static int copro_enable_sw_irq(struct fsi_master_acf *master)
901{
902 int timeout;
903 uint32_t val;
904
905 /*
906 * Enable coprocessor interrupt input. I've had problems getting the
907 * value to stick, so try in a loop
908 */
909 for (timeout = 0; timeout < 10; timeout++) {
910 iowrite32(0x2, master->cvic + CVIC_EN_REG);
911 val = ioread32(master->cvic + CVIC_EN_REG);
912 if (val & 2)
913 break;
914 msleep(1);
915 }
916 if (!(val & 2)) {
917 dev_err(master->dev, "Failed to enable coprocessor interrupt !\n");
918 return -ENODEV;
919 }
920 return 0;
921}
922
923static int fsi_master_acf_setup(struct fsi_master_acf *master)
924{
925 int timeout, rc;
926 uint32_t val;
927
928 /* Make sure the ColdFire is stopped */
929 reset_cf(master);
930
931 /*
932 * Clear SRAM. This needs to happen before we setup the GPIOs
933 * as we might start trying to arbitrate as soon as that happens.
934 */
935 memset_io(master->sram, 0, SRAM_SIZE);
936
937 /* Configure GPIOs */
938 rc = setup_gpios_for_copro(master);
939 if (rc)
940 return rc;
941
942 /* Load the firmware into the reserved memory */
943 rc = load_copro_firmware(master);
944 if (rc)
945 return rc;
946
947 /* Read signature and check versions */
948 rc = check_firmware_image(master);
949 if (rc)
950 return rc;
951
952 /* Setup coldfire memory map */
953 if (master->is_ast2500) {
954 setup_ast2500_cf_maps(master);
955 setup_ast2500_fw_config(master);
956 } else {
957 setup_ast2400_cf_maps(master);
958 setup_ast2400_fw_config(master);
959 }
960
961 /* Start the ColdFire */
962 start_cf(master);
963
964 /* Wait for status register to indicate command completion
965 * which signals the initialization is complete
966 */
967 for (timeout = 0; timeout < 10; timeout++) {
968 val = ioread8(master->sram + CF_STARTED);
969 if (val)
970 break;
971 msleep(1);
972 }
973 if (!val) {
974 dev_err(master->dev, "Coprocessor startup timeout !\n");
975 rc = -ENODEV;
976 goto err;
977 }
978
979 /* Configure echo & send delay */
980 iowrite8(master->t_send_delay, master->sram + SEND_DLY_REG);
981 iowrite8(master->t_echo_delay, master->sram + ECHO_DLY_REG);
982
983 /* Enable SW interrupt to copro if any */
984 if (master->cvic) {
985 rc = copro_enable_sw_irq(master);
986 if (rc)
987 goto err;
988 }
989 return 0;
990 err:
991 /* An error occurred, don't leave the coprocessor running */
992 reset_cf(master);
993
994 /* Release the GPIOs */
995 release_copro_gpios(master);
996
997 return rc;
998}
999
1000
1001static void fsi_master_acf_terminate(struct fsi_master_acf *master)
1002{
1003 unsigned long flags;
1004
1005 /*
1006 * A GPIO arbitration requestion could come in while this is
1007 * happening. To avoid problems, we disable interrupts so it
1008 * cannot preempt us on this CPU
1009 */
1010
1011 local_irq_save(flags);
1012
1013 /* Stop the coprocessor */
1014 reset_cf(master);
1015
1016 /* We mark the copro not-started */
1017 iowrite32(0, master->sram + CF_STARTED);
1018
1019 /* We mark the ARB register as having given up arbitration to
1020 * deal with a potential race with the arbitration request
1021 */
1022 iowrite8(ARB_ARM_ACK, master->sram + ARB_REG);
1023
1024 local_irq_restore(flags);
1025
1026 /* Return the GPIOs to the ARM */
1027 release_copro_gpios(master);
1028}
1029
1030static void fsi_master_acf_setup_external(struct fsi_master_acf *master)
1031{
1032 /* Setup GPIOs for external FSI master (FSP box) */
1033 gpiod_direction_output(master->gpio_mux, 0);
1034 gpiod_direction_output(master->gpio_trans, 0);
1035 gpiod_direction_output(master->gpio_enable, 1);
1036 gpiod_direction_input(master->gpio_clk);
1037 gpiod_direction_input(master->gpio_data);
1038}
1039
1040static int fsi_master_acf_link_enable(struct fsi_master *_master, int link)
1041{
1042 struct fsi_master_acf *master = to_fsi_master_acf(_master);
1043 int rc = -EBUSY;
1044
1045 if (link != 0)
1046 return -ENODEV;
1047
1048 mutex_lock(&master->lock);
1049 if (!master->external_mode) {
1050 gpiod_set_value(master->gpio_enable, 1);
1051 rc = 0;
1052 }
1053 mutex_unlock(&master->lock);
1054
1055 return rc;
1056}
1057
1058static int fsi_master_acf_link_config(struct fsi_master *_master, int link,
1059 u8 t_send_delay, u8 t_echo_delay)
1060{
1061 struct fsi_master_acf *master = to_fsi_master_acf(_master);
1062
1063 if (link != 0)
1064 return -ENODEV;
1065
1066 mutex_lock(&master->lock);
1067 master->t_send_delay = t_send_delay;
1068 master->t_echo_delay = t_echo_delay;
1069 dev_dbg(master->dev, "Changing delays: send=%d echo=%d\n",
1070 t_send_delay, t_echo_delay);
1071 iowrite8(master->t_send_delay, master->sram + SEND_DLY_REG);
1072 iowrite8(master->t_echo_delay, master->sram + ECHO_DLY_REG);
1073 mutex_unlock(&master->lock);
1074
1075 return 0;
1076}
1077
1078static ssize_t external_mode_show(struct device *dev,
1079 struct device_attribute *attr, char *buf)
1080{
1081 struct fsi_master_acf *master = dev_get_drvdata(dev);
1082
1083 return snprintf(buf, PAGE_SIZE - 1, "%u\n",
1084 master->external_mode ? 1 : 0);
1085}
1086
1087static ssize_t external_mode_store(struct device *dev,
1088 struct device_attribute *attr, const char *buf, size_t count)
1089{
1090 struct fsi_master_acf *master = dev_get_drvdata(dev);
1091 unsigned long val;
1092 bool external_mode;
1093 int err;
1094
1095 err = kstrtoul(buf, 0, &val);
1096 if (err)
1097 return err;
1098
1099 external_mode = !!val;
1100
1101 mutex_lock(&master->lock);
1102
1103 if (external_mode == master->external_mode) {
1104 mutex_unlock(&master->lock);
1105 return count;
1106 }
1107
1108 master->external_mode = external_mode;
1109 if (master->external_mode) {
1110 fsi_master_acf_terminate(master);
1111 fsi_master_acf_setup_external(master);
1112 } else
1113 fsi_master_acf_setup(master);
1114
1115 mutex_unlock(&master->lock);
1116
1117 fsi_master_rescan(&master->master);
1118
1119 return count;
1120}
1121
1122static DEVICE_ATTR(external_mode, 0664,
1123 external_mode_show, external_mode_store);
1124
1125static int fsi_master_acf_gpio_request(void *data)
1126{
1127 struct fsi_master_acf *master = data;
1128 int timeout;
1129 u8 val;
1130
1131 /* Note: This doesn't require holding out mutex */
1132
1133 /* Write reqest */
1134 iowrite8(ARB_ARM_REQ, master->sram + ARB_REG);
1135
1136 /*
1137 * There is a race (which does happen at boot time) when we get an
1138 * arbitration request as we are either about to or just starting
1139 * the coprocessor.
1140 *
1141 * To handle it, we first check if we are running. If not yet we
1142 * check whether the copro is started in the SCU.
1143 *
1144 * If it's not started, we can basically just assume we have arbitration
1145 * and return. Otherwise, we wait normally expecting for the arbitration
1146 * to eventually complete.
1147 */
1148 if (ioread32(master->sram + CF_STARTED) == 0) {
1149 unsigned int reg = 0;
1150
1151 regmap_read(master->scu, SCU_COPRO_CTRL, &reg);
1152 if (!(reg & SCU_COPRO_CLK_EN))
1153 return 0;
1154 }
1155
1156 /* Ring doorbell if any */
1157 if (master->cvic)
1158 iowrite32(0x2, master->cvic + CVIC_TRIG_REG);
1159
1160 for (timeout = 0; timeout < 10000; timeout++) {
1161 val = ioread8(master->sram + ARB_REG);
1162 if (val != ARB_ARM_REQ)
1163 break;
1164 udelay(1);
1165 }
1166
1167 /* If it failed, override anyway */
1168 if (val != ARB_ARM_ACK)
1169 dev_warn(master->dev, "GPIO request arbitration timeout\n");
1170
1171 return 0;
1172}
1173
1174static int fsi_master_acf_gpio_release(void *data)
1175{
1176 struct fsi_master_acf *master = data;
1177
1178 /* Write release */
1179 iowrite8(0, master->sram + ARB_REG);
1180
1181 /* Ring doorbell if any */
1182 if (master->cvic)
1183 iowrite32(0x2, master->cvic + CVIC_TRIG_REG);
1184
1185 return 0;
1186}
1187
1188static void fsi_master_acf_release(struct device *dev)
1189{
1190 struct fsi_master_acf *master = to_fsi_master_acf(dev_to_fsi_master(dev));
1191
1192 /* Cleanup, stop coprocessor */
1193 mutex_lock(&master->lock);
1194 fsi_master_acf_terminate(master);
1195 aspeed_gpio_copro_set_ops(NULL, NULL);
1196 mutex_unlock(&master->lock);
1197
1198 /* Free resources */
1199 gen_pool_free(master->sram_pool, (unsigned long)master->sram, SRAM_SIZE);
1200 of_node_put(dev_of_node(master->dev));
1201
1202 kfree(master);
1203}
1204
1205static const struct aspeed_gpio_copro_ops fsi_master_acf_gpio_ops = {
1206 .request_access = fsi_master_acf_gpio_request,
1207 .release_access = fsi_master_acf_gpio_release,
1208};
1209
1210static int fsi_master_acf_probe(struct platform_device *pdev)
1211{
1212 struct device_node *np, *mnode = dev_of_node(&pdev->dev);
1213 struct genpool_data_fixed gpdf;
1214 struct fsi_master_acf *master;
1215 struct gpio_desc *gpio;
1216 struct resource res;
1217 uint32_t cf_mem_align;
1218 int rc;
1219
1220 master = kzalloc(sizeof(*master), GFP_KERNEL);
1221 if (!master)
1222 return -ENOMEM;
1223
1224 master->dev = &pdev->dev;
1225 master->master.dev.parent = master->dev;
1226 master->last_addr = LAST_ADDR_INVALID;
1227
1228 /* AST2400 vs. AST2500 */
1229 master->is_ast2500 = of_device_is_compatible(mnode, "aspeed,ast2500-cf-fsi-master");
1230
1231 /* Grab the SCU, we'll need to access it to configure the coprocessor */
1232 if (master->is_ast2500)
1233 master->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2500-scu");
1234 else
1235 master->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2400-scu");
1236 if (IS_ERR(master->scu)) {
1237 dev_err(&pdev->dev, "failed to find SCU regmap\n");
1238 rc = PTR_ERR(master->scu);
1239 goto err_free;
1240 }
1241
1242 /* Grab all the GPIOs we need */
1243 gpio = devm_gpiod_get(&pdev->dev, "clock", 0);
1244 if (IS_ERR(gpio)) {
1245 dev_err(&pdev->dev, "failed to get clock gpio\n");
1246 rc = PTR_ERR(gpio);
1247 goto err_free;
1248 }
1249 master->gpio_clk = gpio;
1250
1251 gpio = devm_gpiod_get(&pdev->dev, "data", 0);
1252 if (IS_ERR(gpio)) {
1253 dev_err(&pdev->dev, "failed to get data gpio\n");
1254 rc = PTR_ERR(gpio);
1255 goto err_free;
1256 }
1257 master->gpio_data = gpio;
1258
1259 /* Optional GPIOs */
1260 gpio = devm_gpiod_get_optional(&pdev->dev, "trans", 0);
1261 if (IS_ERR(gpio)) {
1262 dev_err(&pdev->dev, "failed to get trans gpio\n");
1263 rc = PTR_ERR(gpio);
1264 goto err_free;
1265 }
1266 master->gpio_trans = gpio;
1267
1268 gpio = devm_gpiod_get_optional(&pdev->dev, "enable", 0);
1269 if (IS_ERR(gpio)) {
1270 dev_err(&pdev->dev, "failed to get enable gpio\n");
1271 rc = PTR_ERR(gpio);
1272 goto err_free;
1273 }
1274 master->gpio_enable = gpio;
1275
1276 gpio = devm_gpiod_get_optional(&pdev->dev, "mux", 0);
1277 if (IS_ERR(gpio)) {
1278 dev_err(&pdev->dev, "failed to get mux gpio\n");
1279 rc = PTR_ERR(gpio);
1280 goto err_free;
1281 }
1282 master->gpio_mux = gpio;
1283
1284 /* Grab the reserved memory region (use DMA API instead ?) */
1285 np = of_parse_phandle(mnode, "memory-region", 0);
1286 if (!np) {
1287 dev_err(&pdev->dev, "Didn't find reserved memory\n");
1288 rc = -EINVAL;
1289 goto err_free;
1290 }
1291 rc = of_address_to_resource(np, 0, &res);
1292 of_node_put(np);
1293 if (rc) {
1294 dev_err(&pdev->dev, "Couldn't address to resource for reserved memory\n");
1295 rc = -ENOMEM;
1296 goto err_free;
1297 }
1298 master->cf_mem_size = resource_size(&res);
1299 master->cf_mem_addr = (uint32_t)res.start;
1300 cf_mem_align = master->is_ast2500 ? 0x00100000 : 0x00200000;
1301 if (master->cf_mem_addr & (cf_mem_align - 1)) {
1302 dev_err(&pdev->dev, "Reserved memory has insufficient alignment\n");
1303 rc = -ENOMEM;
1304 goto err_free;
1305 }
1306 master->cf_mem = devm_ioremap_resource(&pdev->dev, &res);
1307 if (IS_ERR(master->cf_mem)) {
1308 rc = PTR_ERR(master->cf_mem);
1309 dev_err(&pdev->dev, "Error %d mapping coldfire memory\n", rc);
1310 goto err_free;
1311 }
1312 dev_dbg(&pdev->dev, "DRAM allocation @%x\n", master->cf_mem_addr);
1313
1314 /* AST2500 has a SW interrupt to the coprocessor */
1315 if (master->is_ast2500) {
1316 /* Grab the CVIC (ColdFire interrupts controller) */
1317 np = of_parse_phandle(mnode, "aspeed,cvic", 0);
1318 if (!np) {
1319 dev_err(&pdev->dev, "Didn't find CVIC\n");
1320 rc = -EINVAL;
1321 goto err_free;
1322 }
1323 master->cvic = devm_of_iomap(&pdev->dev, np, 0, NULL);
1324 if (IS_ERR(master->cvic)) {
1325 rc = PTR_ERR(master->cvic);
1326 dev_err(&pdev->dev, "Error %d mapping CVIC\n", rc);
1327 goto err_free;
1328 }
1329 rc = of_property_read_u32(np, "copro-sw-interrupts",
1330 &master->cvic_sw_irq);
1331 if (rc) {
1332 dev_err(&pdev->dev, "Can't find coprocessor SW interrupt\n");
1333 goto err_free;
1334 }
1335 }
1336
1337 /* Grab the SRAM */
1338 master->sram_pool = of_gen_pool_get(dev_of_node(&pdev->dev), "aspeed,sram", 0);
1339 if (!master->sram_pool) {
1340 rc = -ENODEV;
1341 dev_err(&pdev->dev, "Can't find sram pool\n");
1342 goto err_free;
1343 }
1344
1345 /* Current microcode only deals with fixed location in SRAM */
1346 gpdf.offset = 0;
1347 master->sram = (void __iomem *)gen_pool_alloc_algo(master->sram_pool, SRAM_SIZE,
1348 gen_pool_fixed_alloc, &gpdf);
1349 if (!master->sram) {
1350 rc = -ENOMEM;
1351 dev_err(&pdev->dev, "Failed to allocate sram from pool\n");
1352 goto err_free;
1353 }
1354 dev_dbg(&pdev->dev, "SRAM allocation @%lx\n",
1355 (unsigned long)gen_pool_virt_to_phys(master->sram_pool,
1356 (unsigned long)master->sram));
1357
1358 /*
1359 * Hookup with the GPIO driver for arbitration of GPIO banks
1360 * ownership.
1361 */
1362 aspeed_gpio_copro_set_ops(&fsi_master_acf_gpio_ops, master);
1363
1364 /* Default FSI command delays */
1365 master->t_send_delay = FSI_SEND_DELAY_CLOCKS;
1366 master->t_echo_delay = FSI_ECHO_DELAY_CLOCKS;
1367 master->master.n_links = 1;
1368 if (master->is_ast2500)
1369 master->master.flags = FSI_MASTER_FLAG_SWCLOCK;
1370 master->master.read = fsi_master_acf_read;
1371 master->master.write = fsi_master_acf_write;
1372 master->master.term = fsi_master_acf_term;
1373 master->master.send_break = fsi_master_acf_break;
1374 master->master.link_enable = fsi_master_acf_link_enable;
1375 master->master.link_config = fsi_master_acf_link_config;
1376 master->master.dev.of_node = of_node_get(dev_of_node(master->dev));
1377 master->master.dev.release = fsi_master_acf_release;
1378 platform_set_drvdata(pdev, master);
1379 mutex_init(&master->lock);
1380
1381 mutex_lock(&master->lock);
1382 rc = fsi_master_acf_setup(master);
1383 mutex_unlock(&master->lock);
1384 if (rc)
1385 goto release_of_dev;
1386
1387 rc = device_create_file(&pdev->dev, &dev_attr_external_mode);
1388 if (rc)
1389 goto stop_copro;
1390
1391 rc = fsi_master_register(&master->master);
1392 if (!rc)
1393 return 0;
1394
1395 device_remove_file(master->dev, &dev_attr_external_mode);
1396 put_device(&master->master.dev);
1397 return rc;
1398
1399 stop_copro:
1400 fsi_master_acf_terminate(master);
1401 release_of_dev:
1402 aspeed_gpio_copro_set_ops(NULL, NULL);
1403 gen_pool_free(master->sram_pool, (unsigned long)master->sram, SRAM_SIZE);
1404 of_node_put(dev_of_node(master->dev));
1405 err_free:
1406 kfree(master);
1407 return rc;
1408}
1409
1410
1411static int fsi_master_acf_remove(struct platform_device *pdev)
1412{
1413 struct fsi_master_acf *master = platform_get_drvdata(pdev);
1414
1415 device_remove_file(master->dev, &dev_attr_external_mode);
1416
1417 fsi_master_unregister(&master->master);
1418
1419 return 0;
1420}
1421
1422static const struct of_device_id fsi_master_acf_match[] = {
1423 { .compatible = "aspeed,ast2400-cf-fsi-master" },
1424 { .compatible = "aspeed,ast2500-cf-fsi-master" },
1425 { },
1426};
1427
1428static struct platform_driver fsi_master_acf = {
1429 .driver = {
1430 .name = "fsi-master-acf",
1431 .of_match_table = fsi_master_acf_match,
1432 },
1433 .probe = fsi_master_acf_probe,
1434 .remove = fsi_master_acf_remove,
1435};
1436
1437module_platform_driver(fsi_master_acf);
1438MODULE_LICENSE("GPL");
diff --git a/include/trace/events/fsi_master_ast_cf.h b/include/trace/events/fsi_master_ast_cf.h
new file mode 100644
index 000000000000..a0fdfa58622a
--- /dev/null
+++ b/include/trace/events/fsi_master_ast_cf.h
@@ -0,0 +1,150 @@
1
2#undef TRACE_SYSTEM
3#define TRACE_SYSTEM fsi_master_ast_cf
4
5#if !defined(_TRACE_FSI_MASTER_ACF_H) || defined(TRACE_HEADER_MULTI_READ)
6#define _TRACE_FSI_MASTER_ACF_H
7
8#include <linux/tracepoint.h>
9
10TRACE_EVENT(fsi_master_acf_copro_command,
11 TP_PROTO(const struct fsi_master_acf *master, uint32_t op),
12 TP_ARGS(master, op),
13 TP_STRUCT__entry(
14 __field(int, master_idx)
15 __field(uint32_t, op)
16 ),
17 TP_fast_assign(
18 __entry->master_idx = master->master.idx;
19 __entry->op = op;
20 ),
21 TP_printk("fsi-acf%d command %08x",
22 __entry->master_idx, __entry->op
23 )
24);
25
26TRACE_EVENT(fsi_master_acf_send_request,
27 TP_PROTO(const struct fsi_master_acf *master, const struct fsi_msg *cmd, u8 rbits),
28 TP_ARGS(master, cmd, rbits),
29 TP_STRUCT__entry(
30 __field(int, master_idx)
31 __field(uint64_t, msg)
32 __field(u8, bits)
33 __field(u8, rbits)
34 ),
35 TP_fast_assign(
36 __entry->master_idx = master->master.idx;
37 __entry->msg = cmd->msg;
38 __entry->bits = cmd->bits;
39 __entry->rbits = rbits;
40 ),
41 TP_printk("fsi-acf%d cmd: %016llx/%d/%d",
42 __entry->master_idx, (unsigned long long)__entry->msg,
43 __entry->bits, __entry->rbits
44 )
45);
46
47TRACE_EVENT(fsi_master_acf_copro_response,
48 TP_PROTO(const struct fsi_master_acf *master, u8 rtag, u8 rcrc, __be32 rdata, bool crc_ok),
49 TP_ARGS(master, rtag, rcrc, rdata, crc_ok),
50 TP_STRUCT__entry(
51 __field(int, master_idx)
52 __field(u8, rtag)
53 __field(u8, rcrc)
54 __field(u32, rdata)
55 __field(bool, crc_ok)
56 ),
57 TP_fast_assign(
58 __entry->master_idx = master->master.idx;
59 __entry->rtag = rtag;
60 __entry->rcrc = rcrc;
61 __entry->rdata = be32_to_cpu(rdata);
62 __entry->crc_ok = crc_ok;
63 ),
64 TP_printk("fsi-acf%d rsp: tag=%04x crc=%04x data=%08x %c\n",
65 __entry->master_idx, __entry->rtag, __entry->rcrc,
66 __entry->rdata, __entry->crc_ok ? ' ' : '!'
67 )
68);
69
70TRACE_EVENT(fsi_master_acf_crc_rsp_error,
71 TP_PROTO(const struct fsi_master_acf *master, int retries),
72 TP_ARGS(master, retries),
73 TP_STRUCT__entry(
74 __field(int, master_idx)
75 __field(int, retries)
76 ),
77 TP_fast_assign(
78 __entry->master_idx = master->master.idx;
79 __entry->retries = retries;
80 ),
81 TP_printk("fsi-acf%d CRC error in response retry %d",
82 __entry->master_idx, __entry->retries
83 )
84);
85
86TRACE_EVENT(fsi_master_acf_poll_response_busy,
87 TP_PROTO(const struct fsi_master_acf *master, int busy_count),
88 TP_ARGS(master, busy_count),
89 TP_STRUCT__entry(
90 __field(int, master_idx)
91 __field(int, busy_count)
92 ),
93 TP_fast_assign(
94 __entry->master_idx = master->master.idx;
95 __entry->busy_count = busy_count;
96 ),
97 TP_printk("fsi-acf%d: device reported busy %d times",
98 __entry->master_idx, __entry->busy_count
99 )
100);
101
102TRACE_EVENT(fsi_master_acf_cmd_abs_addr,
103 TP_PROTO(const struct fsi_master_acf *master, u32 addr),
104 TP_ARGS(master, addr),
105 TP_STRUCT__entry(
106 __field(int, master_idx)
107 __field(u32, addr)
108 ),
109 TP_fast_assign(
110 __entry->master_idx = master->master.idx;
111 __entry->addr = addr;
112 ),
113 TP_printk("fsi-acf%d: Sending ABS_ADR %06x",
114 __entry->master_idx, __entry->addr
115 )
116);
117
118TRACE_EVENT(fsi_master_acf_cmd_rel_addr,
119 TP_PROTO(const struct fsi_master_acf *master, u32 rel_addr),
120 TP_ARGS(master, rel_addr),
121 TP_STRUCT__entry(
122 __field(int, master_idx)
123 __field(u32, rel_addr)
124 ),
125 TP_fast_assign(
126 __entry->master_idx = master->master.idx;
127 __entry->rel_addr = rel_addr;
128 ),
129 TP_printk("fsi-acf%d: Sending REL_ADR %03x",
130 __entry->master_idx, __entry->rel_addr
131 )
132);
133
134TRACE_EVENT(fsi_master_acf_cmd_same_addr,
135 TP_PROTO(const struct fsi_master_acf *master),
136 TP_ARGS(master),
137 TP_STRUCT__entry(
138 __field(int, master_idx)
139 ),
140 TP_fast_assign(
141 __entry->master_idx = master->master.idx;
142 ),
143 TP_printk("fsi-acf%d: Sending SAME_ADR",
144 __entry->master_idx
145 )
146);
147
148#endif /* _TRACE_FSI_MASTER_ACF_H */
149
150#include <trace/define_trace.h>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-24 20:15:12 -0400