arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support

Initial device tree support for Qualcomm MSM8992 SoC and
LG Bullhead / Google Nexus 5X support.

Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

4 files changed, 267 insertions, 2 deletions

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 5dd05de5619b..439e40e15261 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -1,6 +1,8 @@
-dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb
-dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
 dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
 
 always          := $(dtb-y)
 subdir-y        := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
new file mode 100644
index 000000000000..454213391671
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
@@ -0,0 +1,41 @@
+/* Copyright (c) 2015, LGE Inc. All rights reserved.
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "msm8992.dtsi"
+
+/ {
+        model = "LG Nexus 5X";
+        compatible = "lg,bullhead", "qcom,msm8992";
+        /* required for bootloader to select correct board */
+        qcom,board-id = <0xb64 0>;
+        qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
+
+        aliases {
+                serial0 = &blsp1_uart2;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        soc {
+                serial@f991e000 {
+                        status = "okay";
+                        pinctrl-names = "default", "sleep";
+                        pinctrl-0 = <&blsp1_uart2_default>;
+                        pinctrl-1 = <&blsp1_uart2_sleep>;
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
new file mode 100644
index 000000000000..d2a26f0f8d73
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&msmgpio {
+        blsp1_uart2_default: blsp1_uart2_default {
+                pinmux {
+                        function = "blsp_uart2";
+                        pins = "gpio4", "gpio5";
+                };
+                pinconf {
+                        pins = "gpio4", "gpio5";
+                        drive-strength = <16>;
+                        bias-disable;
+                };
+        };
+
+        blsp1_uart2_sleep: blsp1_uart2_sleep {
+                pinmux {
+                        function = "gpio";
+                        pins = "gpio4", "gpio5";
+                };
+                pinconf {
+                        pins = "gpio4", "gpio5";
+                        drive-strength = <2>;
+                        bias-pull-down;
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
new file mode 100644
index 000000000000..44b2d37d8c4b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
@@ -0,0 +1,184 @@
+/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-msm8994.h>
+
+/ {
+        model = "Qualcomm Technologies, Inc. MSM 8992";
+        compatible = "qcom,msm8992";
+        // msm-id needed by bootloader for selecting correct blob
+        qcom,msm-id = <251 0>, <252 0>;
+        interrupt-parent = <&intc>;
+
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        chosen { };
+
+        cpus {
+                #address-cells = <2>;
+                #size-cells = <0>;
+                cpu-map {
+                        cluster0 {
+                                core0 {
+                                        cpu = <&CPU0>;
+                                };
+                        };
+                };
+
+                CPU0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        reg = <0x0 0x0>;
+                        next-level-cache = <&L2_0>;
+                        L2_0: l2-cache {
+                                compatible = "cache";
+                                cache-level = <2>;
+                        };
+                };
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+        };
+
+        xo_board: xo_board {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <19200000>;
+        };
+
+        sleep_clk: sleep_clk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0 0 0xffffffff>;
+                compatible = "simple-bus";
+
+                intc: interrupt-controller@f9000000 {
+                        compatible = "qcom,msm-qgic2";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0xf9000000 0x1000>,
+                                <0xf9002000 0x1000>;
+                };
+
+                timer@f9020000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        compatible = "arm,armv7-timer-mem";
+                        reg = <0xf9020000 0x1000>;
+
+                        frame@f9021000 {
+                                frame-number = <0>;
+                                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+                                                <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                                reg = <0xf9021000 0x1000>,
+                                        <0xf9022000 0x1000>;
+                        };
+
+                        frame@f9023000 {
+                                frame-number = <1>;
+                                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+                                reg = <0xf9023000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@f9024000 {
+                                frame-number = <2>;
+                                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                                reg = <0xf9024000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@f9025000 {
+                                frame-number = <3>;
+                                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                                reg = <0xf9025000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@f9026000 {
+                                frame-number = <4>;
+                                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                                reg = <0xf9026000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@f9027000 {
+                                frame-number = <5>;
+                                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                                reg = <0xf9027000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@f9028000 {
+                                frame-number = <6>;
+                                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                                reg = <0xf9028000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+
+                restart@fc4ab000 {
+                        compatible = "qcom,pshold";
+                        reg = <0xfc4ab000 0x4>;
+                };
+
+                msmgpio: pinctrl@fd510000 {
+                        compatible = "qcom,msm8994-pinctrl";
+                        reg = <0xfd510000 0x4000>;
+                        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                blsp1_uart2: serial@f991e000 {
+                        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+                        reg = <0xf991e000 0x1000>;
+                        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
+                        status = "disabled";
+                        clock-names = "core", "iface";
+                        clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
+                                <&clock_gcc GCC_BLSP1_AHB_CLK>;
+                };
+
+                clock_gcc: clock-controller@fc400000 {
+                        compatible = "qcom,gcc-msm8994";
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                        #power-domain-cells = <1>;
+                        reg = <0xfc400000 0x2000>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0 0 0 0>; // bootloader will update
+        };
+};
+
+
+#include "msm8992-pins.dtsi"