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authorUlrich Hecht <ulrich.hecht+renesas@gmail.com>2016-12-07 11:44:47 -0500
committerSimon Horman <horms+renesas@verge.net.au>2017-03-07 01:50:25 -0500
commit68cd161072605c276d4e6c8cd06fbe7b00a0f680 (patch)
tree924d180a98ca58a3f97c9d807ba02aee3d8ae28d
parentef3f08c83fd186ab4bbad6a6250c5a347fbf6551 (diff)
arm64: dts: r8a7796 dtsi: Add all HSCIF nodes
Add the device nodes for all HSCIF serial ports, incl. clocks, and power domain. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> [simon: express register size in hex; refer to power domain in changelog] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796.dtsi70
1 files changed, 70 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 1c1c1eae9cba..714fd96b29eb 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -489,6 +489,76 @@
489 status = "disabled"; 489 status = "disabled";
490 }; 490 };
491 491
492 hscif0: serial@e6540000 {
493 compatible = "renesas,hscif-r8a7796",
494 "renesas,rcar-gen3-hscif",
495 "renesas,hscif";
496 reg = <0 0xe6540000 0 0x60>;
497 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cpg CPG_MOD 520>,
499 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
500 <&scif_clk>;
501 clock-names = "fck", "brg_int", "scif_clk";
502 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
503 status = "disabled";
504 };
505
506 hscif1: serial@e6550000 {
507 compatible = "renesas,hscif-r8a7796",
508 "renesas,rcar-gen3-hscif",
509 "renesas,hscif";
510 reg = <0 0xe6550000 0 0x60>;
511 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&cpg CPG_MOD 519>,
513 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
514 <&scif_clk>;
515 clock-names = "fck", "brg_int", "scif_clk";
516 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
517 status = "disabled";
518 };
519
520 hscif2: serial@e6560000 {
521 compatible = "renesas,hscif-r8a7796",
522 "renesas,rcar-gen3-hscif",
523 "renesas,hscif";
524 reg = <0 0xe6560000 0 0x60>;
525 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&cpg CPG_MOD 518>,
527 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
528 <&scif_clk>;
529 clock-names = "fck", "brg_int", "scif_clk";
530 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
531 status = "disabled";
532 };
533
534 hscif3: serial@e66a0000 {
535 compatible = "renesas,hscif-r8a7796",
536 "renesas,rcar-gen3-hscif",
537 "renesas,hscif";
538 reg = <0 0xe66a0000 0 0x60>;
539 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&cpg CPG_MOD 517>,
541 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
542 <&scif_clk>;
543 clock-names = "fck", "brg_int", "scif_clk";
544 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
545 status = "disabled";
546 };
547
548 hscif4: serial@e66b0000 {
549 compatible = "renesas,hscif-r8a7796",
550 "renesas,rcar-gen3-hscif",
551 "renesas,hscif";
552 reg = <0 0xe66b0000 0 0x60>;
553 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&cpg CPG_MOD 516>,
555 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
556 <&scif_clk>;
557 clock-names = "fck", "brg_int", "scif_clk";
558 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
559 status = "disabled";
560 };
561
492 scif2: serial@e6e88000 { 562 scif2: serial@e6e88000 {
493 compatible = "renesas,scif-r8a7796", 563 compatible = "renesas,scif-r8a7796",
494 "renesas,rcar-gen3-scif", "renesas,scif"; 564 "renesas,rcar-gen3-scif", "renesas,scif";