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authorAlex Deucher <alexander.deucher@amd.com>2019-06-27 10:13:41 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-06-27 10:35:07 -0400
commit687ac4a702ea92873fb8c45acec0c30eae9acfa9 (patch)
tree2e3d94ff80f67d6ad3ecc9bd56cc4b55d564444c
parentd8dfc3bd461def65fbd180acab7c49a8d8394d7b (diff)
drm/amdgpu: drop copy/paste leftover to fix big endian
The buf swap field doesn't exist on RB1. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 0061a0e8ab78..2932ade7dbd0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -2624,9 +2624,6 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
2624 rb_bufsz = order_base_2(ring->ring_size / 8); 2624 rb_bufsz = order_base_2(ring->ring_size / 8);
2625 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 2625 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2626 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 2626 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2627#ifdef __BIG_ENDIAN
2628 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, BUF_SWAP, 1);
2629#endif
2630 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 2627 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2631 /* Initialize the ring buffer's write pointers */ 2628 /* Initialize the ring buffer's write pointers */
2632 ring->wptr = 0; 2629 ring->wptr = 0;