Merge tag 'amlogic-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/soc

Pull "Amlogic SoC updates for v4.15" from Kevin Hilman:

- add SMP support to Meson8/8b

* tag 'amlogic-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM: meson: enable MESON_IRQ_GPIO in Kconfig for meson8b
  ARM: meson: Add SMP bringup code for Meson8 and Meson8b
  ARM: smp_scu: allow the platform code to read the SCU CPU status
  ARM: smp_scu: add a helper for powering on a specific CPU
  dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation

9 files changed, 545 insertions, 6 deletions

diff --git a/Documentation/devicetree/bindings/arm/amlogic/pmu.txt b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt
new file mode 100644
index 000000000000..72f8d08198b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt
@@ -0,0 +1,18 @@
+Amlogic Meson8 and Meson8b power-management-unit:
+-------------------------------------------------
+
+The pmu is used to turn off and on different power domains of the SoCs
+This includes the power to the CPU cores.
+
+Required node properties:
+- compatible value : depending on the SoC this should be one of:
+                        "amlogic,meson8-pmu"
+                        "amlogic,meson8b-pmu"
+- reg : physical base address and the size of the registers window
+
+Example:
+
+        pmu@c81000e4 {
+                compatible = "amlogic,meson8b-pmu", "syscon";
+                reg = <0xc81000e0 0x18>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt
new file mode 100644
index 000000000000..3473ddaadfac
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt
@@ -0,0 +1,32 @@
+Amlogic Meson8 and Meson8b SRAM for smp bringup:
+------------------------------------------------
+
+Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
+Once the core gets powered up it executes the code that is residing at a
+specific location.
+
+Therefore a reserved section sub-node has to be added to the mmio-sram
+declaration.
+
+Required sub-node properties:
+- compatible : depending on the SoC this should be one of:
+                "amlogic,meson8-smp-sram"
+                "amlogic,meson8b-smp-sram"
+
+The rest of the properties should follow the generic mmio-sram discription
+found in ../../misc/sram.txt
+
+Example:
+
+        sram: sram@d9000000 {
+                compatible = "mmio-sram";
+                reg = <0xd9000000 0x20000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0xd9000000 0x20000>;
+
+                smp-sram@1ff80 {
+                        compatible = "amlogic,meson8b-smp-sram";
+                        reg = <0x1ff80 0x8>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index b92f12bd5244..a0009b72e9be 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -197,6 +197,8 @@ described below.
                             "actions,s500-smp"
                             "allwinner,sun6i-a31"
                             "allwinner,sun8i-a23"
+                            "amlogic,meson8-smp"
+                            "amlogic,meson8b-smp"
                             "arm,realview-smp"
                             "brcm,bcm11351-cpu-method"
                             "brcm,bcm23550"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 47d3a1ab08d2..82faa958ab88 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -147,6 +147,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
 endif
 textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
+textofs-$(CONFIG_ARCH_MESON) := 0x00208000
 textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
 
 # Machine directory name.  This list is sorted alphanumerically
diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index 5983f6bc62d5..1529d1ae2f8d 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -27,6 +27,8 @@ static inline unsigned long scu_a9_get_base(void)
 #ifdef CONFIG_HAVE_ARM_SCU
 unsigned int scu_get_core_count(void __iomem *);
 int scu_power_mode(void __iomem *, unsigned int);
+int scu_cpu_power_enable(void __iomem *, unsigned int);
+int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu);
 #else
 static inline unsigned int scu_get_core_count(void __iomem *scu_base)
 {
@@ -36,6 +38,16 @@ static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode)
 {
         return -EINVAL;
 }
+static inline int scu_cpu_power_enable(void __iomem *scu_base,
+                                       unsigned int mode)
+{
+        return -EINVAL;
+}
+static inline int scu_get_cpu_power_mode(void __iomem *scu_base,
+                                         unsigned int logical_cpu)
+{
+        return -EINVAL;
+}
 #endif
 
 #if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 72f9241ad5db..c6b33074c393 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -21,6 +21,7 @@
 #define SCU_STANDBY_ENABLE      (1 << 5)
 #define SCU_CONFIG              0x04
 #define SCU_CPU_STATUS          0x08
+#define SCU_CPU_STATUS_MASK     GENMASK(1, 0)
 #define SCU_INVALIDATE          0x0c
 #define SCU_FPGA_REVISION       0x10
 
@@ -72,6 +73,24 @@ void scu_enable(void __iomem *scu_base)
 }
 #endif
 
+static int scu_set_power_mode_internal(void __iomem *scu_base,
+                                       unsigned int logical_cpu,
+                                       unsigned int mode)
+{
+        unsigned int val;
+        int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0);
+
+        if (mode > 3 || mode == 1 || cpu > 3)
+                return -EINVAL;
+
+        val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
+        val &= ~SCU_CPU_STATUS_MASK;
+        val |= mode;
+        writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
+
+        return 0;
+}
+
 /*
  * Set the executing CPUs power mode as defined.  This will be in
  * preparation for it executing a WFI instruction.
@@ -82,15 +101,27 @@ void scu_enable(void __iomem *scu_base)
  */
 int scu_power_mode(void __iomem *scu_base, unsigned int mode)
 {
+        return scu_set_power_mode_internal(scu_base, smp_processor_id(), mode);
+}
+
+/*
+ * Set the given (logical) CPU's power mode to SCU_PM_NORMAL.
+ */
+int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu)
+{
+        return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL);
+}
+
+int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu)
+{
         unsigned int val;
-        int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
+        int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0);
 
-        if (mode > 3 || mode == 1 || cpu > 3)
+        if (cpu > 3)
                 return -EINVAL;
 
-        val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
-        val |= mode;
-        writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
+        val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
+        val &= SCU_CPU_STATUS_MASK;
 
-        return 0;
+        return val;
 }
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index ee30511849ca..aff6164b2083 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -9,6 +9,7 @@ menuconfig ARCH_MESON
         select PINCTRL_MESON
         select COMMON_CLK
         select COMMON_CLK_AMLOGIC
+        select HAVE_ARM_SCU if SMP
 
 if ARCH_MESON
 
@@ -28,5 +29,6 @@ config MACH_MESON8B
         default ARCH_MESON
         select MESON6_TIMER
         select COMMON_CLK_MESON8B
+        select MESON_IRQ_GPIO
 
 endif
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
index 9d7380eeeedd..bc26c85a7e8f 100644
--- a/arch/arm/mach-meson/Makefile
+++ b/arch/arm/mach-meson/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_ARCH_MESON) += meson.o
+obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c
new file mode 100644
index 000000000000..2555f9056a33
--- /dev/null
+++ b/arch/arm/mach-meson/platsmp.c
@@ -0,0 +1,440 @@
+/*
+ * Copyright (C) 2015 Carlo Caione <carlo@endlessm.com>
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/smp.h>
+#include <linux/mfd/syscon.h>
+
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_plat.h>
+
+#define MESON_SMP_SRAM_CPU_CTRL_REG             (0x00)
+#define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c)     (0x04 + ((c - 1) << 2))
+
+#define MESON_CPU_AO_RTI_PWR_A9_CNTL0           (0x00)
+#define MESON_CPU_AO_RTI_PWR_A9_CNTL1           (0x04)
+#define MESON_CPU_AO_RTI_PWR_A9_MEM_PD0         (0x14)
+
+#define MESON_CPU_PWR_A9_CNTL0_M(c)             (0x03 << ((c * 2) + 16))
+#define MESON_CPU_PWR_A9_CNTL1_M(c)             (0x03 << ((c + 1) << 1))
+#define MESON_CPU_PWR_A9_MEM_PD0_M(c)           (0x0f << (32 - (c * 4)))
+#define MESON_CPU_PWR_A9_CNTL1_ST(c)            (0x01 << (c + 16))
+
+static void __iomem *sram_base;
+static void __iomem *scu_base;
+static struct regmap *pmu;
+
+static struct reset_control *meson_smp_get_core_reset(int cpu)
+{
+        struct device_node *np = of_get_cpu_node(cpu, 0);
+
+        return of_reset_control_get_exclusive(np, NULL);
+}
+
+static void meson_smp_set_cpu_ctrl(int cpu, bool on_off)
+{
+        u32 val = readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_REG);
+
+        if (on_off)
+                val |= BIT(cpu);
+        else
+                val &= ~BIT(cpu);
+
+        /* keep bit 0 always enabled */
+        val |= BIT(0);
+
+        writel(val, sram_base + MESON_SMP_SRAM_CPU_CTRL_REG);
+}
+
+static void __init meson_smp_prepare_cpus(const char *scu_compatible,
+                                          const char *pmu_compatible,
+                                          const char *sram_compatible)
+{
+        static struct device_node *node;
+
+        /* SMP SRAM */
+        node = of_find_compatible_node(NULL, NULL, sram_compatible);
+        if (!node) {
+                pr_err("Missing SRAM node\n");
+                return;
+        }
+
+        sram_base = of_iomap(node, 0);
+        if (!sram_base) {
+                pr_err("Couldn't map SRAM registers\n");
+                return;
+        }
+
+        /* PMU */
+        pmu = syscon_regmap_lookup_by_compatible(pmu_compatible);
+        if (IS_ERR(pmu)) {
+                pr_err("Couldn't map PMU registers\n");
+                return;
+        }
+
+        /* SCU */
+        node = of_find_compatible_node(NULL, NULL, scu_compatible);
+        if (!node) {
+                pr_err("Missing SCU node\n");
+                return;
+        }
+
+        scu_base = of_iomap(node, 0);
+        if (!scu_base) {
+                pr_err("Couln't map SCU registers\n");
+                return;
+        }
+
+        scu_enable(scu_base);
+}
+
+static void __init meson8b_smp_prepare_cpus(unsigned int max_cpus)
+{
+        meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu",
+                               "amlogic,meson8b-smp-sram");
+}
+
+static void __init meson8_smp_prepare_cpus(unsigned int max_cpus)
+{
+        meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu",
+                               "amlogic,meson8-smp-sram");
+}
+
+static void meson_smp_begin_secondary_boot(unsigned int cpu)
+{
+        /*
+         * Set the entry point before powering on the CPU through the SCU. This
+         * is needed if the CPU is in "warm" state (= after rebooting the
+         * system without power-cycling, or when taking the CPU offline and
+         * then taking it online again.
+         */
+        writel(__pa_symbol(secondary_startup),
+               sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));
+
+        /*
+         * SCU Power on CPU (needs to be done before starting the CPU,
+         * otherwise the secondary CPU will not start).
+         */
+        scu_cpu_power_enable(scu_base, cpu);
+}
+
+static int meson_smp_finalize_secondary_boot(unsigned int cpu)
+{
+        unsigned long timeout;
+
+        timeout = jiffies + (10 * HZ);
+        while (readl(sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu))) {
+                if (!time_before(jiffies, timeout)) {
+                        pr_err("Timeout while waiting for CPU%d status\n",
+                               cpu);
+                        return -ETIMEDOUT;
+                }
+        }
+
+        writel(__pa_symbol(secondary_startup),
+               sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu));
+
+        meson_smp_set_cpu_ctrl(cpu, true);
+
+        return 0;
+}
+
+static int meson8_smp_boot_secondary(unsigned int cpu,
+                                     struct task_struct *idle)
+{
+        struct reset_control *rstc;
+        int ret;
+
+        rstc = meson_smp_get_core_reset(cpu);
+        if (IS_ERR(rstc)) {
+                pr_err("Couldn't get the reset controller for CPU%d\n", cpu);
+                return PTR_ERR(rstc);
+        }
+
+        meson_smp_begin_secondary_boot(cpu);
+
+        /* Reset enable */
+        ret = reset_control_assert(rstc);
+        if (ret) {
+                pr_err("Failed to assert CPU%d reset\n", cpu);
+                goto out;
+        }
+
+        /* CPU power ON */
+        ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
+                                 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0);
+        if (ret < 0) {
+                pr_err("Couldn't wake up CPU%d\n", cpu);
+                goto out;
+        }
+
+        udelay(10);
+
+        /* Isolation disable */
+        ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
+                                 0);
+        if (ret < 0) {
+                pr_err("Error when disabling isolation of CPU%d\n", cpu);
+                goto out;
+        }
+
+        /* Reset disable */
+        ret = reset_control_deassert(rstc);
+        if (ret) {
+                pr_err("Failed to de-assert CPU%d reset\n", cpu);
+                goto out;
+        }
+
+        ret = meson_smp_finalize_secondary_boot(cpu);
+        if (ret)
+                goto out;
+
+out:
+        reset_control_put(rstc);
+
+        return 0;
+}
+
+static int meson8b_smp_boot_secondary(unsigned int cpu,
+                                     struct task_struct *idle)
+{
+        struct reset_control *rstc;
+        int ret;
+        u32 val;
+
+        rstc = meson_smp_get_core_reset(cpu);
+        if (IS_ERR(rstc)) {
+                pr_err("Couldn't get the reset controller for CPU%d\n", cpu);
+                return PTR_ERR(rstc);
+        }
+
+        meson_smp_begin_secondary_boot(cpu);
+
+        /* CPU power UP */
+        ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
+                                 MESON_CPU_PWR_A9_CNTL0_M(cpu), 0);
+        if (ret < 0) {
+                pr_err("Couldn't power up CPU%d\n", cpu);
+                goto out;
+        }
+
+        udelay(5);
+
+        /* Reset enable */
+        ret = reset_control_assert(rstc);
+        if (ret) {
+                pr_err("Failed to assert CPU%d reset\n", cpu);
+                goto out;
+        }
+
+        /* Memory power UP */
+        ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
+                                 MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0);
+        if (ret < 0) {
+                pr_err("Couldn't power up the memory for CPU%d\n", cpu);
+                goto out;
+        }
+
+        /* Wake up CPU */
+        ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
+                                 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0);
+        if (ret < 0) {
+                pr_err("Couldn't wake up CPU%d\n", cpu);
+                goto out;
+        }
+
+        udelay(10);
+
+        ret = regmap_read_poll_timeout(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, val,
+                                       val & MESON_CPU_PWR_A9_CNTL1_ST(cpu),
+                                       10, 10000);
+        if (ret) {
+                pr_err("Timeout while polling PMU for CPU%d status\n", cpu);
+                goto out;
+        }
+
+        /* Isolation disable */
+        ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
+                                 0);
+        if (ret < 0) {
+                pr_err("Error when disabling isolation of CPU%d\n", cpu);
+                goto out;
+        }
+
+        /* Reset disable */
+        ret = reset_control_deassert(rstc);
+        if (ret) {
+                pr_err("Failed to de-assert CPU%d reset\n", cpu);
+                goto out;
+        }
+
+        ret = meson_smp_finalize_secondary_boot(cpu);
+        if (ret)
+                goto out;
+
+out:
+        reset_control_put(rstc);
+
+        return 0;
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+static void meson8_smp_cpu_die(unsigned int cpu)
+{
+        meson_smp_set_cpu_ctrl(cpu, false);
+
+        v7_exit_coherency_flush(louis);
+
+        scu_power_mode(scu_base, SCU_PM_POWEROFF);
+
+        dsb();
+        wfi();
+
+        /* we should never get here */
+        WARN_ON(1);
+}
+
+static int meson8_smp_cpu_kill(unsigned int cpu)
+{
+        int ret, power_mode;
+        unsigned long timeout;
+
+        timeout = jiffies + (50 * HZ);
+        do {
+                power_mode = scu_get_cpu_power_mode(scu_base, cpu);
+
+                if (power_mode == SCU_PM_POWEROFF)
+                        break;
+
+                usleep_range(10000, 15000);
+        } while (time_before(jiffies, timeout));
+
+        if (power_mode != SCU_PM_POWEROFF) {
+                pr_err("Error while waiting for SCU power-off on CPU%d\n",
+                       cpu);
+                return -ETIMEDOUT;
+        }
+
+        msleep(30);
+
+        /* Isolation enable */
+        ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
+                                 0x3);
+        if (ret < 0) {
+                pr_err("Error when enabling isolation for CPU%d\n", cpu);
+                return ret;
+        }
+
+        udelay(10);
+
+        /* CPU power OFF */
+        ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
+                                 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3);
+        if (ret < 0) {
+                pr_err("Couldn't change sleep status of CPU%d\n", cpu);
+                return ret;
+        }
+
+        return 1;
+}
+
+static int meson8b_smp_cpu_kill(unsigned int cpu)
+{
+        int ret, power_mode, count = 5000;
+
+        do {
+                power_mode = scu_get_cpu_power_mode(scu_base, cpu);
+
+                if (power_mode == SCU_PM_POWEROFF)
+                        break;
+
+                udelay(10);
+        } while (++count);
+
+        if (power_mode != SCU_PM_POWEROFF) {
+                pr_err("Error while waiting for SCU power-off on CPU%d\n",
+                       cpu);
+                return -ETIMEDOUT;
+        }
+
+        udelay(10);
+
+        /* CPU power DOWN */
+        ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0,
+                                 MESON_CPU_PWR_A9_CNTL0_M(cpu), 0x3);
+        if (ret < 0) {
+                pr_err("Couldn't power down CPU%d\n", cpu);
+                return ret;
+        }
+
+        /* Isolation enable */
+        ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, BIT(cpu),
+                                 0x3);
+        if (ret < 0) {
+                pr_err("Error when enabling isolation for CPU%d\n", cpu);
+                return ret;
+        }
+
+        udelay(10);
+
+        /* Sleep status */
+        ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1,
+                                 MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3);
+        if (ret < 0) {
+                pr_err("Couldn't change sleep status of CPU%d\n", cpu);
+                return ret;
+        }
+
+        /* Memory power DOWN */
+        ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0,
+                                 MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0xf);
+        if (ret < 0) {
+                pr_err("Couldn't power down the memory of CPU%d\n", cpu);
+                return ret;
+        }
+
+        return 1;
+}
+#endif
+
+static struct smp_operations meson8_smp_ops __initdata = {
+        .smp_prepare_cpus       = meson8_smp_prepare_cpus,
+        .smp_boot_secondary     = meson8_smp_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = meson8_smp_cpu_die,
+        .cpu_kill               = meson8_smp_cpu_kill,
+#endif
+};
+
+static struct smp_operations meson8b_smp_ops __initdata = {
+        .smp_prepare_cpus       = meson8b_smp_prepare_cpus,
+        .smp_boot_secondary     = meson8b_smp_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = meson8_smp_cpu_die,
+        .cpu_kill               = meson8b_smp_cpu_kill,
+#endif
+};
+
+CPU_METHOD_OF_DECLARE(meson8_smp, "amlogic,meson8-smp", &meson8_smp_ops);
+CPU_METHOD_OF_DECLARE(meson8b_smp, "amlogic,meson8b-smp", &meson8b_smp_ops);