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authorJames Liao <jamesjj.liao@mediatek.com>2015-08-10 05:50:28 -0400
committerMatthias Brugger <matthias.bgg@gmail.com>2015-10-14 09:24:16 -0400
commit67e56c5651d30cd5adddcf32ab41c71dabf2bcec (patch)
treefba860066bb06c135eb1aa236b48d74c835c907d
parentb0c936f59c8928dac2b230322dd51cbfae289151 (diff)
arm64: dts: mt8173: Add subsystem clock controller device nodes
This patch adds device nodes providing subsystem clocks on MT8173, includes mmsys, imgsys, vdecsys, vencsys and vencltsys. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8173.dtsi37
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 4bce1676fbd1..42540b208a8f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -116,6 +116,13 @@
116 clock-output-names = "clk32k"; 116 clock-output-names = "clk32k";
117 }; 117 };
118 118
119 cpum_ck: oscillator@2 {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <0>;
123 clock-output-names = "cpum_ck";
124 };
125
119 timer { 126 timer {
120 compatible = "arm,armv8-timer"; 127 compatible = "arm,armv8-timer";
121 interrupt-parent = <&gic>; 128 interrupt-parent = <&gic>;
@@ -500,6 +507,36 @@
500 clock-names = "source", "hclk"; 507 clock-names = "source", "hclk";
501 status = "disabled"; 508 status = "disabled";
502 }; 509 };
510
511 mmsys: clock-controller@14000000 {
512 compatible = "mediatek,mt8173-mmsys", "syscon";
513 reg = <0 0x14000000 0 0x1000>;
514 #clock-cells = <1>;
515 };
516
517 imgsys: clock-controller@15000000 {
518 compatible = "mediatek,mt8173-imgsys", "syscon";
519 reg = <0 0x15000000 0 0x1000>;
520 #clock-cells = <1>;
521 };
522
523 vdecsys: clock-controller@16000000 {
524 compatible = "mediatek,mt8173-vdecsys", "syscon";
525 reg = <0 0x16000000 0 0x1000>;
526 #clock-cells = <1>;
527 };
528
529 vencsys: clock-controller@18000000 {
530 compatible = "mediatek,mt8173-vencsys", "syscon";
531 reg = <0 0x18000000 0 0x1000>;
532 #clock-cells = <1>;
533 };
534
535 vencltsys: clock-controller@19000000 {
536 compatible = "mediatek,mt8173-vencltsys", "syscon";
537 reg = <0 0x19000000 0 0x1000>;
538 #clock-cells = <1>;
539 };
503 }; 540 };
504}; 541};
505 542