Merge tag 'clk-v4.11-samsung-dphy' of git://linuxtv.org/snawrocki/samsung into next/dt64

Exporting clocks for MIPI DSI DPHY and the display PLL
frequency list update for Exynos5433 SoC.

2 files changed, 10 insertions, 3 deletions

diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index f096bd7df40c..3feaea8be40e 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -739,7 +739,9 @@ static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst =
         PLL_35XX_RATE(350000000U,  350, 6,  2),
         PLL_35XX_RATE(333000000U,  222, 4,  2),
         PLL_35XX_RATE(300000000U,  500, 5,  3),
+        PLL_35XX_RATE(278000000U,  556, 6,  3),
         PLL_35XX_RATE(266000000U,  532, 6,  3),
+        PLL_35XX_RATE(250000000U,  500, 6,  3),
         PLL_35XX_RATE(200000000U,  400, 6,  3),
         PLL_35XX_RATE(166000000U,  332, 6,  3),
         PLL_35XX_RATE(160000000U,  320, 6,  3),
@@ -2559,8 +2561,10 @@ static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
         FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
         FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
         /* PHY clocks from MIPI_DPHY0 */
-        FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000),
-        FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000),
+        FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
+                        NULL, 0, 188000000),
+        FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
+                        NULL, 0, 100000000),
         /* PHY clocks from HDMI_PHY */
         FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
                         NULL, 0, 300000000),
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 4fa6bb2136e3..be39d23e6a32 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -771,7 +771,10 @@
 
 #define CLK_PCLK_DECON                                  113
 
-#define DISP_NR_CLK                                     114
+#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY             114
+#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY              115
+
+#define DISP_NR_CLK                                     116
 
 /* CMU_AUD */
 #define CLK_MOUT_AUD_PLL_USER                           1