Merge branch 'drm-header-fixes' of https://github.com/GabrielL/linux into drm-next

Fix all the problems with the header files and userspace builds
off them. I really care so little about this, but hey who am
I to stop progress.

* 'drm-header-fixes' of https://github.com/GabrielL/linux: (30 commits)
  drm: fix inclusion of drm.h in via_drm.h
  drm: fix inclusion of drm.h in vmwgfx_drm.h
  drm: fix inclusion of drm.h in virtgpu_drm.h
  drm: fix inclusion of drm.h in tegra_drm.h
  drm: fix inclusion of drm.h in savage_drm.h
  drm: fix inclusion of drm.h in r128_drm.h
  drm: fix inclusion of drm.h in qxl_drm.h
  drm: fix inclusion of drm.h in omap_drm.h
  drm: fix inclusion of drm.h in msm_drm.h
  drm: fix inclusion of drm.h in mga_drm.h
  drm: fix inclusion of drm.h in exynos_sarea.h
  drm: fix inclusion of drm.h in i810_drm.h
  drm: fix inclusion of drm.h in exynos_sarea.h
  drm: fix inclusion of drm.h in drm_sarea.h
  drm: drm_mode.h fix includes
  drm: drm_fourcc.h fix includes
  drm: include drm.h in armada_drm.h
  include/uapi/drm/amdgpu_drm.h: use __u32 and __u64 from <linux/types.h>
  drm: Kbuild: add admgpu_drm.h to the installed headers
  drm: use __u{32,64} instead of uint{32,64}_t in virtgpu_drm.h
  ...

24 files changed, 508 insertions, 509 deletions

diff --git a/include/uapi/drm/Kbuild b/include/uapi/drm/Kbuild
index 38d437096c35..159551f49313 100644
--- a/include/uapi/drm/Kbuild
+++ b/include/uapi/drm/Kbuild
@@ -3,6 +3,7 @@ header-y += drm.h
 header-y += drm_fourcc.h
 header-y += drm_mode.h
 header-y += drm_sarea.h
+header-y += amdgpu_drm.h
 header-y += exynos_drm.h
 header-y += i810_drm.h
 header-y += i915_drm.h
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index e52933a73580..453a76af123c 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -76,19 +76,19 @@
 
 struct drm_amdgpu_gem_create_in  {
         /** the requested memory size */
-        uint64_t bo_size;
+        __u64 bo_size;
         /** physical start_addr alignment in bytes for some HW requirements */
-        uint64_t alignment;
+        __u64 alignment;
         /** the requested memory domains */
-        uint64_t domains;
+        __u64 domains;
         /** allocation flags */
-        uint64_t domain_flags;
+        __u64 domain_flags;
 };
 
 struct drm_amdgpu_gem_create_out  {
         /** returned GEM object handle */
-        uint32_t handle;
-        uint32_t _pad;
+        __u32 handle;
+        __u32 _pad;
 };
 
 union drm_amdgpu_gem_create {
@@ -105,28 +105,28 @@ union drm_amdgpu_gem_create {
 
 struct drm_amdgpu_bo_list_in {
         /** Type of operation */
-        uint32_t operation;
+        __u32 operation;
         /** Handle of list or 0 if we want to create one */
-        uint32_t list_handle;
+        __u32 list_handle;
         /** Number of BOs in list  */
-        uint32_t bo_number;
+        __u32 bo_number;
         /** Size of each element describing BO */
-        uint32_t bo_info_size;
+        __u32 bo_info_size;
         /** Pointer to array describing BOs */
-        uint64_t bo_info_ptr;
+        __u64 bo_info_ptr;
 };
 
 struct drm_amdgpu_bo_list_entry {
         /** Handle of BO */
-        uint32_t bo_handle;
+        __u32 bo_handle;
         /** New (if specified) BO priority to be used during migration */
-        uint32_t bo_priority;
+        __u32 bo_priority;
 };
 
 struct drm_amdgpu_bo_list_out {
         /** Handle of resource list  */
-        uint32_t list_handle;
-        uint32_t _pad;
+        __u32 list_handle;
+        __u32 _pad;
 };
 
 union drm_amdgpu_bo_list {
@@ -150,26 +150,26 @@ union drm_amdgpu_bo_list {
 
 struct drm_amdgpu_ctx_in {
         /** AMDGPU_CTX_OP_* */
-        uint32_t        op;
+        __u32   op;
         /** For future use, no flags defined so far */
-        uint32_t        flags;
-        uint32_t        ctx_id;
-        uint32_t        _pad;
+        __u32   flags;
+        __u32   ctx_id;
+        __u32   _pad;
 };
 
 union drm_amdgpu_ctx_out {
                 struct {
-                        uint32_t        ctx_id;
-                        uint32_t        _pad;
+                        __u32   ctx_id;
+                        __u32   _pad;
                 } alloc;
 
                 struct {
                         /** For future use, no flags defined so far */
-                        uint64_t        flags;
+                        __u64   flags;
                         /** Number of resets caused by this context so far. */
-                        uint32_t        hangs;
+                        __u32   hangs;
                         /** Reset status since the last call of the ioctl. */
-                        uint32_t        reset_status;
+                        __u32   reset_status;
                 } state;
 };
 
@@ -189,12 +189,12 @@ union drm_amdgpu_ctx {
 #define AMDGPU_GEM_USERPTR_REGISTER     (1 << 3)
 
 struct drm_amdgpu_gem_userptr {
-        uint64_t                addr;
-        uint64_t                size;
+        __u64           addr;
+        __u64           size;
         /* AMDGPU_GEM_USERPTR_* */
-        uint32_t                flags;
+        __u32           flags;
         /* Resulting GEM handle */
-        uint32_t                handle;
+        __u32           handle;
 };
 
 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
@@ -226,28 +226,28 @@ struct drm_amdgpu_gem_userptr {
 /** The same structure is shared for input/output */
 struct drm_amdgpu_gem_metadata {
         /** GEM Object handle */
-        uint32_t        handle;
+        __u32   handle;
         /** Do we want get or set metadata */
-        uint32_t        op;
+        __u32   op;
         struct {
                 /** For future use, no flags defined so far */
-                uint64_t        flags;
+                __u64   flags;
                 /** family specific tiling info */
-                uint64_t        tiling_info;
-                uint32_t        data_size_bytes;
-                uint32_t        data[64];
+                __u64   tiling_info;
+                __u32   data_size_bytes;
+                __u32   data[64];
         } data;
 };
 
 struct drm_amdgpu_gem_mmap_in {
         /** the GEM object handle */
-        uint32_t handle;
-        uint32_t _pad;
+        __u32 handle;
+        __u32 _pad;
 };
 
 struct drm_amdgpu_gem_mmap_out {
         /** mmap offset from the vma offset manager */
-        uint64_t addr_ptr;
+        __u64 addr_ptr;
 };
 
 union drm_amdgpu_gem_mmap {
@@ -257,18 +257,18 @@ union drm_amdgpu_gem_mmap {
 
 struct drm_amdgpu_gem_wait_idle_in {
         /** GEM object handle */
-        uint32_t handle;
+        __u32 handle;
         /** For future use, no flags defined so far */
-        uint32_t flags;
+        __u32 flags;
         /** Absolute timeout to wait */
-        uint64_t timeout;
+        __u64 timeout;
 };
 
 struct drm_amdgpu_gem_wait_idle_out {
         /** BO status:  0 - BO is idle, 1 - BO is busy */
-        uint32_t status;
+        __u32 status;
         /** Returned current memory domain */
-        uint32_t domain;
+        __u32 domain;
 };
 
 union drm_amdgpu_gem_wait_idle {
@@ -278,18 +278,18 @@ union drm_amdgpu_gem_wait_idle {
 
 struct drm_amdgpu_wait_cs_in {
         /** Command submission handle */
-        uint64_t handle;
+        __u64 handle;
         /** Absolute timeout to wait */
-        uint64_t timeout;
-        uint32_t ip_type;
-        uint32_t ip_instance;
-        uint32_t ring;
-        uint32_t ctx_id;
+        __u64 timeout;
+        __u32 ip_type;
+        __u32 ip_instance;
+        __u32 ring;
+        __u32 ctx_id;
 };
 
 struct drm_amdgpu_wait_cs_out {
         /** CS status:  0 - CS completed, 1 - CS still busy */
-        uint64_t status;
+        __u64 status;
 };
 
 union drm_amdgpu_wait_cs {
@@ -303,11 +303,11 @@ union drm_amdgpu_wait_cs {
 /* Sets or returns a value associated with a buffer. */
 struct drm_amdgpu_gem_op {
         /** GEM object handle */
-        uint32_t        handle;
+        __u32   handle;
         /** AMDGPU_GEM_OP_* */
-        uint32_t        op;
+        __u32   op;
         /** Input or return value */
-        uint64_t        value;
+        __u64   value;
 };
 
 #define AMDGPU_VA_OP_MAP                        1
@@ -326,18 +326,18 @@ struct drm_amdgpu_gem_op {
 
 struct drm_amdgpu_gem_va {
         /** GEM object handle */
-        uint32_t handle;
-        uint32_t _pad;
+        __u32 handle;
+        __u32 _pad;
         /** AMDGPU_VA_OP_* */
-        uint32_t operation;
+        __u32 operation;
         /** AMDGPU_VM_PAGE_* */
-        uint32_t flags;
+        __u32 flags;
         /** va address to assign . Must be correctly aligned.*/
-        uint64_t va_address;
+        __u64 va_address;
         /** Specify offset inside of BO to assign. Must be correctly aligned.*/
-        uint64_t offset_in_bo;
+        __u64 offset_in_bo;
         /** Specify mapping size. Must be correctly aligned. */
-        uint64_t map_size;
+        __u64 map_size;
 };
 
 #define AMDGPU_HW_IP_GFX          0
@@ -354,24 +354,24 @@ struct drm_amdgpu_gem_va {
 #define AMDGPU_CHUNK_ID_DEPENDENCIES    0x03
 
 struct drm_amdgpu_cs_chunk {
-        uint32_t                chunk_id;
-        uint32_t                length_dw;
-        uint64_t                chunk_data;
+        __u32           chunk_id;
+        __u32           length_dw;
+        __u64           chunk_data;
 };
 
 struct drm_amdgpu_cs_in {
         /** Rendering context id */
-        uint32_t                ctx_id;
+        __u32           ctx_id;
         /**  Handle of resource list associated with CS */
-        uint32_t                bo_list_handle;
-        uint32_t                num_chunks;
-        uint32_t                _pad;
-        /** this points to uint64_t * which point to cs chunks */
-        uint64_t                chunks;
+        __u32           bo_list_handle;
+        __u32           num_chunks;
+        __u32           _pad;
+        /** this points to __u64 * which point to cs chunks */
+        __u64           chunks;
 };
 
 struct drm_amdgpu_cs_out {
-        uint64_t handle;
+        __u64 handle;
 };
 
 union drm_amdgpu_cs {
@@ -388,32 +388,32 @@ union drm_amdgpu_cs {
 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
 
 struct drm_amdgpu_cs_chunk_ib {
-        uint32_t _pad;
+        __u32 _pad;
         /** AMDGPU_IB_FLAG_* */
-        uint32_t flags;
+        __u32 flags;
         /** Virtual address to begin IB execution */
-        uint64_t va_start;
+        __u64 va_start;
         /** Size of submission */
-        uint32_t ib_bytes;
+        __u32 ib_bytes;
         /** HW IP to submit to */
-        uint32_t ip_type;
+        __u32 ip_type;
         /** HW IP index of the same type to submit to  */
-        uint32_t ip_instance;
+        __u32 ip_instance;
         /** Ring index to submit to */
-        uint32_t ring;
+        __u32 ring;
 };
 
 struct drm_amdgpu_cs_chunk_dep {
-        uint32_t ip_type;
-        uint32_t ip_instance;
-        uint32_t ring;
-        uint32_t ctx_id;
-        uint64_t handle;
+        __u32 ip_type;
+        __u32 ip_instance;
+        __u32 ring;
+        __u32 ctx_id;
+        __u64 handle;
 };
 
 struct drm_amdgpu_cs_chunk_fence {
-        uint32_t handle;
-        uint32_t offset;
+        __u32 handle;
+        __u32 offset;
 };
 
 struct drm_amdgpu_cs_chunk_data {
@@ -486,83 +486,83 @@ struct drm_amdgpu_cs_chunk_data {
 /* Input structure for the INFO ioctl */
 struct drm_amdgpu_info {
         /* Where the return value will be stored */
-        uint64_t return_pointer;
+        __u64 return_pointer;
         /* The size of the return value. Just like "size" in "snprintf",
          * it limits how many bytes the kernel can write. */
-        uint32_t return_size;
+        __u32 return_size;
         /* The query request id. */
-        uint32_t query;
+        __u32 query;
 
         union {
                 struct {
-                        uint32_t id;
-                        uint32_t _pad;
+                        __u32 id;
+                        __u32 _pad;
                 } mode_crtc;
 
                 struct {
                         /** AMDGPU_HW_IP_* */
-                        uint32_t type;
+                        __u32 type;
                         /**
                          * Index of the IP if there are more IPs of the same
                          * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
                          */
-                        uint32_t ip_instance;
+                        __u32 ip_instance;
                 } query_hw_ip;
 
                 struct {
-                        uint32_t dword_offset;
+                        __u32 dword_offset;
                         /** number of registers to read */
-                        uint32_t count;
-                        uint32_t instance;
+                        __u32 count;
+                        __u32 instance;
                         /** For future use, no flags defined so far */
-                        uint32_t flags;
+                        __u32 flags;
                 } read_mmr_reg;
 
                 struct {
                         /** AMDGPU_INFO_FW_* */
-                        uint32_t fw_type;
+                        __u32 fw_type;
                         /**
                          * Index of the IP if there are more IPs of
                          * the same type.
                          */
-                        uint32_t ip_instance;
+                        __u32 ip_instance;
                         /**
                          * Index of the engine. Whether this is used depends
                          * on the firmware type. (e.g. MEC, SDMA)
                          */
-                        uint32_t index;
-                        uint32_t _pad;
+                        __u32 index;
+                        __u32 _pad;
                 } query_fw;
         };
 };
 
 struct drm_amdgpu_info_gds {
         /** GDS GFX partition size */
-        uint32_t gds_gfx_partition_size;
+        __u32 gds_gfx_partition_size;
         /** GDS compute partition size */
-        uint32_t compute_partition_size;
+        __u32 compute_partition_size;
         /** total GDS memory size */
-        uint32_t gds_total_size;
+        __u32 gds_total_size;
         /** GWS size per GFX partition */
-        uint32_t gws_per_gfx_partition;
+        __u32 gws_per_gfx_partition;
         /** GSW size per compute partition */
-        uint32_t gws_per_compute_partition;
+        __u32 gws_per_compute_partition;
         /** OA size per GFX partition */
-        uint32_t oa_per_gfx_partition;
+        __u32 oa_per_gfx_partition;
         /** OA size per compute partition */
-        uint32_t oa_per_compute_partition;
-        uint32_t _pad;
+        __u32 oa_per_compute_partition;
+        __u32 _pad;
 };
 
 struct drm_amdgpu_info_vram_gtt {
-        uint64_t vram_size;
-        uint64_t vram_cpu_accessible_size;
-        uint64_t gtt_size;
+        __u64 vram_size;
+        __u64 vram_cpu_accessible_size;
+        __u64 gtt_size;
 };
 
 struct drm_amdgpu_info_firmware {
-        uint32_t ver;
-        uint32_t feature;
+        __u32 ver;
+        __u32 feature;
 };
 
 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
@@ -576,61 +576,61 @@ struct drm_amdgpu_info_firmware {
 
 struct drm_amdgpu_info_device {
         /** PCI Device ID */
-        uint32_t device_id;
+        __u32 device_id;
         /** Internal chip revision: A0, A1, etc.) */
-        uint32_t chip_rev;
-        uint32_t external_rev;
+        __u32 chip_rev;
+        __u32 external_rev;
         /** Revision id in PCI Config space */
-        uint32_t pci_rev;
-        uint32_t family;
-        uint32_t num_shader_engines;
-        uint32_t num_shader_arrays_per_engine;
+        __u32 pci_rev;
+        __u32 family;
+        __u32 num_shader_engines;
+        __u32 num_shader_arrays_per_engine;
         /* in KHz */
-        uint32_t gpu_counter_freq;
-        uint64_t max_engine_clock;
-        uint64_t max_memory_clock;
+        __u32 gpu_counter_freq;
+        __u64 max_engine_clock;
+        __u64 max_memory_clock;
         /* cu information */
-        uint32_t cu_active_number;
-        uint32_t cu_ao_mask;
-        uint32_t cu_bitmap[4][4];
+        __u32 cu_active_number;
+        __u32 cu_ao_mask;
+        __u32 cu_bitmap[4][4];
         /** Render backend pipe mask. One render backend is CB+DB. */
-        uint32_t enabled_rb_pipes_mask;
-        uint32_t num_rb_pipes;
-        uint32_t num_hw_gfx_contexts;
-        uint32_t _pad;
-        uint64_t ids_flags;
+        __u32 enabled_rb_pipes_mask;
+        __u32 num_rb_pipes;
+        __u32 num_hw_gfx_contexts;
+        __u32 _pad;
+        __u64 ids_flags;
         /** Starting virtual address for UMDs. */
-        uint64_t virtual_address_offset;
+        __u64 virtual_address_offset;
         /** The maximum virtual address */
-        uint64_t virtual_address_max;
+        __u64 virtual_address_max;
         /** Required alignment of virtual addresses. */
-        uint32_t virtual_address_alignment;
+        __u32 virtual_address_alignment;
         /** Page table entry - fragment size */
-        uint32_t pte_fragment_size;
-        uint32_t gart_page_size;
+        __u32 pte_fragment_size;
+        __u32 gart_page_size;
         /** constant engine ram size*/
-        uint32_t ce_ram_size;
+        __u32 ce_ram_size;
         /** video memory type info*/
-        uint32_t vram_type;
+        __u32 vram_type;
         /** video memory bit width*/
-        uint32_t vram_bit_width;
+        __u32 vram_bit_width;
         /* vce harvesting instance */
-        uint32_t vce_harvest_config;
+        __u32 vce_harvest_config;
 };
 
 struct drm_amdgpu_info_hw_ip {
         /** Version of h/w IP */
-        uint32_t  hw_ip_version_major;
-        uint32_t  hw_ip_version_minor;
+        __u32  hw_ip_version_major;
+        __u32  hw_ip_version_minor;
         /** Capabilities */
-        uint64_t  capabilities_flags;
+        __u64  capabilities_flags;
         /** command buffer address start alignment*/
-        uint32_t  ib_start_alignment;
+        __u32  ib_start_alignment;
         /** command buffer size alignment*/
-        uint32_t  ib_size_alignment;
+        __u32  ib_size_alignment;
         /** Bitmask of available rings. Bit 0 means ring 0, etc. */
-        uint32_t  available_rings;
-        uint32_t  _pad;
+        __u32  available_rings;
+        __u32  _pad;
 };
 
 /*
diff --git a/include/uapi/drm/armada_drm.h b/include/uapi/drm/armada_drm.h
index 8dec3fdc99c7..6de7f0196ca0 100644
--- a/include/uapi/drm/armada_drm.h
+++ b/include/uapi/drm/armada_drm.h
@@ -9,6 +9,8 @@
 #ifndef DRM_ARMADA_IOCTL_H
 #define DRM_ARMADA_IOCTL_H
 
+#include "drm.h"
+
 #define DRM_ARMADA_GEM_CREATE           0x00
 #define DRM_ARMADA_GEM_MMAP             0x02
 #define DRM_ARMADA_GEM_PWRITE           0x03
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 3801584a0c53..b4e92eb12044 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -54,6 +54,7 @@ typedef int32_t  __s32;
 typedef uint32_t __u32;
 typedef int64_t  __s64;
 typedef uint64_t __u64;
+typedef size_t   __kernel_size_t;
 typedef unsigned long drm_handle_t;
 
 #endif
@@ -129,11 +130,11 @@ struct drm_version {
         int version_major;        /**< Major version */
         int version_minor;        /**< Minor version */
         int version_patchlevel;   /**< Patch level */
-        size_t name_len;          /**< Length of name buffer */
+        __kernel_size_t name_len;         /**< Length of name buffer */
         char __user *name;        /**< Name of driver */
-        size_t date_len;          /**< Length of date buffer */
+        __kernel_size_t date_len;         /**< Length of date buffer */
         char __user *date;        /**< User-space buffer to hold date */
-        size_t desc_len;          /**< Length of desc buffer */
+        __kernel_size_t desc_len;         /**< Length of desc buffer */
         char __user *desc;        /**< User-space buffer to hold desc */
 };
 
@@ -143,7 +144,7 @@ struct drm_version {
  * \sa drmGetBusid() and drmSetBusId().
  */
 struct drm_unique {
-        size_t unique_len;        /**< Length of unique */
+        __kernel_size_t unique_len;       /**< Length of unique */
         char __user *unique;      /**< Unique name for driver instantiation */
 };
 
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 0b69a7753558..998bd253faad 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -24,7 +24,7 @@
 #ifndef DRM_FOURCC_H
 #define DRM_FOURCC_H
 
-#include <linux/types.h>
+#include "drm.h"
 
 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
                                  ((__u32)(c) << 16) | ((__u32)(d) << 24))
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 6c11ca401de8..50adb46204c2 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -27,7 +27,7 @@
 #ifndef _DRM_MODE_H
 #define _DRM_MODE_H
 
-#include <linux/types.h>
+#include "drm.h"
 
 #define DRM_DISPLAY_INFO_LEN    32
 #define DRM_CONNECTOR_NAME_LEN  32
@@ -526,14 +526,14 @@ struct drm_mode_crtc_page_flip {
 
 /* create a dumb scanout buffer */
 struct drm_mode_create_dumb {
-        uint32_t height;
-        uint32_t width;
-        uint32_t bpp;
-        uint32_t flags;
+        __u32 height;
+        __u32 width;
+        __u32 bpp;
+        __u32 flags;
         /* handle, pitch, size will be returned */
-        uint32_t handle;
-        uint32_t pitch;
-        uint64_t size;
+        __u32 handle;
+        __u32 pitch;
+        __u64 size;
 };
 
 /* set up for mmap of a dumb scanout buffer */
@@ -550,7 +550,7 @@ struct drm_mode_map_dumb {
 };
 
 struct drm_mode_destroy_dumb {
-        uint32_t handle;
+        __u32 handle;
 };
 
 /* page-flip flags are valid, plus: */
diff --git a/include/uapi/drm/drm_sarea.h b/include/uapi/drm/drm_sarea.h
index 413a5642d49f..1d1a858a203d 100644
--- a/include/uapi/drm/drm_sarea.h
+++ b/include/uapi/drm/drm_sarea.h
@@ -32,7 +32,7 @@
 #ifndef _DRM_SAREA_H_
 #define _DRM_SAREA_H_
 
-#include <drm/drm.h>
+#include "drm.h"
 
 /* SAREA area needs to be at least a page */
 #if defined(__alpha__)
diff --git a/include/uapi/drm/exynos_drm.h b/include/uapi/drm/exynos_drm.h
index 5575ed1598bd..312c67d744ae 100644
--- a/include/uapi/drm/exynos_drm.h
+++ b/include/uapi/drm/exynos_drm.h
@@ -15,7 +15,7 @@
 #ifndef _UAPI_EXYNOS_DRM_H_
 #define _UAPI_EXYNOS_DRM_H_
 
-#include <drm/drm.h>
+#include "drm.h"
 
 /**
  * User-desired buffer creation information structure.
@@ -27,7 +27,7 @@
  *      - this handle will be set by gem module of kernel side.
  */
 struct drm_exynos_gem_create {
-        uint64_t size;
+        __u64 size;
         unsigned int flags;
         unsigned int handle;
 };
@@ -44,7 +44,7 @@ struct drm_exynos_gem_create {
 struct drm_exynos_gem_info {
         unsigned int handle;
         unsigned int flags;
-        uint64_t size;
+        __u64 size;
 };
 
 /**
@@ -58,7 +58,7 @@ struct drm_exynos_gem_info {
 struct drm_exynos_vidi_connection {
         unsigned int connection;
         unsigned int extensions;
-        uint64_t edid;
+        __u64 edid;
 };
 
 /* memory type definitions. */
diff --git a/include/uapi/drm/i810_drm.h b/include/uapi/drm/i810_drm.h
index 34736efd5824..bdb028723ded 100644
--- a/include/uapi/drm/i810_drm.h
+++ b/include/uapi/drm/i810_drm.h
@@ -1,7 +1,7 @@
 #ifndef _I810_DRM_H_
 #define _I810_DRM_H_
 
-#include <drm/drm.h>
+#include "drm.h"
 
 /* WARNING: These defines must be the same as what the Xserver uses.
  * if you change them, you must change the defines in the Xserver.
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 67ef73a5d6eb..c937a3628190 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -27,7 +27,7 @@
 #ifndef _UAPI_I915_DRM_H_
 #define _UAPI_I915_DRM_H_
 
-#include <drm/drm.h>
+#include "drm.h"
 
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints.
diff --git a/include/uapi/drm/mga_drm.h b/include/uapi/drm/mga_drm.h
index 2375bfd6e5e9..fca817009e13 100644
--- a/include/uapi/drm/mga_drm.h
+++ b/include/uapi/drm/mga_drm.h
@@ -35,7 +35,7 @@
 #ifndef __MGA_DRM_H__
 #define __MGA_DRM_H__
 
-#include <drm/drm.h>
+#include "drm.h"
 
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the Xserver file (mga_sarea.h)
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index 75a232b9a970..e995ffbcf86a 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -18,8 +18,7 @@
 #ifndef __MSM_DRM_H__
 #define __MSM_DRM_H__
 
-#include <stddef.h>
-#include <drm/drm.h>
+#include "drm.h"
 
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints:
diff --git a/include/uapi/drm/nouveau_drm.h b/include/uapi/drm/nouveau_drm.h
index fd594cc73cc0..500d82aecbe4 100644
--- a/include/uapi/drm/nouveau_drm.h
+++ b/include/uapi/drm/nouveau_drm.h
@@ -27,6 +27,8 @@
 
 #define DRM_NOUVEAU_EVENT_NVIF                                       0x80000000
 
+#include <drm/drm.h>
+
 #define NOUVEAU_GEM_DOMAIN_CPU       (1 << 0)
 #define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
 #define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
@@ -41,34 +43,34 @@
 #define NOUVEAU_GEM_TILE_NONCONTIG   0x00000008
 
 struct drm_nouveau_gem_info {
-        uint32_t handle;
-        uint32_t domain;
-        uint64_t size;
-        uint64_t offset;
-        uint64_t map_handle;
-        uint32_t tile_mode;
-        uint32_t tile_flags;
+        __u32 handle;
+        __u32 domain;
+        __u64 size;
+        __u64 offset;
+        __u64 map_handle;
+        __u32 tile_mode;
+        __u32 tile_flags;
 };
 
 struct drm_nouveau_gem_new {
         struct drm_nouveau_gem_info info;
-        uint32_t channel_hint;
-        uint32_t align;
+        __u32 channel_hint;
+        __u32 align;
 };
 
 #define NOUVEAU_GEM_MAX_BUFFERS 1024
 struct drm_nouveau_gem_pushbuf_bo_presumed {
-        uint32_t valid;
-        uint32_t domain;
-        uint64_t offset;
+        __u32 valid;
+        __u32 domain;
+        __u64 offset;
 };
 
 struct drm_nouveau_gem_pushbuf_bo {
-        uint64_t user_priv;
-        uint32_t handle;
-        uint32_t read_domains;
-        uint32_t write_domains;
-        uint32_t valid_domains;
+        __u64 user_priv;
+        __u32 handle;
+        __u32 read_domains;
+        __u32 write_domains;
+        __u32 valid_domains;
         struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
 };
 
@@ -77,46 +79,46 @@ struct drm_nouveau_gem_pushbuf_bo {
 #define NOUVEAU_GEM_RELOC_OR   (1 << 2)
 #define NOUVEAU_GEM_MAX_RELOCS 1024
 struct drm_nouveau_gem_pushbuf_reloc {
-        uint32_t reloc_bo_index;
-        uint32_t reloc_bo_offset;
-        uint32_t bo_index;
-        uint32_t flags;
-        uint32_t data;
-        uint32_t vor;
-        uint32_t tor;
+        __u32 reloc_bo_index;
+        __u32 reloc_bo_offset;
+        __u32 bo_index;
+        __u32 flags;
+        __u32 data;
+        __u32 vor;
+        __u32 tor;
 };
 
 #define NOUVEAU_GEM_MAX_PUSH 512
 struct drm_nouveau_gem_pushbuf_push {
-        uint32_t bo_index;
-        uint32_t pad;
-        uint64_t offset;
-        uint64_t length;
+        __u32 bo_index;
+        __u32 pad;
+        __u64 offset;
+        __u64 length;
 };
 
 struct drm_nouveau_gem_pushbuf {
-        uint32_t channel;
-        uint32_t nr_buffers;
-        uint64_t buffers;
-        uint32_t nr_relocs;
-        uint32_t nr_push;
-        uint64_t relocs;
-        uint64_t push;
-        uint32_t suffix0;
-        uint32_t suffix1;
-        uint64_t vram_available;
-        uint64_t gart_available;
+        __u32 channel;
+        __u32 nr_buffers;
+        __u64 buffers;
+        __u32 nr_relocs;
+        __u32 nr_push;
+        __u64 relocs;
+        __u64 push;
+        __u32 suffix0;
+        __u32 suffix1;
+        __u64 vram_available;
+        __u64 gart_available;
 };
 
 #define NOUVEAU_GEM_CPU_PREP_NOWAIT                                  0x00000001
 #define NOUVEAU_GEM_CPU_PREP_WRITE                                   0x00000004
 struct drm_nouveau_gem_cpu_prep {
-        uint32_t handle;
-        uint32_t flags;
+        __u32 handle;
+        __u32 flags;
 };
 
 struct drm_nouveau_gem_cpu_fini {
-        uint32_t handle;
+        __u32 handle;
 };
 
 #define DRM_NOUVEAU_GETPARAM           0x00 /* deprecated */
diff --git a/include/uapi/drm/omap_drm.h b/include/uapi/drm/omap_drm.h
index 1d0b1172664e..0750c01bb480 100644
--- a/include/uapi/drm/omap_drm.h
+++ b/include/uapi/drm/omap_drm.h
@@ -20,7 +20,7 @@
 #ifndef __OMAP_DRM_H__
 #define __OMAP_DRM_H__
 
-#include <drm/drm.h>
+#include "drm.h"
 
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints.
diff --git a/include/uapi/drm/qxl_drm.h b/include/uapi/drm/qxl_drm.h
index ebebd36c4117..4d1e32640463 100644
--- a/include/uapi/drm/qxl_drm.h
+++ b/include/uapi/drm/qxl_drm.h
@@ -24,13 +24,12 @@
 #ifndef QXL_DRM_H
 #define QXL_DRM_H
 
-#include <stddef.h>
-#include "drm/drm.h"
+#include "drm.h"
 
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints.
  *
- * Do not use pointers, use uint64_t instead for 32 bit / 64 bit user/kernel
+ * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
  * compatibility Keep fields aligned to their size
  */
 
@@ -48,14 +47,14 @@
 #define DRM_QXL_ALLOC_SURF  0x06
 
 struct drm_qxl_alloc {
-        uint32_t size;
-        uint32_t handle; /* 0 is an invalid handle */
+        __u32 size;
+        __u32 handle; /* 0 is an invalid handle */
 };
 
 struct drm_qxl_map {
-        uint64_t offset; /* use for mmap system call */
-        uint32_t handle;
-        uint32_t pad;
+        __u64 offset; /* use for mmap system call */
+        __u32 handle;
+        __u32 pad;
 };
 
 /*
@@ -68,59 +67,59 @@ struct drm_qxl_map {
 #define QXL_RELOC_TYPE_SURF 2
 
 struct drm_qxl_reloc {
-        uint64_t src_offset; /* offset into src_handle or src buffer */
-        uint64_t dst_offset; /* offset in dest handle */
-        uint32_t src_handle; /* dest handle to compute address from */
-        uint32_t dst_handle; /* 0 if to command buffer */
-        uint32_t reloc_type;
-        uint32_t pad;
+        __u64 src_offset; /* offset into src_handle or src buffer */
+        __u64 dst_offset; /* offset in dest handle */
+        __u32 src_handle; /* dest handle to compute address from */
+        __u32 dst_handle; /* 0 if to command buffer */
+        __u32 reloc_type;
+        __u32 pad;
 };
 
 struct drm_qxl_command {
-        uint64_t         __user command; /* void* */
-        uint64_t         __user relocs; /* struct drm_qxl_reloc* */
-        uint32_t                type;
-        uint32_t                command_size;
-        uint32_t                relocs_num;
-        uint32_t                pad;
+        __u64    __user command; /* void* */
+        __u64    __user relocs; /* struct drm_qxl_reloc* */
+        __u32           type;
+        __u32           command_size;
+        __u32           relocs_num;
+        __u32                pad;
 };
 
 /* XXX: call it drm_qxl_commands? */
 struct drm_qxl_execbuffer {
-        uint32_t                flags;          /* for future use */
-        uint32_t                commands_num;
-        uint64_t         __user commands;       /* struct drm_qxl_command* */
+        __u32           flags;          /* for future use */
+        __u32           commands_num;
+        __u64    __user commands;       /* struct drm_qxl_command* */
 };
 
 struct drm_qxl_update_area {
-        uint32_t handle;
-        uint32_t top;
-        uint32_t left;
-        uint32_t bottom;
-        uint32_t right;
-        uint32_t pad;
+        __u32 handle;
+        __u32 top;
+        __u32 left;
+        __u32 bottom;
+        __u32 right;
+        __u32 pad;
 };
 
 #define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */
 #define QXL_PARAM_MAX_RELOCS 2
 struct drm_qxl_getparam {
-        uint64_t param;
-        uint64_t value;
+        __u64 param;
+        __u64 value;
 };
 
 /* these are one bit values */
 struct drm_qxl_clientcap {
-        uint32_t index;
-        uint32_t pad;
+        __u32 index;
+        __u32 pad;
 };
 
 struct drm_qxl_alloc_surf {
-        uint32_t format;
-        uint32_t width;
-        uint32_t height;
-        int32_t stride;
-        uint32_t handle;
-        uint32_t pad;
+        __u32 format;
+        __u32 width;
+        __u32 height;
+        __s32 stride;
+        __u32 handle;
+        __u32 pad;
 };
 
 #define DRM_IOCTL_QXL_ALLOC \
diff --git a/include/uapi/drm/r128_drm.h b/include/uapi/drm/r128_drm.h
index 76b0aa3e8210..7a44c6500a7e 100644
--- a/include/uapi/drm/r128_drm.h
+++ b/include/uapi/drm/r128_drm.h
@@ -33,7 +33,7 @@
 #ifndef __R128_DRM_H__
 #define __R128_DRM_H__
 
-#include <drm/drm.h>
+#include "drm.h"
 
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the X server file (r128_sarea.h)
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index 01aa2a8e3f8d..ccb9bcd82685 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -793,9 +793,9 @@ typedef struct drm_radeon_surface_free {
 #define RADEON_GEM_DOMAIN_VRAM          0x4
 
 struct drm_radeon_gem_info {
-        uint64_t        gart_size;
-        uint64_t        vram_size;
-        uint64_t        vram_visible;
+        __u64   gart_size;
+        __u64   vram_size;
+        __u64   vram_visible;
 };
 
 #define RADEON_GEM_NO_BACKING_STORE     (1 << 0)
@@ -807,11 +807,11 @@ struct drm_radeon_gem_info {
 #define RADEON_GEM_NO_CPU_ACCESS        (1 << 4)
 
 struct drm_radeon_gem_create {
-        uint64_t        size;
-        uint64_t        alignment;
-        uint32_t        handle;
-        uint32_t        initial_domain;
-        uint32_t        flags;
+        __u64   size;
+        __u64   alignment;
+        __u32   handle;
+        __u32   initial_domain;
+        __u32   flags;
 };
 
 /*
@@ -825,10 +825,10 @@ struct drm_radeon_gem_create {
 #define RADEON_GEM_USERPTR_REGISTER     (1 << 3)
 
 struct drm_radeon_gem_userptr {
-        uint64_t                addr;
-        uint64_t                size;
-        uint32_t                flags;
-        uint32_t                handle;
+        __u64           addr;
+        __u64           size;
+        __u32           flags;
+        __u32           handle;
 };
 
 #define RADEON_TILING_MACRO                             0x1
@@ -850,72 +850,72 @@ struct drm_radeon_gem_userptr {
 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK        0xf
 
 struct drm_radeon_gem_set_tiling {
-        uint32_t        handle;
-        uint32_t        tiling_flags;
-        uint32_t        pitch;
+        __u32   handle;
+        __u32   tiling_flags;
+        __u32   pitch;
 };
 
 struct drm_radeon_gem_get_tiling {
-        uint32_t        handle;
-        uint32_t        tiling_flags;
-        uint32_t        pitch;
+        __u32   handle;
+        __u32   tiling_flags;
+        __u32   pitch;
 };
 
 struct drm_radeon_gem_mmap {
-        uint32_t        handle;
-        uint32_t        pad;
-        uint64_t        offset;
-        uint64_t        size;
-        uint64_t        addr_ptr;
+        __u32   handle;
+        __u32   pad;
+        __u64   offset;
+        __u64   size;
+        __u64   addr_ptr;
 };
 
 struct drm_radeon_gem_set_domain {
-        uint32_t        handle;
-        uint32_t        read_domains;
-        uint32_t        write_domain;
+        __u32   handle;
+        __u32   read_domains;
+        __u32   write_domain;
 };
 
 struct drm_radeon_gem_wait_idle {
-        uint32_t        handle;
-        uint32_t        pad;
+        __u32   handle;
+        __u32   pad;
 };
 
 struct drm_radeon_gem_busy {
-        uint32_t        handle;
-        uint32_t        domain;
+        __u32   handle;
+        __u32        domain;
 };
 
 struct drm_radeon_gem_pread {
         /** Handle for the object being read. */
-        uint32_t handle;
-        uint32_t pad;
+        __u32 handle;
+        __u32 pad;
         /** Offset into the object to read from */
-        uint64_t offset;
+        __u64 offset;
         /** Length of data to read */
-        uint64_t size;
+        __u64 size;
         /** Pointer to write the data into. */
         /* void *, but pointers are not 32/64 compatible */
-        uint64_t data_ptr;
+        __u64 data_ptr;
 };
 
 struct drm_radeon_gem_pwrite {
         /** Handle for the object being written to. */
-        uint32_t handle;
-        uint32_t pad;
+        __u32 handle;
+        __u32 pad;
         /** Offset into the object to write to */
-        uint64_t offset;
+        __u64 offset;
         /** Length of data to write */
-        uint64_t size;
+        __u64 size;
         /** Pointer to read the data from. */
         /* void *, but pointers are not 32/64 compatible */
-        uint64_t data_ptr;
+        __u64 data_ptr;
 };
 
 /* Sets or returns a value associated with a buffer. */
 struct drm_radeon_gem_op {
-        uint32_t        handle; /* buffer */
-        uint32_t        op;     /* RADEON_GEM_OP_* */
-        uint64_t        value;  /* input or return value */
+        __u32   handle; /* buffer */
+        __u32   op;     /* RADEON_GEM_OP_* */
+        __u64   value;  /* input or return value */
 };
 
 #define RADEON_GEM_OP_GET_INITIAL_DOMAIN        0
@@ -935,11 +935,11 @@ struct drm_radeon_gem_op {
 #define RADEON_VM_PAGE_SNOOPED          (1 << 4)
 
 struct drm_radeon_gem_va {
-        uint32_t                handle;
-        uint32_t                operation;
-        uint32_t                vm_id;
-        uint32_t                flags;
-        uint64_t                offset;
+        __u32           handle;
+        __u32           operation;
+        __u32           vm_id;
+        __u32           flags;
+        __u64           offset;
 };
 
 #define RADEON_CHUNK_ID_RELOCS  0x01
@@ -961,29 +961,29 @@ struct drm_radeon_gem_va {
 /* 0 = normal, + = higher priority, - = lower priority */
 
 struct drm_radeon_cs_chunk {
-        uint32_t                chunk_id;
-        uint32_t                length_dw;
-        uint64_t                chunk_data;
+        __u32           chunk_id;
+        __u32           length_dw;
+        __u64           chunk_data;
 };
 
 /* drm_radeon_cs_reloc.flags */
 #define RADEON_RELOC_PRIO_MASK          (0xf << 0)
 
 struct drm_radeon_cs_reloc {
-        uint32_t                handle;
-        uint32_t                read_domains;
-        uint32_t                write_domain;
-        uint32_t                flags;
+        __u32           handle;
+        __u32           read_domains;
+        __u32           write_domain;
+        __u32           flags;
 };
 
 struct drm_radeon_cs {
-        uint32_t                num_chunks;
-        uint32_t                cs_id;
-        /* this points to uint64_t * which point to cs chunks */
-        uint64_t                chunks;
+        __u32           num_chunks;
+        __u32           cs_id;
+        /* this points to __u64 * which point to cs chunks */
+        __u64           chunks;
         /* updates to the limits after this CS ioctl */
-        uint64_t                gart_limit;
-        uint64_t                vram_limit;
+        __u64           gart_limit;
+        __u64           vram_limit;
 };
 
 #define RADEON_INFO_DEVICE_ID           0x00
@@ -1042,9 +1042,9 @@ struct drm_radeon_cs {
 #define RADEON_INFO_GPU_RESET_COUNTER   0x26
 
 struct drm_radeon_info {
-        uint32_t                request;
-        uint32_t                pad;
-        uint64_t                value;
+        __u32           request;
+        __u32           pad;
+        __u64           value;
 };
 
 /* Those correspond to the tile index to use, this is to explicitly state
diff --git a/include/uapi/drm/savage_drm.h b/include/uapi/drm/savage_drm.h
index 9dc9dc1a7753..574147489c60 100644
--- a/include/uapi/drm/savage_drm.h
+++ b/include/uapi/drm/savage_drm.h
@@ -26,7 +26,7 @@
 #ifndef __SAVAGE_DRM_H__
 #define __SAVAGE_DRM_H__
 
-#include <drm/drm.h>
+#include "drm.h"
 
 #ifndef __SAVAGE_SAREA_DEFINES__
 #define __SAVAGE_SAREA_DEFINES__
diff --git a/include/uapi/drm/tegra_drm.h b/include/uapi/drm/tegra_drm.h
index 5391780c2b05..27d0b054aed0 100644
--- a/include/uapi/drm/tegra_drm.h
+++ b/include/uapi/drm/tegra_drm.h
@@ -23,7 +23,7 @@
 #ifndef _UAPI_TEGRA_DRM_H_
 #define _UAPI_TEGRA_DRM_H_
 
-#include <drm/drm.h>
+#include "drm.h"
 
 #define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
 #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
diff --git a/include/uapi/drm/via_drm.h b/include/uapi/drm/via_drm.h
index 45bc80c3714b..fa21ed185520 100644
--- a/include/uapi/drm/via_drm.h
+++ b/include/uapi/drm/via_drm.h
@@ -24,7 +24,7 @@
 #ifndef _VIA_DRM_H_
 #define _VIA_DRM_H_
 
-#include <drm/drm.h>
+#include "drm.h"
 
 /* WARNING: These defines must be the same as what the Xserver uses.
  * if you change them, you must change the defines in the Xserver.
@@ -33,9 +33,6 @@
 #ifndef _VIA_DEFINES_
 #define _VIA_DEFINES_
 
-#ifndef __KERNEL__
-#include "via_drmclient.h"
-#endif
 
 #define VIA_NR_SAREA_CLIPRECTS          8
 #define VIA_NR_XVMC_PORTS               10
diff --git a/include/uapi/drm/virtgpu_drm.h b/include/uapi/drm/virtgpu_drm.h
index fc9e2d6e5e2f..c74f1f90cb37 100644
--- a/include/uapi/drm/virtgpu_drm.h
+++ b/include/uapi/drm/virtgpu_drm.h
@@ -24,13 +24,12 @@
 #ifndef VIRTGPU_DRM_H
 #define VIRTGPU_DRM_H
 
-#include <stddef.h>
-#include "drm/drm.h"
+#include "drm.h"
 
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints.
  *
- * Do not use pointers, use uint64_t instead for 32 bit / 64 bit user/kernel
+ * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
  * compatibility Keep fields aligned to their size
  */
 
@@ -45,88 +44,88 @@
 #define DRM_VIRTGPU_GET_CAPS  0x09
 
 struct drm_virtgpu_map {
-        uint64_t offset; /* use for mmap system call */
-        uint32_t handle;
-        uint32_t pad;
+        __u64 offset; /* use for mmap system call */
+        __u32 handle;
+        __u32 pad;
 };
 
 struct drm_virtgpu_execbuffer {
-        uint32_t                flags;          /* for future use */
-        uint32_t size;
-        uint64_t command; /* void* */
-        uint64_t bo_handles;
-        uint32_t num_bo_handles;
-        uint32_t pad;
+        __u32           flags;          /* for future use */
+        __u32 size;
+        __u64 command; /* void* */
+        __u64 bo_handles;
+        __u32 num_bo_handles;
+        __u32 pad;
 };
 
 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
 
 struct drm_virtgpu_getparam {
-        uint64_t param;
-        uint64_t value;
+        __u64 param;
+        __u64 value;
 };
 
 /* NO_BO flags? NO resource flag? */
 /* resource flag for y_0_top */
 struct drm_virtgpu_resource_create {
-        uint32_t target;
-        uint32_t format;
-        uint32_t bind;
-        uint32_t width;
-        uint32_t height;
-        uint32_t depth;
-        uint32_t array_size;
-        uint32_t last_level;
-        uint32_t nr_samples;
-        uint32_t flags;
-        uint32_t bo_handle; /* if this is set - recreate a new resource attached to this bo ? */
-        uint32_t res_handle;  /* returned by kernel */
-        uint32_t size;        /* validate transfer in the host */
-        uint32_t stride;      /* validate transfer in the host */
+        __u32 target;
+        __u32 format;
+        __u32 bind;
+        __u32 width;
+        __u32 height;
+        __u32 depth;
+        __u32 array_size;
+        __u32 last_level;
+        __u32 nr_samples;
+        __u32 flags;
+        __u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */
+        __u32 res_handle;  /* returned by kernel */
+        __u32 size;        /* validate transfer in the host */
+        __u32 stride;      /* validate transfer in the host */
 };
 
 struct drm_virtgpu_resource_info {
-        uint32_t bo_handle;
-        uint32_t res_handle;
-        uint32_t size;
-        uint32_t stride;
+        __u32 bo_handle;
+        __u32 res_handle;
+        __u32 size;
+        __u32 stride;
 };
 
 struct drm_virtgpu_3d_box {
-        uint32_t x;
-        uint32_t y;
-        uint32_t z;
-        uint32_t w;
-        uint32_t h;
-        uint32_t d;
+        __u32 x;
+        __u32 y;
+        __u32 z;
+        __u32 w;
+        __u32 h;
+        __u32 d;
 };
 
 struct drm_virtgpu_3d_transfer_to_host {
-        uint32_t bo_handle;
+        __u32 bo_handle;
         struct drm_virtgpu_3d_box box;
-        uint32_t level;
-        uint32_t offset;
+        __u32 level;
+        __u32 offset;
 };
 
 struct drm_virtgpu_3d_transfer_from_host {
-        uint32_t bo_handle;
+        __u32 bo_handle;
         struct drm_virtgpu_3d_box box;
-        uint32_t level;
-        uint32_t offset;
+        __u32 level;
+        __u32 offset;
 };
 
 #define VIRTGPU_WAIT_NOWAIT 1 /* like it */
 struct drm_virtgpu_3d_wait {
-        uint32_t handle; /* 0 is an invalid handle */
-        uint32_t flags;
+        __u32 handle; /* 0 is an invalid handle */
+        __u32 flags;
 };
 
 struct drm_virtgpu_get_caps {
-        uint32_t cap_set_id;
-        uint32_t cap_set_ver;
-        uint64_t addr;
-        uint32_t size;
-        uint32_t pad;
+        __u32 cap_set_id;
+        __u32 cap_set_ver;
+        __u64 addr;
+        __u32 size;
+        __u32 pad;
 };
 
 #define DRM_IOCTL_VIRTGPU_MAP \
diff --git a/include/uapi/drm/vmwgfx_drm.h b/include/uapi/drm/vmwgfx_drm.h
index 05b204954d16..5b68b4d10884 100644
--- a/include/uapi/drm/vmwgfx_drm.h
+++ b/include/uapi/drm/vmwgfx_drm.h
@@ -28,9 +28,7 @@
 #ifndef __VMWGFX_DRM_H__
 #define __VMWGFX_DRM_H__
 
-#ifndef __KERNEL__
-#include <drm/drm.h>
-#endif
+#include "drm.h"
 
 #define DRM_VMW_MAX_SURFACE_FACES 6
 #define DRM_VMW_MAX_MIP_LEVELS 24
@@ -111,9 +109,9 @@ enum drm_vmw_handle_type {
  */
 
 struct drm_vmw_getparam_arg {
-        uint64_t value;
-        uint32_t param;
-        uint32_t pad64;
+        __u64 value;
+        __u32 param;
+        __u32 pad64;
 };
 
 /*************************************************************************/
@@ -134,8 +132,8 @@ struct drm_vmw_getparam_arg {
  */
 
 struct drm_vmw_context_arg {
-        int32_t cid;
-        uint32_t pad64;
+        __s32 cid;
+        __u32 pad64;
 };
 
 /*************************************************************************/
@@ -165,7 +163,7 @@ struct drm_vmw_context_arg {
  * @mip_levels: Number of mip levels for each face.
  * An unused face should have 0 encoded.
  * @size_addr: Address of a user-space array of sruct drm_vmw_size
- * cast to an uint64_t for 32-64 bit compatibility.
+ * cast to an __u64 for 32-64 bit compatibility.
  * The size of the array should equal the total number of mipmap levels.
  * @shareable: Boolean whether other clients (as identified by file descriptors)
  * may reference this surface.
@@ -177,12 +175,12 @@ struct drm_vmw_context_arg {
  */
 
 struct drm_vmw_surface_create_req {
-        uint32_t flags;
-        uint32_t format;
-        uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES];
-        uint64_t size_addr;
-        int32_t shareable;
-        int32_t scanout;
+        __u32 flags;
+        __u32 format;
+        __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES];
+        __u64 size_addr;
+        __s32 shareable;
+        __s32 scanout;
 };
 
 /**
@@ -197,7 +195,7 @@ struct drm_vmw_surface_create_req {
  */
 
 struct drm_vmw_surface_arg {
-        int32_t sid;
+        __s32 sid;
         enum drm_vmw_handle_type handle_type;
 };
 
@@ -213,10 +211,10 @@ struct drm_vmw_surface_arg {
  */
 
 struct drm_vmw_size {
-        uint32_t width;
-        uint32_t height;
-        uint32_t depth;
-        uint32_t pad64;
+        __u32 width;
+        __u32 height;
+        __u32 depth;
+        __u32 pad64;
 };
 
 /**
@@ -284,13 +282,13 @@ union drm_vmw_surface_reference_arg {
 /**
  * struct drm_vmw_execbuf_arg
  *
- * @commands: User-space address of a command buffer cast to an uint64_t.
+ * @commands: User-space address of a command buffer cast to an __u64.
  * @command-size: Size in bytes of the command buffer.
  * @throttle-us: Sleep until software is less than @throttle_us
  * microseconds ahead of hardware. The driver may round this value
  * to the nearest kernel tick.
  * @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an
- * uint64_t.
+ * __u64.
  * @version: Allows expanding the execbuf ioctl parameters without breaking
  * backwards compatibility, since user-space will always tell the kernel
  * which version it uses.
@@ -302,14 +300,14 @@ union drm_vmw_surface_reference_arg {
 #define DRM_VMW_EXECBUF_VERSION 2
 
 struct drm_vmw_execbuf_arg {
-        uint64_t commands;
-        uint32_t command_size;
-        uint32_t throttle_us;
-        uint64_t fence_rep;
-        uint32_t version;
-        uint32_t flags;
-        uint32_t context_handle;
-        uint32_t pad64;
+        __u64 commands;
+        __u32 command_size;
+        __u32 throttle_us;
+        __u64 fence_rep;
+        __u32 version;
+        __u32 flags;
+        __u32 context_handle;
+        __u32 pad64;
 };
 
 /**
@@ -338,12 +336,12 @@ struct drm_vmw_execbuf_arg {
  */
 
 struct drm_vmw_fence_rep {
-        uint32_t handle;
-        uint32_t mask;
-        uint32_t seqno;
-        uint32_t passed_seqno;
-        uint32_t pad64;
-        int32_t error;
+        __u32 handle;
+        __u32 mask;
+        __u32 seqno;
+        __u32 passed_seqno;
+        __u32 pad64;
+        __s32 error;
 };
 
 /*************************************************************************/
@@ -373,8 +371,8 @@ struct drm_vmw_fence_rep {
  */
 
 struct drm_vmw_alloc_dmabuf_req {
-        uint32_t size;
-        uint32_t pad64;
+        __u32 size;
+        __u32 pad64;
 };
 
 /**
@@ -391,11 +389,11 @@ struct drm_vmw_alloc_dmabuf_req {
  */
 
 struct drm_vmw_dmabuf_rep {
-        uint64_t map_handle;
-        uint32_t handle;
-        uint32_t cur_gmr_id;
-        uint32_t cur_gmr_offset;
-        uint32_t pad64;
+        __u64 map_handle;
+        __u32 handle;
+        __u32 cur_gmr_id;
+        __u32 cur_gmr_offset;
+        __u32 pad64;
 };
 
 /**
@@ -428,8 +426,8 @@ union drm_vmw_alloc_dmabuf_arg {
  */
 
 struct drm_vmw_unref_dmabuf_arg {
-        uint32_t handle;
-        uint32_t pad64;
+        __u32 handle;
+        __u32 pad64;
 };
 
 /*************************************************************************/
@@ -452,10 +450,10 @@ struct drm_vmw_unref_dmabuf_arg {
  */
 
 struct drm_vmw_rect {
-        int32_t x;
-        int32_t y;
-        uint32_t w;
-        uint32_t h;
+        __s32 x;
+        __s32 y;
+        __u32 w;
+        __u32 h;
 };
 
 /**
@@ -477,21 +475,21 @@ struct drm_vmw_rect {
  */
 
 struct drm_vmw_control_stream_arg {
-        uint32_t stream_id;
-        uint32_t enabled;
+        __u32 stream_id;
+        __u32 enabled;
 
-        uint32_t flags;
-        uint32_t color_key;
+        __u32 flags;
+        __u32 color_key;
 
-        uint32_t handle;
-        uint32_t offset;
-        int32_t format;
-        uint32_t size;
-        uint32_t width;
-        uint32_t height;
-        uint32_t pitch[3];
+        __u32 handle;
+        __u32 offset;
+        __s32 format;
+        __u32 size;
+        __u32 width;
+        __u32 height;
+        __u32 pitch[3];
 
-        uint32_t pad64;
+        __u32 pad64;
         struct drm_vmw_rect src;
         struct drm_vmw_rect dst;
 };
@@ -519,12 +517,12 @@ struct drm_vmw_control_stream_arg {
  */
 
 struct drm_vmw_cursor_bypass_arg {
-        uint32_t flags;
-        uint32_t crtc_id;
-        int32_t xpos;
-        int32_t ypos;
-        int32_t xhot;
-        int32_t yhot;
+        __u32 flags;
+        __u32 crtc_id;
+        __s32 xpos;
+        __s32 ypos;
+        __s32 xhot;
+        __s32 yhot;
 };
 
 /*************************************************************************/
@@ -542,8 +540,8 @@ struct drm_vmw_cursor_bypass_arg {
  */
 
 struct drm_vmw_stream_arg {
-        uint32_t stream_id;
-        uint32_t pad64;
+        __u32 stream_id;
+        __u32 pad64;
 };
 
 /*************************************************************************/
@@ -565,7 +563,7 @@ struct drm_vmw_stream_arg {
 /**
  * struct drm_vmw_get_3d_cap_arg
  *
- * @buffer: Pointer to a buffer for capability data, cast to an uint64_t
+ * @buffer: Pointer to a buffer for capability data, cast to an __u64
  * @size: Max size to copy
  *
  * Input argument to the DRM_VMW_GET_3D_CAP_IOCTL
@@ -573,9 +571,9 @@ struct drm_vmw_stream_arg {
  */
 
 struct drm_vmw_get_3d_cap_arg {
-        uint64_t buffer;
-        uint32_t max_size;
-        uint32_t pad64;
+        __u64 buffer;
+        __u32 max_size;
+        __u32 pad64;
 };
 
 /*************************************************************************/
@@ -624,14 +622,14 @@ struct drm_vmw_get_3d_cap_arg {
  */
 
 struct drm_vmw_fence_wait_arg {
-        uint32_t handle;
-        int32_t  cookie_valid;
-        uint64_t kernel_cookie;
-        uint64_t timeout_us;
-        int32_t lazy;
-        int32_t flags;
-        int32_t wait_options;
-        int32_t pad64;
+        __u32 handle;
+        __s32  cookie_valid;
+        __u64 kernel_cookie;
+        __u64 timeout_us;
+        __s32 lazy;
+        __s32 flags;
+        __s32 wait_options;
+        __s32 pad64;
 };
 
 /*************************************************************************/
@@ -655,12 +653,12 @@ struct drm_vmw_fence_wait_arg {
  */
 
 struct drm_vmw_fence_signaled_arg {
-         uint32_t handle;
-         uint32_t flags;
-         int32_t signaled;
-         uint32_t passed_seqno;
-         uint32_t signaled_flags;
-         uint32_t pad64;
+         __u32 handle;
+         __u32 flags;
+         __s32 signaled;
+         __u32 passed_seqno;
+         __u32 signaled_flags;
+         __u32 pad64;
 };
 
 /*************************************************************************/
@@ -681,8 +679,8 @@ struct drm_vmw_fence_signaled_arg {
  */
 
 struct drm_vmw_fence_arg {
-         uint32_t handle;
-         uint32_t pad64;
+         __u32 handle;
+         __u32 pad64;
 };
 
 
@@ -703,9 +701,9 @@ struct drm_vmw_fence_arg {
 
 struct drm_vmw_event_fence {
         struct drm_event base;
-        uint64_t user_data;
-        uint32_t tv_sec;
-        uint32_t tv_usec;
+        __u64 user_data;
+        __u32 tv_sec;
+        __u32 tv_usec;
 };
 
 /*
@@ -717,17 +715,17 @@ struct drm_vmw_event_fence {
 /**
  * struct drm_vmw_fence_event_arg
  *
- * @fence_rep: Pointer to fence_rep structure cast to uint64_t or 0 if
+ * @fence_rep: Pointer to fence_rep structure cast to __u64 or 0 if
  * the fence is not supposed to be referenced by user-space.
  * @user_info: Info to be delivered with the event.
  * @handle: Attach the event to this fence only.
  * @flags: A set of flags as defined above.
  */
 struct drm_vmw_fence_event_arg {
-        uint64_t fence_rep;
-        uint64_t user_data;
-        uint32_t handle;
-        uint32_t flags;
+        __u64 fence_rep;
+        __u64 user_data;
+        __u32 handle;
+        __u32 flags;
 };
 
 
@@ -747,7 +745,7 @@ struct drm_vmw_fence_event_arg {
  * @sid: Surface id to present from.
  * @dest_x: X placement coordinate for surface.
  * @dest_y: Y placement coordinate for surface.
- * @clips_ptr: Pointer to an array of clip rects cast to an uint64_t.
+ * @clips_ptr: Pointer to an array of clip rects cast to an __u64.
  * @num_clips: Number of cliprects given relative to the framebuffer origin,
  * in the same coordinate space as the frame buffer.
  * @pad64: Unused 64-bit padding.
@@ -756,13 +754,13 @@ struct drm_vmw_fence_event_arg {
  */
 
 struct drm_vmw_present_arg {
-        uint32_t fb_id;
-        uint32_t sid;
-        int32_t dest_x;
-        int32_t dest_y;
-        uint64_t clips_ptr;
-        uint32_t num_clips;
-        uint32_t pad64;
+        __u32 fb_id;
+        __u32 sid;
+        __s32 dest_x;
+        __s32 dest_y;
+        __u64 clips_ptr;
+        __u32 num_clips;
+        __u32 pad64;
 };
 
 
@@ -780,16 +778,16 @@ struct drm_vmw_present_arg {
  * struct drm_vmw_present_arg
  * @fb_id: fb_id to present / read back from.
  * @num_clips: Number of cliprects.
- * @clips_ptr: Pointer to an array of clip rects cast to an uint64_t.
- * @fence_rep: Pointer to a struct drm_vmw_fence_rep, cast to an uint64_t.
+ * @clips_ptr: Pointer to an array of clip rects cast to an __u64.
+ * @fence_rep: Pointer to a struct drm_vmw_fence_rep, cast to an __u64.
  * If this member is NULL, then the ioctl should not return a fence.
  */
 
 struct drm_vmw_present_readback_arg {
-         uint32_t fb_id;
-         uint32_t num_clips;
-         uint64_t clips_ptr;
-         uint64_t fence_rep;
+         __u32 fb_id;
+         __u32 num_clips;
+         __u64 clips_ptr;
+         __u64 fence_rep;
 };
 
 /*************************************************************************/
@@ -805,14 +803,14 @@ struct drm_vmw_present_readback_arg {
  * struct drm_vmw_update_layout_arg
  *
  * @num_outputs: number of active connectors
- * @rects: pointer to array of drm_vmw_rect cast to an uint64_t
+ * @rects: pointer to array of drm_vmw_rect cast to an __u64
  *
  * Input argument to the DRM_VMW_UPDATE_LAYOUT Ioctl.
  */
 struct drm_vmw_update_layout_arg {
-        uint32_t num_outputs;
-        uint32_t pad64;
-        uint64_t rects;
+        __u32 num_outputs;
+        __u32 pad64;
+        __u64 rects;
 };
 
 
@@ -849,10 +847,10 @@ enum drm_vmw_shader_type {
  */
 struct drm_vmw_shader_create_arg {
         enum drm_vmw_shader_type shader_type;
-        uint32_t size;
-        uint32_t buffer_handle;
-        uint32_t shader_handle;
-        uint64_t offset;
+        __u32 size;
+        __u32 buffer_handle;
+        __u32 shader_handle;
+        __u64 offset;
 };
 
 /*************************************************************************/
@@ -871,8 +869,8 @@ struct drm_vmw_shader_create_arg {
  * Input argument to the DRM_VMW_UNREF_SHADER ioctl.
  */
 struct drm_vmw_shader_arg {
-        uint32_t handle;
-        uint32_t pad64;
+        __u32 handle;
+        __u32 pad64;
 };
 
 /*************************************************************************/
@@ -918,14 +916,14 @@ enum drm_vmw_surface_flags {
  * Part of output argument for the DRM_VMW_GB_SURFACE_REF Ioctl.
  */
 struct drm_vmw_gb_surface_create_req {
-        uint32_t svga3d_flags;
-        uint32_t format;
-        uint32_t mip_levels;
+        __u32 svga3d_flags;
+        __u32 format;
+        __u32 mip_levels;
         enum drm_vmw_surface_flags drm_surface_flags;
-        uint32_t multisample_count;
-        uint32_t autogen_filter;
-        uint32_t buffer_handle;
-        uint32_t array_size;
+        __u32 multisample_count;
+        __u32 autogen_filter;
+        __u32 buffer_handle;
+        __u32 array_size;
         struct drm_vmw_size base_size;
 };
 
@@ -944,11 +942,11 @@ struct drm_vmw_gb_surface_create_req {
  * Output argument for the DRM_VMW_GB_SURFACE_CREATE ioctl.
  */
 struct drm_vmw_gb_surface_create_rep {
-        uint32_t handle;
-        uint32_t backup_size;
-        uint32_t buffer_handle;
-        uint32_t buffer_size;
-        uint64_t buffer_map_handle;
+        __u32 handle;
+        __u32 backup_size;
+        __u32 buffer_handle;
+        __u32 buffer_size;
+        __u64 buffer_map_handle;
 };
 
 /**
@@ -1061,8 +1059,8 @@ enum drm_vmw_synccpu_op {
 struct drm_vmw_synccpu_arg {
         enum drm_vmw_synccpu_op op;
         enum drm_vmw_synccpu_flags flags;
-        uint32_t handle;
-        uint32_t pad64;
+        __u32 handle;
+        __u32 pad64;
 };
 
 /*************************************************************************/
diff --git a/include/uapi/linux/agpgart.h b/include/uapi/linux/agpgart.h
index 4e828cf487bc..f5251045181a 100644
--- a/include/uapi/linux/agpgart.h
+++ b/include/uapi/linux/agpgart.h
@@ -52,6 +52,7 @@
 
 #ifndef __KERNEL__
 #include <linux/types.h>
+#include <stdlib.h>
 
 struct agp_version {
         __u16 major;
diff --git a/include/uapi/linux/virtio_gpu.h b/include/uapi/linux/virtio_gpu.h
index 7a63faa9065c..4b04ead26cd9 100644
--- a/include/uapi/linux/virtio_gpu.h
+++ b/include/uapi/linux/virtio_gpu.h
@@ -287,7 +287,7 @@ struct virtio_gpu_get_capset {
 /* VIRTIO_GPU_RESP_OK_CAPSET */
 struct virtio_gpu_resp_capset {
         struct virtio_gpu_ctrl_hdr hdr;
-        uint8_t capset_data[];
+        __u8 capset_data[];
 };
 
 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)