diff options
author | Vinod Koul <vinod.koul@intel.com> | 2016-10-02 23:46:03 -0400 |
---|---|---|
committer | Vinod Koul <vinod.koul@intel.com> | 2016-10-02 23:46:03 -0400 |
commit | 6619f035a64dd44c7238b7341c138a3975d59111 (patch) | |
tree | fce47632273afaa50960abb2c60a04bf63e44783 | |
parent | 02aa84860c29f3f5a57e959982c811df46a2736c (diff) | |
parent | 509cf0b8146c73e6f29bcf732d1af1b1aed5ec01 (diff) |
Merge branch 'topic/compile_test' into for-linus
-rw-r--r-- | drivers/dma/Kconfig | 38 | ||||
-rw-r--r-- | drivers/dma/coh901318.c | 20 | ||||
-rw-r--r-- | drivers/dma/coh901318_lli.c | 4 | ||||
-rw-r--r-- | drivers/dma/dma-jz4740.c | 2 | ||||
-rw-r--r-- | drivers/dma/dma-jz4780.c | 2 | ||||
-rw-r--r-- | drivers/dma/edma.c | 26 | ||||
-rw-r--r-- | drivers/dma/ep93xx_dma.c | 12 | ||||
-rw-r--r-- | drivers/dma/mmp_tdma.c | 2 | ||||
-rw-r--r-- | drivers/dma/s3c24xx-dma.c | 6 | ||||
-rw-r--r-- | drivers/dma/sa11x0-dma.c | 14 | ||||
-rw-r--r-- | drivers/dma/stm32-dma.c | 2 | ||||
-rw-r--r-- | drivers/dma/ti-dma-crossbar.c | 30 | ||||
-rw-r--r-- | include/linux/omap-dma.h | 19 | ||||
-rw-r--r-- | include/linux/platform_data/dma-mmp_tdma.h | 2 |
14 files changed, 100 insertions, 79 deletions
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 739f797b40d9..9e680ecf31d6 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig | |||
@@ -102,7 +102,7 @@ config AXI_DMAC | |||
102 | config COH901318 | 102 | config COH901318 |
103 | bool "ST-Ericsson COH901318 DMA support" | 103 | bool "ST-Ericsson COH901318 DMA support" |
104 | select DMA_ENGINE | 104 | select DMA_ENGINE |
105 | depends on ARCH_U300 | 105 | depends on ARCH_U300 || COMPILE_TEST |
106 | help | 106 | help |
107 | Enable support for ST-Ericsson COH 901 318 DMA. | 107 | Enable support for ST-Ericsson COH 901 318 DMA. |
108 | 108 | ||
@@ -114,13 +114,13 @@ config DMA_BCM2835 | |||
114 | 114 | ||
115 | config DMA_JZ4740 | 115 | config DMA_JZ4740 |
116 | tristate "JZ4740 DMA support" | 116 | tristate "JZ4740 DMA support" |
117 | depends on MACH_JZ4740 | 117 | depends on MACH_JZ4740 || COMPILE_TEST |
118 | select DMA_ENGINE | 118 | select DMA_ENGINE |
119 | select DMA_VIRTUAL_CHANNELS | 119 | select DMA_VIRTUAL_CHANNELS |
120 | 120 | ||
121 | config DMA_JZ4780 | 121 | config DMA_JZ4780 |
122 | tristate "JZ4780 DMA support" | 122 | tristate "JZ4780 DMA support" |
123 | depends on MACH_JZ4780 | 123 | depends on MACH_JZ4780 || COMPILE_TEST |
124 | select DMA_ENGINE | 124 | select DMA_ENGINE |
125 | select DMA_VIRTUAL_CHANNELS | 125 | select DMA_VIRTUAL_CHANNELS |
126 | help | 126 | help |
@@ -130,14 +130,14 @@ config DMA_JZ4780 | |||
130 | 130 | ||
131 | config DMA_OMAP | 131 | config DMA_OMAP |
132 | tristate "OMAP DMA support" | 132 | tristate "OMAP DMA support" |
133 | depends on ARCH_OMAP | 133 | depends on ARCH_OMAP || COMPILE_TEST |
134 | select DMA_ENGINE | 134 | select DMA_ENGINE |
135 | select DMA_VIRTUAL_CHANNELS | 135 | select DMA_VIRTUAL_CHANNELS |
136 | select TI_DMA_CROSSBAR if SOC_DRA7XX | 136 | select TI_DMA_CROSSBAR if (SOC_DRA7XX || COMPILE_TEST) |
137 | 137 | ||
138 | config DMA_SA11X0 | 138 | config DMA_SA11X0 |
139 | tristate "SA-11x0 DMA support" | 139 | tristate "SA-11x0 DMA support" |
140 | depends on ARCH_SA1100 | 140 | depends on ARCH_SA1100 || COMPILE_TEST |
141 | select DMA_ENGINE | 141 | select DMA_ENGINE |
142 | select DMA_VIRTUAL_CHANNELS | 142 | select DMA_VIRTUAL_CHANNELS |
143 | help | 143 | help |
@@ -150,7 +150,6 @@ config DMA_SUN4I | |||
150 | depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | 150 | depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
151 | default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) | 151 | default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) |
152 | select DMA_ENGINE | 152 | select DMA_ENGINE |
153 | select DMA_OF | ||
154 | select DMA_VIRTUAL_CHANNELS | 153 | select DMA_VIRTUAL_CHANNELS |
155 | help | 154 | help |
156 | Enable support for the DMA controller present in the sun4i, | 155 | Enable support for the DMA controller present in the sun4i, |
@@ -167,7 +166,7 @@ config DMA_SUN6I | |||
167 | 166 | ||
168 | config EP93XX_DMA | 167 | config EP93XX_DMA |
169 | bool "Cirrus Logic EP93xx DMA support" | 168 | bool "Cirrus Logic EP93xx DMA support" |
170 | depends on ARCH_EP93XX | 169 | depends on ARCH_EP93XX || COMPILE_TEST |
171 | select DMA_ENGINE | 170 | select DMA_ENGINE |
172 | help | 171 | help |
173 | Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller. | 172 | Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller. |
@@ -297,16 +296,16 @@ config LPC18XX_DMAMUX | |||
297 | 296 | ||
298 | config MMP_PDMA | 297 | config MMP_PDMA |
299 | bool "MMP PDMA support" | 298 | bool "MMP PDMA support" |
300 | depends on (ARCH_MMP || ARCH_PXA) | 299 | depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST |
301 | select DMA_ENGINE | 300 | select DMA_ENGINE |
302 | help | 301 | help |
303 | Support the MMP PDMA engine for PXA and MMP platform. | 302 | Support the MMP PDMA engine for PXA and MMP platform. |
304 | 303 | ||
305 | config MMP_TDMA | 304 | config MMP_TDMA |
306 | bool "MMP Two-Channel DMA support" | 305 | bool "MMP Two-Channel DMA support" |
307 | depends on ARCH_MMP | 306 | depends on ARCH_MMP || COMPILE_TEST |
308 | select DMA_ENGINE | 307 | select DMA_ENGINE |
309 | select MMP_SRAM | 308 | select MMP_SRAM if ARCH_MMP |
310 | help | 309 | help |
311 | Support the MMP Two-Channel DMA engine. | 310 | Support the MMP Two-Channel DMA engine. |
312 | This engine used for MMP Audio DMA and pxa910 SQU. | 311 | This engine used for MMP Audio DMA and pxa910 SQU. |
@@ -316,7 +315,6 @@ config MOXART_DMA | |||
316 | tristate "MOXART DMA support" | 315 | tristate "MOXART DMA support" |
317 | depends on ARCH_MOXART | 316 | depends on ARCH_MOXART |
318 | select DMA_ENGINE | 317 | select DMA_ENGINE |
319 | select DMA_OF | ||
320 | select DMA_VIRTUAL_CHANNELS | 318 | select DMA_VIRTUAL_CHANNELS |
321 | help | 319 | help |
322 | Enable support for the MOXA ART SoC DMA controller. | 320 | Enable support for the MOXA ART SoC DMA controller. |
@@ -439,9 +437,8 @@ config STE_DMA40 | |||
439 | 437 | ||
440 | config STM32_DMA | 438 | config STM32_DMA |
441 | bool "STMicroelectronics STM32 DMA support" | 439 | bool "STMicroelectronics STM32 DMA support" |
442 | depends on ARCH_STM32 | 440 | depends on ARCH_STM32 || COMPILE_TEST |
443 | select DMA_ENGINE | 441 | select DMA_ENGINE |
444 | select DMA_OF | ||
445 | select DMA_VIRTUAL_CHANNELS | 442 | select DMA_VIRTUAL_CHANNELS |
446 | help | 443 | help |
447 | Enable support for the on-chip DMA controller on STMicroelectronics | 444 | Enable support for the on-chip DMA controller on STMicroelectronics |
@@ -451,7 +448,7 @@ config STM32_DMA | |||
451 | 448 | ||
452 | config S3C24XX_DMAC | 449 | config S3C24XX_DMAC |
453 | bool "Samsung S3C24XX DMA support" | 450 | bool "Samsung S3C24XX DMA support" |
454 | depends on ARCH_S3C24XX | 451 | depends on ARCH_S3C24XX || COMPILE_TEST |
455 | select DMA_ENGINE | 452 | select DMA_ENGINE |
456 | select DMA_VIRTUAL_CHANNELS | 453 | select DMA_VIRTUAL_CHANNELS |
457 | help | 454 | help |
@@ -483,10 +480,9 @@ config TEGRA20_APB_DMA | |||
483 | 480 | ||
484 | config TEGRA210_ADMA | 481 | config TEGRA210_ADMA |
485 | bool "NVIDIA Tegra210 ADMA support" | 482 | bool "NVIDIA Tegra210 ADMA support" |
486 | depends on ARCH_TEGRA_210_SOC | 483 | depends on (ARCH_TEGRA_210_SOC || COMPILE_TEST) && PM_CLK |
487 | select DMA_ENGINE | 484 | select DMA_ENGINE |
488 | select DMA_VIRTUAL_CHANNELS | 485 | select DMA_VIRTUAL_CHANNELS |
489 | select PM_CLK | ||
490 | help | 486 | help |
491 | Support for the NVIDIA Tegra210 ADMA controller driver. The | 487 | Support for the NVIDIA Tegra210 ADMA controller driver. The |
492 | DMA controller has multiple DMA channels and is used to service | 488 | DMA controller has multiple DMA channels and is used to service |
@@ -497,7 +493,7 @@ config TEGRA210_ADMA | |||
497 | 493 | ||
498 | config TIMB_DMA | 494 | config TIMB_DMA |
499 | tristate "Timberdale FPGA DMA support" | 495 | tristate "Timberdale FPGA DMA support" |
500 | depends on MFD_TIMBERDALE | 496 | depends on MFD_TIMBERDALE || COMPILE_TEST |
501 | select DMA_ENGINE | 497 | select DMA_ENGINE |
502 | help | 498 | help |
503 | Enable support for the Timberdale FPGA DMA engine. | 499 | Enable support for the Timberdale FPGA DMA engine. |
@@ -515,10 +511,10 @@ config TI_DMA_CROSSBAR | |||
515 | 511 | ||
516 | config TI_EDMA | 512 | config TI_EDMA |
517 | bool "TI EDMA support" | 513 | bool "TI EDMA support" |
518 | depends on ARCH_DAVINCI || ARCH_OMAP || ARCH_KEYSTONE | 514 | depends on ARCH_DAVINCI || ARCH_OMAP || ARCH_KEYSTONE || COMPILE_TEST |
519 | select DMA_ENGINE | 515 | select DMA_ENGINE |
520 | select DMA_VIRTUAL_CHANNELS | 516 | select DMA_VIRTUAL_CHANNELS |
521 | select TI_DMA_CROSSBAR if ARCH_OMAP | 517 | select TI_DMA_CROSSBAR if (ARCH_OMAP || COMPILE_TEST) |
522 | default n | 518 | default n |
523 | help | 519 | help |
524 | Enable support for the TI EDMA controller. This DMA | 520 | Enable support for the TI EDMA controller. This DMA |
@@ -561,7 +557,7 @@ config XILINX_ZYNQMP_DMA | |||
561 | 557 | ||
562 | config ZX_DMA | 558 | config ZX_DMA |
563 | tristate "ZTE ZX296702 DMA support" | 559 | tristate "ZTE ZX296702 DMA support" |
564 | depends on ARCH_ZX | 560 | depends on ARCH_ZX || COMPILE_TEST |
565 | select DMA_ENGINE | 561 | select DMA_ENGINE |
566 | select DMA_VIRTUAL_CHANNELS | 562 | select DMA_VIRTUAL_CHANNELS |
567 | help | 563 | help |
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c index 5b1d4a39b30b..472be1d09586 100644 --- a/drivers/dma/coh901318.c +++ b/drivers/dma/coh901318.c | |||
@@ -1319,10 +1319,10 @@ static void coh901318_list_print(struct coh901318_chan *cohc, | |||
1319 | int i = 0; | 1319 | int i = 0; |
1320 | 1320 | ||
1321 | while (l) { | 1321 | while (l) { |
1322 | dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x" | 1322 | dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%pad" |
1323 | ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n", | 1323 | ", dst 0x%pad, link 0x%pad virt_link_addr 0x%p\n", |
1324 | i, l, l->control, l->src_addr, l->dst_addr, | 1324 | i, l, l->control, &l->src_addr, &l->dst_addr, |
1325 | l->link_addr, l->virt_link_addr); | 1325 | &l->link_addr, l->virt_link_addr); |
1326 | i++; | 1326 | i++; |
1327 | l = l->virt_link_addr; | 1327 | l = l->virt_link_addr; |
1328 | } | 1328 | } |
@@ -1335,7 +1335,7 @@ static void coh901318_list_print(struct coh901318_chan *cohc, | |||
1335 | static struct coh901318_base *debugfs_dma_base; | 1335 | static struct coh901318_base *debugfs_dma_base; |
1336 | static struct dentry *dma_dentry; | 1336 | static struct dentry *dma_dentry; |
1337 | 1337 | ||
1338 | static int coh901318_debugfs_read(struct file *file, char __user *buf, | 1338 | static ssize_t coh901318_debugfs_read(struct file *file, char __user *buf, |
1339 | size_t count, loff_t *f_pos) | 1339 | size_t count, loff_t *f_pos) |
1340 | { | 1340 | { |
1341 | u64 started_channels = debugfs_dma_base->pm.started_channels; | 1341 | u64 started_channels = debugfs_dma_base->pm.started_channels; |
@@ -1753,7 +1753,7 @@ static int coh901318_resume(struct dma_chan *chan) | |||
1753 | 1753 | ||
1754 | bool coh901318_filter_id(struct dma_chan *chan, void *chan_id) | 1754 | bool coh901318_filter_id(struct dma_chan *chan, void *chan_id) |
1755 | { | 1755 | { |
1756 | unsigned int ch_nr = (unsigned int) chan_id; | 1756 | unsigned long ch_nr = (unsigned long) chan_id; |
1757 | 1757 | ||
1758 | if (ch_nr == to_coh901318_chan(chan)->id) | 1758 | if (ch_nr == to_coh901318_chan(chan)->id) |
1759 | return true; | 1759 | return true; |
@@ -2234,8 +2234,8 @@ coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |||
2234 | spin_lock_irqsave(&cohc->lock, flg); | 2234 | spin_lock_irqsave(&cohc->lock, flg); |
2235 | 2235 | ||
2236 | dev_vdbg(COHC_2_DEV(cohc), | 2236 | dev_vdbg(COHC_2_DEV(cohc), |
2237 | "[%s] channel %d src 0x%x dest 0x%x size %d\n", | 2237 | "[%s] channel %d src 0x%pad dest 0x%pad size %zu\n", |
2238 | __func__, cohc->id, src, dest, size); | 2238 | __func__, cohc->id, &src, &dest, size); |
2239 | 2239 | ||
2240 | if (flags & DMA_PREP_INTERRUPT) | 2240 | if (flags & DMA_PREP_INTERRUPT) |
2241 | /* Trigger interrupt after last lli */ | 2241 | /* Trigger interrupt after last lli */ |
@@ -2731,8 +2731,8 @@ static int __init coh901318_probe(struct platform_device *pdev) | |||
2731 | goto err_register_of_dma; | 2731 | goto err_register_of_dma; |
2732 | 2732 | ||
2733 | platform_set_drvdata(pdev, base); | 2733 | platform_set_drvdata(pdev, base); |
2734 | dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n", | 2734 | dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%p\n", |
2735 | (u32) base->virtbase); | 2735 | base->virtbase); |
2736 | 2736 | ||
2737 | return err; | 2737 | return err; |
2738 | 2738 | ||
diff --git a/drivers/dma/coh901318_lli.c b/drivers/dma/coh901318_lli.c index 702112d547c8..d612b2e5abc4 100644 --- a/drivers/dma/coh901318_lli.c +++ b/drivers/dma/coh901318_lli.c | |||
@@ -75,7 +75,7 @@ coh901318_lli_alloc(struct coh901318_pool *pool, unsigned int len) | |||
75 | lli = head; | 75 | lli = head; |
76 | lli->phy_this = phy; | 76 | lli->phy_this = phy; |
77 | lli->link_addr = 0x00000000; | 77 | lli->link_addr = 0x00000000; |
78 | lli->virt_link_addr = 0x00000000U; | 78 | lli->virt_link_addr = NULL; |
79 | 79 | ||
80 | for (i = 1; i < len; i++) { | 80 | for (i = 1; i < len; i++) { |
81 | lli_prev = lli; | 81 | lli_prev = lli; |
@@ -88,7 +88,7 @@ coh901318_lli_alloc(struct coh901318_pool *pool, unsigned int len) | |||
88 | DEBUGFS_POOL_COUNTER_ADD(pool, 1); | 88 | DEBUGFS_POOL_COUNTER_ADD(pool, 1); |
89 | lli->phy_this = phy; | 89 | lli->phy_this = phy; |
90 | lli->link_addr = 0x00000000; | 90 | lli->link_addr = 0x00000000; |
91 | lli->virt_link_addr = 0x00000000U; | 91 | lli->virt_link_addr = NULL; |
92 | 92 | ||
93 | lli_prev->link_addr = phy; | 93 | lli_prev->link_addr = phy; |
94 | lli_prev->virt_link_addr = lli; | 94 | lli_prev->virt_link_addr = lli; |
diff --git a/drivers/dma/dma-jz4740.c b/drivers/dma/dma-jz4740.c index 9689b36c005a..d50273fed715 100644 --- a/drivers/dma/dma-jz4740.c +++ b/drivers/dma/dma-jz4740.c | |||
@@ -21,8 +21,6 @@ | |||
21 | #include <linux/irq.h> | 21 | #include <linux/irq.h> |
22 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
23 | 23 | ||
24 | #include <asm/mach-jz4740/dma.h> | ||
25 | |||
26 | #include "virt-dma.h" | 24 | #include "virt-dma.h" |
27 | 25 | ||
28 | #define JZ_DMA_NR_CHANS 6 | 26 | #define JZ_DMA_NR_CHANS 6 |
diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c index 27e93368b62c..7373b7a555ec 100644 --- a/drivers/dma/dma-jz4780.c +++ b/drivers/dma/dma-jz4780.c | |||
@@ -400,7 +400,7 @@ static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_cyclic( | |||
400 | return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags); | 400 | return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags); |
401 | } | 401 | } |
402 | 402 | ||
403 | struct dma_async_tx_descriptor *jz4780_dma_prep_dma_memcpy( | 403 | static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_memcpy( |
404 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | 404 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
405 | size_t len, unsigned long flags) | 405 | size_t len, unsigned long flags) |
406 | { | 406 | { |
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 9d5dff4a43fd..e18a58068bca 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c | |||
@@ -263,22 +263,29 @@ static const struct edmacc_param dummy_paramset = { | |||
263 | 263 | ||
264 | #define EDMA_BINDING_LEGACY 0 | 264 | #define EDMA_BINDING_LEGACY 0 |
265 | #define EDMA_BINDING_TPCC 1 | 265 | #define EDMA_BINDING_TPCC 1 |
266 | static const u32 edma_binding_type[] = { | ||
267 | [EDMA_BINDING_LEGACY] = EDMA_BINDING_LEGACY, | ||
268 | [EDMA_BINDING_TPCC] = EDMA_BINDING_TPCC, | ||
269 | }; | ||
270 | |||
266 | static const struct of_device_id edma_of_ids[] = { | 271 | static const struct of_device_id edma_of_ids[] = { |
267 | { | 272 | { |
268 | .compatible = "ti,edma3", | 273 | .compatible = "ti,edma3", |
269 | .data = (void *)EDMA_BINDING_LEGACY, | 274 | .data = &edma_binding_type[EDMA_BINDING_LEGACY], |
270 | }, | 275 | }, |
271 | { | 276 | { |
272 | .compatible = "ti,edma3-tpcc", | 277 | .compatible = "ti,edma3-tpcc", |
273 | .data = (void *)EDMA_BINDING_TPCC, | 278 | .data = &edma_binding_type[EDMA_BINDING_TPCC], |
274 | }, | 279 | }, |
275 | {} | 280 | {} |
276 | }; | 281 | }; |
282 | MODULE_DEVICE_TABLE(of, edma_of_ids); | ||
277 | 283 | ||
278 | static const struct of_device_id edma_tptc_of_ids[] = { | 284 | static const struct of_device_id edma_tptc_of_ids[] = { |
279 | { .compatible = "ti,edma3-tptc", }, | 285 | { .compatible = "ti,edma3-tptc", }, |
280 | {} | 286 | {} |
281 | }; | 287 | }; |
288 | MODULE_DEVICE_TABLE(of, edma_tptc_of_ids); | ||
282 | 289 | ||
283 | static inline unsigned int edma_read(struct edma_cc *ecc, int offset) | 290 | static inline unsigned int edma_read(struct edma_cc *ecc, int offset) |
284 | { | 291 | { |
@@ -405,18 +412,12 @@ static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no, | |||
405 | edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or); | 412 | edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or); |
406 | } | 413 | } |
407 | 414 | ||
408 | static inline void set_bits(int offset, int len, unsigned long *p) | 415 | static inline void edma_set_bits(int offset, int len, unsigned long *p) |
409 | { | 416 | { |
410 | for (; len > 0; len--) | 417 | for (; len > 0; len--) |
411 | set_bit(offset + (len - 1), p); | 418 | set_bit(offset + (len - 1), p); |
412 | } | 419 | } |
413 | 420 | ||
414 | static inline void clear_bits(int offset, int len, unsigned long *p) | ||
415 | { | ||
416 | for (; len > 0; len--) | ||
417 | clear_bit(offset + (len - 1), p); | ||
418 | } | ||
419 | |||
420 | static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, | 421 | static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, |
421 | int priority) | 422 | int priority) |
422 | { | 423 | { |
@@ -2023,8 +2024,7 @@ static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, | |||
2023 | { | 2024 | { |
2024 | struct edma_soc_info *info; | 2025 | struct edma_soc_info *info; |
2025 | struct property *prop; | 2026 | struct property *prop; |
2026 | size_t sz; | 2027 | int sz, ret; |
2027 | int ret; | ||
2028 | 2028 | ||
2029 | info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL); | 2029 | info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL); |
2030 | if (!info) | 2030 | if (!info) |
@@ -2186,7 +2186,7 @@ static int edma_probe(struct platform_device *pdev) | |||
2186 | const struct of_device_id *match; | 2186 | const struct of_device_id *match; |
2187 | 2187 | ||
2188 | match = of_match_node(edma_of_ids, node); | 2188 | match = of_match_node(edma_of_ids, node); |
2189 | if (match && (u32)match->data == EDMA_BINDING_TPCC) | 2189 | if (match && (*(u32 *)match->data) == EDMA_BINDING_TPCC) |
2190 | legacy_mode = false; | 2190 | legacy_mode = false; |
2191 | 2191 | ||
2192 | info = edma_setup_info_from_dt(dev, legacy_mode); | 2192 | info = edma_setup_info_from_dt(dev, legacy_mode); |
@@ -2264,7 +2264,7 @@ static int edma_probe(struct platform_device *pdev) | |||
2264 | for (i = 0; rsv_slots[i][0] != -1; i++) { | 2264 | for (i = 0; rsv_slots[i][0] != -1; i++) { |
2265 | off = rsv_slots[i][0]; | 2265 | off = rsv_slots[i][0]; |
2266 | ln = rsv_slots[i][1]; | 2266 | ln = rsv_slots[i][1]; |
2267 | set_bits(off, ln, ecc->slot_inuse); | 2267 | edma_set_bits(off, ln, ecc->slot_inuse); |
2268 | } | 2268 | } |
2269 | } | 2269 | } |
2270 | } | 2270 | } |
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c index 2ffaca25267e..ca17e8751af2 100644 --- a/drivers/dma/ep93xx_dma.c +++ b/drivers/dma/ep93xx_dma.c | |||
@@ -1045,11 +1045,11 @@ ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |||
1045 | 1045 | ||
1046 | first = NULL; | 1046 | first = NULL; |
1047 | for_each_sg(sgl, sg, sg_len, i) { | 1047 | for_each_sg(sgl, sg, sg_len, i) { |
1048 | size_t sg_len = sg_dma_len(sg); | 1048 | size_t len = sg_dma_len(sg); |
1049 | 1049 | ||
1050 | if (sg_len > DMA_MAX_CHAN_BYTES) { | 1050 | if (len > DMA_MAX_CHAN_BYTES) { |
1051 | dev_warn(chan2dev(edmac), "too big transfer size %d\n", | 1051 | dev_warn(chan2dev(edmac), "too big transfer size %zu\n", |
1052 | sg_len); | 1052 | len); |
1053 | goto fail; | 1053 | goto fail; |
1054 | } | 1054 | } |
1055 | 1055 | ||
@@ -1066,7 +1066,7 @@ ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |||
1066 | desc->src_addr = edmac->runtime_addr; | 1066 | desc->src_addr = edmac->runtime_addr; |
1067 | desc->dst_addr = sg_dma_address(sg); | 1067 | desc->dst_addr = sg_dma_address(sg); |
1068 | } | 1068 | } |
1069 | desc->size = sg_len; | 1069 | desc->size = len; |
1070 | 1070 | ||
1071 | if (!first) | 1071 | if (!first) |
1072 | first = desc; | 1072 | first = desc; |
@@ -1123,7 +1123,7 @@ ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, | |||
1123 | } | 1123 | } |
1124 | 1124 | ||
1125 | if (period_len > DMA_MAX_CHAN_BYTES) { | 1125 | if (period_len > DMA_MAX_CHAN_BYTES) { |
1126 | dev_warn(chan2dev(edmac), "too big period length %d\n", | 1126 | dev_warn(chan2dev(edmac), "too big period length %zu\n", |
1127 | period_len); | 1127 | period_len); |
1128 | return NULL; | 1128 | return NULL; |
1129 | } | 1129 | } |
diff --git a/drivers/dma/mmp_tdma.c b/drivers/dma/mmp_tdma.c index b3441f57a364..d7422b1bf406 100644 --- a/drivers/dma/mmp_tdma.c +++ b/drivers/dma/mmp_tdma.c | |||
@@ -433,7 +433,7 @@ static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic( | |||
433 | 433 | ||
434 | if (period_len > TDMA_MAX_XFER_BYTES) { | 434 | if (period_len > TDMA_MAX_XFER_BYTES) { |
435 | dev_err(tdmac->dev, | 435 | dev_err(tdmac->dev, |
436 | "maximum period size exceeded: %d > %d\n", | 436 | "maximum period size exceeded: %zu > %d\n", |
437 | period_len, TDMA_MAX_XFER_BYTES); | 437 | period_len, TDMA_MAX_XFER_BYTES); |
438 | goto err_out; | 438 | goto err_out; |
439 | } | 439 | } |
diff --git a/drivers/dma/s3c24xx-dma.c b/drivers/dma/s3c24xx-dma.c index d5c85e7d2061..3c579abbabb7 100644 --- a/drivers/dma/s3c24xx-dma.c +++ b/drivers/dma/s3c24xx-dma.c | |||
@@ -823,11 +823,11 @@ static struct dma_async_tx_descriptor *s3c24xx_dma_prep_memcpy( | |||
823 | struct s3c24xx_sg *dsg; | 823 | struct s3c24xx_sg *dsg; |
824 | int src_mod, dest_mod; | 824 | int src_mod, dest_mod; |
825 | 825 | ||
826 | dev_dbg(&s3cdma->pdev->dev, "prepare memcpy of %d bytes from %s\n", | 826 | dev_dbg(&s3cdma->pdev->dev, "prepare memcpy of %zu bytes from %s\n", |
827 | len, s3cchan->name); | 827 | len, s3cchan->name); |
828 | 828 | ||
829 | if ((len & S3C24XX_DCON_TC_MASK) != len) { | 829 | if ((len & S3C24XX_DCON_TC_MASK) != len) { |
830 | dev_err(&s3cdma->pdev->dev, "memcpy size %d to large\n", len); | 830 | dev_err(&s3cdma->pdev->dev, "memcpy size %zu to large\n", len); |
831 | return NULL; | 831 | return NULL; |
832 | } | 832 | } |
833 | 833 | ||
@@ -1421,7 +1421,7 @@ bool s3c24xx_dma_filter(struct dma_chan *chan, void *param) | |||
1421 | 1421 | ||
1422 | s3cchan = to_s3c24xx_dma_chan(chan); | 1422 | s3cchan = to_s3c24xx_dma_chan(chan); |
1423 | 1423 | ||
1424 | return s3cchan->id == (int)param; | 1424 | return s3cchan->id == (uintptr_t)param; |
1425 | } | 1425 | } |
1426 | EXPORT_SYMBOL(s3c24xx_dma_filter); | 1426 | EXPORT_SYMBOL(s3c24xx_dma_filter); |
1427 | 1427 | ||
diff --git a/drivers/dma/sa11x0-dma.c b/drivers/dma/sa11x0-dma.c index 43db255050d2..1adeb3265085 100644 --- a/drivers/dma/sa11x0-dma.c +++ b/drivers/dma/sa11x0-dma.c | |||
@@ -463,7 +463,7 @@ static enum dma_status sa11x0_dma_tx_status(struct dma_chan *chan, | |||
463 | dma_addr_t addr = sa11x0_dma_pos(p); | 463 | dma_addr_t addr = sa11x0_dma_pos(p); |
464 | unsigned i; | 464 | unsigned i; |
465 | 465 | ||
466 | dev_vdbg(d->slave.dev, "tx_status: addr:%x\n", addr); | 466 | dev_vdbg(d->slave.dev, "tx_status: addr:%pad\n", &addr); |
467 | 467 | ||
468 | for (i = 0; i < txd->sglen; i++) { | 468 | for (i = 0; i < txd->sglen; i++) { |
469 | dev_vdbg(d->slave.dev, "tx_status: [%u] %x+%x\n", | 469 | dev_vdbg(d->slave.dev, "tx_status: [%u] %x+%x\n", |
@@ -491,7 +491,7 @@ static enum dma_status sa11x0_dma_tx_status(struct dma_chan *chan, | |||
491 | } | 491 | } |
492 | spin_unlock_irqrestore(&c->vc.lock, flags); | 492 | spin_unlock_irqrestore(&c->vc.lock, flags); |
493 | 493 | ||
494 | dev_vdbg(d->slave.dev, "tx_status: bytes 0x%zx\n", state->residue); | 494 | dev_vdbg(d->slave.dev, "tx_status: bytes 0x%x\n", state->residue); |
495 | 495 | ||
496 | return ret; | 496 | return ret; |
497 | } | 497 | } |
@@ -551,8 +551,8 @@ static struct dma_async_tx_descriptor *sa11x0_dma_prep_slave_sg( | |||
551 | if (len > DMA_MAX_SIZE) | 551 | if (len > DMA_MAX_SIZE) |
552 | j += DIV_ROUND_UP(len, DMA_MAX_SIZE & ~DMA_ALIGN) - 1; | 552 | j += DIV_ROUND_UP(len, DMA_MAX_SIZE & ~DMA_ALIGN) - 1; |
553 | if (addr & DMA_ALIGN) { | 553 | if (addr & DMA_ALIGN) { |
554 | dev_dbg(chan->device->dev, "vchan %p: bad buffer alignment: %08x\n", | 554 | dev_dbg(chan->device->dev, "vchan %p: bad buffer alignment: %pad\n", |
555 | &c->vc, addr); | 555 | &c->vc, &addr); |
556 | return NULL; | 556 | return NULL; |
557 | } | 557 | } |
558 | } | 558 | } |
@@ -599,7 +599,7 @@ static struct dma_async_tx_descriptor *sa11x0_dma_prep_slave_sg( | |||
599 | txd->size = size; | 599 | txd->size = size; |
600 | txd->sglen = j; | 600 | txd->sglen = j; |
601 | 601 | ||
602 | dev_dbg(chan->device->dev, "vchan %p: txd %p: size %u nr %u\n", | 602 | dev_dbg(chan->device->dev, "vchan %p: txd %p: size %zu nr %u\n", |
603 | &c->vc, &txd->vd, txd->size, txd->sglen); | 603 | &c->vc, &txd->vd, txd->size, txd->sglen); |
604 | 604 | ||
605 | return vchan_tx_prep(&c->vc, &txd->vd, flags); | 605 | return vchan_tx_prep(&c->vc, &txd->vd, flags); |
@@ -693,8 +693,8 @@ static int sa11x0_dma_device_config(struct dma_chan *chan, | |||
693 | if (maxburst == 8) | 693 | if (maxburst == 8) |
694 | ddar |= DDAR_BS; | 694 | ddar |= DDAR_BS; |
695 | 695 | ||
696 | dev_dbg(c->vc.chan.device->dev, "vchan %p: dma_slave_config addr %x width %u burst %u\n", | 696 | dev_dbg(c->vc.chan.device->dev, "vchan %p: dma_slave_config addr %pad width %u burst %u\n", |
697 | &c->vc, addr, width, maxburst); | 697 | &c->vc, &addr, width, maxburst); |
698 | 698 | ||
699 | c->ddar = ddar | (addr & 0xf0000000) | (addr & 0x003ffffc) << 6; | 699 | c->ddar = ddar | (addr & 0xf0000000) | (addr & 0x003ffffc) << 6; |
700 | 700 | ||
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c index 047476a1383d..307547f4848d 100644 --- a/drivers/dma/stm32-dma.c +++ b/drivers/dma/stm32-dma.c | |||
@@ -954,7 +954,7 @@ static void stm32_dma_desc_free(struct virt_dma_desc *vdesc) | |||
954 | kfree(container_of(vdesc, struct stm32_dma_desc, vdesc)); | 954 | kfree(container_of(vdesc, struct stm32_dma_desc, vdesc)); |
955 | } | 955 | } |
956 | 956 | ||
957 | void stm32_dma_set_config(struct stm32_dma_chan *chan, | 957 | static void stm32_dma_set_config(struct stm32_dma_chan *chan, |
958 | struct stm32_dma_cfg *cfg) | 958 | struct stm32_dma_cfg *cfg) |
959 | { | 959 | { |
960 | stm32_dma_clear_reg(&chan->chan_reg); | 960 | stm32_dma_clear_reg(&chan->chan_reg); |
diff --git a/drivers/dma/ti-dma-crossbar.c b/drivers/dma/ti-dma-crossbar.c index 5ae294b256a7..3f24aeb48c0e 100644 --- a/drivers/dma/ti-dma-crossbar.c +++ b/drivers/dma/ti-dma-crossbar.c | |||
@@ -18,15 +18,19 @@ | |||
18 | 18 | ||
19 | #define TI_XBAR_DRA7 0 | 19 | #define TI_XBAR_DRA7 0 |
20 | #define TI_XBAR_AM335X 1 | 20 | #define TI_XBAR_AM335X 1 |
21 | static const u32 ti_xbar_type[] = { | ||
22 | [TI_XBAR_DRA7] = TI_XBAR_DRA7, | ||
23 | [TI_XBAR_AM335X] = TI_XBAR_AM335X, | ||
24 | }; | ||
21 | 25 | ||
22 | static const struct of_device_id ti_dma_xbar_match[] = { | 26 | static const struct of_device_id ti_dma_xbar_match[] = { |
23 | { | 27 | { |
24 | .compatible = "ti,dra7-dma-crossbar", | 28 | .compatible = "ti,dra7-dma-crossbar", |
25 | .data = (void *)TI_XBAR_DRA7, | 29 | .data = &ti_xbar_type[TI_XBAR_DRA7], |
26 | }, | 30 | }, |
27 | { | 31 | { |
28 | .compatible = "ti,am335x-edma-crossbar", | 32 | .compatible = "ti,am335x-edma-crossbar", |
29 | .data = (void *)TI_XBAR_AM335X, | 33 | .data = &ti_xbar_type[TI_XBAR_AM335X], |
30 | }, | 34 | }, |
31 | {}, | 35 | {}, |
32 | }; | 36 | }; |
@@ -190,9 +194,6 @@ static int ti_am335x_xbar_probe(struct platform_device *pdev) | |||
190 | #define TI_DRA7_XBAR_OUTPUTS 127 | 194 | #define TI_DRA7_XBAR_OUTPUTS 127 |
191 | #define TI_DRA7_XBAR_INPUTS 256 | 195 | #define TI_DRA7_XBAR_INPUTS 256 |
192 | 196 | ||
193 | #define TI_XBAR_EDMA_OFFSET 0 | ||
194 | #define TI_XBAR_SDMA_OFFSET 1 | ||
195 | |||
196 | struct ti_dra7_xbar_data { | 197 | struct ti_dra7_xbar_data { |
197 | void __iomem *iomem; | 198 | void __iomem *iomem; |
198 | 199 | ||
@@ -280,18 +281,25 @@ static void *ti_dra7_xbar_route_allocate(struct of_phandle_args *dma_spec, | |||
280 | return map; | 281 | return map; |
281 | } | 282 | } |
282 | 283 | ||
284 | #define TI_XBAR_EDMA_OFFSET 0 | ||
285 | #define TI_XBAR_SDMA_OFFSET 1 | ||
286 | static const u32 ti_dma_offset[] = { | ||
287 | [TI_XBAR_EDMA_OFFSET] = 0, | ||
288 | [TI_XBAR_SDMA_OFFSET] = 1, | ||
289 | }; | ||
290 | |||
283 | static const struct of_device_id ti_dra7_master_match[] = { | 291 | static const struct of_device_id ti_dra7_master_match[] = { |
284 | { | 292 | { |
285 | .compatible = "ti,omap4430-sdma", | 293 | .compatible = "ti,omap4430-sdma", |
286 | .data = (void *)TI_XBAR_SDMA_OFFSET, | 294 | .data = &ti_dma_offset[TI_XBAR_SDMA_OFFSET], |
287 | }, | 295 | }, |
288 | { | 296 | { |
289 | .compatible = "ti,edma3", | 297 | .compatible = "ti,edma3", |
290 | .data = (void *)TI_XBAR_EDMA_OFFSET, | 298 | .data = &ti_dma_offset[TI_XBAR_EDMA_OFFSET], |
291 | }, | 299 | }, |
292 | { | 300 | { |
293 | .compatible = "ti,edma3-tpcc", | 301 | .compatible = "ti,edma3-tpcc", |
294 | .data = (void *)TI_XBAR_EDMA_OFFSET, | 302 | .data = &ti_dma_offset[TI_XBAR_EDMA_OFFSET], |
295 | }, | 303 | }, |
296 | {}, | 304 | {}, |
297 | }; | 305 | }; |
@@ -311,7 +319,7 @@ static int ti_dra7_xbar_probe(struct platform_device *pdev) | |||
311 | struct property *prop; | 319 | struct property *prop; |
312 | struct resource *res; | 320 | struct resource *res; |
313 | u32 safe_val; | 321 | u32 safe_val; |
314 | size_t sz; | 322 | int sz; |
315 | void __iomem *iomem; | 323 | void __iomem *iomem; |
316 | int i, ret; | 324 | int i, ret; |
317 | 325 | ||
@@ -395,7 +403,7 @@ static int ti_dra7_xbar_probe(struct platform_device *pdev) | |||
395 | 403 | ||
396 | xbar->dmarouter.dev = &pdev->dev; | 404 | xbar->dmarouter.dev = &pdev->dev; |
397 | xbar->dmarouter.route_free = ti_dra7_xbar_free; | 405 | xbar->dmarouter.route_free = ti_dra7_xbar_free; |
398 | xbar->dma_offset = (u32)match->data; | 406 | xbar->dma_offset = *(u32 *)match->data; |
399 | 407 | ||
400 | mutex_init(&xbar->mutex); | 408 | mutex_init(&xbar->mutex); |
401 | platform_set_drvdata(pdev, xbar); | 409 | platform_set_drvdata(pdev, xbar); |
@@ -428,7 +436,7 @@ static int ti_dma_xbar_probe(struct platform_device *pdev) | |||
428 | if (unlikely(!match)) | 436 | if (unlikely(!match)) |
429 | return -EINVAL; | 437 | return -EINVAL; |
430 | 438 | ||
431 | switch ((u32)match->data) { | 439 | switch (*(u32 *)match->data) { |
432 | case TI_XBAR_DRA7: | 440 | case TI_XBAR_DRA7: |
433 | ret = ti_dra7_xbar_probe(pdev); | 441 | ret = ti_dra7_xbar_probe(pdev); |
434 | break; | 442 | break; |
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h index 1d99b61adc65..290081620b3e 100644 --- a/include/linux/omap-dma.h +++ b/include/linux/omap-dma.h | |||
@@ -297,6 +297,7 @@ struct omap_system_dma_plat_info { | |||
297 | #define dma_omap15xx() __dma_omap15xx(d) | 297 | #define dma_omap15xx() __dma_omap15xx(d) |
298 | #define dma_omap16xx() __dma_omap16xx(d) | 298 | #define dma_omap16xx() __dma_omap16xx(d) |
299 | 299 | ||
300 | #if defined(CONFIG_ARCH_OMAP) | ||
300 | extern struct omap_system_dma_plat_info *omap_get_plat_info(void); | 301 | extern struct omap_system_dma_plat_info *omap_get_plat_info(void); |
301 | 302 | ||
302 | extern void omap_set_dma_priority(int lch, int dst_port, int priority); | 303 | extern void omap_set_dma_priority(int lch, int dst_port, int priority); |
@@ -355,4 +356,22 @@ static inline int omap_lcd_dma_running(void) | |||
355 | } | 356 | } |
356 | #endif | 357 | #endif |
357 | 358 | ||
359 | #else /* CONFIG_ARCH_OMAP */ | ||
360 | |||
361 | static inline struct omap_system_dma_plat_info *omap_get_plat_info(void) | ||
362 | { | ||
363 | return NULL; | ||
364 | } | ||
365 | |||
366 | static inline int omap_request_dma(int dev_id, const char *dev_name, | ||
367 | void (*callback)(int lch, u16 ch_status, void *data), | ||
368 | void *data, int *dma_ch) | ||
369 | { | ||
370 | return -ENODEV; | ||
371 | } | ||
372 | |||
373 | static inline void omap_free_dma(int ch) { } | ||
374 | |||
375 | #endif /* CONFIG_ARCH_OMAP */ | ||
376 | |||
358 | #endif /* __LINUX_OMAP_DMA_H */ | 377 | #endif /* __LINUX_OMAP_DMA_H */ |
diff --git a/include/linux/platform_data/dma-mmp_tdma.h b/include/linux/platform_data/dma-mmp_tdma.h index 0c72886030ef..422d4504dbac 100644 --- a/include/linux/platform_data/dma-mmp_tdma.h +++ b/include/linux/platform_data/dma-mmp_tdma.h | |||
@@ -28,7 +28,7 @@ struct sram_platdata { | |||
28 | int granularity; | 28 | int granularity; |
29 | }; | 29 | }; |
30 | 30 | ||
31 | #ifdef CONFIG_ARM | 31 | #ifdef CONFIG_MMP_SRAM |
32 | extern struct gen_pool *sram_get_gpool(char *pool_name); | 32 | extern struct gen_pool *sram_get_gpool(char *pool_name); |
33 | #else | 33 | #else |
34 | static inline struct gen_pool *sram_get_gpool(char *pool_name) | 34 | static inline struct gen_pool *sram_get_gpool(char *pool_name) |