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authorAlexandre Belloni <alexandre.belloni@free-electrons.com>2017-01-31 12:12:57 -0500
committerAlexandre Belloni <alexandre.belloni@free-electrons.com>2017-03-31 14:36:05 -0400
commit65cc1a59d192be1df33633d3fe668a1e3e0edc36 (patch)
tree0d9b421633860e02720fde8bc6db10e4ef10e7ae
parent9e07c3ce2c1054af503b0cb5860df0f8c8ee2619 (diff)
ARM: at91: pm: Use struct at91_pm_data in pm_suspend.S
The number of register we can safely pass to at91_pm_suspend_in_sram is limited. Instead, pass the address to the at91_pm_data structure. The offsets are automatically generated to avoid hardcoding them. Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
-rw-r--r--arch/arm/mach-at91/Makefile33
-rw-r--r--arch/arm/mach-at91/pm.c78
-rw-r--r--arch/arm/mach-at91/pm.h16
-rw-r--r--arch/arm/mach-at91/pm_data-offsets.c13
-rw-r--r--arch/arm/mach-at91/pm_suspend.S29
5 files changed, 102 insertions, 67 deletions
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c5bbf8bb8c0f..858ef14f961c 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -18,3 +18,36 @@ endif
18ifeq ($(CONFIG_PM_DEBUG),y) 18ifeq ($(CONFIG_PM_DEBUG),y)
19CFLAGS_pm.o += -DDEBUG 19CFLAGS_pm.o += -DDEBUG
20endif 20endif
21
22# Default sed regexp - multiline due to syntax constraints
23define sed-y
24 "/^->/{s:->#\(.*\):/* \1 */:; \
25 s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \
26 s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
27 s:->::; p;}"
28endef
29
30# Use filechk to avoid rebuilds when a header changes, but the resulting file
31# does not
32define filechk_offsets
33 (set -e; \
34 echo "#ifndef $2"; \
35 echo "#define $2"; \
36 echo "/*"; \
37 echo " * DO NOT MODIFY."; \
38 echo " *"; \
39 echo " * This file was generated by Kbuild"; \
40 echo " */"; \
41 echo ""; \
42 sed -ne $(sed-y); \
43 echo ""; \
44 echo "#endif" )
45endef
46
47arch/arm/mach-at91/pm_data-offsets.s: arch/arm/mach-at91/pm_data-offsets.c
48 $(call if_changed_dep,cc_s_c)
49
50include/generated/at91_pm_data-offsets.h: arch/arm/mach-at91/pm_data-offsets.s FORCE
51 $(call filechk,offsets,__PM_DATA_OFFSETS_H__)
52
53arch/arm/mach-at91/pm_suspend.o: include/generated/at91_pm_data-offsets.h
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index c780dda3b604..a35b1541b328 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -37,18 +37,13 @@ extern void at91_pinctrl_gpio_suspend(void);
37extern void at91_pinctrl_gpio_resume(void); 37extern void at91_pinctrl_gpio_resume(void);
38#endif 38#endif
39 39
40static struct { 40static struct at91_pm_data pm_data;
41 void __iomem *pmc;
42 void __iomem *ramc[2];
43 unsigned long uhp_udp_mask;
44 int memctrl;
45} at91_pm_data;
46 41
47#define at91_ramc_read(id, field) \ 42#define at91_ramc_read(id, field) \
48 __raw_readl(at91_pm_data.ramc[id] + field) 43 __raw_readl(pm_data.ramc[id] + field)
49 44
50#define at91_ramc_write(id, field, value) \ 45#define at91_ramc_write(id, field, value) \
51 __raw_writel(value, at91_pm_data.ramc[id] + field) 46 __raw_writel(value, pm_data.ramc[id] + field)
52 47
53static int at91_pm_valid_state(suspend_state_t state) 48static int at91_pm_valid_state(suspend_state_t state)
54{ 49{
@@ -84,10 +79,10 @@ static int at91_pm_verify_clocks(void)
84 unsigned long scsr; 79 unsigned long scsr;
85 int i; 80 int i;
86 81
87 scsr = readl(at91_pm_data.pmc + AT91_PMC_SCSR); 82 scsr = readl(pm_data.pmc + AT91_PMC_SCSR);
88 83
89 /* USB must not be using PLLB */ 84 /* USB must not be using PLLB */
90 if ((scsr & at91_pm_data.uhp_udp_mask) != 0) { 85 if ((scsr & pm_data.uhp_udp_mask) != 0) {
91 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); 86 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
92 return 0; 87 return 0;
93 } 88 }
@@ -98,7 +93,7 @@ static int at91_pm_verify_clocks(void)
98 93
99 if ((scsr & (AT91_PMC_PCK0 << i)) == 0) 94 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
100 continue; 95 continue;
101 css = readl(at91_pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; 96 css = readl(pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
102 if (css != AT91_PMC_CSS_SLOW) { 97 if (css != AT91_PMC_CSS_SLOW) {
103 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); 98 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
104 return 0; 99 return 0;
@@ -124,25 +119,18 @@ int at91_suspend_entering_slow_clock(void)
124} 119}
125EXPORT_SYMBOL(at91_suspend_entering_slow_clock); 120EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
126 121
127static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0, 122static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
128 void __iomem *ramc1, int memctrl); 123extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
129
130extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
131 void __iomem *ramc1, int memctrl);
132extern u32 at91_pm_suspend_in_sram_sz; 124extern u32 at91_pm_suspend_in_sram_sz;
133 125
134static void at91_pm_suspend(suspend_state_t state) 126static void at91_pm_suspend(suspend_state_t state)
135{ 127{
136 unsigned int pm_data = at91_pm_data.memctrl; 128 pm_data.mode = (state == PM_SUSPEND_MEM) ? AT91_PM_SLOW_CLOCK : 0;
137
138 pm_data |= (state == PM_SUSPEND_MEM) ?
139 AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
140 129
141 flush_cache_all(); 130 flush_cache_all();
142 outer_disable(); 131 outer_disable();
143 132
144 at91_suspend_sram_fn(at91_pm_data.pmc, at91_pm_data.ramc[0], 133 at91_suspend_sram_fn(&pm_data);
145 at91_pm_data.ramc[1], pm_data);
146 134
147 outer_resume(); 135 outer_resume();
148} 136}
@@ -245,7 +233,7 @@ static void at91rm9200_standby(void)
245 " mcr p15, 0, %0, c7, c0, 4\n\t" 233 " mcr p15, 0, %0, c7, c0, 4\n\t"
246 " str %5, [%1, %2]" 234 " str %5, [%1, %2]"
247 : 235 :
248 : "r" (0), "r" (at91_pm_data.ramc[0]), "r" (AT91_MC_SDRAMC_LPR), 236 : "r" (0), "r" (pm_data.ramc[0]), "r" (AT91_MC_SDRAMC_LPR),
249 "r" (1), "r" (AT91_MC_SDRAMC_SRR), 237 "r" (1), "r" (AT91_MC_SDRAMC_SRR),
250 "r" (lpr)); 238 "r" (lpr));
251} 239}
@@ -260,7 +248,7 @@ static void at91_ddr_standby(void)
260 u32 lpr0, lpr1 = 0; 248 u32 lpr0, lpr1 = 0;
261 u32 saved_lpr0, saved_lpr1 = 0; 249 u32 saved_lpr0, saved_lpr1 = 0;
262 250
263 if (at91_pm_data.ramc[1]) { 251 if (pm_data.ramc[1]) {
264 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); 252 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
265 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; 253 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
266 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; 254 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
@@ -272,13 +260,13 @@ static void at91_ddr_standby(void)
272 260
273 /* self-refresh mode now */ 261 /* self-refresh mode now */
274 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); 262 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
275 if (at91_pm_data.ramc[1]) 263 if (pm_data.ramc[1])
276 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); 264 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
277 265
278 cpu_do_idle(); 266 cpu_do_idle();
279 267
280 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); 268 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
281 if (at91_pm_data.ramc[1]) 269 if (pm_data.ramc[1])
282 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); 270 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
283} 271}
284 272
@@ -306,7 +294,7 @@ static void at91sam9_sdram_standby(void)
306 u32 lpr0, lpr1 = 0; 294 u32 lpr0, lpr1 = 0;
307 u32 saved_lpr0, saved_lpr1 = 0; 295 u32 saved_lpr0, saved_lpr1 = 0;
308 296
309 if (at91_pm_data.ramc[1]) { 297 if (pm_data.ramc[1]) {
310 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); 298 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
311 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; 299 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
312 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; 300 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
@@ -318,13 +306,13 @@ static void at91sam9_sdram_standby(void)
318 306
319 /* self-refresh mode now */ 307 /* self-refresh mode now */
320 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); 308 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
321 if (at91_pm_data.ramc[1]) 309 if (pm_data.ramc[1])
322 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); 310 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
323 311
324 cpu_do_idle(); 312 cpu_do_idle();
325 313
326 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); 314 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
327 if (at91_pm_data.ramc[1]) 315 if (pm_data.ramc[1])
328 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); 316 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
329} 317}
330 318
@@ -344,8 +332,8 @@ static __init void at91_dt_ramc(void)
344 const void *standby = NULL; 332 const void *standby = NULL;
345 333
346 for_each_matching_node_and_match(np, ramc_ids, &of_id) { 334 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
347 at91_pm_data.ramc[idx] = of_iomap(np, 0); 335 pm_data.ramc[idx] = of_iomap(np, 0);
348 if (!at91_pm_data.ramc[idx]) 336 if (!pm_data.ramc[idx])
349 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx); 337 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
350 338
351 if (!standby) 339 if (!standby)
@@ -371,12 +359,12 @@ static void at91rm9200_idle(void)
371 * Disable the processor clock. The processor will be automatically 359 * Disable the processor clock. The processor will be automatically
372 * re-enabled by an interrupt or by a reset. 360 * re-enabled by an interrupt or by a reset.
373 */ 361 */
374 writel(AT91_PMC_PCK, at91_pm_data.pmc + AT91_PMC_SCDR); 362 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
375} 363}
376 364
377static void at91sam9_idle(void) 365static void at91sam9_idle(void)
378{ 366{
379 writel(AT91_PMC_PCK, at91_pm_data.pmc + AT91_PMC_SCDR); 367 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
380 cpu_do_idle(); 368 cpu_do_idle();
381} 369}
382 370
@@ -445,8 +433,8 @@ static void __init at91_pm_init(void (*pm_idle)(void))
445 platform_device_register(&at91_cpuidle_device); 433 platform_device_register(&at91_cpuidle_device);
446 434
447 pmc_np = of_find_matching_node(NULL, atmel_pmc_ids); 435 pmc_np = of_find_matching_node(NULL, atmel_pmc_ids);
448 at91_pm_data.pmc = of_iomap(pmc_np, 0); 436 pm_data.pmc = of_iomap(pmc_np, 0);
449 if (!at91_pm_data.pmc) { 437 if (!pm_data.pmc) {
450 pr_err("AT91: PM not supported, PMC not found\n"); 438 pr_err("AT91: PM not supported, PMC not found\n");
451 return; 439 return;
452 } 440 }
@@ -471,8 +459,8 @@ void __init at91rm9200_pm_init(void)
471 */ 459 */
472 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); 460 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
473 461
474 at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP; 462 pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
475 at91_pm_data.memctrl = AT91_MEMCTRL_MC; 463 pm_data.memctrl = AT91_MEMCTRL_MC;
476 464
477 at91_pm_init(at91rm9200_idle); 465 at91_pm_init(at91rm9200_idle);
478} 466}
@@ -480,31 +468,31 @@ void __init at91rm9200_pm_init(void)
480void __init at91sam9260_pm_init(void) 468void __init at91sam9260_pm_init(void)
481{ 469{
482 at91_dt_ramc(); 470 at91_dt_ramc();
483 at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC; 471 pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
484 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; 472 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
485 at91_pm_init(at91sam9_idle); 473 at91_pm_init(at91sam9_idle);
486} 474}
487 475
488void __init at91sam9g45_pm_init(void) 476void __init at91sam9g45_pm_init(void)
489{ 477{
490 at91_dt_ramc(); 478 at91_dt_ramc();
491 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP; 479 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
492 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; 480 pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
493 at91_pm_init(at91sam9_idle); 481 at91_pm_init(at91sam9_idle);
494} 482}
495 483
496void __init at91sam9x5_pm_init(void) 484void __init at91sam9x5_pm_init(void)
497{ 485{
498 at91_dt_ramc(); 486 at91_dt_ramc();
499 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; 487 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
500 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; 488 pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
501 at91_pm_init(at91sam9_idle); 489 at91_pm_init(at91sam9_idle);
502} 490}
503 491
504void __init sama5_pm_init(void) 492void __init sama5_pm_init(void)
505{ 493{
506 at91_dt_ramc(); 494 at91_dt_ramc();
507 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; 495 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
508 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; 496 pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
509 at91_pm_init(NULL); 497 at91_pm_init(NULL);
510} 498}
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 8eed156ef19a..fc0f7d048187 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -21,12 +21,16 @@
21#define AT91_MEMCTRL_SDRAMC 1 21#define AT91_MEMCTRL_SDRAMC 1
22#define AT91_MEMCTRL_DDRSDR 2 22#define AT91_MEMCTRL_DDRSDR 2
23 23
24#define AT91_PM_MEMTYPE_MASK 0x0f
25
26#define AT91_PM_MODE_OFFSET 4
27#define AT91_PM_MODE_MASK 0x01
28#define AT91_PM_MODE(x) (((x) & AT91_PM_MODE_MASK) << AT91_PM_MODE_OFFSET)
29
30#define AT91_PM_SLOW_CLOCK 0x01 24#define AT91_PM_SLOW_CLOCK 0x01
31 25
26#ifndef __ASSEMBLY__
27struct at91_pm_data {
28 void __iomem *pmc;
29 void __iomem *ramc[2];
30 unsigned long uhp_udp_mask;
31 unsigned int memctrl;
32 unsigned int mode;
33};
34#endif
35
32#endif 36#endif
diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_data-offsets.c
new file mode 100644
index 000000000000..30302cb16df0
--- /dev/null
+++ b/arch/arm/mach-at91/pm_data-offsets.c
@@ -0,0 +1,13 @@
1#include <linux/stddef.h>
2#include <linux/kbuild.h>
3#include "pm.h"
4
5int main(void)
6{
7 DEFINE(PM_DATA_PMC, offsetof(struct at91_pm_data, pmc));
8 DEFINE(PM_DATA_RAMC0, offsetof(struct at91_pm_data, ramc[0]));
9 DEFINE(PM_DATA_RAMC1, offsetof(struct at91_pm_data, ramc[1]));
10 DEFINE(PM_DATA_MEMCTRL, offsetof(struct at91_pm_data, memctrl));
11 DEFINE(PM_DATA_MODE, offsetof(struct at91_pm_data, mode));
12 return 0;
13}
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index a25defda3d22..ed317657e760 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -14,6 +14,7 @@
14#include <linux/linkage.h> 14#include <linux/linkage.h>
15#include <linux/clk/at91_pmc.h> 15#include <linux/clk/at91_pmc.h>
16#include "pm.h" 16#include "pm.h"
17#include "generated/at91_pm_data-offsets.h"
17 18
18#define SRAMC_SELF_FRESH_ACTIVE 0x01 19#define SRAMC_SELF_FRESH_ACTIVE 0x01
19#define SRAMC_SELF_FRESH_EXIT 0x00 20#define SRAMC_SELF_FRESH_EXIT 0x00
@@ -72,13 +73,9 @@ tmp2 .req r5
72 .arm 73 .arm
73 74
74/* 75/*
75 * void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *sdramc, 76 * void at91_suspend_sram_fn(struct at91_pm_data*)
76 * void __iomem *ramc1, int memctrl)
77 * @input param: 77 * @input param:
78 * @r0: base address of AT91_PMC 78 * @r0: base address of struct at91_pm_data
79 * @r1: base address of SDRAM Controller (SDRAM, DDRSDR, or AT91_SYS)
80 * @r2: base address of second SDRAM Controller or 0 if not present
81 * @r3: pm information
82 */ 79 */
83/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */ 80/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
84 .align 3 81 .align 3
@@ -90,16 +87,16 @@ ENTRY(at91_pm_suspend_in_sram)
90 mov tmp1, #0 87 mov tmp1, #0
91 mcr p15, 0, tmp1, c7, c10, 4 88 mcr p15, 0, tmp1, c7, c10, 4
92 89
93 str r0, .pmc_base 90 ldr tmp1, [r0, #PM_DATA_PMC]
94 str r1, .sramc_base 91 str tmp1, .pmc_base
95 str r2, .sramc1_base 92 ldr tmp1, [r0, #PM_DATA_RAMC0]
96 93 str tmp1, .sramc_base
97 and r0, r3, #AT91_PM_MEMTYPE_MASK 94 ldr tmp1, [r0, #PM_DATA_RAMC1]
98 str r0, .memtype 95 str tmp1, .sramc1_base
99 96 ldr tmp1, [r0, #PM_DATA_MEMCTRL]
100 lsr r0, r3, #AT91_PM_MODE_OFFSET 97 str tmp1, .memtype
101 and r0, r0, #AT91_PM_MODE_MASK 98 ldr tmp1, [r0, #PM_DATA_MODE]
102 str r0, .pm_mode 99 str tmp1, .pm_mode
103 100
104 /* Active the self-refresh mode */ 101 /* Active the self-refresh mode */
105 mov r0, #SRAMC_SELF_FRESH_ACTIVE 102 mov r0, #SRAMC_SELF_FRESH_ACTIVE