diff options
| author | Jagan Teki <jagan@amarulasolutions.com> | 2018-09-04 00:40:43 -0400 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-09-05 03:15:26 -0400 |
| commit | 65b1e8a6ca5f5305962daee6af730bd2d210bb0b (patch) | |
| tree | 5d2f79e5796f7690919aa212e013094195db6dfd | |
| parent | c2ff8383cc33c2d9c169e4daf1e37a434c3bb420 (diff) | |
clk: sunxi-ng: a64: Add minimal rate for video PLLs
According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.
Because of that, set minimal rate to both A64 video PLLs to 192 MHz.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 46 |
1 files changed, 24 insertions, 22 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index ee9c12cf3f08..d0e30192f0cf 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c | |||
| @@ -64,17 +64,18 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", | |||
| 64 | BIT(28), /* lock */ | 64 | BIT(28), /* lock */ |
| 65 | CLK_SET_RATE_UNGATE); | 65 | CLK_SET_RATE_UNGATE); |
| 66 | 66 | ||
| 67 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", | 67 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0", |
| 68 | "osc24M", 0x010, | 68 | "osc24M", 0x010, |
| 69 | 8, 7, /* N */ | 69 | 192000000, /* Minimum rate */ |
| 70 | 0, 4, /* M */ | 70 | 8, 7, /* N */ |
| 71 | BIT(24), /* frac enable */ | 71 | 0, 4, /* M */ |
| 72 | BIT(25), /* frac select */ | 72 | BIT(24), /* frac enable */ |
| 73 | 270000000, /* frac rate 0 */ | 73 | BIT(25), /* frac select */ |
| 74 | 297000000, /* frac rate 1 */ | 74 | 270000000, /* frac rate 0 */ |
| 75 | BIT(31), /* gate */ | 75 | 297000000, /* frac rate 1 */ |
| 76 | BIT(28), /* lock */ | 76 | BIT(31), /* gate */ |
| 77 | CLK_SET_RATE_UNGATE); | 77 | BIT(28), /* lock */ |
| 78 | CLK_SET_RATE_UNGATE); | ||
| 78 | 79 | ||
| 79 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", | 80 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", |
| 80 | "osc24M", 0x018, | 81 | "osc24M", 0x018, |
| @@ -125,17 +126,18 @@ static struct ccu_nk pll_periph1_clk = { | |||
| 125 | }, | 126 | }, |
| 126 | }; | 127 | }; |
| 127 | 128 | ||
| 128 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1", | 129 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1", |
| 129 | "osc24M", 0x030, | 130 | "osc24M", 0x030, |
| 130 | 8, 7, /* N */ | 131 | 192000000, /* Minimum rate */ |
| 131 | 0, 4, /* M */ | 132 | 8, 7, /* N */ |
| 132 | BIT(24), /* frac enable */ | 133 | 0, 4, /* M */ |
| 133 | BIT(25), /* frac select */ | 134 | BIT(24), /* frac enable */ |
| 134 | 270000000, /* frac rate 0 */ | 135 | BIT(25), /* frac select */ |
| 135 | 297000000, /* frac rate 1 */ | 136 | 270000000, /* frac rate 0 */ |
| 136 | BIT(31), /* gate */ | 137 | 297000000, /* frac rate 1 */ |
| 137 | BIT(28), /* lock */ | 138 | BIT(31), /* gate */ |
| 138 | CLK_SET_RATE_UNGATE); | 139 | BIT(28), /* lock */ |
| 140 | CLK_SET_RATE_UNGATE); | ||
| 139 | 141 | ||
| 140 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", | 142 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", |
| 141 | "osc24M", 0x038, | 143 | "osc24M", 0x038, |