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authorMagnus Damm <damm+renesas@opensource.se>2016-06-28 10:10:42 -0400
committerSimon Horman <horms+renesas@verge.net.au>2016-06-29 08:30:30 -0400
commit65b133cd79cfde9f4e0157deb0e0f88f92811ad3 (patch)
treeb235aa92a978fbc9a3cdbb537bfaa16c96e3c413
parent477cbcbd8f089ab72721a90760bc5d7987d3a713 (diff)
ARM: dts: r8a7793: Add APMU node and second CPU core
Add DT nodes for the Advanced Power Management Unit (APMU) and the second CPU core. Use the enable-method to point out that the APMU should be used for SMP support. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm/boot/dts/r8a7793.dtsi15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 9b55c1c6ee31..8d02aacf2892 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -35,6 +35,7 @@
35 cpus { 35 cpus {
36 #address-cells = <1>; 36 #address-cells = <1>;
37 #size-cells = <0>; 37 #size-cells = <0>;
38 enable-method = "renesas,apmu";
38 39
39 cpu0: cpu@0 { 40 cpu0: cpu@0 {
40 device_type = "cpu"; 41 device_type = "cpu";
@@ -56,6 +57,14 @@
56 next-level-cache = <&L2_CA15>; 57 next-level-cache = <&L2_CA15>;
57 }; 58 };
58 59
60 cpu1: cpu@1 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a15";
63 reg = <1>;
64 clock-frequency = <1500000000>;
65 power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
66 };
67
59 L2_CA15: cache-controller@0 { 68 L2_CA15: cache-controller@0 {
60 compatible = "cache"; 69 compatible = "cache";
61 reg = <0>; 70 reg = <0>;
@@ -65,6 +74,12 @@
65 }; 74 };
66 }; 75 };
67 76
77 apmu@e6152000 {
78 compatible = "renesas,r8a7793-apmu", "renesas,apmu";
79 reg = <0 0xe6152000 0 0x188>;
80 cpus = <&cpu0 &cpu1>;
81 };
82
68 thermal-zones { 83 thermal-zones {
69 cpu_thermal: cpu-thermal { 84 cpu_thermal: cpu-thermal {
70 polling-delay-passive = <0>; 85 polling-delay-passive = <0>;