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authorOlof Johansson <olof@lixom.net>2015-10-26 01:27:33 -0400
committerOlof Johansson <olof@lixom.net>2015-10-26 01:27:33 -0400
commit64ebda3acd6ea592e6f97dcd0682e87aa7cf8d61 (patch)
tree04ab95e8bcb5046f08f96912d4af5a7d7987f003
parent5f76048695eea2233b75d95161fa6170d83807ce (diff)
parent121432c7a02f3818eefcad88c9ec428b7139b84a (diff)
Merge tag 'arm/soc/for-4.4/rpi-dt-v2' of https://github.com/Broadcom/stblinux into next/dt
This pull request contains the DT changes for BCM2835 in 4.4. It pulls in clk/clk-bcm2835 (which Stephen Boyd has said would be stable) because the DT changes to enable the clock driver need the driver itself to be present. These changes include the following: - Eric Anholt, moves the bcm2835 clock driver under bcm/ where it belongs with other Broadcom clock providers drivers, defines the binding for new clock driver, adds support for programming the BCM2835 audio domain, adds the DDC I2C controller to Device Tree, and finally migrates the Device Tree to use the new clock driver binding - Lubomir Rintel adds support for the Raspberry Pi Model A+ and B revision 2, and remove the I2S controller which is non-existent on Raspberry Pi Model B - Stefan Wahren adds an uart0 label for referencing the UART adapter * tag 'arm/soc/for-4.4/rpi-dt-v2' of https://github.com/Broadcom/stblinux: ARM: bcm2835: Add the DDC I2C controller to the device tree. ARM: bcm2835: Switch to using the new clock driver support. ARM: bcm2835: dt: Add Raspberry Pi Model A+ ARM: bcm2835: dt: Add Raspberry Pi Model B rev2 ARM: bcm2835: dt: Raspberry Pi Model B had no I2S ARM: bcm2835: add label for uart0 clk: bcm2835: Add support for programming the audio domain clocks clk: bcm2835: Add binding docs for the new platform clock driver. clk: bcm2835: Move under bcm/ with other Broadcom SoC clk drivers. Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt45
-rw-r--r--arch/arm/boot/dts/Makefile4
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi-a-plus.dts30
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts23
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi-b.dts8
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi.dtsi4
-rw-r--r--arch/arm/boot/dts/bcm2835.dtsi64
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/bcm/Makefile1
-rw-r--r--drivers/clk/bcm/clk-bcm2835.c1575
-rw-r--r--drivers/clk/clk-bcm2835.c55
-rw-r--r--include/dt-bindings/clock/bcm2835.h47
12 files changed, 1768 insertions, 89 deletions
diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt
new file mode 100644
index 000000000000..e56a1df3a9d3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt
@@ -0,0 +1,45 @@
1Broadcom BCM2835 CPRMAN clocks
2
3This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
5
6The CPRMAN clock controller generates clocks in the audio power domain
7of the BCM2835. There is a level of PLLs deriving from an external
8oscillator, a level of PLL dividers that produce channels off of the
9few PLLs, and a level of mostly-generic clock generators sourcing from
10the PLL channels. Most other hardware components source from the
11clock generators, but a few (like the ARM or HDMI) will source from
12the PLL dividers directly.
13
14Required properties:
15- compatible: Should be "brcm,bcm2835-cprman"
16- #clock-cells: Should be <1>. The permitted clock-specifier values can be
17 found in include/dt-bindings/clock/bcm2835.h
18- reg: Specifies base physical address and size of the registers
19- clocks: The external oscillator clock phandle
20
21Example:
22
23 clk_osc: clock@3 {
24 compatible = "fixed-clock";
25 reg = <3>;
26 #clock-cells = <0>;
27 clock-output-names = "osc";
28 clock-frequency = <19200000>;
29 };
30
31 clocks: cprman@7e101000 {
32 compatible = "brcm,bcm2835-cprman";
33 #clock-cells = <1>;
34 reg = <0x7e101000 0x2000>;
35 clocks = <&clk_osc>;
36 };
37
38 i2c0: i2c@7e205000 {
39 compatible = "brcm,bcm2835-i2c";
40 reg = <0x7e205000 0x1000>;
41 interrupts = <2 21>;
42 clocks = <&clocks BCM2835_CLOCK_VPU>;
43 #address-cells = <1>;
44 #size-cells = <0>;
45 };
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b5e0ff97db15..1a8d79944013 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -58,7 +58,9 @@ dtb-$(CONFIG_ARCH_AXXIA) += \
58 axm5516-amarillo.dtb 58 axm5516-amarillo.dtb
59dtb-$(CONFIG_ARCH_BCM2835) += \ 59dtb-$(CONFIG_ARCH_BCM2835) += \
60 bcm2835-rpi-b.dtb \ 60 bcm2835-rpi-b.dtb \
61 bcm2835-rpi-b-plus.dtb 61 bcm2835-rpi-b-rev2.dtb \
62 bcm2835-rpi-b-plus.dtb \
63 bcm2835-rpi-a-plus.dtb
62dtb-$(CONFIG_ARCH_BCM_5301X) += \ 64dtb-$(CONFIG_ARCH_BCM_5301X) += \
63 bcm4708-asus-rt-ac56u.dtb \ 65 bcm4708-asus-rt-ac56u.dtb \
64 bcm4708-asus-rt-ac68u.dtb \ 66 bcm4708-asus-rt-ac68u.dtb \
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
new file mode 100644
index 000000000000..b2bff43b135c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
@@ -0,0 +1,30 @@
1/dts-v1/;
2#include "bcm2835-rpi.dtsi"
3
4/ {
5 compatible = "raspberrypi,model-a-plus", "brcm,bcm2835";
6 model = "Raspberry Pi Model A+";
7
8 leds {
9 act {
10 gpios = <&gpio 47 0>;
11 };
12
13 pwr {
14 label = "PWR";
15 gpios = <&gpio 35 0>;
16 default-state = "keep";
17 linux,default-trigger = "default-on";
18 };
19 };
20};
21
22&gpio {
23 pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
24
25 /* I2S interface */
26 i2s_alt0: i2s_alt0 {
27 brcm,pins = <18 19 20 21>;
28 brcm,function = <BCM2835_FSEL_ALT0>;
29 };
30};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
new file mode 100644
index 000000000000..eab8b5916e8a
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
@@ -0,0 +1,23 @@
1/dts-v1/;
2#include "bcm2835-rpi.dtsi"
3
4/ {
5 compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835";
6 model = "Raspberry Pi Model B rev2";
7
8 leds {
9 act {
10 gpios = <&gpio 16 1>;
11 };
12 };
13};
14
15&gpio {
16 pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
17
18 /* I2S interface */
19 i2s_alt2: i2s_alt2 {
20 brcm,pins = <28 29 30 31>;
21 brcm,function = <BCM2835_FSEL_ALT2>;
22 };
23};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index ee89b79426cf..ff6b2d1c6c90 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -13,11 +13,5 @@
13}; 13};
14 14
15&gpio { 15&gpio {
16 pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>; 16 pinctrl-0 = <&gpioout &alt0 &alt3>;
17
18 /* I2S interface */
19 i2s_alt2: i2s_alt2 {
20 brcm,pins = <28 29 30 31>;
21 brcm,function = <BCM2835_FSEL_ALT2>;
22 };
23}; 17};
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index ab5474e5d1c8..3572f0367baf 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -52,6 +52,10 @@
52 clock-frequency = <100000>; 52 clock-frequency = <100000>;
53}; 53};
54 54
55&i2c2 {
56 status = "okay";
57};
58
55&sdhci { 59&sdhci {
56 status = "okay"; 60 status = "okay";
57 bus-width = <4>; 61 bus-width = <4>;
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 301c73f4ca33..aef64de77495 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -1,4 +1,5 @@
1#include <dt-bindings/pinctrl/bcm2835.h> 1#include <dt-bindings/pinctrl/bcm2835.h>
2#include <dt-bindings/clock/bcm2835.h>
2#include "skeleton.dtsi" 3#include "skeleton.dtsi"
3 4
4/ { 5/ {
@@ -21,6 +22,10 @@
21 compatible = "brcm,bcm2835-system-timer"; 22 compatible = "brcm,bcm2835-system-timer";
22 reg = <0x7e003000 0x1000>; 23 reg = <0x7e003000 0x1000>;
23 interrupts = <1 0>, <1 1>, <1 2>, <1 3>; 24 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
25 /* This could be a reference to BCM2835_CLOCK_TIMER,
26 * but we don't have the driver using the common clock
27 * support yet.
28 */
24 clock-frequency = <1000000>; 29 clock-frequency = <1000000>;
25 }; 30 };
26 31
@@ -57,6 +62,17 @@
57 reg = <0x7e100000 0x28>; 62 reg = <0x7e100000 0x28>;
58 }; 63 };
59 64
65 clocks: cprman@7e101000 {
66 compatible = "brcm,bcm2835-cprman";
67 #clock-cells = <1>;
68 reg = <0x7e101000 0x2000>;
69
70 /* CPRMAN derives everything from the platform's
71 * oscillator.
72 */
73 clocks = <&clk_osc>;
74 };
75
60 rng@7e104000 { 76 rng@7e104000 {
61 compatible = "brcm,bcm2835-rng"; 77 compatible = "brcm,bcm2835-rng";
62 reg = <0x7e104000 0x10>; 78 reg = <0x7e104000 0x10>;
@@ -92,11 +108,13 @@
92 #interrupt-cells = <2>; 108 #interrupt-cells = <2>;
93 }; 109 };
94 110
95 uart@7e201000 { 111 uart0: uart@7e201000 {
96 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; 112 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
97 reg = <0x7e201000 0x1000>; 113 reg = <0x7e201000 0x1000>;
98 interrupts = <2 25>; 114 interrupts = <2 25>;
99 clock-frequency = <3000000>; 115 clocks = <&clocks BCM2835_CLOCK_UART>,
116 <&clocks BCM2835_CLOCK_VPU>;
117 clock-names = "uartclk", "apb_pclk";
100 arm,primecell-periphid = <0x00241011>; 118 arm,primecell-periphid = <0x00241011>;
101 }; 119 };
102 120
@@ -115,7 +133,7 @@
115 compatible = "brcm,bcm2835-spi"; 133 compatible = "brcm,bcm2835-spi";
116 reg = <0x7e204000 0x1000>; 134 reg = <0x7e204000 0x1000>;
117 interrupts = <2 22>; 135 interrupts = <2 22>;
118 clocks = <&clk_spi>; 136 clocks = <&clocks BCM2835_CLOCK_VPU>;
119 #address-cells = <1>; 137 #address-cells = <1>;
120 #size-cells = <0>; 138 #size-cells = <0>;
121 status = "disabled"; 139 status = "disabled";
@@ -125,7 +143,7 @@
125 compatible = "brcm,bcm2835-i2c"; 143 compatible = "brcm,bcm2835-i2c";
126 reg = <0x7e205000 0x1000>; 144 reg = <0x7e205000 0x1000>;
127 interrupts = <2 21>; 145 interrupts = <2 21>;
128 clocks = <&clk_i2c>; 146 clocks = <&clocks BCM2835_CLOCK_VPU>;
129 #address-cells = <1>; 147 #address-cells = <1>;
130 #size-cells = <0>; 148 #size-cells = <0>;
131 status = "disabled"; 149 status = "disabled";
@@ -135,7 +153,7 @@
135 compatible = "brcm,bcm2835-sdhci"; 153 compatible = "brcm,bcm2835-sdhci";
136 reg = <0x7e300000 0x100>; 154 reg = <0x7e300000 0x100>;
137 interrupts = <2 30>; 155 interrupts = <2 30>;
138 clocks = <&clk_mmc>; 156 clocks = <&clocks BCM2835_CLOCK_EMMC>;
139 status = "disabled"; 157 status = "disabled";
140 }; 158 };
141 159
@@ -143,7 +161,17 @@
143 compatible = "brcm,bcm2835-i2c"; 161 compatible = "brcm,bcm2835-i2c";
144 reg = <0x7e804000 0x1000>; 162 reg = <0x7e804000 0x1000>;
145 interrupts = <2 21>; 163 interrupts = <2 21>;
146 clocks = <&clk_i2c>; 164 clocks = <&clocks BCM2835_CLOCK_VPU>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 status = "disabled";
168 };
169
170 i2c2: i2c@7e805000 {
171 compatible = "brcm,bcm2835-i2c";
172 reg = <0x7e805000 0x1000>;
173 interrupts = <2 21>;
174 clocks = <&clocks BCM2835_CLOCK_VPU>;
147 #address-cells = <1>; 175 #address-cells = <1>;
148 #size-cells = <0>; 176 #size-cells = <0>;
149 status = "disabled"; 177 status = "disabled";
@@ -165,28 +193,14 @@
165 #address-cells = <1>; 193 #address-cells = <1>;
166 #size-cells = <0>; 194 #size-cells = <0>;
167 195
168 clk_mmc: clock@0 { 196 /* The oscillator is the root of the clock tree. */
197 clk_osc: clock@3 {
169 compatible = "fixed-clock"; 198 compatible = "fixed-clock";
170 reg = <0>; 199 reg = <3>;
171 #clock-cells = <0>; 200 #clock-cells = <0>;
172 clock-output-names = "mmc"; 201 clock-output-names = "osc";
173 clock-frequency = <100000000>; 202 clock-frequency = <19200000>;
174 }; 203 };
175 204
176 clk_i2c: clock@1 {
177 compatible = "fixed-clock";
178 reg = <1>;
179 #clock-cells = <0>;
180 clock-output-names = "i2c";
181 clock-frequency = <250000000>;
182 };
183
184 clk_spi: clock@2 {
185 compatible = "fixed-clock";
186 reg = <2>;
187 #clock-cells = <0>;
188 clock-output-names = "spi";
189 clock-frequency = <250000000>;
190 };
191 }; 205 };
192}; 206};
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d08b3e5985be..9f7155855391 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -19,7 +19,6 @@ endif
19obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o 19obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o
20obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o 20obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
21obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o 21obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
22obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
23obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o 22obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o
24obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o 23obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
25obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o 24obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 8a7a477862c7..ee2349bbe1f1 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -3,4 +3,5 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
3obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o 3obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
4obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o 4obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
5obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o 5obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
6obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
6obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o 7obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
new file mode 100644
index 000000000000..39bf5820297e
--- /dev/null
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -0,0 +1,1575 @@
1/*
2 * Copyright (C) 2010,2015 Broadcom
3 * Copyright (C) 2012 Stephen Warren
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20/**
21 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
22 *
23 * The clock tree on the 2835 has several levels. There's a root
24 * oscillator running at 19.2Mhz. After the oscillator there are 5
25 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
26 * and "HDMI displays". Those 5 PLLs each can divide their output to
27 * produce up to 4 channels. Finally, there is the level of clocks to
28 * be consumed by other hardware components (like "H264" or "HDMI
29 * state machine"), which divide off of some subset of the PLL
30 * channels.
31 *
32 * All of the clocks in the tree are exposed in the DT, because the DT
33 * may want to make assignments of the final layer of clocks to the
34 * PLL channels, and some components of the hardware will actually
35 * skip layers of the tree (for example, the pixel clock comes
36 * directly from the PLLH PIX channel without using a CM_*CTL clock
37 * generator).
38 */
39
40#include <linux/clk-provider.h>
41#include <linux/clkdev.h>
42#include <linux/clk/bcm2835.h>
43#include <linux/module.h>
44#include <linux/of.h>
45#include <linux/platform_device.h>
46#include <linux/slab.h>
47#include <dt-bindings/clock/bcm2835.h>
48
49#define CM_PASSWORD 0x5a000000
50
51#define CM_GNRICCTL 0x000
52#define CM_GNRICDIV 0x004
53# define CM_DIV_FRAC_BITS 12
54
55#define CM_VPUCTL 0x008
56#define CM_VPUDIV 0x00c
57#define CM_SYSCTL 0x010
58#define CM_SYSDIV 0x014
59#define CM_PERIACTL 0x018
60#define CM_PERIADIV 0x01c
61#define CM_PERIICTL 0x020
62#define CM_PERIIDIV 0x024
63#define CM_H264CTL 0x028
64#define CM_H264DIV 0x02c
65#define CM_ISPCTL 0x030
66#define CM_ISPDIV 0x034
67#define CM_V3DCTL 0x038
68#define CM_V3DDIV 0x03c
69#define CM_CAM0CTL 0x040
70#define CM_CAM0DIV 0x044
71#define CM_CAM1CTL 0x048
72#define CM_CAM1DIV 0x04c
73#define CM_CCP2CTL 0x050
74#define CM_CCP2DIV 0x054
75#define CM_DSI0ECTL 0x058
76#define CM_DSI0EDIV 0x05c
77#define CM_DSI0PCTL 0x060
78#define CM_DSI0PDIV 0x064
79#define CM_DPICTL 0x068
80#define CM_DPIDIV 0x06c
81#define CM_GP0CTL 0x070
82#define CM_GP0DIV 0x074
83#define CM_GP1CTL 0x078
84#define CM_GP1DIV 0x07c
85#define CM_GP2CTL 0x080
86#define CM_GP2DIV 0x084
87#define CM_HSMCTL 0x088
88#define CM_HSMDIV 0x08c
89#define CM_OTPCTL 0x090
90#define CM_OTPDIV 0x094
91#define CM_PWMCTL 0x0a0
92#define CM_PWMDIV 0x0a4
93#define CM_SMICTL 0x0b0
94#define CM_SMIDIV 0x0b4
95#define CM_TSENSCTL 0x0e0
96#define CM_TSENSDIV 0x0e4
97#define CM_TIMERCTL 0x0e8
98#define CM_TIMERDIV 0x0ec
99#define CM_UARTCTL 0x0f0
100#define CM_UARTDIV 0x0f4
101#define CM_VECCTL 0x0f8
102#define CM_VECDIV 0x0fc
103#define CM_PULSECTL 0x190
104#define CM_PULSEDIV 0x194
105#define CM_SDCCTL 0x1a8
106#define CM_SDCDIV 0x1ac
107#define CM_ARMCTL 0x1b0
108#define CM_EMMCCTL 0x1c0
109#define CM_EMMCDIV 0x1c4
110
111/* General bits for the CM_*CTL regs */
112# define CM_ENABLE BIT(4)
113# define CM_KILL BIT(5)
114# define CM_GATE_BIT 6
115# define CM_GATE BIT(CM_GATE_BIT)
116# define CM_BUSY BIT(7)
117# define CM_BUSYD BIT(8)
118# define CM_SRC_SHIFT 0
119# define CM_SRC_BITS 4
120# define CM_SRC_MASK 0xf
121# define CM_SRC_GND 0
122# define CM_SRC_OSC 1
123# define CM_SRC_TESTDEBUG0 2
124# define CM_SRC_TESTDEBUG1 3
125# define CM_SRC_PLLA_CORE 4
126# define CM_SRC_PLLA_PER 4
127# define CM_SRC_PLLC_CORE0 5
128# define CM_SRC_PLLC_PER 5
129# define CM_SRC_PLLC_CORE1 8
130# define CM_SRC_PLLD_CORE 6
131# define CM_SRC_PLLD_PER 6
132# define CM_SRC_PLLH_AUX 7
133# define CM_SRC_PLLC_CORE1 8
134# define CM_SRC_PLLC_CORE2 9
135
136#define CM_OSCCOUNT 0x100
137
138#define CM_PLLA 0x104
139# define CM_PLL_ANARST BIT(8)
140# define CM_PLLA_HOLDPER BIT(7)
141# define CM_PLLA_LOADPER BIT(6)
142# define CM_PLLA_HOLDCORE BIT(5)
143# define CM_PLLA_LOADCORE BIT(4)
144# define CM_PLLA_HOLDCCP2 BIT(3)
145# define CM_PLLA_LOADCCP2 BIT(2)
146# define CM_PLLA_HOLDDSI0 BIT(1)
147# define CM_PLLA_LOADDSI0 BIT(0)
148
149#define CM_PLLC 0x108
150# define CM_PLLC_HOLDPER BIT(7)
151# define CM_PLLC_LOADPER BIT(6)
152# define CM_PLLC_HOLDCORE2 BIT(5)
153# define CM_PLLC_LOADCORE2 BIT(4)
154# define CM_PLLC_HOLDCORE1 BIT(3)
155# define CM_PLLC_LOADCORE1 BIT(2)
156# define CM_PLLC_HOLDCORE0 BIT(1)
157# define CM_PLLC_LOADCORE0 BIT(0)
158
159#define CM_PLLD 0x10c
160# define CM_PLLD_HOLDPER BIT(7)
161# define CM_PLLD_LOADPER BIT(6)
162# define CM_PLLD_HOLDCORE BIT(5)
163# define CM_PLLD_LOADCORE BIT(4)
164# define CM_PLLD_HOLDDSI1 BIT(3)
165# define CM_PLLD_LOADDSI1 BIT(2)
166# define CM_PLLD_HOLDDSI0 BIT(1)
167# define CM_PLLD_LOADDSI0 BIT(0)
168
169#define CM_PLLH 0x110
170# define CM_PLLH_LOADRCAL BIT(2)
171# define CM_PLLH_LOADAUX BIT(1)
172# define CM_PLLH_LOADPIX BIT(0)
173
174#define CM_LOCK 0x114
175# define CM_LOCK_FLOCKH BIT(12)
176# define CM_LOCK_FLOCKD BIT(11)
177# define CM_LOCK_FLOCKC BIT(10)
178# define CM_LOCK_FLOCKB BIT(9)
179# define CM_LOCK_FLOCKA BIT(8)
180
181#define CM_EVENT 0x118
182#define CM_DSI1ECTL 0x158
183#define CM_DSI1EDIV 0x15c
184#define CM_DSI1PCTL 0x160
185#define CM_DSI1PDIV 0x164
186#define CM_DFTCTL 0x168
187#define CM_DFTDIV 0x16c
188
189#define CM_PLLB 0x170
190# define CM_PLLB_HOLDARM BIT(1)
191# define CM_PLLB_LOADARM BIT(0)
192
193#define A2W_PLLA_CTRL 0x1100
194#define A2W_PLLC_CTRL 0x1120
195#define A2W_PLLD_CTRL 0x1140
196#define A2W_PLLH_CTRL 0x1160
197#define A2W_PLLB_CTRL 0x11e0
198# define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
199# define A2W_PLL_CTRL_PWRDN BIT(16)
200# define A2W_PLL_CTRL_PDIV_MASK 0x000007000
201# define A2W_PLL_CTRL_PDIV_SHIFT 12
202# define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
203# define A2W_PLL_CTRL_NDIV_SHIFT 0
204
205#define A2W_PLLA_ANA0 0x1010
206#define A2W_PLLC_ANA0 0x1030
207#define A2W_PLLD_ANA0 0x1050
208#define A2W_PLLH_ANA0 0x1070
209#define A2W_PLLB_ANA0 0x10f0
210
211#define A2W_PLL_KA_SHIFT 7
212#define A2W_PLL_KA_MASK GENMASK(9, 7)
213#define A2W_PLL_KI_SHIFT 19
214#define A2W_PLL_KI_MASK GENMASK(21, 19)
215#define A2W_PLL_KP_SHIFT 15
216#define A2W_PLL_KP_MASK GENMASK(18, 15)
217
218#define A2W_PLLH_KA_SHIFT 19
219#define A2W_PLLH_KA_MASK GENMASK(21, 19)
220#define A2W_PLLH_KI_LOW_SHIFT 22
221#define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
222#define A2W_PLLH_KI_HIGH_SHIFT 0
223#define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
224#define A2W_PLLH_KP_SHIFT 1
225#define A2W_PLLH_KP_MASK GENMASK(4, 1)
226
227#define A2W_XOSC_CTRL 0x1190
228# define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
229# define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
230# define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
231# define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
232# define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
233# define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
234# define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
235# define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
236
237#define A2W_PLLA_FRAC 0x1200
238#define A2W_PLLC_FRAC 0x1220
239#define A2W_PLLD_FRAC 0x1240
240#define A2W_PLLH_FRAC 0x1260
241#define A2W_PLLB_FRAC 0x12e0
242# define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
243# define A2W_PLL_FRAC_BITS 20
244
245#define A2W_PLL_CHANNEL_DISABLE BIT(8)
246#define A2W_PLL_DIV_BITS 8
247#define A2W_PLL_DIV_SHIFT 0
248
249#define A2W_PLLA_DSI0 0x1300
250#define A2W_PLLA_CORE 0x1400
251#define A2W_PLLA_PER 0x1500
252#define A2W_PLLA_CCP2 0x1600
253
254#define A2W_PLLC_CORE2 0x1320
255#define A2W_PLLC_CORE1 0x1420
256#define A2W_PLLC_PER 0x1520
257#define A2W_PLLC_CORE0 0x1620
258
259#define A2W_PLLD_DSI0 0x1340
260#define A2W_PLLD_CORE 0x1440
261#define A2W_PLLD_PER 0x1540
262#define A2W_PLLD_DSI1 0x1640
263
264#define A2W_PLLH_AUX 0x1360
265#define A2W_PLLH_RCAL 0x1460
266#define A2W_PLLH_PIX 0x1560
267#define A2W_PLLH_STS 0x1660
268
269#define A2W_PLLH_CTRLR 0x1960
270#define A2W_PLLH_FRACR 0x1a60
271#define A2W_PLLH_AUXR 0x1b60
272#define A2W_PLLH_RCALR 0x1c60
273#define A2W_PLLH_PIXR 0x1d60
274#define A2W_PLLH_STSR 0x1e60
275
276#define A2W_PLLB_ARM 0x13e0
277#define A2W_PLLB_SP0 0x14e0
278#define A2W_PLLB_SP1 0x15e0
279#define A2W_PLLB_SP2 0x16e0
280
281#define LOCK_TIMEOUT_NS 100000000
282#define BCM2835_MAX_FB_RATE 1750000000u
283
284struct bcm2835_cprman {
285 struct device *dev;
286 void __iomem *regs;
287 spinlock_t regs_lock;
288 const char *osc_name;
289
290 struct clk_onecell_data onecell;
291 struct clk *clks[BCM2835_CLOCK_COUNT];
292};
293
294static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
295{
296 writel(CM_PASSWORD | val, cprman->regs + reg);
297}
298
299static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg)
300{
301 return readl(cprman->regs + reg);
302}
303
304/*
305 * These are fixed clocks. They're probably not all root clocks and it may
306 * be possible to turn them on and off but until this is mapped out better
307 * it's the only way they can be used.
308 */
309void __init bcm2835_init_clocks(void)
310{
311 struct clk *clk;
312 int ret;
313
314 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT,
315 126000000);
316 if (IS_ERR(clk))
317 pr_err("apb_pclk not registered\n");
318
319 clk = clk_register_fixed_rate(NULL, "uart0_pclk", NULL, CLK_IS_ROOT,
320 3000000);
321 if (IS_ERR(clk))
322 pr_err("uart0_pclk not registered\n");
323 ret = clk_register_clkdev(clk, NULL, "20201000.uart");
324 if (ret)
325 pr_err("uart0_pclk alias not registered\n");
326
327 clk = clk_register_fixed_rate(NULL, "uart1_pclk", NULL, CLK_IS_ROOT,
328 125000000);
329 if (IS_ERR(clk))
330 pr_err("uart1_pclk not registered\n");
331 ret = clk_register_clkdev(clk, NULL, "20215000.uart");
332 if (ret)
333 pr_err("uart1_pclk alias not registered\n");
334}
335
336struct bcm2835_pll_data {
337 const char *name;
338 u32 cm_ctrl_reg;
339 u32 a2w_ctrl_reg;
340 u32 frac_reg;
341 u32 ana_reg_base;
342 u32 reference_enable_mask;
343 /* Bit in CM_LOCK to indicate when the PLL has locked. */
344 u32 lock_mask;
345
346 const struct bcm2835_pll_ana_bits *ana;
347
348 unsigned long min_rate;
349 unsigned long max_rate;
350 /*
351 * Highest rate for the VCO before we have to use the
352 * pre-divide-by-2.
353 */
354 unsigned long max_fb_rate;
355};
356
357struct bcm2835_pll_ana_bits {
358 u32 mask0;
359 u32 set0;
360 u32 mask1;
361 u32 set1;
362 u32 mask3;
363 u32 set3;
364 u32 fb_prediv_mask;
365};
366
367static const struct bcm2835_pll_ana_bits bcm2835_ana_default = {
368 .mask0 = 0,
369 .set0 = 0,
370 .mask1 = ~(A2W_PLL_KI_MASK | A2W_PLL_KP_MASK),
371 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT),
372 .mask3 = ~A2W_PLL_KA_MASK,
373 .set3 = (2 << A2W_PLL_KA_SHIFT),
374 .fb_prediv_mask = BIT(14),
375};
376
377static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {
378 .mask0 = ~(A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK),
379 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),
380 .mask1 = ~(A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK),
381 .set1 = (6 << A2W_PLLH_KP_SHIFT),
382 .mask3 = 0,
383 .set3 = 0,
384 .fb_prediv_mask = BIT(11),
385};
386
387/*
388 * PLLA is the auxiliary PLL, used to drive the CCP2 (Compact Camera
389 * Port 2) transmitter clock.
390 *
391 * It is in the PX LDO power domain, which is on when the AUDIO domain
392 * is on.
393 */
394static const struct bcm2835_pll_data bcm2835_plla_data = {
395 .name = "plla",
396 .cm_ctrl_reg = CM_PLLA,
397 .a2w_ctrl_reg = A2W_PLLA_CTRL,
398 .frac_reg = A2W_PLLA_FRAC,
399 .ana_reg_base = A2W_PLLA_ANA0,
400 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
401 .lock_mask = CM_LOCK_FLOCKA,
402
403 .ana = &bcm2835_ana_default,
404
405 .min_rate = 600000000u,
406 .max_rate = 2400000000u,
407 .max_fb_rate = BCM2835_MAX_FB_RATE,
408};
409
410/* PLLB is used for the ARM's clock. */
411static const struct bcm2835_pll_data bcm2835_pllb_data = {
412 .name = "pllb",
413 .cm_ctrl_reg = CM_PLLB,
414 .a2w_ctrl_reg = A2W_PLLB_CTRL,
415 .frac_reg = A2W_PLLB_FRAC,
416 .ana_reg_base = A2W_PLLB_ANA0,
417 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
418 .lock_mask = CM_LOCK_FLOCKB,
419
420 .ana = &bcm2835_ana_default,
421
422 .min_rate = 600000000u,
423 .max_rate = 3000000000u,
424 .max_fb_rate = BCM2835_MAX_FB_RATE,
425};
426
427/*
428 * PLLC is the core PLL, used to drive the core VPU clock.
429 *
430 * It is in the PX LDO power domain, which is on when the AUDIO domain
431 * is on.
432*/
433static const struct bcm2835_pll_data bcm2835_pllc_data = {
434 .name = "pllc",
435 .cm_ctrl_reg = CM_PLLC,
436 .a2w_ctrl_reg = A2W_PLLC_CTRL,
437 .frac_reg = A2W_PLLC_FRAC,
438 .ana_reg_base = A2W_PLLC_ANA0,
439 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
440 .lock_mask = CM_LOCK_FLOCKC,
441
442 .ana = &bcm2835_ana_default,
443
444 .min_rate = 600000000u,
445 .max_rate = 3000000000u,
446 .max_fb_rate = BCM2835_MAX_FB_RATE,
447};
448
449/*
450 * PLLD is the display PLL, used to drive DSI display panels.
451 *
452 * It is in the PX LDO power domain, which is on when the AUDIO domain
453 * is on.
454 */
455static const struct bcm2835_pll_data bcm2835_plld_data = {
456 .name = "plld",
457 .cm_ctrl_reg = CM_PLLD,
458 .a2w_ctrl_reg = A2W_PLLD_CTRL,
459 .frac_reg = A2W_PLLD_FRAC,
460 .ana_reg_base = A2W_PLLD_ANA0,
461 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
462 .lock_mask = CM_LOCK_FLOCKD,
463
464 .ana = &bcm2835_ana_default,
465
466 .min_rate = 600000000u,
467 .max_rate = 2400000000u,
468 .max_fb_rate = BCM2835_MAX_FB_RATE,
469};
470
471/*
472 * PLLH is used to supply the pixel clock or the AUX clock for the TV
473 * encoder.
474 *
475 * It is in the HDMI power domain.
476 */
477static const struct bcm2835_pll_data bcm2835_pllh_data = {
478 "pllh",
479 .cm_ctrl_reg = CM_PLLH,
480 .a2w_ctrl_reg = A2W_PLLH_CTRL,
481 .frac_reg = A2W_PLLH_FRAC,
482 .ana_reg_base = A2W_PLLH_ANA0,
483 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
484 .lock_mask = CM_LOCK_FLOCKH,
485
486 .ana = &bcm2835_ana_pllh,
487
488 .min_rate = 600000000u,
489 .max_rate = 3000000000u,
490 .max_fb_rate = BCM2835_MAX_FB_RATE,
491};
492
493struct bcm2835_pll_divider_data {
494 const char *name;
495 const struct bcm2835_pll_data *source_pll;
496 u32 cm_reg;
497 u32 a2w_reg;
498
499 u32 load_mask;
500 u32 hold_mask;
501 u32 fixed_divider;
502};
503
504static const struct bcm2835_pll_divider_data bcm2835_plla_core_data = {
505 .name = "plla_core",
506 .source_pll = &bcm2835_plla_data,
507 .cm_reg = CM_PLLA,
508 .a2w_reg = A2W_PLLA_CORE,
509 .load_mask = CM_PLLA_LOADCORE,
510 .hold_mask = CM_PLLA_HOLDCORE,
511 .fixed_divider = 1,
512};
513
514static const struct bcm2835_pll_divider_data bcm2835_plla_per_data = {
515 .name = "plla_per",
516 .source_pll = &bcm2835_plla_data,
517 .cm_reg = CM_PLLA,
518 .a2w_reg = A2W_PLLA_PER,
519 .load_mask = CM_PLLA_LOADPER,
520 .hold_mask = CM_PLLA_HOLDPER,
521 .fixed_divider = 1,
522};
523
524static const struct bcm2835_pll_divider_data bcm2835_pllb_arm_data = {
525 .name = "pllb_arm",
526 .source_pll = &bcm2835_pllb_data,
527 .cm_reg = CM_PLLB,
528 .a2w_reg = A2W_PLLB_ARM,
529 .load_mask = CM_PLLB_LOADARM,
530 .hold_mask = CM_PLLB_HOLDARM,
531 .fixed_divider = 1,
532};
533
534static const struct bcm2835_pll_divider_data bcm2835_pllc_core0_data = {
535 .name = "pllc_core0",
536 .source_pll = &bcm2835_pllc_data,
537 .cm_reg = CM_PLLC,
538 .a2w_reg = A2W_PLLC_CORE0,
539 .load_mask = CM_PLLC_LOADCORE0,
540 .hold_mask = CM_PLLC_HOLDCORE0,
541 .fixed_divider = 1,
542};
543
544static const struct bcm2835_pll_divider_data bcm2835_pllc_core1_data = {
545 .name = "pllc_core1", .source_pll = &bcm2835_pllc_data,
546 .cm_reg = CM_PLLC, A2W_PLLC_CORE1,
547 .load_mask = CM_PLLC_LOADCORE1,
548 .hold_mask = CM_PLLC_HOLDCORE1,
549 .fixed_divider = 1,
550};
551
552static const struct bcm2835_pll_divider_data bcm2835_pllc_core2_data = {
553 .name = "pllc_core2",
554 .source_pll = &bcm2835_pllc_data,
555 .cm_reg = CM_PLLC,
556 .a2w_reg = A2W_PLLC_CORE2,
557 .load_mask = CM_PLLC_LOADCORE2,
558 .hold_mask = CM_PLLC_HOLDCORE2,
559 .fixed_divider = 1,
560};
561
562static const struct bcm2835_pll_divider_data bcm2835_pllc_per_data = {
563 .name = "pllc_per",
564 .source_pll = &bcm2835_pllc_data,
565 .cm_reg = CM_PLLC,
566 .a2w_reg = A2W_PLLC_PER,
567 .load_mask = CM_PLLC_LOADPER,
568 .hold_mask = CM_PLLC_HOLDPER,
569 .fixed_divider = 1,
570};
571
572static const struct bcm2835_pll_divider_data bcm2835_plld_core_data = {
573 .name = "plld_core",
574 .source_pll = &bcm2835_plld_data,
575 .cm_reg = CM_PLLD,
576 .a2w_reg = A2W_PLLD_CORE,
577 .load_mask = CM_PLLD_LOADCORE,
578 .hold_mask = CM_PLLD_HOLDCORE,
579 .fixed_divider = 1,
580};
581
582static const struct bcm2835_pll_divider_data bcm2835_plld_per_data = {
583 .name = "plld_per",
584 .source_pll = &bcm2835_plld_data,
585 .cm_reg = CM_PLLD,
586 .a2w_reg = A2W_PLLD_PER,
587 .load_mask = CM_PLLD_LOADPER,
588 .hold_mask = CM_PLLD_HOLDPER,
589 .fixed_divider = 1,
590};
591
592static const struct bcm2835_pll_divider_data bcm2835_pllh_rcal_data = {
593 .name = "pllh_rcal",
594 .source_pll = &bcm2835_pllh_data,
595 .cm_reg = CM_PLLH,
596 .a2w_reg = A2W_PLLH_RCAL,
597 .load_mask = CM_PLLH_LOADRCAL,
598 .hold_mask = 0,
599 .fixed_divider = 10,
600};
601
602static const struct bcm2835_pll_divider_data bcm2835_pllh_aux_data = {
603 .name = "pllh_aux",
604 .source_pll = &bcm2835_pllh_data,
605 .cm_reg = CM_PLLH,
606 .a2w_reg = A2W_PLLH_AUX,
607 .load_mask = CM_PLLH_LOADAUX,
608 .hold_mask = 0,
609 .fixed_divider = 10,
610};
611
612static const struct bcm2835_pll_divider_data bcm2835_pllh_pix_data = {
613 .name = "pllh_pix",
614 .source_pll = &bcm2835_pllh_data,
615 .cm_reg = CM_PLLH,
616 .a2w_reg = A2W_PLLH_PIX,
617 .load_mask = CM_PLLH_LOADPIX,
618 .hold_mask = 0,
619 .fixed_divider = 10,
620};
621
622struct bcm2835_clock_data {
623 const char *name;
624
625 const char *const *parents;
626 int num_mux_parents;
627
628 u32 ctl_reg;
629 u32 div_reg;
630
631 /* Number of integer bits in the divider */
632 u32 int_bits;
633 /* Number of fractional bits in the divider */
634 u32 frac_bits;
635
636 bool is_vpu_clock;
637};
638
639static const char *const bcm2835_clock_per_parents[] = {
640 "gnd",
641 "xosc",
642 "testdebug0",
643 "testdebug1",
644 "plla_per",
645 "pllc_per",
646 "plld_per",
647 "pllh_aux",
648};
649
650static const char *const bcm2835_clock_vpu_parents[] = {
651 "gnd",
652 "xosc",
653 "testdebug0",
654 "testdebug1",
655 "plla_core",
656 "pllc_core0",
657 "plld_core",
658 "pllh_aux",
659 "pllc_core1",
660 "pllc_core2",
661};
662
663static const char *const bcm2835_clock_osc_parents[] = {
664 "gnd",
665 "xosc",
666 "testdebug0",
667 "testdebug1"
668};
669
670/*
671 * Used for a 1Mhz clock for the system clocksource, and also used by
672 * the watchdog timer and the camera pulse generator.
673 */
674static const struct bcm2835_clock_data bcm2835_clock_timer_data = {
675 .name = "timer",
676 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
677 .parents = bcm2835_clock_osc_parents,
678 .ctl_reg = CM_TIMERCTL,
679 .div_reg = CM_TIMERDIV,
680 .int_bits = 6,
681 .frac_bits = 12,
682};
683
684/* One Time Programmable Memory clock. Maximum 10Mhz. */
685static const struct bcm2835_clock_data bcm2835_clock_otp_data = {
686 .name = "otp",
687 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
688 .parents = bcm2835_clock_osc_parents,
689 .ctl_reg = CM_OTPCTL,
690 .div_reg = CM_OTPDIV,
691 .int_bits = 4,
692 .frac_bits = 0,
693};
694
695/*
696 * VPU clock. This doesn't have an enable bit, since it drives the
697 * bus for everything else, and is special so it doesn't need to be
698 * gated for rate changes. It is also known as "clk_audio" in various
699 * hardware documentation.
700 */
701static const struct bcm2835_clock_data bcm2835_clock_vpu_data = {
702 .name = "vpu",
703 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
704 .parents = bcm2835_clock_vpu_parents,
705 .ctl_reg = CM_VPUCTL,
706 .div_reg = CM_VPUDIV,
707 .int_bits = 12,
708 .frac_bits = 8,
709 .is_vpu_clock = true,
710};
711
712static const struct bcm2835_clock_data bcm2835_clock_v3d_data = {
713 .name = "v3d",
714 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
715 .parents = bcm2835_clock_vpu_parents,
716 .ctl_reg = CM_V3DCTL,
717 .div_reg = CM_V3DDIV,
718 .int_bits = 4,
719 .frac_bits = 8,
720};
721
722static const struct bcm2835_clock_data bcm2835_clock_isp_data = {
723 .name = "isp",
724 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
725 .parents = bcm2835_clock_vpu_parents,
726 .ctl_reg = CM_ISPCTL,
727 .div_reg = CM_ISPDIV,
728 .int_bits = 4,
729 .frac_bits = 8,
730};
731
732static const struct bcm2835_clock_data bcm2835_clock_h264_data = {
733 .name = "h264",
734 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
735 .parents = bcm2835_clock_vpu_parents,
736 .ctl_reg = CM_H264CTL,
737 .div_reg = CM_H264DIV,
738 .int_bits = 4,
739 .frac_bits = 8,
740};
741
742/* TV encoder clock. Only operating frequency is 108Mhz. */
743static const struct bcm2835_clock_data bcm2835_clock_vec_data = {
744 .name = "vec",
745 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
746 .parents = bcm2835_clock_per_parents,
747 .ctl_reg = CM_VECCTL,
748 .div_reg = CM_VECDIV,
749 .int_bits = 4,
750 .frac_bits = 0,
751};
752
753static const struct bcm2835_clock_data bcm2835_clock_uart_data = {
754 .name = "uart",
755 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
756 .parents = bcm2835_clock_per_parents,
757 .ctl_reg = CM_UARTCTL,
758 .div_reg = CM_UARTDIV,
759 .int_bits = 10,
760 .frac_bits = 12,
761};
762
763/* HDMI state machine */
764static const struct bcm2835_clock_data bcm2835_clock_hsm_data = {
765 .name = "hsm",
766 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
767 .parents = bcm2835_clock_per_parents,
768 .ctl_reg = CM_HSMCTL,
769 .div_reg = CM_HSMDIV,
770 .int_bits = 4,
771 .frac_bits = 8,
772};
773
774/*
775 * Secondary SDRAM clock. Used for low-voltage modes when the PLL in
776 * the SDRAM controller can't be used.
777 */
778static const struct bcm2835_clock_data bcm2835_clock_sdram_data = {
779 .name = "sdram",
780 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
781 .parents = bcm2835_clock_vpu_parents,
782 .ctl_reg = CM_SDCCTL,
783 .div_reg = CM_SDCDIV,
784 .int_bits = 6,
785 .frac_bits = 0,
786};
787
788/* Clock for the temperature sensor. Generally run at 2Mhz, max 5Mhz. */
789static const struct bcm2835_clock_data bcm2835_clock_tsens_data = {
790 .name = "tsens",
791 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
792 .parents = bcm2835_clock_osc_parents,
793 .ctl_reg = CM_TSENSCTL,
794 .div_reg = CM_TSENSDIV,
795 .int_bits = 5,
796 .frac_bits = 0,
797};
798
799/* Arasan EMMC clock */
800static const struct bcm2835_clock_data bcm2835_clock_emmc_data = {
801 .name = "emmc",
802 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
803 .parents = bcm2835_clock_per_parents,
804 .ctl_reg = CM_EMMCCTL,
805 .div_reg = CM_EMMCDIV,
806 .int_bits = 4,
807 .frac_bits = 8,
808};
809
810struct bcm2835_pll {
811 struct clk_hw hw;
812 struct bcm2835_cprman *cprman;
813 const struct bcm2835_pll_data *data;
814};
815
816static int bcm2835_pll_is_on(struct clk_hw *hw)
817{
818 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
819 struct bcm2835_cprman *cprman = pll->cprman;
820 const struct bcm2835_pll_data *data = pll->data;
821
822 return cprman_read(cprman, data->a2w_ctrl_reg) &
823 A2W_PLL_CTRL_PRST_DISABLE;
824}
825
826static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,
827 unsigned long parent_rate,
828 u32 *ndiv, u32 *fdiv)
829{
830 u64 div;
831
832 div = (u64)rate << A2W_PLL_FRAC_BITS;
833 do_div(div, parent_rate);
834
835 *ndiv = div >> A2W_PLL_FRAC_BITS;
836 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
837}
838
839static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
840 u32 ndiv, u32 fdiv, u32 pdiv)
841{
842 u64 rate;
843
844 if (pdiv == 0)
845 return 0;
846
847 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv);
848 do_div(rate, pdiv);
849 return rate >> A2W_PLL_FRAC_BITS;
850}
851
852static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,
853 unsigned long *parent_rate)
854{
855 u32 ndiv, fdiv;
856
857 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);
858
859 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);
860}
861
862static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
863 unsigned long parent_rate)
864{
865 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
866 struct bcm2835_cprman *cprman = pll->cprman;
867 const struct bcm2835_pll_data *data = pll->data;
868 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg);
869 u32 ndiv, pdiv, fdiv;
870 bool using_prediv;
871
872 if (parent_rate == 0)
873 return 0;
874
875 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;
876 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT;
877 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT;
878 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
879 data->ana->fb_prediv_mask;
880
881 if (using_prediv)
882 ndiv *= 2;
883
884 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
885}
886
887static void bcm2835_pll_off(struct clk_hw *hw)
888{
889 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
890 struct bcm2835_cprman *cprman = pll->cprman;
891 const struct bcm2835_pll_data *data = pll->data;
892
893 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
894 cprman_write(cprman, data->a2w_ctrl_reg, A2W_PLL_CTRL_PWRDN);
895}
896
897static int bcm2835_pll_on(struct clk_hw *hw)
898{
899 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
900 struct bcm2835_cprman *cprman = pll->cprman;
901 const struct bcm2835_pll_data *data = pll->data;
902 ktime_t timeout;
903
904 /* Take the PLL out of reset. */
905 cprman_write(cprman, data->cm_ctrl_reg,
906 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
907
908 /* Wait for the PLL to lock. */
909 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
910 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {
911 if (ktime_after(ktime_get(), timeout)) {
912 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
913 clk_hw_get_name(hw));
914 return -ETIMEDOUT;
915 }
916
917 cpu_relax();
918 }
919
920 return 0;
921}
922
923static void
924bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana)
925{
926 int i;
927
928 /*
929 * ANA register setup is done as a series of writes to
930 * ANA3-ANA0, in that order. This lets us write all 4
931 * registers as a single cycle of the serdes interface (taking
932 * 100 xosc clocks), whereas if we were to update ana0, 1, and
933 * 3 individually through their partial-write registers, each
934 * would be their own serdes cycle.
935 */
936 for (i = 3; i >= 0; i--)
937 cprman_write(cprman, ana_reg_base + i * 4, ana[i]);
938}
939
940static int bcm2835_pll_set_rate(struct clk_hw *hw,
941 unsigned long rate, unsigned long parent_rate)
942{
943 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
944 struct bcm2835_cprman *cprman = pll->cprman;
945 const struct bcm2835_pll_data *data = pll->data;
946 bool was_using_prediv, use_fb_prediv, do_ana_setup_first;
947 u32 ndiv, fdiv, a2w_ctl;
948 u32 ana[4];
949 int i;
950
951 if (rate < data->min_rate || rate > data->max_rate) {
952 dev_err(cprman->dev, "%s: rate out of spec: %lu vs (%lu, %lu)\n",
953 clk_hw_get_name(hw), rate,
954 data->min_rate, data->max_rate);
955 return -EINVAL;
956 }
957
958 if (rate > data->max_fb_rate) {
959 use_fb_prediv = true;
960 rate /= 2;
961 } else {
962 use_fb_prediv = false;
963 }
964
965 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv);
966
967 for (i = 3; i >= 0; i--)
968 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);
969
970 was_using_prediv = ana[1] & data->ana->fb_prediv_mask;
971
972 ana[0] &= ~data->ana->mask0;
973 ana[0] |= data->ana->set0;
974 ana[1] &= ~data->ana->mask1;
975 ana[1] |= data->ana->set1;
976 ana[3] &= ~data->ana->mask3;
977 ana[3] |= data->ana->set3;
978
979 if (was_using_prediv && !use_fb_prediv) {
980 ana[1] &= ~data->ana->fb_prediv_mask;
981 do_ana_setup_first = true;
982 } else if (!was_using_prediv && use_fb_prediv) {
983 ana[1] |= data->ana->fb_prediv_mask;
984 do_ana_setup_first = false;
985 } else {
986 do_ana_setup_first = true;
987 }
988
989 /* Unmask the reference clock from the oscillator. */
990 cprman_write(cprman, A2W_XOSC_CTRL,
991 cprman_read(cprman, A2W_XOSC_CTRL) |
992 data->reference_enable_mask);
993
994 if (do_ana_setup_first)
995 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
996
997 /* Set the PLL multiplier from the oscillator. */
998 cprman_write(cprman, data->frac_reg, fdiv);
999
1000 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg);
1001 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK;
1002 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT;
1003 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK;
1004 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT;
1005 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl);
1006
1007 if (!do_ana_setup_first)
1008 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
1009
1010 return 0;
1011}
1012
1013static const struct clk_ops bcm2835_pll_clk_ops = {
1014 .is_prepared = bcm2835_pll_is_on,
1015 .prepare = bcm2835_pll_on,
1016 .unprepare = bcm2835_pll_off,
1017 .recalc_rate = bcm2835_pll_get_rate,
1018 .set_rate = bcm2835_pll_set_rate,
1019 .round_rate = bcm2835_pll_round_rate,
1020};
1021
1022struct bcm2835_pll_divider {
1023 struct clk_divider div;
1024 struct bcm2835_cprman *cprman;
1025 const struct bcm2835_pll_divider_data *data;
1026};
1027
1028static struct bcm2835_pll_divider *
1029bcm2835_pll_divider_from_hw(struct clk_hw *hw)
1030{
1031 return container_of(hw, struct bcm2835_pll_divider, div.hw);
1032}
1033
1034static int bcm2835_pll_divider_is_on(struct clk_hw *hw)
1035{
1036 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
1037 struct bcm2835_cprman *cprman = divider->cprman;
1038 const struct bcm2835_pll_divider_data *data = divider->data;
1039
1040 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
1041}
1042
1043static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
1044 unsigned long rate,
1045 unsigned long *parent_rate)
1046{
1047 return clk_divider_ops.round_rate(hw, rate, parent_rate);
1048}
1049
1050static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
1051 unsigned long parent_rate)
1052{
1053 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
1054 struct bcm2835_cprman *cprman = divider->cprman;
1055 const struct bcm2835_pll_divider_data *data = divider->data;
1056 u32 div = cprman_read(cprman, data->a2w_reg);
1057
1058 div &= (1 << A2W_PLL_DIV_BITS) - 1;
1059 if (div == 0)
1060 div = 256;
1061
1062 return parent_rate / div;
1063}
1064
1065static void bcm2835_pll_divider_off(struct clk_hw *hw)
1066{
1067 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
1068 struct bcm2835_cprman *cprman = divider->cprman;
1069 const struct bcm2835_pll_divider_data *data = divider->data;
1070
1071 cprman_write(cprman, data->cm_reg,
1072 (cprman_read(cprman, data->cm_reg) &
1073 ~data->load_mask) | data->hold_mask);
1074 cprman_write(cprman, data->a2w_reg, A2W_PLL_CHANNEL_DISABLE);
1075}
1076
1077static int bcm2835_pll_divider_on(struct clk_hw *hw)
1078{
1079 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
1080 struct bcm2835_cprman *cprman = divider->cprman;
1081 const struct bcm2835_pll_divider_data *data = divider->data;
1082
1083 cprman_write(cprman, data->a2w_reg,
1084 cprman_read(cprman, data->a2w_reg) &
1085 ~A2W_PLL_CHANNEL_DISABLE);
1086
1087 cprman_write(cprman, data->cm_reg,
1088 cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
1089
1090 return 0;
1091}
1092
1093static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
1094 unsigned long rate,
1095 unsigned long parent_rate)
1096{
1097 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
1098 struct bcm2835_cprman *cprman = divider->cprman;
1099 const struct bcm2835_pll_divider_data *data = divider->data;
1100 u32 cm;
1101 int ret;
1102
1103 ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
1104 if (ret)
1105 return ret;
1106
1107 cm = cprman_read(cprman, data->cm_reg);
1108 cprman_write(cprman, data->cm_reg, cm | data->load_mask);
1109 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
1110
1111 return 0;
1112}
1113
1114static const struct clk_ops bcm2835_pll_divider_clk_ops = {
1115 .is_prepared = bcm2835_pll_divider_is_on,
1116 .prepare = bcm2835_pll_divider_on,
1117 .unprepare = bcm2835_pll_divider_off,
1118 .recalc_rate = bcm2835_pll_divider_get_rate,
1119 .set_rate = bcm2835_pll_divider_set_rate,
1120 .round_rate = bcm2835_pll_divider_round_rate,
1121};
1122
1123/*
1124 * The CM dividers do fixed-point division, so we can't use the
1125 * generic integer divider code like the PLL dividers do (and we can't
1126 * fake it by having some fixed shifts preceding it in the clock tree,
1127 * because we'd run out of bits in a 32-bit unsigned long).
1128 */
1129struct bcm2835_clock {
1130 struct clk_hw hw;
1131 struct bcm2835_cprman *cprman;
1132 const struct bcm2835_clock_data *data;
1133};
1134
1135static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw)
1136{
1137 return container_of(hw, struct bcm2835_clock, hw);
1138}
1139
1140static int bcm2835_clock_is_on(struct clk_hw *hw)
1141{
1142 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1143 struct bcm2835_cprman *cprman = clock->cprman;
1144 const struct bcm2835_clock_data *data = clock->data;
1145
1146 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;
1147}
1148
1149static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
1150 unsigned long rate,
1151 unsigned long parent_rate)
1152{
1153 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1154 const struct bcm2835_clock_data *data = clock->data;
1155 u32 unused_frac_mask = GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0);
1156 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
1157 u32 div;
1158
1159 do_div(temp, rate);
1160 div = temp;
1161
1162 /* Round and mask off the unused bits */
1163 if (unused_frac_mask != 0) {
1164 div += unused_frac_mask >> 1;
1165 div &= ~unused_frac_mask;
1166 }
1167
1168 /* Clamp to the limits. */
1169 div = max(div, unused_frac_mask + 1);
1170 div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
1171 CM_DIV_FRAC_BITS - data->frac_bits));
1172
1173 return div;
1174}
1175
1176static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
1177 unsigned long parent_rate,
1178 u32 div)
1179{
1180 const struct bcm2835_clock_data *data = clock->data;
1181 u64 temp;
1182
1183 /*
1184 * The divisor is a 12.12 fixed point field, but only some of
1185 * the bits are populated in any given clock.
1186 */
1187 div >>= CM_DIV_FRAC_BITS - data->frac_bits;
1188 div &= (1 << (data->int_bits + data->frac_bits)) - 1;
1189
1190 if (div == 0)
1191 return 0;
1192
1193 temp = (u64)parent_rate << data->frac_bits;
1194
1195 do_div(temp, div);
1196
1197 return temp;
1198}
1199
1200static long bcm2835_clock_round_rate(struct clk_hw *hw,
1201 unsigned long rate,
1202 unsigned long *parent_rate)
1203{
1204 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1205 u32 div = bcm2835_clock_choose_div(hw, rate, *parent_rate);
1206
1207 return bcm2835_clock_rate_from_divisor(clock, *parent_rate, div);
1208}
1209
1210static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
1211 unsigned long parent_rate)
1212{
1213 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1214 struct bcm2835_cprman *cprman = clock->cprman;
1215 const struct bcm2835_clock_data *data = clock->data;
1216 u32 div = cprman_read(cprman, data->div_reg);
1217
1218 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
1219}
1220
1221static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
1222{
1223 struct bcm2835_cprman *cprman = clock->cprman;
1224 const struct bcm2835_clock_data *data = clock->data;
1225 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
1226
1227 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {
1228 if (ktime_after(ktime_get(), timeout)) {
1229 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
1230 clk_hw_get_name(&clock->hw));
1231 return;
1232 }
1233 cpu_relax();
1234 }
1235}
1236
1237static void bcm2835_clock_off(struct clk_hw *hw)
1238{
1239 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1240 struct bcm2835_cprman *cprman = clock->cprman;
1241 const struct bcm2835_clock_data *data = clock->data;
1242
1243 spin_lock(&cprman->regs_lock);
1244 cprman_write(cprman, data->ctl_reg,
1245 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);
1246 spin_unlock(&cprman->regs_lock);
1247
1248 /* BUSY will remain high until the divider completes its cycle. */
1249 bcm2835_clock_wait_busy(clock);
1250}
1251
1252static int bcm2835_clock_on(struct clk_hw *hw)
1253{
1254 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1255 struct bcm2835_cprman *cprman = clock->cprman;
1256 const struct bcm2835_clock_data *data = clock->data;
1257
1258 spin_lock(&cprman->regs_lock);
1259 cprman_write(cprman, data->ctl_reg,
1260 cprman_read(cprman, data->ctl_reg) |
1261 CM_ENABLE |
1262 CM_GATE);
1263 spin_unlock(&cprman->regs_lock);
1264
1265 return 0;
1266}
1267
1268static int bcm2835_clock_set_rate(struct clk_hw *hw,
1269 unsigned long rate, unsigned long parent_rate)
1270{
1271 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1272 struct bcm2835_cprman *cprman = clock->cprman;
1273 const struct bcm2835_clock_data *data = clock->data;
1274 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate);
1275
1276 cprman_write(cprman, data->div_reg, div);
1277
1278 return 0;
1279}
1280
1281static const struct clk_ops bcm2835_clock_clk_ops = {
1282 .is_prepared = bcm2835_clock_is_on,
1283 .prepare = bcm2835_clock_on,
1284 .unprepare = bcm2835_clock_off,
1285 .recalc_rate = bcm2835_clock_get_rate,
1286 .set_rate = bcm2835_clock_set_rate,
1287 .round_rate = bcm2835_clock_round_rate,
1288};
1289
1290static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
1291{
1292 return true;
1293}
1294
1295/*
1296 * The VPU clock can never be disabled (it doesn't have an ENABLE
1297 * bit), so it gets its own set of clock ops.
1298 */
1299static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
1300 .is_prepared = bcm2835_vpu_clock_is_on,
1301 .recalc_rate = bcm2835_clock_get_rate,
1302 .set_rate = bcm2835_clock_set_rate,
1303 .round_rate = bcm2835_clock_round_rate,
1304};
1305
1306static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman,
1307 const struct bcm2835_pll_data *data)
1308{
1309 struct bcm2835_pll *pll;
1310 struct clk_init_data init;
1311
1312 memset(&init, 0, sizeof(init));
1313
1314 /* All of the PLLs derive from the external oscillator. */
1315 init.parent_names = &cprman->osc_name;
1316 init.num_parents = 1;
1317 init.name = data->name;
1318 init.ops = &bcm2835_pll_clk_ops;
1319 init.flags = CLK_IGNORE_UNUSED;
1320
1321 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1322 if (!pll)
1323 return NULL;
1324
1325 pll->cprman = cprman;
1326 pll->data = data;
1327 pll->hw.init = &init;
1328
1329 return devm_clk_register(cprman->dev, &pll->hw);
1330}
1331
1332static struct clk *
1333bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
1334 const struct bcm2835_pll_divider_data *data)
1335{
1336 struct bcm2835_pll_divider *divider;
1337 struct clk_init_data init;
1338 struct clk *clk;
1339 const char *divider_name;
1340
1341 if (data->fixed_divider != 1) {
1342 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,
1343 "%s_prediv", data->name);
1344 if (!divider_name)
1345 return NULL;
1346 } else {
1347 divider_name = data->name;
1348 }
1349
1350 memset(&init, 0, sizeof(init));
1351
1352 init.parent_names = &data->source_pll->name;
1353 init.num_parents = 1;
1354 init.name = divider_name;
1355 init.ops = &bcm2835_pll_divider_clk_ops;
1356 init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED;
1357
1358 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
1359 if (!divider)
1360 return NULL;
1361
1362 divider->div.reg = cprman->regs + data->a2w_reg;
1363 divider->div.shift = A2W_PLL_DIV_SHIFT;
1364 divider->div.width = A2W_PLL_DIV_BITS;
1365 divider->div.flags = 0;
1366 divider->div.lock = &cprman->regs_lock;
1367 divider->div.hw.init = &init;
1368 divider->div.table = NULL;
1369
1370 divider->cprman = cprman;
1371 divider->data = data;
1372
1373 clk = devm_clk_register(cprman->dev, &divider->div.hw);
1374 if (IS_ERR(clk))
1375 return clk;
1376
1377 /*
1378 * PLLH's channels have a fixed divide by 10 afterwards, which
1379 * is what our consumers are actually using.
1380 */
1381 if (data->fixed_divider != 1) {
1382 return clk_register_fixed_factor(cprman->dev, data->name,
1383 divider_name,
1384 CLK_SET_RATE_PARENT,
1385 1,
1386 data->fixed_divider);
1387 }
1388
1389 return clk;
1390}
1391
1392static struct clk *bcm2835_register_clock(struct bcm2835_cprman *cprman,
1393 const struct bcm2835_clock_data *data)
1394{
1395 struct bcm2835_clock *clock;
1396 struct clk_init_data init;
1397 const char *parent;
1398
1399 /*
1400 * Most of the clock generators have a mux field, so we
1401 * instantiate a generic mux as our parent to handle it.
1402 */
1403 if (data->num_mux_parents) {
1404 const char *parents[1 << CM_SRC_BITS];
1405 int i;
1406
1407 parent = devm_kasprintf(cprman->dev, GFP_KERNEL,
1408 "mux_%s", data->name);
1409 if (!parent)
1410 return NULL;
1411
1412 /*
1413 * Replace our "xosc" references with the oscillator's
1414 * actual name.
1415 */
1416 for (i = 0; i < data->num_mux_parents; i++) {
1417 if (strcmp(data->parents[i], "xosc") == 0)
1418 parents[i] = cprman->osc_name;
1419 else
1420 parents[i] = data->parents[i];
1421 }
1422
1423 clk_register_mux(cprman->dev, parent,
1424 parents, data->num_mux_parents,
1425 CLK_SET_RATE_PARENT,
1426 cprman->regs + data->ctl_reg,
1427 CM_SRC_SHIFT, CM_SRC_BITS,
1428 0, &cprman->regs_lock);
1429 } else {
1430 parent = data->parents[0];
1431 }
1432
1433 memset(&init, 0, sizeof(init));
1434 init.parent_names = &parent;
1435 init.num_parents = 1;
1436 init.name = data->name;
1437 init.flags = CLK_IGNORE_UNUSED;
1438
1439 if (data->is_vpu_clock) {
1440 init.ops = &bcm2835_vpu_clock_clk_ops;
1441 } else {
1442 init.ops = &bcm2835_clock_clk_ops;
1443 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
1444 }
1445
1446 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);
1447 if (!clock)
1448 return NULL;
1449
1450 clock->cprman = cprman;
1451 clock->data = data;
1452 clock->hw.init = &init;
1453
1454 return devm_clk_register(cprman->dev, &clock->hw);
1455}
1456
1457static int bcm2835_clk_probe(struct platform_device *pdev)
1458{
1459 struct device *dev = &pdev->dev;
1460 struct clk **clks;
1461 struct bcm2835_cprman *cprman;
1462 struct resource *res;
1463
1464 cprman = devm_kzalloc(dev, sizeof(*cprman), GFP_KERNEL);
1465 if (!cprman)
1466 return -ENOMEM;
1467
1468 spin_lock_init(&cprman->regs_lock);
1469 cprman->dev = dev;
1470 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1471 cprman->regs = devm_ioremap_resource(dev, res);
1472 if (IS_ERR(cprman->regs))
1473 return PTR_ERR(cprman->regs);
1474
1475 cprman->osc_name = of_clk_get_parent_name(dev->of_node, 0);
1476 if (!cprman->osc_name)
1477 return -ENODEV;
1478
1479 platform_set_drvdata(pdev, cprman);
1480
1481 cprman->onecell.clk_num = BCM2835_CLOCK_COUNT;
1482 cprman->onecell.clks = cprman->clks;
1483 clks = cprman->clks;
1484
1485 clks[BCM2835_PLLA] = bcm2835_register_pll(cprman, &bcm2835_plla_data);
1486 clks[BCM2835_PLLB] = bcm2835_register_pll(cprman, &bcm2835_pllb_data);
1487 clks[BCM2835_PLLC] = bcm2835_register_pll(cprman, &bcm2835_pllc_data);
1488 clks[BCM2835_PLLD] = bcm2835_register_pll(cprman, &bcm2835_plld_data);
1489 clks[BCM2835_PLLH] = bcm2835_register_pll(cprman, &bcm2835_pllh_data);
1490
1491 clks[BCM2835_PLLA_CORE] =
1492 bcm2835_register_pll_divider(cprman, &bcm2835_plla_core_data);
1493 clks[BCM2835_PLLA_PER] =
1494 bcm2835_register_pll_divider(cprman, &bcm2835_plla_per_data);
1495 clks[BCM2835_PLLC_CORE0] =
1496 bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core0_data);
1497 clks[BCM2835_PLLC_CORE1] =
1498 bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core1_data);
1499 clks[BCM2835_PLLC_CORE2] =
1500 bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core2_data);
1501 clks[BCM2835_PLLC_PER] =
1502 bcm2835_register_pll_divider(cprman, &bcm2835_pllc_per_data);
1503 clks[BCM2835_PLLD_CORE] =
1504 bcm2835_register_pll_divider(cprman, &bcm2835_plld_core_data);
1505 clks[BCM2835_PLLD_PER] =
1506 bcm2835_register_pll_divider(cprman, &bcm2835_plld_per_data);
1507 clks[BCM2835_PLLH_RCAL] =
1508 bcm2835_register_pll_divider(cprman, &bcm2835_pllh_rcal_data);
1509 clks[BCM2835_PLLH_AUX] =
1510 bcm2835_register_pll_divider(cprman, &bcm2835_pllh_aux_data);
1511 clks[BCM2835_PLLH_PIX] =
1512 bcm2835_register_pll_divider(cprman, &bcm2835_pllh_pix_data);
1513
1514 clks[BCM2835_CLOCK_TIMER] =
1515 bcm2835_register_clock(cprman, &bcm2835_clock_timer_data);
1516 clks[BCM2835_CLOCK_OTP] =
1517 bcm2835_register_clock(cprman, &bcm2835_clock_otp_data);
1518 clks[BCM2835_CLOCK_TSENS] =
1519 bcm2835_register_clock(cprman, &bcm2835_clock_tsens_data);
1520 clks[BCM2835_CLOCK_VPU] =
1521 bcm2835_register_clock(cprman, &bcm2835_clock_vpu_data);
1522 clks[BCM2835_CLOCK_V3D] =
1523 bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
1524 clks[BCM2835_CLOCK_ISP] =
1525 bcm2835_register_clock(cprman, &bcm2835_clock_isp_data);
1526 clks[BCM2835_CLOCK_H264] =
1527 bcm2835_register_clock(cprman, &bcm2835_clock_h264_data);
1528 clks[BCM2835_CLOCK_V3D] =
1529 bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
1530 clks[BCM2835_CLOCK_SDRAM] =
1531 bcm2835_register_clock(cprman, &bcm2835_clock_sdram_data);
1532 clks[BCM2835_CLOCK_UART] =
1533 bcm2835_register_clock(cprman, &bcm2835_clock_uart_data);
1534 clks[BCM2835_CLOCK_VEC] =
1535 bcm2835_register_clock(cprman, &bcm2835_clock_vec_data);
1536 clks[BCM2835_CLOCK_HSM] =
1537 bcm2835_register_clock(cprman, &bcm2835_clock_hsm_data);
1538 clks[BCM2835_CLOCK_EMMC] =
1539 bcm2835_register_clock(cprman, &bcm2835_clock_emmc_data);
1540
1541 /*
1542 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
1543 * you have the debug bit set in the power manager, which we
1544 * don't bother exposing) are individual gates off of the
1545 * non-stop vpu clock.
1546 */
1547 clks[BCM2835_CLOCK_PERI_IMAGE] =
1548 clk_register_gate(dev, "peri_image", "vpu",
1549 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1550 cprman->regs + CM_PERIICTL, CM_GATE_BIT,
1551 0, &cprman->regs_lock);
1552
1553 return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
1554 &cprman->onecell);
1555}
1556
1557static const struct of_device_id bcm2835_clk_of_match[] = {
1558 { .compatible = "brcm,bcm2835-cprman", },
1559 {}
1560};
1561MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
1562
1563static struct platform_driver bcm2835_clk_driver = {
1564 .driver = {
1565 .name = "bcm2835-clk",
1566 .of_match_table = bcm2835_clk_of_match,
1567 },
1568 .probe = bcm2835_clk_probe,
1569};
1570
1571builtin_platform_driver(bcm2835_clk_driver);
1572
1573MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
1574MODULE_DESCRIPTION("BCM2835 clock driver");
1575MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/clk-bcm2835.c b/drivers/clk/clk-bcm2835.c
deleted file mode 100644
index dd295e498309..000000000000
--- a/drivers/clk/clk-bcm2835.c
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * Copyright (C) 2010 Broadcom
3 * Copyright (C) 2012 Stephen Warren
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/clk-provider.h>
21#include <linux/clkdev.h>
22#include <linux/clk/bcm2835.h>
23#include <linux/of.h>
24
25/*
26 * These are fixed clocks. They're probably not all root clocks and it may
27 * be possible to turn them on and off but until this is mapped out better
28 * it's the only way they can be used.
29 */
30void __init bcm2835_init_clocks(void)
31{
32 struct clk *clk;
33 int ret;
34
35 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT,
36 126000000);
37 if (IS_ERR(clk))
38 pr_err("apb_pclk not registered\n");
39
40 clk = clk_register_fixed_rate(NULL, "uart0_pclk", NULL, CLK_IS_ROOT,
41 3000000);
42 if (IS_ERR(clk))
43 pr_err("uart0_pclk not registered\n");
44 ret = clk_register_clkdev(clk, NULL, "20201000.uart");
45 if (ret)
46 pr_err("uart0_pclk alias not registered\n");
47
48 clk = clk_register_fixed_rate(NULL, "uart1_pclk", NULL, CLK_IS_ROOT,
49 125000000);
50 if (IS_ERR(clk))
51 pr_err("uart1_pclk not registered\n");
52 ret = clk_register_clkdev(clk, NULL, "20215000.uart");
53 if (ret)
54 pr_err("uart1_pclk alias not registered\n");
55}
diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
new file mode 100644
index 000000000000..d323efac7edf
--- /dev/null
+++ b/include/dt-bindings/clock/bcm2835.h
@@ -0,0 +1,47 @@
1/*
2 * Copyright (C) 2015 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#define BCM2835_PLLA 0
15#define BCM2835_PLLB 1
16#define BCM2835_PLLC 2
17#define BCM2835_PLLD 3
18#define BCM2835_PLLH 4
19
20#define BCM2835_PLLA_CORE 5
21#define BCM2835_PLLA_PER 6
22#define BCM2835_PLLB_ARM 7
23#define BCM2835_PLLC_CORE0 8
24#define BCM2835_PLLC_CORE1 9
25#define BCM2835_PLLC_CORE2 10
26#define BCM2835_PLLC_PER 11
27#define BCM2835_PLLD_CORE 12
28#define BCM2835_PLLD_PER 13
29#define BCM2835_PLLH_RCAL 14
30#define BCM2835_PLLH_AUX 15
31#define BCM2835_PLLH_PIX 16
32
33#define BCM2835_CLOCK_TIMER 17
34#define BCM2835_CLOCK_OTP 18
35#define BCM2835_CLOCK_UART 19
36#define BCM2835_CLOCK_VPU 20
37#define BCM2835_CLOCK_V3D 21
38#define BCM2835_CLOCK_ISP 22
39#define BCM2835_CLOCK_H264 23
40#define BCM2835_CLOCK_VEC 24
41#define BCM2835_CLOCK_HSM 25
42#define BCM2835_CLOCK_SDRAM 26
43#define BCM2835_CLOCK_TSENS 27
44#define BCM2835_CLOCK_EMMC 28
45#define BCM2835_CLOCK_PERI_IMAGE 29
46
47#define BCM2835_CLOCK_COUNT 30
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 02:05:00 -0400