diff options
author | Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> | 2018-04-26 07:51:31 -0400 |
---|---|---|
committer | Eduardo Valentin <edubezval@gmail.com> | 2018-05-06 19:46:22 -0400 |
commit | 64e94192451ea5810768797e002021950f671ae0 (patch) | |
tree | 3589888c393a9bfad1555a55e052811c31e5d85f | |
parent | 89335c203a8d45a9380c9fec4cdc8cda404569ad (diff) |
thermal: exynos: cleanup code for enabling threshold interrupts
Cleanup code for enabling threshold interrupts in ->tmu_control
method implementations.
There should be no functional changes caused by this patch.
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
-rw-r--r-- | drivers/thermal/samsung/exynos_tmu.c | 98 |
1 files changed, 33 insertions, 65 deletions
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index ff72f71a0078..f72b5ed15926 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c | |||
@@ -76,9 +76,6 @@ | |||
76 | #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 | 76 | #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 |
77 | 77 | ||
78 | #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 | 78 | #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 |
79 | #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4 | ||
80 | #define EXYNOS_TMU_INTEN_RISE2_SHIFT 8 | ||
81 | #define EXYNOS_TMU_INTEN_RISE3_SHIFT 12 | ||
82 | #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 | 79 | #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 |
83 | 80 | ||
84 | #define EXYNOS_EMUL_TIME 0x57F0 | 81 | #define EXYNOS_EMUL_TIME 0x57F0 |
@@ -136,13 +133,6 @@ | |||
136 | #define EXYNOS7_TMU_TEMP_MASK 0x1ff | 133 | #define EXYNOS7_TMU_TEMP_MASK 0x1ff |
137 | #define EXYNOS7_PD_DET_EN_SHIFT 23 | 134 | #define EXYNOS7_PD_DET_EN_SHIFT 23 |
138 | #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 | 135 | #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 |
139 | #define EXYNOS7_TMU_INTEN_RISE1_SHIFT 1 | ||
140 | #define EXYNOS7_TMU_INTEN_RISE2_SHIFT 2 | ||
141 | #define EXYNOS7_TMU_INTEN_RISE3_SHIFT 3 | ||
142 | #define EXYNOS7_TMU_INTEN_RISE4_SHIFT 4 | ||
143 | #define EXYNOS7_TMU_INTEN_RISE5_SHIFT 5 | ||
144 | #define EXYNOS7_TMU_INTEN_RISE6_SHIFT 6 | ||
145 | #define EXYNOS7_TMU_INTEN_RISE7_SHIFT 7 | ||
146 | #define EXYNOS7_EMUL_DATA_SHIFT 7 | 136 | #define EXYNOS7_EMUL_DATA_SHIFT 7 |
147 | #define EXYNOS7_EMUL_DATA_MASK 0x1ff | 137 | #define EXYNOS7_EMUL_DATA_MASK 0x1ff |
148 | 138 | ||
@@ -615,29 +605,28 @@ static void exynos4210_tmu_control(struct platform_device *pdev, bool on) | |||
615 | { | 605 | { |
616 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | 606 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
617 | struct thermal_zone_device *tz = data->tzd; | 607 | struct thermal_zone_device *tz = data->tzd; |
618 | unsigned int con, interrupt_en; | 608 | unsigned int con, interrupt_en = 0, i; |
619 | 609 | ||
620 | con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); | 610 | con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); |
621 | 611 | ||
622 | if (on) { | 612 | if (on) { |
623 | con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); | 613 | for (i = 0; i < data->ntrip; i++) { |
624 | interrupt_en = | 614 | if (!of_thermal_is_trip_valid(tz, i)) |
625 | (of_thermal_is_trip_valid(tz, 3) | 615 | continue; |
626 | << EXYNOS_TMU_INTEN_RISE3_SHIFT) | | 616 | |
627 | (of_thermal_is_trip_valid(tz, 2) | 617 | interrupt_en |= |
628 | << EXYNOS_TMU_INTEN_RISE2_SHIFT) | | 618 | (1 << (EXYNOS_TMU_INTEN_RISE0_SHIFT + i * 4)); |
629 | (of_thermal_is_trip_valid(tz, 1) | 619 | } |
630 | << EXYNOS_TMU_INTEN_RISE1_SHIFT) | | ||
631 | (of_thermal_is_trip_valid(tz, 0) | ||
632 | << EXYNOS_TMU_INTEN_RISE0_SHIFT); | ||
633 | 620 | ||
634 | if (data->soc != SOC_ARCH_EXYNOS4210) | 621 | if (data->soc != SOC_ARCH_EXYNOS4210) |
635 | interrupt_en |= | 622 | interrupt_en |= |
636 | interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; | 623 | interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; |
624 | |||
625 | con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); | ||
637 | } else { | 626 | } else { |
638 | con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); | 627 | con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); |
639 | interrupt_en = 0; /* Disable all interrupts */ | ||
640 | } | 628 | } |
629 | |||
641 | writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); | 630 | writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); |
642 | writel(con, data->base + EXYNOS_TMU_REG_CONTROL); | 631 | writel(con, data->base + EXYNOS_TMU_REG_CONTROL); |
643 | } | 632 | } |
@@ -646,36 +635,25 @@ static void exynos5433_tmu_control(struct platform_device *pdev, bool on) | |||
646 | { | 635 | { |
647 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | 636 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
648 | struct thermal_zone_device *tz = data->tzd; | 637 | struct thermal_zone_device *tz = data->tzd; |
649 | unsigned int con, interrupt_en, pd_det_en; | 638 | unsigned int con, interrupt_en = 0, pd_det_en, i; |
650 | 639 | ||
651 | con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); | 640 | con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); |
652 | 641 | ||
653 | if (on) { | 642 | if (on) { |
654 | con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); | 643 | for (i = 0; i < data->ntrip; i++) { |
655 | interrupt_en = | 644 | if (!of_thermal_is_trip_valid(tz, i)) |
656 | (of_thermal_is_trip_valid(tz, 7) | 645 | continue; |
657 | << EXYNOS7_TMU_INTEN_RISE7_SHIFT) | | 646 | |
658 | (of_thermal_is_trip_valid(tz, 6) | 647 | interrupt_en |= |
659 | << EXYNOS7_TMU_INTEN_RISE6_SHIFT) | | 648 | (1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i)); |
660 | (of_thermal_is_trip_valid(tz, 5) | 649 | } |
661 | << EXYNOS7_TMU_INTEN_RISE5_SHIFT) | | ||
662 | (of_thermal_is_trip_valid(tz, 4) | ||
663 | << EXYNOS7_TMU_INTEN_RISE4_SHIFT) | | ||
664 | (of_thermal_is_trip_valid(tz, 3) | ||
665 | << EXYNOS7_TMU_INTEN_RISE3_SHIFT) | | ||
666 | (of_thermal_is_trip_valid(tz, 2) | ||
667 | << EXYNOS7_TMU_INTEN_RISE2_SHIFT) | | ||
668 | (of_thermal_is_trip_valid(tz, 1) | ||
669 | << EXYNOS7_TMU_INTEN_RISE1_SHIFT) | | ||
670 | (of_thermal_is_trip_valid(tz, 0) | ||
671 | << EXYNOS7_TMU_INTEN_RISE0_SHIFT); | ||
672 | 650 | ||
673 | interrupt_en |= | 651 | interrupt_en |= |
674 | interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; | 652 | interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; |
675 | } else { | 653 | |
654 | con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); | ||
655 | } else | ||
676 | con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); | 656 | con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); |
677 | interrupt_en = 0; /* Disable all interrupts */ | ||
678 | } | ||
679 | 657 | ||
680 | pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0; | 658 | pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0; |
681 | 659 | ||
@@ -688,37 +666,27 @@ static void exynos7_tmu_control(struct platform_device *pdev, bool on) | |||
688 | { | 666 | { |
689 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | 667 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
690 | struct thermal_zone_device *tz = data->tzd; | 668 | struct thermal_zone_device *tz = data->tzd; |
691 | unsigned int con, interrupt_en; | 669 | unsigned int con, interrupt_en = 0, i; |
692 | 670 | ||
693 | con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); | 671 | con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); |
694 | 672 | ||
695 | if (on) { | 673 | if (on) { |
696 | con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); | 674 | for (i = 0; i < data->ntrip; i++) { |
697 | con |= (1 << EXYNOS7_PD_DET_EN_SHIFT); | 675 | if (!of_thermal_is_trip_valid(tz, i)) |
698 | interrupt_en = | 676 | continue; |
699 | (of_thermal_is_trip_valid(tz, 7) | 677 | |
700 | << EXYNOS7_TMU_INTEN_RISE7_SHIFT) | | 678 | interrupt_en |= |
701 | (of_thermal_is_trip_valid(tz, 6) | 679 | (1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i)); |
702 | << EXYNOS7_TMU_INTEN_RISE6_SHIFT) | | 680 | } |
703 | (of_thermal_is_trip_valid(tz, 5) | ||
704 | << EXYNOS7_TMU_INTEN_RISE5_SHIFT) | | ||
705 | (of_thermal_is_trip_valid(tz, 4) | ||
706 | << EXYNOS7_TMU_INTEN_RISE4_SHIFT) | | ||
707 | (of_thermal_is_trip_valid(tz, 3) | ||
708 | << EXYNOS7_TMU_INTEN_RISE3_SHIFT) | | ||
709 | (of_thermal_is_trip_valid(tz, 2) | ||
710 | << EXYNOS7_TMU_INTEN_RISE2_SHIFT) | | ||
711 | (of_thermal_is_trip_valid(tz, 1) | ||
712 | << EXYNOS7_TMU_INTEN_RISE1_SHIFT) | | ||
713 | (of_thermal_is_trip_valid(tz, 0) | ||
714 | << EXYNOS7_TMU_INTEN_RISE0_SHIFT); | ||
715 | 681 | ||
716 | interrupt_en |= | 682 | interrupt_en |= |
717 | interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; | 683 | interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; |
684 | |||
685 | con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); | ||
686 | con |= (1 << EXYNOS7_PD_DET_EN_SHIFT); | ||
718 | } else { | 687 | } else { |
719 | con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); | 688 | con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); |
720 | con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT); | 689 | con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT); |
721 | interrupt_en = 0; /* Disable all interrupts */ | ||
722 | } | 690 | } |
723 | 691 | ||
724 | writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN); | 692 | writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN); |