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authorAndrzej Hajda <a.hajda@samsung.com>2017-01-20 01:52:19 -0500
committerInki Dae <inki.dae@samsung.com>2017-02-06 23:52:49 -0500
commit648225880264fde99eba8e57f6ac81801be1405d (patch)
treeaa0025bd3bc8d4e0a8152c8a324faad2e042f8f0
parentd796ddc9ea0c88f7a1cc1e8df10553f8bbc6ba6b (diff)
drm/exynos/hdmi: add 297MHz pixel clock support
297MHz is used by Ultra HD modes. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
-rw-r--r--drivers/gpu/drm/exynos/exynos_hdmi.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 5ed8b1effe71..bef8965c9f53 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -587,6 +587,15 @@ static const struct hdmiphy_config hdmiphy_5433_configs[] = {
587 0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40, 587 0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40,
588 }, 588 },
589 }, 589 },
590 {
591 .pixel_clock = 297000000,
592 .conf = {
593 0x01, 0x51, 0x3E, 0x05, 0x40, 0xF0, 0x88, 0xC2,
594 0x52, 0x53, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
595 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
596 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
597 },
598 },
590}; 599};
591 600
592static const char * const hdmi_clk_gates4[] = { 601static const char * const hdmi_clk_gates4[] = {