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authorChen-Yu Tsai <wens@csie.org>2017-01-28 07:22:39 -0500
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-01-30 02:39:22 -0500
commit64507fe38de3eb7ed60f26843e0ddf1c565a9b21 (patch)
tree231fad27b0831b5cebf3fbb2067f8b3f1070107f
parent783ab76ae553abc23f80ef7511052d055697531b (diff)
ARM: dts: sun9i: Switch to new clock bindings
Now that we have a full clock driver for sun9i, switch to it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/sun9i-a80.dtsi404
1 files changed, 107 insertions, 297 deletions
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 979ad1aacfb1..cee403294d0e 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -48,6 +48,13 @@
48 48
49#include <dt-bindings/pinctrl/sun4i-a10.h> 49#include <dt-bindings/pinctrl/sun4i-a10.h>
50 50
51#include <dt-bindings/clock/sun9i-a80-ccu.h>
52#include <dt-bindings/clock/sun9i-a80-de.h>
53#include <dt-bindings/clock/sun9i-a80-usb.h>
54#include <dt-bindings/reset/sun9i-a80-ccu.h>
55#include <dt-bindings/reset/sun9i-a80-de.h>
56#include <dt-bindings/reset/sun9i-a80-usb.h>
57
51/ { 58/ {
52 interrupt-parent = <&gic>; 59 interrupt-parent = <&gic>;
53 60
@@ -159,228 +166,13 @@
159 clock-output-names = "osc32k"; 166 clock-output-names = "osc32k";
160 }; 167 };
161 168
162 usb_mod_clk: clk@00a08000 {
163 #clock-cells = <1>;
164 #reset-cells = <1>;
165 compatible = "allwinner,sun9i-a80-usb-mod-clk";
166 reg = <0x00a08000 0x4>;
167 clocks = <&ahb1_gates 1>;
168 clock-output-names = "usb0_ahb", "usb_ohci0",
169 "usb1_ahb", "usb_ohci1",
170 "usb2_ahb", "usb_ohci2";
171 };
172
173 usb_phy_clk: clk@00a08004 {
174 #clock-cells = <1>;
175 #reset-cells = <1>;
176 compatible = "allwinner,sun9i-a80-usb-phy-clk";
177 reg = <0x00a08004 0x4>;
178 clocks = <&ahb1_gates 1>;
179 clock-output-names = "usb_phy0", "usb_hsic1_480M",
180 "usb_phy1", "usb_hsic2_480M",
181 "usb_phy2", "usb_hsic_12M";
182 };
183
184 pll3: clk@06000008 {
185 /* placeholder until implemented */
186 #clock-cells = <0>;
187 compatible = "fixed-clock";
188 clock-rate = <0>;
189 clock-output-names = "pll3";
190 };
191
192 pll4: clk@0600000c {
193 #clock-cells = <0>;
194 compatible = "allwinner,sun9i-a80-pll4-clk";
195 reg = <0x0600000c 0x4>;
196 clocks = <&osc24M>;
197 clock-output-names = "pll4";
198 };
199
200 pll12: clk@0600002c {
201 #clock-cells = <0>;
202 compatible = "allwinner,sun9i-a80-pll4-clk";
203 reg = <0x0600002c 0x4>;
204 clocks = <&osc24M>;
205 clock-output-names = "pll12";
206 };
207
208 gt_clk: clk@0600005c {
209 #clock-cells = <0>;
210 compatible = "allwinner,sun9i-a80-gt-clk";
211 reg = <0x0600005c 0x4>;
212 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
213 clock-output-names = "gt";
214 };
215
216 ahb0: clk@06000060 {
217 #clock-cells = <0>;
218 compatible = "allwinner,sun9i-a80-ahb-clk";
219 reg = <0x06000060 0x4>;
220 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
221 clock-output-names = "ahb0";
222 };
223
224 ahb1: clk@06000064 {
225 #clock-cells = <0>;
226 compatible = "allwinner,sun9i-a80-ahb-clk";
227 reg = <0x06000064 0x4>;
228 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
229 clock-output-names = "ahb1";
230 };
231
232 ahb2: clk@06000068 {
233 #clock-cells = <0>;
234 compatible = "allwinner,sun9i-a80-ahb-clk";
235 reg = <0x06000068 0x4>;
236 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
237 clock-output-names = "ahb2";
238 };
239
240 apb0: clk@06000070 {
241 #clock-cells = <0>;
242 compatible = "allwinner,sun9i-a80-apb0-clk";
243 reg = <0x06000070 0x4>;
244 clocks = <&osc24M>, <&pll4>;
245 clock-output-names = "apb0";
246 };
247
248 apb1: clk@06000074 {
249 #clock-cells = <0>;
250 compatible = "allwinner,sun9i-a80-apb1-clk";
251 reg = <0x06000074 0x4>;
252 clocks = <&osc24M>, <&pll4>;
253 clock-output-names = "apb1";
254 };
255
256 cci400_clk: clk@06000078 {
257 #clock-cells = <0>;
258 compatible = "allwinner,sun9i-a80-gt-clk";
259 reg = <0x06000078 0x4>;
260 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
261 clock-output-names = "cci400";
262 };
263
264 mmc0_clk: clk@06000410 {
265 #clock-cells = <1>;
266 compatible = "allwinner,sun9i-a80-mmc-clk";
267 reg = <0x06000410 0x4>;
268 clocks = <&osc24M>, <&pll4>;
269 clock-output-names = "mmc0", "mmc0_output",
270 "mmc0_sample";
271 };
272
273 mmc1_clk: clk@06000414 {
274 #clock-cells = <1>;
275 compatible = "allwinner,sun9i-a80-mmc-clk";
276 reg = <0x06000414 0x4>;
277 clocks = <&osc24M>, <&pll4>;
278 clock-output-names = "mmc1", "mmc1_output",
279 "mmc1_sample";
280 };
281
282 mmc2_clk: clk@06000418 {
283 #clock-cells = <1>;
284 compatible = "allwinner,sun9i-a80-mmc-clk";
285 reg = <0x06000418 0x4>;
286 clocks = <&osc24M>, <&pll4>;
287 clock-output-names = "mmc2", "mmc2_output",
288 "mmc2_sample";
289 };
290
291 mmc3_clk: clk@0600041c {
292 #clock-cells = <1>;
293 compatible = "allwinner,sun9i-a80-mmc-clk";
294 reg = <0x0600041c 0x4>;
295 clocks = <&osc24M>, <&pll4>;
296 clock-output-names = "mmc3", "mmc3_output",
297 "mmc3_sample";
298 };
299
300 ahb0_gates: clk@06000580 {
301 #clock-cells = <1>;
302 compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
303 reg = <0x06000580 0x4>;
304 clocks = <&ahb0>;
305 clock-indices = <0>, <1>, <3>,
306 <5>, <8>, <12>,
307 <13>, <14>,
308 <15>, <16>, <18>,
309 <20>, <21>, <22>,
310 <23>;
311 clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
312 "ahb0_ss", "ahb0_sd", "ahb0_nand1",
313 "ahb0_nand0", "ahb0_sdram",
314 "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
315 "ahb0_spi0", "ahb0_spi1", "ahb0_spi2",
316 "ahb0_spi3";
317 };
318
319 ahb1_gates: clk@06000584 {
320 #clock-cells = <1>;
321 compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
322 reg = <0x06000584 0x4>;
323 clocks = <&ahb1>;
324 clock-indices = <0>, <1>,
325 <17>, <21>,
326 <22>, <23>,
327 <24>;
328 clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
329 "ahb1_gmac", "ahb1_msgbox",
330 "ahb1_spinlock", "ahb1_hstimer",
331 "ahb1_dma";
332 };
333
334 ahb2_gates: clk@06000588 {
335 #clock-cells = <1>;
336 compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
337 reg = <0x06000588 0x4>;
338 clocks = <&ahb2>;
339 clock-indices = <0>, <1>,
340 <2>, <4>, <5>,
341 <7>, <8>, <11>;
342 clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
343 "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
344 "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
345 };
346
347 apb0_gates: clk@06000590 {
348 #clock-cells = <1>;
349 compatible = "allwinner,sun9i-a80-apb0-gates-clk";
350 reg = <0x06000590 0x4>;
351 clocks = <&apb0>;
352 clock-indices = <1>, <5>,
353 <11>, <12>, <13>,
354 <15>, <17>, <18>,
355 <19>;
356 clock-output-names = "apb0_spdif", "apb0_pio",
357 "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
358 "apb0_lradc", "apb0_gpadc", "apb0_twd",
359 "apb0_cirtx";
360 };
361
362 apb1_gates: clk@06000594 {
363 #clock-cells = <1>;
364 compatible = "allwinner,sun9i-a80-apb1-gates-clk";
365 reg = <0x06000594 0x4>;
366 clocks = <&apb1>;
367 clock-indices = <0>, <1>,
368 <2>, <3>, <4>,
369 <16>, <17>,
370 <18>, <19>,
371 <20>, <21>;
372 clock-output-names = "apb1_i2c0", "apb1_i2c1",
373 "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
374 "apb1_uart0", "apb1_uart1",
375 "apb1_uart2", "apb1_uart3",
376 "apb1_uart4", "apb1_uart5";
377 };
378
379 cpus_clk: clk@08001410 { 169 cpus_clk: clk@08001410 {
380 compatible = "allwinner,sun9i-a80-cpus-clk"; 170 compatible = "allwinner,sun9i-a80-cpus-clk";
381 reg = <0x08001410 0x4>; 171 reg = <0x08001410 0x4>;
382 #clock-cells = <0>; 172 #clock-cells = <0>;
383 clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>; 173 clocks = <&osc32k>, <&osc24M>,
174 <&ccu CLK_PLL_PERIPH0>,
175 <&ccu CLK_PLL_AUDIO>;
384 clock-output-names = "cpus"; 176 clock-output-names = "cpus";
385 }; 177 };
386 178
@@ -453,8 +245,8 @@
453 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; 245 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
454 reg = <0x00a00000 0x100>; 246 reg = <0x00a00000 0x100>;
455 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 247 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&usb_mod_clk 1>; 248 clocks = <&usb_clocks CLK_BUS_HCI0>;
457 resets = <&usb_mod_clk 17>; 249 resets = <&usb_clocks RST_USB0_HCI>;
458 phys = <&usbphy1>; 250 phys = <&usbphy1>;
459 phy-names = "usb"; 251 phy-names = "usb";
460 status = "disabled"; 252 status = "disabled";
@@ -464,8 +256,9 @@
464 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; 256 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
465 reg = <0x00a00400 0x100>; 257 reg = <0x00a00400 0x100>;
466 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 258 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>; 259 clocks = <&usb_clocks CLK_BUS_HCI0>,
468 resets = <&usb_mod_clk 17>; 260 <&usb_clocks CLK_USB_OHCI0>;
261 resets = <&usb_clocks RST_USB0_HCI>;
469 phys = <&usbphy1>; 262 phys = <&usbphy1>;
470 phy-names = "usb"; 263 phy-names = "usb";
471 status = "disabled"; 264 status = "disabled";
@@ -474,9 +267,9 @@
474 usbphy1: phy@00a00800 { 267 usbphy1: phy@00a00800 {
475 compatible = "allwinner,sun9i-a80-usb-phy"; 268 compatible = "allwinner,sun9i-a80-usb-phy";
476 reg = <0x00a00800 0x4>; 269 reg = <0x00a00800 0x4>;
477 clocks = <&usb_phy_clk 1>; 270 clocks = <&usb_clocks CLK_USB0_PHY>;
478 clock-names = "phy"; 271 clock-names = "phy";
479 resets = <&usb_phy_clk 17>; 272 resets = <&usb_clocks RST_USB0_PHY>;
480 reset-names = "phy"; 273 reset-names = "phy";
481 status = "disabled"; 274 status = "disabled";
482 #phy-cells = <0>; 275 #phy-cells = <0>;
@@ -486,8 +279,8 @@
486 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; 279 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
487 reg = <0x00a01000 0x100>; 280 reg = <0x00a01000 0x100>;
488 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 281 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&usb_mod_clk 3>; 282 clocks = <&usb_clocks CLK_BUS_HCI1>;
490 resets = <&usb_mod_clk 18>; 283 resets = <&usb_clocks RST_USB1_HCI>;
491 phys = <&usbphy2>; 284 phys = <&usbphy2>;
492 phy-names = "usb"; 285 phy-names = "usb";
493 status = "disabled"; 286 status = "disabled";
@@ -496,11 +289,16 @@
496 usbphy2: phy@00a01800 { 289 usbphy2: phy@00a01800 {
497 compatible = "allwinner,sun9i-a80-usb-phy"; 290 compatible = "allwinner,sun9i-a80-usb-phy";
498 reg = <0x00a01800 0x4>; 291 reg = <0x00a01800 0x4>;
499 clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>, 292 clocks = <&usb_clocks CLK_USB1_HSIC>,
500 <&usb_phy_clk 3>; 293 <&usb_clocks CLK_USB_HSIC>,
501 clock-names = "hsic_480M", "hsic_12M", "phy"; 294 <&usb_clocks CLK_USB1_PHY>;
502 resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>; 295 clock-names = "hsic_480M",
503 reset-names = "hsic", "phy"; 296 "hsic_12M",
297 "phy";
298 resets = <&usb_clocks RST_USB1_HSIC>,
299 <&usb_clocks RST_USB1_PHY>;
300 reset-names = "hsic",
301 "phy";
504 status = "disabled"; 302 status = "disabled";
505 #phy-cells = <0>; 303 #phy-cells = <0>;
506 /* usb1 is always used with HSIC */ 304 /* usb1 is always used with HSIC */
@@ -511,8 +309,8 @@
511 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; 309 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
512 reg = <0x00a02000 0x100>; 310 reg = <0x00a02000 0x100>;
513 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 311 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&usb_mod_clk 5>; 312 clocks = <&usb_clocks CLK_BUS_HCI2>;
515 resets = <&usb_mod_clk 19>; 313 resets = <&usb_clocks RST_USB2_HCI>;
516 phys = <&usbphy3>; 314 phys = <&usbphy3>;
517 phy-names = "usb"; 315 phy-names = "usb";
518 status = "disabled"; 316 status = "disabled";
@@ -522,8 +320,9 @@
522 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; 320 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
523 reg = <0x00a02400 0x100>; 321 reg = <0x00a02400 0x100>;
524 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 322 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>; 323 clocks = <&usb_clocks CLK_BUS_HCI2>,
526 resets = <&usb_mod_clk 19>; 324 <&usb_clocks CLK_USB_OHCI2>;
325 resets = <&usb_clocks RST_USB2_HCI>;
527 phys = <&usbphy3>; 326 phys = <&usbphy3>;
528 phy-names = "usb"; 327 phy-names = "usb";
529 status = "disabled"; 328 status = "disabled";
@@ -532,20 +331,35 @@
532 usbphy3: phy@00a02800 { 331 usbphy3: phy@00a02800 {
533 compatible = "allwinner,sun9i-a80-usb-phy"; 332 compatible = "allwinner,sun9i-a80-usb-phy";
534 reg = <0x00a02800 0x4>; 333 reg = <0x00a02800 0x4>;
535 clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>, 334 clocks = <&usb_clocks CLK_USB2_HSIC>,
536 <&usb_phy_clk 5>; 335 <&usb_clocks CLK_USB_HSIC>,
537 clock-names = "hsic_480M", "hsic_12M", "phy"; 336 <&usb_clocks CLK_USB2_PHY>;
538 resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>; 337 clock-names = "hsic_480M",
539 reset-names = "hsic", "phy"; 338 "hsic_12M",
339 "phy";
340 resets = <&usb_clocks RST_USB2_HSIC>,
341 <&usb_clocks RST_USB2_PHY>;
342 reset-names = "hsic",
343 "phy";
540 status = "disabled"; 344 status = "disabled";
541 #phy-cells = <0>; 345 #phy-cells = <0>;
542 }; 346 };
543 347
348 usb_clocks: clock@00a08000 {
349 compatible = "allwinner,sun9i-a80-usb-clks";
350 reg = <0x00a08000 0x8>;
351 clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
352 clock-names = "bus", "hosc";
353 #clock-cells = <1>;
354 #reset-cells = <1>;
355 };
356
544 mmc0: mmc@01c0f000 { 357 mmc0: mmc@01c0f000 {
545 compatible = "allwinner,sun9i-a80-mmc"; 358 compatible = "allwinner,sun9i-a80-mmc";
546 reg = <0x01c0f000 0x1000>; 359 reg = <0x01c0f000 0x1000>;
547 clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>, 360 clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
548 <&mmc0_clk 1>, <&mmc0_clk 2>; 361 <&ccu CLK_MMC0_OUTPUT>,
362 <&ccu CLK_MMC0_SAMPLE>;
549 clock-names = "ahb", "mmc", "output", "sample"; 363 clock-names = "ahb", "mmc", "output", "sample";
550 resets = <&mmc_config_clk 0>; 364 resets = <&mmc_config_clk 0>;
551 reset-names = "ahb"; 365 reset-names = "ahb";
@@ -558,8 +372,9 @@
558 mmc1: mmc@01c10000 { 372 mmc1: mmc@01c10000 {
559 compatible = "allwinner,sun9i-a80-mmc"; 373 compatible = "allwinner,sun9i-a80-mmc";
560 reg = <0x01c10000 0x1000>; 374 reg = <0x01c10000 0x1000>;
561 clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>, 375 clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
562 <&mmc1_clk 1>, <&mmc1_clk 2>; 376 <&ccu CLK_MMC1_OUTPUT>,
377 <&ccu CLK_MMC1_SAMPLE>;
563 clock-names = "ahb", "mmc", "output", "sample"; 378 clock-names = "ahb", "mmc", "output", "sample";
564 resets = <&mmc_config_clk 1>; 379 resets = <&mmc_config_clk 1>;
565 reset-names = "ahb"; 380 reset-names = "ahb";
@@ -572,8 +387,9 @@
572 mmc2: mmc@01c11000 { 387 mmc2: mmc@01c11000 {
573 compatible = "allwinner,sun9i-a80-mmc"; 388 compatible = "allwinner,sun9i-a80-mmc";
574 reg = <0x01c11000 0x1000>; 389 reg = <0x01c11000 0x1000>;
575 clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>, 390 clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
576 <&mmc2_clk 1>, <&mmc2_clk 2>; 391 <&ccu CLK_MMC2_OUTPUT>,
392 <&ccu CLK_MMC2_SAMPLE>;
577 clock-names = "ahb", "mmc", "output", "sample"; 393 clock-names = "ahb", "mmc", "output", "sample";
578 resets = <&mmc_config_clk 2>; 394 resets = <&mmc_config_clk 2>;
579 reset-names = "ahb"; 395 reset-names = "ahb";
@@ -586,8 +402,9 @@
586 mmc3: mmc@01c12000 { 402 mmc3: mmc@01c12000 {
587 compatible = "allwinner,sun9i-a80-mmc"; 403 compatible = "allwinner,sun9i-a80-mmc";
588 reg = <0x01c12000 0x1000>; 404 reg = <0x01c12000 0x1000>;
589 clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>, 405 clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
590 <&mmc3_clk 1>, <&mmc3_clk 2>; 406 <&ccu CLK_MMC3_OUTPUT>,
407 <&ccu CLK_MMC3_SAMPLE>;
591 clock-names = "ahb", "mmc", "output", "sample"; 408 clock-names = "ahb", "mmc", "output", "sample";
592 resets = <&mmc_config_clk 3>; 409 resets = <&mmc_config_clk 3>;
593 reset-names = "ahb"; 410 reset-names = "ahb";
@@ -600,9 +417,9 @@
600 mmc_config_clk: clk@01c13000 { 417 mmc_config_clk: clk@01c13000 {
601 compatible = "allwinner,sun9i-a80-mmc-config-clk"; 418 compatible = "allwinner,sun9i-a80-mmc-config-clk";
602 reg = <0x01c13000 0x10>; 419 reg = <0x01c13000 0x10>;
603 clocks = <&ahb0_gates 8>; 420 clocks = <&ccu CLK_BUS_MMC>;
604 clock-names = "ahb"; 421 clock-names = "ahb";
605 resets = <&ahb0_resets 8>; 422 resets = <&ccu RST_BUS_MMC>;
606 reset-names = "ahb"; 423 reset-names = "ahb";
607 #clock-cells = <1>; 424 #clock-cells = <1>;
608 #reset-cells = <1>; 425 #reset-cells = <1>;
@@ -621,34 +438,27 @@
621 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 438 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
622 }; 439 };
623 440
624 ahb0_resets: reset@060005a0 { 441 de_clocks: clock@03000000 {
625 #reset-cells = <1>; 442 compatible = "allwinner,sun9i-a80-de-clks";
626 compatible = "allwinner,sun6i-a31-clock-reset"; 443 reg = <0x03000000 0x30>;
627 reg = <0x060005a0 0x4>; 444 clocks = <&ccu CLK_DE>,
628 }; 445 <&ccu CLK_SDRAM>,
629 446 <&ccu CLK_BUS_DE>;
630 ahb1_resets: reset@060005a4 { 447 clock-names = "mod",
631 #reset-cells = <1>; 448 "dram",
632 compatible = "allwinner,sun6i-a31-clock-reset"; 449 "bus";
633 reg = <0x060005a4 0x4>; 450 resets = <&ccu RST_BUS_DE>;
634 }; 451 #clock-cells = <1>;
635
636 ahb2_resets: reset@060005a8 {
637 #reset-cells = <1>;
638 compatible = "allwinner,sun6i-a31-clock-reset";
639 reg = <0x060005a8 0x4>;
640 };
641
642 apb0_resets: reset@060005b0 {
643 #reset-cells = <1>; 452 #reset-cells = <1>;
644 compatible = "allwinner,sun6i-a31-clock-reset";
645 reg = <0x060005b0 0x4>;
646 }; 453 };
647 454
648 apb1_resets: reset@060005b4 { 455 ccu: clock@06000000 {
456 compatible = "allwinner,sun9i-a80-ccu";
457 reg = <0x06000000 0x800>;
458 clocks = <&osc24M>, <&osc32k>;
459 clock-names = "hosc", "losc";
460 #clock-cells = <1>;
649 #reset-cells = <1>; 461 #reset-cells = <1>;
650 compatible = "allwinner,sun6i-a31-clock-reset";
651 reg = <0x060005b4 0x4>;
652 }; 462 };
653 463
654 timer@06000c00 { 464 timer@06000c00 {
@@ -678,7 +488,7 @@
678 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 490 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; 491 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
682 clock-names = "apb", "hosc", "losc"; 492 clock-names = "apb", "hosc", "losc";
683 gpio-controller; 493 gpio-controller;
684 interrupt-controller; 494 interrupt-controller;
@@ -740,8 +550,8 @@
740 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 550 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
741 reg-shift = <2>; 551 reg-shift = <2>;
742 reg-io-width = <4>; 552 reg-io-width = <4>;
743 clocks = <&apb1_gates 16>; 553 clocks = <&ccu CLK_BUS_UART0>;
744 resets = <&apb1_resets 16>; 554 resets = <&ccu RST_BUS_UART0>;
745 status = "disabled"; 555 status = "disabled";
746 }; 556 };
747 557
@@ -751,8 +561,8 @@
751 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 561 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
752 reg-shift = <2>; 562 reg-shift = <2>;
753 reg-io-width = <4>; 563 reg-io-width = <4>;
754 clocks = <&apb1_gates 17>; 564 clocks = <&ccu CLK_BUS_UART1>;
755 resets = <&apb1_resets 17>; 565 resets = <&ccu RST_BUS_UART1>;
756 status = "disabled"; 566 status = "disabled";
757 }; 567 };
758 568
@@ -762,8 +572,8 @@
762 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 572 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
763 reg-shift = <2>; 573 reg-shift = <2>;
764 reg-io-width = <4>; 574 reg-io-width = <4>;
765 clocks = <&apb1_gates 18>; 575 clocks = <&ccu CLK_BUS_UART2>;
766 resets = <&apb1_resets 18>; 576 resets = <&ccu RST_BUS_UART2>;
767 status = "disabled"; 577 status = "disabled";
768 }; 578 };
769 579
@@ -773,8 +583,8 @@
773 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 583 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
774 reg-shift = <2>; 584 reg-shift = <2>;
775 reg-io-width = <4>; 585 reg-io-width = <4>;
776 clocks = <&apb1_gates 19>; 586 clocks = <&ccu CLK_BUS_UART3>;
777 resets = <&apb1_resets 19>; 587 resets = <&ccu RST_BUS_UART3>;
778 status = "disabled"; 588 status = "disabled";
779 }; 589 };
780 590
@@ -784,8 +594,8 @@
784 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 594 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
785 reg-shift = <2>; 595 reg-shift = <2>;
786 reg-io-width = <4>; 596 reg-io-width = <4>;
787 clocks = <&apb1_gates 20>; 597 clocks = <&ccu CLK_BUS_UART4>;
788 resets = <&apb1_resets 20>; 598 resets = <&ccu RST_BUS_UART4>;
789 status = "disabled"; 599 status = "disabled";
790 }; 600 };
791 601
@@ -795,8 +605,8 @@
795 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 605 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
796 reg-shift = <2>; 606 reg-shift = <2>;
797 reg-io-width = <4>; 607 reg-io-width = <4>;
798 clocks = <&apb1_gates 21>; 608 clocks = <&ccu CLK_BUS_UART5>;
799 resets = <&apb1_resets 21>; 609 resets = <&ccu RST_BUS_UART5>;
800 status = "disabled"; 610 status = "disabled";
801 }; 611 };
802 612
@@ -804,8 +614,8 @@
804 compatible = "allwinner,sun6i-a31-i2c"; 614 compatible = "allwinner,sun6i-a31-i2c";
805 reg = <0x07002800 0x400>; 615 reg = <0x07002800 0x400>;
806 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 616 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&apb1_gates 0>; 617 clocks = <&ccu CLK_BUS_I2C0>;
808 resets = <&apb1_resets 0>; 618 resets = <&ccu RST_BUS_I2C0>;
809 status = "disabled"; 619 status = "disabled";
810 #address-cells = <1>; 620 #address-cells = <1>;
811 #size-cells = <0>; 621 #size-cells = <0>;
@@ -815,8 +625,8 @@
815 compatible = "allwinner,sun6i-a31-i2c"; 625 compatible = "allwinner,sun6i-a31-i2c";
816 reg = <0x07002c00 0x400>; 626 reg = <0x07002c00 0x400>;
817 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 627 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&apb1_gates 1>; 628 clocks = <&ccu CLK_BUS_I2C1>;
819 resets = <&apb1_resets 1>; 629 resets = <&ccu RST_BUS_I2C1>;
820 status = "disabled"; 630 status = "disabled";
821 #address-cells = <1>; 631 #address-cells = <1>;
822 #size-cells = <0>; 632 #size-cells = <0>;
@@ -826,8 +636,8 @@
826 compatible = "allwinner,sun6i-a31-i2c"; 636 compatible = "allwinner,sun6i-a31-i2c";
827 reg = <0x07003000 0x400>; 637 reg = <0x07003000 0x400>;
828 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 638 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&apb1_gates 2>; 639 clocks = <&ccu CLK_BUS_I2C2>;
830 resets = <&apb1_resets 2>; 640 resets = <&ccu RST_BUS_I2C2>;
831 status = "disabled"; 641 status = "disabled";
832 #address-cells = <1>; 642 #address-cells = <1>;
833 #size-cells = <0>; 643 #size-cells = <0>;
@@ -837,8 +647,8 @@
837 compatible = "allwinner,sun6i-a31-i2c"; 647 compatible = "allwinner,sun6i-a31-i2c";
838 reg = <0x07003400 0x400>; 648 reg = <0x07003400 0x400>;
839 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 649 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
840 clocks = <&apb1_gates 3>; 650 clocks = <&ccu CLK_BUS_I2C3>;
841 resets = <&apb1_resets 3>; 651 resets = <&ccu RST_BUS_I2C3>;
842 status = "disabled"; 652 status = "disabled";
843 #address-cells = <1>; 653 #address-cells = <1>;
844 #size-cells = <0>; 654 #size-cells = <0>;
@@ -848,8 +658,8 @@
848 compatible = "allwinner,sun6i-a31-i2c"; 658 compatible = "allwinner,sun6i-a31-i2c";
849 reg = <0x07003800 0x400>; 659 reg = <0x07003800 0x400>;
850 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 660 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&apb1_gates 4>; 661 clocks = <&ccu CLK_BUS_I2C4>;
852 resets = <&apb1_resets 4>; 662 resets = <&ccu RST_BUS_I2C4>;
853 status = "disabled"; 663 status = "disabled";
854 #address-cells = <1>; 664 #address-cells = <1>;
855 #size-cells = <0>; 665 #size-cells = <0>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-25 06:36:22 -0400