Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This time we have a good set of changes to the core framework that do
  some general cleanups, but nothing too major. The majority of the diff
  goes to two SoCs, Actions Semi and Qualcomm. A brand new driver is
  introduced for Actions Semi so it takes up some lines to add all the
  different types, and the Qualcomm diff is there because we add support
  for two SoCs and it's quite a bit of data.

  Otherwise the big driver updates are on TI Davinci and Amlogic
  platforms. And then the long tail of driver updates for various fixes
  and stuff follows after that.

  Core:
   - debugfs cleanups removing error checking and an unused provider API
   - Removal of a clk init typedef that isn't used
   - Usage of match_string() to simplify parent string name matching
   - OF clk helpers moved to their own file (linux/of_clk.h)
   - Make clk warnings more readable across kernel versions

  New Drivers:
   - Qualcomm SDM845 GCC and Video clk controllers
   - Qualcomm MSM8998 GCC
   - Actions Semi S900 SoC support
   - Nuvoton npcm750 microcontroller clks
   - Amlogic axg AO clock controller

  Removed Drivers:
   - Deprecated Rockchip clk-gate driver

  Updates:
   - debugfs functions stopped checking return values
   - Support for the MSIOF module clocks on Rensas R-Car M3-N
   - Support for the new Rensas RZ/G1C and R-Car E3 SoCs
   - Qualcomm GDSC, RCG, and PLL updates for clk changes in new SoCs
   - Berlin and Amlogic SPDX tagging
   - Usage of of_clk_get_parent_count() in more places
   - Proper implementation of the CDEV1/2 clocks on Tegra20
   - Allwinner H6 PRCM clock support and R40 EMAC support
   - Add critical flag to meson8b's fdiv2 as temporary fixup for ethernet
   - Round closest support for meson's mpll driver
   - Support for meson8b nand clocks and gxbb video decoder clocks
   - Mediatek mali clks
   - STM32MP1 fixes
   - Uniphier LD11/LD20 stream demux system clock"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits)
  clk: qcom: Export clk_fabia_pll_configure()
  clk: bcm: Update and add Stingray clock entries
  dt-bindings: clk: Update Stingray binding doc
  clk-si544: Properly round requested frequency to nearest match
  clk: ingenic: jz4770: Add 150us delay after enabling VPU clock
  clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock
  clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle
  clk: ingenic: jz4770: Change OTG from custom to standard gated clock
  clk: ingenic: Support specifying "wait for clock stable" delay
  clk: ingenic: Add support for clocks whose gate bit is inverted
  clk: use match_string() helper
  clk: bcm2835: use match_string() helper
  clk: Return void from debug_init op
  clk: remove clk_debugfs_add_file()
  clk: tegra: no need to check return value of debugfs_create functions
  clk: davinci: no need to check return value of debugfs_create functions
  clk: bcm2835: no need to check return value of debugfs_create functions
  clk: no need to check return value of debugfs_create functions
  clk: imx6: add EPIT clock support
  clk: mvebu: use correct bit for 98DX3236 NAND
  ...

183 files changed, 13842 insertions, 1312 deletions

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
new file mode 100644
index 000000000000..7de43bf41fdc
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
@@ -0,0 +1,30 @@
+MediaTek g3dsys controller
+============================
+
+The MediaTek g3dsys controller provides various clocks and reset controller to
+the GPU.
+
+Required Properties:
+
+- compatible: Should be:
+        - "mediatek,mt2701-g3dsys", "syscon":
+                for MT2701 SoC
+        - "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon":
+                for MT7623 SoC
+- #clock-cells: Must be 1
+- #reset-cells: Must be 1
+
+The g3dsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+g3dsys: clock-controller@13000000 {
+        compatible = "mediatek,mt7623-g3dsys",
+                     "mediatek,mt2701-g3dsys",
+                     "syscon";
+        reg = <0 0x13000000 0 0x200>;
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt b/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
new file mode 100644
index 000000000000..93e4fb827cd6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/actions,s900-cmu.txt
@@ -0,0 +1,47 @@
+* Actions S900 Clock Management Unit (CMU)
+
+The Actions S900 clock management unit generates and supplies clock to various
+controllers within the SoC. The clock binding described here is applicable to
+S900 SoC.
+
+Required Properties:
+
+- compatible: should be "actions,s900-cmu"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- clocks: Reference to the parent clocks ("hosc", "losc")
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier, and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/actions,s900-cmu.h header and can be used in device
+tree sources.
+
+External clocks:
+
+The hosc clock used as input for the plls is generated outside the SoC. It is
+expected that it is defined using standard clock bindings as "hosc".
+
+Actions S900 CMU also requires one more clock:
+ - "losc" - internal low frequency oscillator
+
+Example: Clock Management Unit node:
+
+        cmu: clock-controller@e0160000 {
+                compatible = "actions,s900-cmu";
+                reg = <0x0 0xe0160000 0x0 0x1000>;
+                clocks = <&hosc>, <&losc>;
+                #clock-cells = <1>;
+        };
+
+Example: UART controller node that consumes clock generated by the clock
+management unit:
+
+        uart: serial@e012a000 {
+                compatible = "actions,s900-uart", "actions,owl-uart";
+                reg = <0x0 0xe012a000 0x0 0x2000>;
+                interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cmu CLK_UART5>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
index 786dc39ca904..3a880528030e 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -9,6 +9,7 @@ Required Properties:
         - GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
         - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
         - GXM (S912) : "amlogic,meson-gxm-aoclkc"
+        - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
         followed by the common "amlogic,meson-gx-aoclkc"
 
 - #clock-cells: should be 1.
diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
index f8e4a93466cb..ab730ea0a560 100644
--- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
@@ -276,36 +276,38 @@ These clock IDs are defined in:
     clk_ts_500_ref      genpll2         2       BCM_SR_GENPLL2_TS_500_REF_CLK
     clk_125_nitro       genpll2         3       BCM_SR_GENPLL2_125_NITRO_CLK
     clk_chimp           genpll2         4       BCM_SR_GENPLL2_CHIMP_CLK
-    clk_nic_flash       genpll2         5       BCM_SR_GENPLL2_NIC_FLASH
+    clk_nic_flash       genpll2         5       BCM_SR_GENPLL2_NIC_FLASH_CLK
+    clk_fs              genpll2         6       BCM_SR_GENPLL2_FS_CLK
 
     genpll3             crystal         0       BCM_SR_GENPLL3
     clk_hsls            genpll3         1       BCM_SR_GENPLL3_HSLS_CLK
     clk_sdio            genpll3         2       BCM_SR_GENPLL3_SDIO_CLK
 
     genpll4             crystal         0       BCM_SR_GENPLL4
-    ccn                 genpll4         1       BCM_SR_GENPLL4_CCN_CLK
+    clk_ccn             genpll4         1       BCM_SR_GENPLL4_CCN_CLK
     clk_tpiu_pll        genpll4         2       BCM_SR_GENPLL4_TPIU_PLL_CLK
-    noc_clk             genpll4         3       BCM_SR_GENPLL4_NOC_CLK
+    clk_noc             genpll4         3       BCM_SR_GENPLL4_NOC_CLK
     clk_chclk_fs4       genpll4         4       BCM_SR_GENPLL4_CHCLK_FS4_CLK
     clk_bridge_fscpu    genpll4         5       BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
 
-
     genpll5             crystal         0       BCM_SR_GENPLL5
-    fs4_hf_clk          genpll5         1       BCM_SR_GENPLL5_FS4_HF_CLK
-    crypto_ae_clk       genpll5         2       BCM_SR_GENPLL5_CRYPTO_AE_CLK
-    raid_ae_clk         genpll5         3       BCM_SR_GENPLL5_RAID_AE_CLK
+    clk_fs4_hf          genpll5         1       BCM_SR_GENPLL5_FS4_HF_CLK
+    clk_crypto_ae       genpll5         2       BCM_SR_GENPLL5_CRYPTO_AE_CLK
+    clk_raid_ae         genpll5         3       BCM_SR_GENPLL5_RAID_AE_CLK
 
     genpll6             crystal         0       BCM_SR_GENPLL6
-    48_usb              genpll6         1       BCM_SR_GENPLL6_48_USB_CLK
+    clk_48_usb          genpll6         1       BCM_SR_GENPLL6_48_USB_CLK
 
     lcpll0              crystal         0       BCM_SR_LCPLL0
     clk_sata_refp       lcpll0          1       BCM_SR_LCPLL0_SATA_REFP_CLK
     clk_sata_refn       lcpll0          2       BCM_SR_LCPLL0_SATA_REFN_CLK
-    clk_usb_ref         lcpll0          3       BCM_SR_LCPLL0_USB_REF_CLK
-    sata_refpn          lcpll0          3       BCM_SR_LCPLL0_SATA_REFPN_CLK
+    clk_sata_350        lcpll0          3       BCM_SR_LCPLL0_SATA_350_CLK
+    clk_sata_500        lcpll0          4       BCM_SR_LCPLL0_SATA_500_CLK
 
     lcpll1              crystal         0       BCM_SR_LCPLL1
-    wan                 lcpll1          1       BCM_SR_LCPLL0_WAN_CLK
+    clk_wan             lcpll1          1       BCM_SR_LCPLL1_WAN_CLK
+    clk_usb_ref         lcpll1          2       BCM_SR_LCPLL1_USB_REF_CLK
+    clk_crmu_ts         lcpll1          3       BCM_SR_LCPLL1_CRMU_TS_CLK
 
     lcpll_pcie          crystal         0       BCM_SR_LCPLL_PCIE
-    pcie_phy_ref        lcpll1          1       BCM_SR_LCPLL_PCIE_PHY_REF_CLK
+    clk_pcie_phy_ref    lcpll1          1       BCM_SR_LCPLL_PCIE_PHY_REF_CLK
diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt
new file mode 100644
index 000000000000..f82064546d11
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt
@@ -0,0 +1,100 @@
+* Nuvoton NPCM7XX Clock Controller
+
+Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
+generates and supplies clocks to all modules within the BMC.
+
+External clocks:
+
+There are six fixed clocks that are generated outside the BMC. All clocks are of
+a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
+clk_sysbypck are inputs to the clock controller.
+clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
+network. They are set on the device tree, but not used by the clock module. The
+network devices use them directly.
+Example can be found below.
+
+All available clocks are defined as preprocessor macros in:
+dt-bindings/clock/nuvoton,npcm7xx-clock.h
+and can be reused as DT sources.
+
+Required Properties of clock controller:
+
+        - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
+                  Poleg BMC NPCM750
+
+        - reg: physical base address of the clock controller and length of
+                memory mapped region.
+
+        - #clock-cells: should be 1.
+
+Example: Clock controller node:
+
+        clk: clock-controller@f0801000 {
+                compatible = "nuvoton,npcm750-clk";
+                #clock-cells = <1>;
+                reg = <0xf0801000 0x1000>;
+                clock-names = "refclk", "sysbypck", "mcbypck";
+                clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
+        };
+
+Example: Required external clocks for network:
+
+        /* external reference clock */
+        clk_refclk: clk-refclk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <25000000>;
+                clock-output-names = "refclk";
+        };
+
+        /* external reference clock for cpu. float in normal operation */
+        clk_sysbypck: clk-sysbypck {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <800000000>;
+                clock-output-names = "sysbypck";
+        };
+
+        /* external reference clock for MC. float in normal operation */
+        clk_mcbypck: clk-mcbypck {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <800000000>;
+                clock-output-names = "mcbypck";
+        };
+
+         /* external clock signal rg1refck, supplied by the phy */
+        clk_rg1refck: clk-rg1refck {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <125000000>;
+                clock-output-names = "clk_rg1refck";
+        };
+
+         /* external clock signal rg2refck, supplied by the phy */
+        clk_rg2refck: clk-rg2refck {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <125000000>;
+                clock-output-names = "clk_rg2refck";
+        };
+
+        clk_xin: clk-xin {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <50000000>;
+                clock-output-names = "clk_xin";
+        };
+
+
+Example: GMAC controller node that consumes two clocks: a generated clk by the
+clock controller and a fixed clock from DT (clk_rg1refck).
+
+        ethernet0: ethernet@f0802000 {
+                compatible = "snps,dwmac";
+                reg = <0xf0802000 0x2000>;
+                interrupts = <0 14 4>;
+                interrupt-names = "macirq";
+                clocks  = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
+                clock-names = "stmmaceth", "clk_gmac";
+        };
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 551d03be9665..664ea1fd6c76 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -17,7 +17,9 @@ Required properties :
                         "qcom,gcc-msm8974pro-ac"
                         "qcom,gcc-msm8994"
                         "qcom,gcc-msm8996"
+                        "qcom,gcc-msm8998"
                         "qcom,gcc-mdm9615"
+                        "qcom,gcc-sdm845"
 
 - reg : shall contain base register location and length
 - #clock-cells : shall contain 1
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
new file mode 100644
index 000000000000..3c007653da31
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
@@ -0,0 +1,22 @@
+Qualcomm Technologies, Inc. RPMh Clocks
+-------------------------------------------------------
+
+Resource Power Manager Hardened (RPMh) manages shared resources on
+some Qualcomm Technologies Inc. SoCs. It accepts clock requests from
+other hardware subsystems via RSC to control clocks.
+
+Required properties :
+- compatible : shall contain "qcom,sdm845-rpmh-clk"
+
+- #clock-cells : must contain 1
+
+Example :
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+
+        &apps_rsc {
+                rpmhcc: clock-controller {
+                        compatible = "qcom,sdm845-rpmh-clk";
+                        #clock-cells = <1>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt
new file mode 100644
index 000000000000..e7c035afa778
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,videocc.txt
@@ -0,0 +1,19 @@
+Qualcomm Video Clock & Reset Controller Binding
+-----------------------------------------------
+
+Required properties :
+- compatible : shall contain "qcom,sdm845-videocc"
+- reg : shall contain base register location and length
+- #clock-cells : from common clock binding, shall contain 1.
+- #power-domain-cells : from generic power domain binding, shall contain 1.
+
+Optional properties :
+- #reset-cells : from common reset binding, shall contain 1.
+
+Example:
+        videocc: clock-controller@ab00000 {
+                compatible = "qcom,sdm845-videocc";
+                reg = <0xab00000 0x10000>;
+                #clock-cells = <1>;
+                #power-domain-cells = <1>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index 773a5226342f..db542abadb75 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -15,6 +15,7 @@ Required Properties:
   - compatible: Must be one of:
       - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
       - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
+      - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
       - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
       - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
       - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
@@ -25,6 +26,7 @@ Required Properties:
       - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
       - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
       - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
+      - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3)
       - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
 
   - reg: Base address and length of the memory resource used by the CPG/MSSR
@@ -33,10 +35,12 @@ Required Properties:
   - clocks: References to external parent clocks, one entry for each entry in
     clock-names
   - clock-names: List of external parent clock names. Valid names are:
-      - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
-                 r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995)
+      - "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,
+                 r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,
+                 r8a77980, r8a77990, r8a77995)
       - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
-      - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
+      - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
+                     r8a7794)
 
   - #clock-cells: Must be 2
       - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
diff --git a/Documentation/devicetree/bindings/clock/rockchip.txt b/Documentation/devicetree/bindings/clock/rockchip.txt
deleted file mode 100644
index 22f6769e5d4a..000000000000
--- a/Documentation/devicetree/bindings/clock/rockchip.txt
+++ /dev/null
@@ -1,77 +0,0 @@
-Device Tree Clock bindings for arch-rockchip
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-== Gate clocks ==
-
-These bindings are deprecated!
-Please use the soc specific CRU bindings instead.
-
-The gate registers form a continuos block which makes the dt node
-structure a matter of taste, as either all gates can be put into
-one gate clock spanning all registers or they can be divided into
-the 10 individual gates containing 16 clocks each.
-The code supports both approaches.
-
-Required properties:
-- compatible : "rockchip,rk2928-gate-clk"
-- reg : shall be the control register address(es) for the clock.
-- #clock-cells : from common clock binding; shall be set to 1
-- clock-output-names : the corresponding gate names that the clock controls
-- clocks : should contain the parent clock for each individual gate,
-  therefore the number of clocks elements should match the number of
-  clock-output-names
-
-Example using multiple gate clocks:
-
-                clk_gates0: gate-clk@200000d0 {
-                        compatible = "rockchip,rk2928-gate-clk";
-                        reg = <0x200000d0 0x4>;
-                        clocks = <&dummy>, <&dummy>,
-                                 <&dummy>, <&dummy>,
-                                 <&dummy>, <&dummy>,
-                                 <&dummy>, <&dummy>,
-                                 <&dummy>, <&dummy>,
-                                 <&dummy>, <&dummy>,
-                                 <&dummy>, <&dummy>,
-                                 <&dummy>, <&dummy>;
-
-                        clock-output-names =
-                                "gate_core_periph", "gate_cpu_gpll",
-                                "gate_ddrphy", "gate_aclk_cpu",
-                                "gate_hclk_cpu", "gate_pclk_cpu",
-                                "gate_atclk_cpu", "gate_i2s0",
-                                "gate_i2s0_frac", "gate_i2s1",
-                                "gate_i2s1_frac", "gate_i2s2",
-                                "gate_i2s2_frac", "gate_spdif",
-                                "gate_spdif_frac", "gate_testclk";
-
-                        #clock-cells = <1>;
-                };
-
-                clk_gates1: gate-clk@200000d4 {
-                        compatible = "rockchip,rk2928-gate-clk";
-                        reg = <0x200000d4 0x4>;
-                        clocks = <&xin24m>, <&xin24m>,
-                                 <&xin24m>, <&dummy>,
-                                 <&dummy>, <&xin24m>,
-                                 <&xin24m>, <&dummy>,
-                                 <&xin24m>, <&dummy>,
-                                 <&xin24m>, <&dummy>,
-                                 <&xin24m>, <&dummy>,
-                                 <&xin24m>, <&dummy>;
-
-                        clock-output-names =
-                                "gate_timer0", "gate_timer1",
-                                "gate_timer2", "gate_jtag",
-                                "gate_aclk_lcdc1_src", "gate_otgphy0",
-                                "gate_otgphy1", "gate_ddr_gpll",
-                                "gate_uart0", "gate_frac_uart0",
-                                "gate_uart1", "gate_frac_uart1",
-                                "gate_uart2", "gate_frac_uart2",
-                                "gate_uart3", "gate_frac_uart3";
-
-                        #clock-cells = <1>;
-                };
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 460ef27b1008..47d2e902ced4 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -21,6 +21,7 @@ Required properties :
                 - "allwinner,sun50i-a64-r-ccu"
                 - "allwinner,sun50i-h5-ccu"
                 - "allwinner,sun50i-h6-ccu"
+                - "allwinner,sun50i-h6-r-ccu"
                 - "nextthing,gr8-ccu"
 
 - reg: Must contain the registers base address and length
@@ -35,7 +36,7 @@ Required properties :
 For the main CCU on H6, one more clock is needed:
 - "iosc": the SoC's internal frequency oscillator
 
-For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
+For the PRCM CCUs on A83T/H3/A64/H6, two more clocks are needed:
 - "pll-periph": the SoC's peripheral PLL from the main CCU
 - "iosc": the SoC's internal frequency oscillator
 
diff --git a/Documentation/driver-api/clk.rst b/Documentation/driver-api/clk.rst
index 511628bb3d3a..593cca5058b1 100644
--- a/Documentation/driver-api/clk.rst
+++ b/Documentation/driver-api/clk.rst
@@ -96,7 +96,7 @@ the operations defined in clk-provider.h::
                 int             (*get_phase)(struct clk_hw *hw);
                 int             (*set_phase)(struct clk_hw *hw, int degrees);
                 void            (*init)(struct clk_hw *hw);
-                int             (*debug_init)(struct clk_hw *hw,
+                void            (*debug_init)(struct clk_hw *hw,
                                               struct dentry *dentry);
         };
 
diff --git a/MAINTAINERS b/MAINTAINERS
index 2648f3113115..01a02c0aa562 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3587,6 +3587,7 @@ F:	drivers/clk/
 X:      drivers/clk/clkdev.c
 F:      include/linux/clk-pr*
 F:      include/linux/clk/
+F:      include/linux/of_clk.h
 
 COMMON INTERNET FILE SYSTEM (CIFS)
 M:      Steve French <sfrench@samba.org>
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 200714e3feea..d74dd7f19507 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -120,7 +120,7 @@
                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+                clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
                         <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index ce85b3ca1a55..69436b9a404c 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -1092,7 +1092,7 @@
                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
                                         <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
                                         <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+                                clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
                                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
                                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
                                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 34968a381d0f..721572a8c429 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -277,6 +277,7 @@ config COMMON_CLK_STM32H7
         ---help---
           Support for stm32h7 SoC family clocks
 
+source "drivers/clk/actions/Kconfig"
 source "drivers/clk/bcm/Kconfig"
 source "drivers/clk/hisilicon/Kconfig"
 source "drivers/clk/imgtec/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index de6d06ac790b..ae40cbe770f0 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_CLK_HSDK)			+= clk-hsdk-pll.o
 obj-$(CONFIG_COMMON_CLK_MAX77686)       += clk-max77686.o
 obj-$(CONFIG_ARCH_MOXART)               += clk-moxart.o
 obj-$(CONFIG_ARCH_NOMADIK)              += clk-nomadik.o
+obj-$(CONFIG_ARCH_NPCM7XX)              += clk-npcm7xx.o
 obj-$(CONFIG_ARCH_NSPIRE)               += clk-nspire.o
 obj-$(CONFIG_COMMON_CLK_OXNAS)          += clk-oxnas.o
 obj-$(CONFIG_COMMON_CLK_PALMAS)         += clk-palmas.o
@@ -59,6 +60,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X)		+= clk-wm831x.o
 obj-$(CONFIG_COMMON_CLK_XGENE)          += clk-xgene.o
 
 # please keep this section sorted lexicographically by directory path name
+obj-y                                   += actions/
 obj-$(CONFIG_COMMON_CLK_AT91)           += at91/
 obj-$(CONFIG_ARCH_ARTPEC)               += axis/
 obj-$(CONFIG_ARC_PLAT_AXS10X)           += axs10x/
diff --git a/drivers/clk/actions/Kconfig b/drivers/clk/actions/Kconfig
new file mode 100644
index 000000000000..8854adb37847
--- /dev/null
+++ b/drivers/clk/actions/Kconfig
@@ -0,0 +1,14 @@
+config CLK_ACTIONS
+        bool "Clock driver for Actions Semi SoCs"
+        depends on ARCH_ACTIONS || COMPILE_TEST
+        default ARCH_ACTIONS
+
+if CLK_ACTIONS
+
+# SoC Drivers
+
+config CLK_OWL_S900
+        bool "Support for the Actions Semi OWL S900 clocks"
+        depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
+        default ARM64 && ARCH_ACTIONS
+endif
diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile
new file mode 100644
index 000000000000..76e431434d10
--- /dev/null
+++ b/drivers/clk/actions/Makefile
@@ -0,0 +1,12 @@
+obj-$(CONFIG_CLK_ACTIONS)       += clk-owl.o
+
+clk-owl-y                       += owl-common.o
+clk-owl-y                       += owl-gate.o
+clk-owl-y                       += owl-mux.o
+clk-owl-y                       += owl-divider.o
+clk-owl-y                       += owl-factor.o
+clk-owl-y                       += owl-composite.o
+clk-owl-y                       += owl-pll.o
+
+# SoC support
+obj-$(CONFIG_CLK_OWL_S900)      += owl-s900.o
diff --git a/drivers/clk/actions/owl-common.c b/drivers/clk/actions/owl-common.c
new file mode 100644
index 000000000000..61c1071b5180
--- /dev/null
+++ b/drivers/clk/actions/owl-common.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL common clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "owl-common.h"
+
+static const struct regmap_config owl_regmap_config = {
+        .reg_bits       = 32,
+        .reg_stride     = 4,
+        .val_bits       = 32,
+        .max_register   = 0x00cc,
+        .fast_io        = true,
+};
+
+static void owl_clk_set_regmap(const struct owl_clk_desc *desc,
+                         struct regmap *regmap)
+{
+        int i;
+        struct owl_clk_common *clks;
+
+        for (i = 0; i < desc->num_clks; i++) {
+                clks = desc->clks[i];
+                if (!clks)
+                        continue;
+
+                clks->regmap = regmap;
+        }
+}
+
+int owl_clk_regmap_init(struct platform_device *pdev,
+                         const struct owl_clk_desc *desc)
+{
+        void __iomem *base;
+        struct regmap *regmap;
+        struct resource *res;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(base))
+                return PTR_ERR(base);
+
+        regmap = devm_regmap_init_mmio(&pdev->dev, base, &owl_regmap_config);
+        if (IS_ERR(regmap)) {
+                pr_err("failed to init regmap\n");
+                return PTR_ERR(regmap);
+        }
+
+        owl_clk_set_regmap(desc, regmap);
+
+        return 0;
+}
+
+int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks)
+{
+        int i, ret;
+        struct clk_hw *hw;
+
+        for (i = 0; i < hw_clks->num; i++) {
+
+                hw = hw_clks->hws[i];
+
+                if (IS_ERR_OR_NULL(hw))
+                        continue;
+
+                ret = devm_clk_hw_register(dev, hw);
+                if (ret) {
+                        dev_err(dev, "Couldn't register clock %d - %s\n",
+                                i, hw->init->name);
+                        return ret;
+                }
+        }
+
+        ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_clks);
+        if (ret)
+                dev_err(dev, "Failed to add clock provider\n");
+
+        return ret;
+}
diff --git a/drivers/clk/actions/owl-common.h b/drivers/clk/actions/owl-common.h
new file mode 100644
index 000000000000..4fd726ec54a6
--- /dev/null
+++ b/drivers/clk/actions/owl-common.h
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL common clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_COMMON_H_
+#define _OWL_COMMON_H_
+
+#include <linux/clk-provider.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+
+struct device_node;
+
+struct owl_clk_common {
+        struct regmap                   *regmap;
+        struct clk_hw                   hw;
+};
+
+struct owl_clk_desc {
+        struct owl_clk_common           **clks;
+        unsigned long                   num_clks;
+        struct clk_hw_onecell_data      *hw_clks;
+};
+
+static inline struct owl_clk_common *
+        hw_to_owl_clk_common(const struct clk_hw *hw)
+{
+        return container_of(hw, struct owl_clk_common, hw);
+}
+
+int owl_clk_regmap_init(struct platform_device *pdev,
+                         const struct owl_clk_desc *desc);
+int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks);
+
+#endif /* _OWL_COMMON_H_ */
diff --git a/drivers/clk/actions/owl-composite.c b/drivers/clk/actions/owl-composite.c
new file mode 100644
index 000000000000..101706e0c66f
--- /dev/null
+++ b/drivers/clk/actions/owl-composite.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL composite clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include "owl-composite.h"
+
+static u8 owl_comp_get_parent(struct clk_hw *hw)
+{
+        struct owl_composite *comp = hw_to_owl_comp(hw);
+
+        return owl_mux_helper_get_parent(&comp->common, &comp->mux_hw);
+}
+
+static int owl_comp_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct owl_composite *comp = hw_to_owl_comp(hw);
+
+        return owl_mux_helper_set_parent(&comp->common, &comp->mux_hw, index);
+}
+
+static void owl_comp_disable(struct clk_hw *hw)
+{
+        struct owl_composite *comp = hw_to_owl_comp(hw);
+        struct owl_clk_common *common = &comp->common;
+
+        owl_gate_set(common, &comp->gate_hw, false);
+}
+
+static int owl_comp_enable(struct clk_hw *hw)
+{
+        struct owl_composite *comp = hw_to_owl_comp(hw);
+        struct owl_clk_common *common = &comp->common;
+
+        owl_gate_set(common, &comp->gate_hw, true);
+
+        return 0;
+}
+
+static int owl_comp_is_enabled(struct clk_hw *hw)
+{
+        struct owl_composite *comp = hw_to_owl_comp(hw);
+        struct owl_clk_common *common = &comp->common;
+
+        return owl_gate_clk_is_enabled(common, &comp->gate_hw);
+}
+
+static long owl_comp_div_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *parent_rate)
+{
+        struct owl_composite *comp = hw_to_owl_comp(hw);
+
+        return owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw,
+                                        rate, parent_rate);
+}
+
+static unsigned long owl_comp_div_recalc_rate(struct clk_hw *hw,
+                                          unsigned long parent_rate)
+{
+        struct owl_composite *comp = hw_to_owl_comp(hw);
+
+        return owl_divider_helper_recalc_rate(&comp->common, &comp->rate.div_hw,
+                                        parent_rate);
+}
+
+static int owl_comp_div_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        struct owl_composite *comp = hw_to_owl_comp(hw);
+
+        return owl_divider_helper_set_rate(&comp->common, &comp->rate.div_hw,
+                                        rate, parent_rate);
+}
+
+static long owl_comp_fact_round_rate(struct clk_hw *hw, unsigned long rate,
+                        unsigned long *parent_rate)
+{
+        struct owl_composite *comp = hw_to_owl_comp(hw);
+
+        return owl_factor_helper_round_rate(&comp->common,
+                                        &comp->rate.factor_hw,
+                                        rate, parent_rate);
+}
+
+static unsigned long owl_comp_fact_recalc_rate(struct clk_hw *hw,
+                        unsigned long parent_rate)
+{
+        struct owl_composite *comp = hw_to_owl_comp(hw);
+
+        return owl_factor_helper_recalc_rate(&comp->common,
+                                        &comp->rate.factor_hw,
+                                        parent_rate);
+}
+
+static int owl_comp_fact_set_rate(struct clk_hw *hw, unsigned long rate,
+                        unsigned long parent_rate)
+{
+        struct owl_composite *comp = hw_to_owl_comp(hw);
+
+        return owl_factor_helper_set_rate(&comp->common,
+                                        &comp->rate.factor_hw,
+                                        rate, parent_rate);
+}
+
+static long owl_comp_fix_fact_round_rate(struct clk_hw *hw, unsigned long rate,
+                        unsigned long *parent_rate)
+{
+        struct owl_composite *comp = hw_to_owl_comp(hw);
+        struct clk_fixed_factor *fix_fact_hw = &comp->rate.fix_fact_hw;
+
+        return comp->fix_fact_ops->round_rate(&fix_fact_hw->hw, rate, parent_rate);
+}
+
+static unsigned long owl_comp_fix_fact_recalc_rate(struct clk_hw *hw,
+                        unsigned long parent_rate)
+{
+        struct owl_composite *comp = hw_to_owl_comp(hw);
+        struct clk_fixed_factor *fix_fact_hw = &comp->rate.fix_fact_hw;
+
+        return comp->fix_fact_ops->recalc_rate(&fix_fact_hw->hw, parent_rate);
+
+}
+
+static int owl_comp_fix_fact_set_rate(struct clk_hw *hw, unsigned long rate,
+                        unsigned long parent_rate)
+{
+        /*
+         * We must report success but we can do so unconditionally because
+         * owl_comp_fix_fact_round_rate returns values that ensure this call is
+         * a nop.
+         */
+
+        return 0;
+}
+
+const struct clk_ops owl_comp_div_ops = {
+        /* mux_ops */
+        .get_parent     = owl_comp_get_parent,
+        .set_parent     = owl_comp_set_parent,
+
+        /* gate_ops */
+        .disable        = owl_comp_disable,
+        .enable         = owl_comp_enable,
+        .is_enabled     = owl_comp_is_enabled,
+
+        /* div_ops */
+        .round_rate     = owl_comp_div_round_rate,
+        .recalc_rate    = owl_comp_div_recalc_rate,
+        .set_rate       = owl_comp_div_set_rate,
+};
+
+
+const struct clk_ops owl_comp_fact_ops = {
+        /* mux_ops */
+        .get_parent     = owl_comp_get_parent,
+        .set_parent     = owl_comp_set_parent,
+
+        /* gate_ops */
+        .disable        = owl_comp_disable,
+        .enable         = owl_comp_enable,
+        .is_enabled     = owl_comp_is_enabled,
+
+        /* fact_ops */
+        .round_rate     = owl_comp_fact_round_rate,
+        .recalc_rate    = owl_comp_fact_recalc_rate,
+        .set_rate       = owl_comp_fact_set_rate,
+};
+
+const struct clk_ops owl_comp_fix_fact_ops = {
+        /* gate_ops */
+        .disable        = owl_comp_disable,
+        .enable         = owl_comp_enable,
+        .is_enabled     = owl_comp_is_enabled,
+
+        /* fix_fact_ops */
+        .round_rate     = owl_comp_fix_fact_round_rate,
+        .recalc_rate    = owl_comp_fix_fact_recalc_rate,
+        .set_rate       = owl_comp_fix_fact_set_rate,
+};
+
+
+const struct clk_ops owl_comp_pass_ops = {
+        /* mux_ops */
+        .get_parent     = owl_comp_get_parent,
+        .set_parent     = owl_comp_set_parent,
+
+        /* gate_ops */
+        .disable        = owl_comp_disable,
+        .enable         = owl_comp_enable,
+        .is_enabled     = owl_comp_is_enabled,
+};
diff --git a/drivers/clk/actions/owl-composite.h b/drivers/clk/actions/owl-composite.h
new file mode 100644
index 000000000000..b410ed5bf308
--- /dev/null
+++ b/drivers/clk/actions/owl-composite.h
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL composite clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_COMPOSITE_H_
+#define _OWL_COMPOSITE_H_
+
+#include "owl-common.h"
+#include "owl-mux.h"
+#include "owl-gate.h"
+#include "owl-factor.h"
+#include "owl-fixed-factor.h"
+#include "owl-divider.h"
+
+union owl_rate {
+        struct owl_divider_hw   div_hw;
+        struct owl_factor_hw    factor_hw;
+        struct clk_fixed_factor fix_fact_hw;
+};
+
+struct owl_composite {
+        struct owl_mux_hw       mux_hw;
+        struct owl_gate_hw      gate_hw;
+        union owl_rate          rate;
+
+        const struct clk_ops    *fix_fact_ops;
+
+        struct owl_clk_common   common;
+};
+
+#define OWL_COMP_DIV(_struct, _name, _parent,                           \
+                     _mux, _gate, _div, _flags)                         \
+        struct owl_composite _struct = {                                \
+                .mux_hw         = _mux,                                 \
+                .gate_hw        = _gate,                                \
+                .rate.div_hw    = _div,                                 \
+                .common = {                                             \
+                        .regmap         = NULL,                         \
+                        .hw.init        = CLK_HW_INIT_PARENTS(_name,    \
+                                                     _parent,           \
+                                                      &owl_comp_div_ops,\
+                                                     _flags),           \
+                },                                                      \
+        }
+
+#define OWL_COMP_DIV_FIXED(_struct, _name, _parent,                     \
+                     _gate, _div, _flags)                               \
+        struct owl_composite _struct = {                                \
+                .gate_hw        = _gate,                                \
+                .rate.div_hw    = _div,                                 \
+                .common = {                                             \
+                        .regmap         = NULL,                         \
+                        .hw.init        = CLK_HW_INIT(_name,            \
+                                                     _parent,           \
+                                                      &owl_comp_div_ops,\
+                                                     _flags),           \
+                },                                                      \
+        }
+
+#define OWL_COMP_FACTOR(_struct, _name, _parent,                        \
+                        _mux, _gate, _factor, _flags)                   \
+        struct owl_composite _struct = {                                \
+                .mux_hw         = _mux,                                 \
+                .gate_hw        = _gate,                                \
+                .rate.factor_hw = _factor,                              \
+                .common = {                                             \
+                        .regmap         = NULL,                         \
+                        .hw.init        = CLK_HW_INIT_PARENTS(_name,    \
+                                                     _parent,           \
+                                                     &owl_comp_fact_ops,\
+                                                     _flags),           \
+                },                                                      \
+        }
+
+#define OWL_COMP_FIXED_FACTOR(_struct, _name, _parent,                  \
+                        _gate, _mul, _div, _flags)                      \
+        struct owl_composite _struct = {                                \
+                .gate_hw                = _gate,                        \
+                .rate.fix_fact_hw.mult  = _mul,                         \
+                .rate.fix_fact_hw.div   = _div,                         \
+                .fix_fact_ops           = &clk_fixed_factor_ops,        \
+                .common = {                                             \
+                        .regmap         = NULL,                         \
+                        .hw.init        = CLK_HW_INIT(_name,            \
+                                                 _parent,               \
+                                                 &owl_comp_fix_fact_ops,\
+                                                 _flags),               \
+                },                                                      \
+        }
+
+#define OWL_COMP_PASS(_struct, _name, _parent,                          \
+                      _mux, _gate, _flags)                              \
+        struct owl_composite _struct = {                                \
+                .mux_hw         = _mux,                                 \
+                .gate_hw        = _gate,                                \
+                .common = {                                             \
+                        .regmap         = NULL,                         \
+                        .hw.init        = CLK_HW_INIT_PARENTS(_name,    \
+                                                     _parent,           \
+                                                     &owl_comp_pass_ops,\
+                                                     _flags),           \
+                },                                                      \
+        }
+
+static inline struct owl_composite *hw_to_owl_comp(const struct clk_hw *hw)
+{
+        struct owl_clk_common *common = hw_to_owl_clk_common(hw);
+
+        return container_of(common, struct owl_composite, common);
+}
+
+extern const struct clk_ops owl_comp_div_ops;
+extern const struct clk_ops owl_comp_fact_ops;
+extern const struct clk_ops owl_comp_fix_fact_ops;
+extern const struct clk_ops owl_comp_pass_ops;
+extern const struct clk_ops clk_fixed_factor_ops;
+
+#endif /* _OWL_COMPOSITE_H_ */
diff --git a/drivers/clk/actions/owl-divider.c b/drivers/clk/actions/owl-divider.c
new file mode 100644
index 000000000000..cddac00fe324
--- /dev/null
+++ b/drivers/clk/actions/owl-divider.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL divider clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include "owl-divider.h"
+
+long owl_divider_helper_round_rate(struct owl_clk_common *common,
+                                const struct owl_divider_hw *div_hw,
+                                unsigned long rate,
+                                unsigned long *parent_rate)
+{
+        return divider_round_rate(&common->hw, rate, parent_rate,
+                                  div_hw->table, div_hw->width,
+                                  div_hw->div_flags);
+}
+
+static long owl_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *parent_rate)
+{
+        struct owl_divider *div = hw_to_owl_divider(hw);
+
+        return owl_divider_helper_round_rate(&div->common, &div->div_hw,
+                                             rate, parent_rate);
+}
+
+unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common,
+                                         const struct owl_divider_hw *div_hw,
+                                         unsigned long parent_rate)
+{
+        unsigned long val;
+        unsigned int reg;
+
+        regmap_read(common->regmap, div_hw->reg, &reg);
+        val = reg >> div_hw->shift;
+        val &= (1 << div_hw->width) - 1;
+
+        return divider_recalc_rate(&common->hw, parent_rate,
+                                   val, div_hw->table,
+                                   div_hw->div_flags,
+                                   div_hw->width);
+}
+
+static unsigned long owl_divider_recalc_rate(struct clk_hw *hw,
+                                          unsigned long parent_rate)
+{
+        struct owl_divider *div = hw_to_owl_divider(hw);
+
+        return owl_divider_helper_recalc_rate(&div->common,
+                                              &div->div_hw, parent_rate);
+}
+
+int owl_divider_helper_set_rate(const struct owl_clk_common *common,
+                                const struct owl_divider_hw *div_hw,
+                                unsigned long rate,
+                                unsigned long parent_rate)
+{
+        unsigned long val;
+        unsigned int reg;
+
+        val = divider_get_val(rate, parent_rate, div_hw->table,
+                              div_hw->width, 0);
+
+        regmap_read(common->regmap, div_hw->reg, &reg);
+        reg &= ~GENMASK(div_hw->width + div_hw->shift - 1, div_hw->shift);
+
+        regmap_write(common->regmap, div_hw->reg,
+                          reg | (val << div_hw->shift));
+
+        return 0;
+}
+
+static int owl_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        struct owl_divider *div = hw_to_owl_divider(hw);
+
+        return owl_divider_helper_set_rate(&div->common, &div->div_hw,
+                                        rate, parent_rate);
+}
+
+const struct clk_ops owl_divider_ops = {
+        .recalc_rate = owl_divider_recalc_rate,
+        .round_rate = owl_divider_round_rate,
+        .set_rate = owl_divider_set_rate,
+};
diff --git a/drivers/clk/actions/owl-divider.h b/drivers/clk/actions/owl-divider.h
new file mode 100644
index 000000000000..92d3e3d23967
--- /dev/null
+++ b/drivers/clk/actions/owl-divider.h
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL divider clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_DIVIDER_H_
+#define _OWL_DIVIDER_H_
+
+#include "owl-common.h"
+
+struct owl_divider_hw {
+        u32                     reg;
+        u8                      shift;
+        u8                      width;
+        u8                      div_flags;
+        struct clk_div_table    *table;
+};
+
+struct owl_divider {
+        struct owl_divider_hw   div_hw;
+        struct owl_clk_common   common;
+};
+
+#define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table)        \
+        {                                                               \
+                .reg            = _reg,                                 \
+                .shift          = _shift,                               \
+                .width          = _width,                               \
+                .div_flags      = _div_flags,                           \
+                .table          = _table,                               \
+        }
+
+#define OWL_DIVIDER(_struct, _name, _parent, _reg,                      \
+                    _shift, _width, _table, _div_flags, _flags)         \
+        struct owl_divider _struct = {                                  \
+                .div_hw = OWL_DIVIDER_HW(_reg, _shift, _width,          \
+                                         _div_flags, _table),           \
+                .common = {                                             \
+                        .regmap         = NULL,                         \
+                        .hw.init        = CLK_HW_INIT(_name,            \
+                                                      _parent,          \
+                                                      &owl_divider_ops, \
+                                                      _flags),          \
+                },                                                      \
+        }
+
+static inline struct owl_divider *hw_to_owl_divider(const struct clk_hw *hw)
+{
+        struct owl_clk_common *common = hw_to_owl_clk_common(hw);
+
+        return container_of(common, struct owl_divider, common);
+}
+
+long owl_divider_helper_round_rate(struct owl_clk_common *common,
+                                const struct owl_divider_hw *div_hw,
+                                unsigned long rate,
+                                unsigned long *parent_rate);
+
+unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common,
+                                         const struct owl_divider_hw *div_hw,
+                                         unsigned long parent_rate);
+
+int owl_divider_helper_set_rate(const struct owl_clk_common *common,
+                                const struct owl_divider_hw *div_hw,
+                                unsigned long rate,
+                                unsigned long parent_rate);
+
+extern const struct clk_ops owl_divider_ops;
+
+#endif /* _OWL_DIVIDER_H_ */
diff --git a/drivers/clk/actions/owl-factor.c b/drivers/clk/actions/owl-factor.c
new file mode 100644
index 000000000000..317d4a9e112e
--- /dev/null
+++ b/drivers/clk/actions/owl-factor.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL factor clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include "owl-factor.h"
+
+static unsigned int _get_table_maxval(const struct clk_factor_table *table)
+{
+        unsigned int maxval = 0;
+        const struct clk_factor_table *clkt;
+
+        for (clkt = table; clkt->div; clkt++)
+                if (clkt->val > maxval)
+                        maxval = clkt->val;
+        return maxval;
+}
+
+static int _get_table_div_mul(const struct clk_factor_table *table,
+                        unsigned int val, unsigned int *mul, unsigned int *div)
+{
+        const struct clk_factor_table *clkt;
+
+        for (clkt = table; clkt->div; clkt++) {
+                if (clkt->val == val) {
+                        *mul = clkt->mul;
+                        *div = clkt->div;
+                        return 1;
+                }
+        }
+
+        return 0;
+}
+
+static unsigned int _get_table_val(const struct clk_factor_table *table,
+                        unsigned long rate, unsigned long parent_rate)
+{
+        const struct clk_factor_table *clkt;
+        int val = -1;
+        u64 calc_rate;
+
+        for (clkt = table; clkt->div; clkt++) {
+                calc_rate = parent_rate * clkt->mul;
+                do_div(calc_rate, clkt->div);
+
+                if ((unsigned long)calc_rate <= rate) {
+                        val = clkt->val;
+                        break;
+                }
+        }
+
+        if (val == -1)
+                val = _get_table_maxval(table);
+
+        return val;
+}
+
+static int clk_val_best(struct clk_hw *hw, unsigned long rate,
+                        unsigned long *best_parent_rate)
+{
+        struct owl_factor *factor = hw_to_owl_factor(hw);
+        struct owl_factor_hw *factor_hw = &factor->factor_hw;
+        const struct clk_factor_table *clkt = factor_hw->table;
+        unsigned long parent_rate, try_parent_rate, best = 0, cur_rate;
+        unsigned long parent_rate_saved = *best_parent_rate;
+        int bestval = 0;
+
+        if (!rate)
+                rate = 1;
+
+        if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
+                parent_rate = *best_parent_rate;
+                bestval = _get_table_val(clkt, rate, parent_rate);
+                return bestval;
+        }
+
+        for (clkt = factor_hw->table; clkt->div; clkt++) {
+                try_parent_rate = rate * clkt->div / clkt->mul;
+
+                if (try_parent_rate == parent_rate_saved) {
+                        pr_debug("%s: [%d %d %d] found try_parent_rate %ld\n",
+                                __func__, clkt->val, clkt->mul, clkt->div,
+                                try_parent_rate);
+                        /*
+                         * It's the most ideal case if the requested rate can be
+                         * divided from parent clock without any need to change
+                         * parent rate, so return the divider immediately.
+                         */
+                        *best_parent_rate = parent_rate_saved;
+                        return clkt->val;
+                }
+
+                parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
+                                try_parent_rate);
+                cur_rate = DIV_ROUND_UP(parent_rate, clkt->div) * clkt->mul;
+                if (cur_rate <= rate && cur_rate > best) {
+                        bestval = clkt->val;
+                        best = cur_rate;
+                        *best_parent_rate = parent_rate;
+                }
+        }
+
+        if (!bestval) {
+                bestval = _get_table_maxval(clkt);
+                *best_parent_rate = clk_hw_round_rate(
+                                clk_hw_get_parent(hw), 1);
+        }
+
+        return bestval;
+}
+
+long owl_factor_helper_round_rate(struct owl_clk_common *common,
+                                const struct owl_factor_hw *factor_hw,
+                                unsigned long rate,
+                                unsigned long *parent_rate)
+{
+        const struct clk_factor_table *clkt = factor_hw->table;
+        unsigned int val, mul = 0, div = 1;
+
+        val = clk_val_best(&common->hw, rate, parent_rate);
+        _get_table_div_mul(clkt, val, &mul, &div);
+
+        return *parent_rate * mul / div;
+}
+
+static long owl_factor_round_rate(struct clk_hw *hw, unsigned long rate,
+                        unsigned long *parent_rate)
+{
+        struct owl_factor *factor = hw_to_owl_factor(hw);
+        struct owl_factor_hw *factor_hw = &factor->factor_hw;
+
+        return owl_factor_helper_round_rate(&factor->common, factor_hw,
+                                        rate, parent_rate);
+}
+
+unsigned long owl_factor_helper_recalc_rate(struct owl_clk_common *common,
+                                         const struct owl_factor_hw *factor_hw,
+                                         unsigned long parent_rate)
+{
+        const struct clk_factor_table *clkt = factor_hw->table;
+        unsigned long long int rate;
+        u32 reg, val, mul, div;
+
+        div = 0;
+        mul = 0;
+
+        regmap_read(common->regmap, factor_hw->reg, &reg);
+
+        val = reg >> factor_hw->shift;
+        val &= div_mask(factor_hw);
+
+        _get_table_div_mul(clkt, val, &mul, &div);
+        if (!div) {
+                WARN(!(factor_hw->fct_flags & CLK_DIVIDER_ALLOW_ZERO),
+                        "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
+                        __clk_get_name(common->hw.clk));
+                return parent_rate;
+        }
+
+        rate = (unsigned long long int)parent_rate * mul;
+        do_div(rate, div);
+
+        return rate;
+}
+
+static unsigned long owl_factor_recalc_rate(struct clk_hw *hw,
+                        unsigned long parent_rate)
+{
+        struct owl_factor *factor = hw_to_owl_factor(hw);
+        struct owl_factor_hw *factor_hw = &factor->factor_hw;
+        struct owl_clk_common *common = &factor->common;
+
+        return owl_factor_helper_recalc_rate(common, factor_hw, parent_rate);
+}
+
+int owl_factor_helper_set_rate(const struct owl_clk_common *common,
+                                const struct owl_factor_hw *factor_hw,
+                                unsigned long rate,
+                                unsigned long parent_rate)
+{
+        u32 val, reg;
+
+        val = _get_table_val(factor_hw->table, rate, parent_rate);
+
+        if (val > div_mask(factor_hw))
+                val = div_mask(factor_hw);
+
+        regmap_read(common->regmap, factor_hw->reg, &reg);
+
+        reg &= ~(div_mask(factor_hw) << factor_hw->shift);
+        reg |= val << factor_hw->shift;
+
+        regmap_write(common->regmap, factor_hw->reg, reg);
+
+        return 0;
+}
+
+static int owl_factor_set_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long parent_rate)
+{
+        struct owl_factor *factor = hw_to_owl_factor(hw);
+        struct owl_factor_hw *factor_hw = &factor->factor_hw;
+        struct owl_clk_common *common = &factor->common;
+
+        return owl_factor_helper_set_rate(common, factor_hw,
+                                        rate, parent_rate);
+}
+
+const struct clk_ops owl_factor_ops = {
+        .round_rate     = owl_factor_round_rate,
+        .recalc_rate    = owl_factor_recalc_rate,
+        .set_rate       = owl_factor_set_rate,
+};
diff --git a/drivers/clk/actions/owl-factor.h b/drivers/clk/actions/owl-factor.h
new file mode 100644
index 000000000000..f1a7ffe896e1
--- /dev/null
+++ b/drivers/clk/actions/owl-factor.h
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL factor clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_FACTOR_H_
+#define _OWL_FACTOR_H_
+
+#include "owl-common.h"
+
+struct clk_factor_table {
+        unsigned int            val;
+        unsigned int            mul;
+        unsigned int            div;
+};
+
+struct owl_factor_hw {
+        u32                     reg;
+        u8                      shift;
+        u8                      width;
+        u8                      fct_flags;
+        struct clk_factor_table *table;
+};
+
+struct owl_factor {
+        struct owl_factor_hw    factor_hw;
+        struct owl_clk_common   common;
+};
+
+#define OWL_FACTOR_HW(_reg, _shift, _width, _fct_flags, _table)         \
+        {                                                               \
+                .reg            = _reg,                                 \
+                .shift          = _shift,                               \
+                .width          = _width,                               \
+                .fct_flags      = _fct_flags,                           \
+                .table          = _table,                               \
+        }
+
+#define OWL_FACTOR(_struct, _name, _parent, _reg,                       \
+                   _shift, _width, _table, _fct_flags, _flags)          \
+        struct owl_factor _struct = {                                   \
+                .factor_hw = OWL_FACTOR_HW(_reg, _shift,                \
+                                           _width, _fct_flags, _table), \
+                .common = {                                             \
+                        .regmap         = NULL,                         \
+                        .hw.init        = CLK_HW_INIT(_name,            \
+                                                      _parent,          \
+                                                      &owl_factor_ops,  \
+                                                      _flags),          \
+                },                                                      \
+        }
+
+#define div_mask(d) ((1 << ((d)->width)) - 1)
+
+static inline struct owl_factor *hw_to_owl_factor(const struct clk_hw *hw)
+{
+        struct owl_clk_common *common = hw_to_owl_clk_common(hw);
+
+        return container_of(common, struct owl_factor, common);
+}
+
+long owl_factor_helper_round_rate(struct owl_clk_common *common,
+                                const struct owl_factor_hw *factor_hw,
+                                unsigned long rate,
+                                unsigned long *parent_rate);
+
+unsigned long owl_factor_helper_recalc_rate(struct owl_clk_common *common,
+                                         const struct owl_factor_hw *factor_hw,
+                                         unsigned long parent_rate);
+
+int owl_factor_helper_set_rate(const struct owl_clk_common *common,
+                                const struct owl_factor_hw *factor_hw,
+                                unsigned long rate,
+                                unsigned long parent_rate);
+
+extern const struct clk_ops owl_factor_ops;
+
+#endif /* _OWL_FACTOR_H_ */
diff --git a/drivers/clk/actions/owl-fixed-factor.h b/drivers/clk/actions/owl-fixed-factor.h
new file mode 100644
index 000000000000..cc9fe36c0964
--- /dev/null
+++ b/drivers/clk/actions/owl-fixed-factor.h
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL fixed factor clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_FIXED_FACTOR_H_
+#define _OWL_FIXED_FACTOR_H_
+
+#include "owl-common.h"
+
+#define OWL_FIX_FACT(_struct, _name, _parent, _mul, _div, _flags)       \
+        struct clk_fixed_factor _struct = {                             \
+                .mult           = _mul,                                 \
+                .div            = _div,                                 \
+                .hw.init        = CLK_HW_INIT(_name,                    \
+                                              _parent,                  \
+                                              &clk_fixed_factor_ops,    \
+                                              _flags),                  \
+        }
+
+extern const struct clk_ops clk_fixed_factor_ops;
+
+#endif /* _OWL_FIXED_FACTOR_H_ */
diff --git a/drivers/clk/actions/owl-gate.c b/drivers/clk/actions/owl-gate.c
new file mode 100644
index 000000000000..f11500ba46a7
--- /dev/null
+++ b/drivers/clk/actions/owl-gate.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL gate clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include "owl-gate.h"
+
+void owl_gate_set(const struct owl_clk_common *common,
+                 const struct owl_gate_hw *gate_hw, bool enable)
+{
+        int set = gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
+        u32 reg;
+
+        set ^= enable;
+
+        regmap_read(common->regmap, gate_hw->reg, &reg);
+
+        if (set)
+                reg |= BIT(gate_hw->bit_idx);
+        else
+                reg &= ~BIT(gate_hw->bit_idx);
+
+        regmap_write(common->regmap, gate_hw->reg, reg);
+}
+
+static void owl_gate_disable(struct clk_hw *hw)
+{
+        struct owl_gate *gate = hw_to_owl_gate(hw);
+        struct owl_clk_common *common = &gate->common;
+
+        owl_gate_set(common, &gate->gate_hw, false);
+}
+
+static int owl_gate_enable(struct clk_hw *hw)
+{
+        struct owl_gate *gate = hw_to_owl_gate(hw);
+        struct owl_clk_common *common = &gate->common;
+
+        owl_gate_set(common, &gate->gate_hw, true);
+
+        return 0;
+}
+
+int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
+                   const struct owl_gate_hw *gate_hw)
+{
+        u32 reg;
+
+        regmap_read(common->regmap, gate_hw->reg, &reg);
+
+        if (gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE)
+                reg ^= BIT(gate_hw->bit_idx);
+
+        return !!(reg & BIT(gate_hw->bit_idx));
+}
+
+static int owl_gate_is_enabled(struct clk_hw *hw)
+{
+        struct owl_gate *gate = hw_to_owl_gate(hw);
+        struct owl_clk_common *common = &gate->common;
+
+        return owl_gate_clk_is_enabled(common, &gate->gate_hw);
+}
+
+const struct clk_ops owl_gate_ops = {
+        .disable        = owl_gate_disable,
+        .enable         = owl_gate_enable,
+        .is_enabled     = owl_gate_is_enabled,
+};
diff --git a/drivers/clk/actions/owl-gate.h b/drivers/clk/actions/owl-gate.h
new file mode 100644
index 000000000000..c2d61ceebce2
--- /dev/null
+++ b/drivers/clk/actions/owl-gate.h
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL gate clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_GATE_H_
+#define _OWL_GATE_H_
+
+#include "owl-common.h"
+
+struct owl_gate_hw {
+        u32                     reg;
+        u8                      bit_idx;
+        u8                      gate_flags;
+};
+
+struct owl_gate {
+        struct owl_gate_hw      gate_hw;
+        struct owl_clk_common   common;
+};
+
+#define OWL_GATE_HW(_reg, _bit_idx, _gate_flags)        \
+        {                                               \
+                .reg            = _reg,                 \
+                .bit_idx        = _bit_idx,             \
+                .gate_flags     = _gate_flags,          \
+        }
+
+#define OWL_GATE(_struct, _name, _parent, _reg,                         \
+                _bit_idx, _gate_flags, _flags)                          \
+        struct owl_gate _struct = {                                     \
+                .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags),    \
+                .common = {                                             \
+                        .regmap         = NULL,                         \
+                        .hw.init        = CLK_HW_INIT(_name,            \
+                                                      _parent,          \
+                                                      &owl_gate_ops,    \
+                                                      _flags),          \
+                }                                                       \
+        }                                                               \
+
+#define OWL_GATE_NO_PARENT(_struct, _name, _reg,                        \
+                _bit_idx, _gate_flags, _flags)                          \
+        struct owl_gate _struct = {                                     \
+                .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags),    \
+                .common = {                                             \
+                        .regmap         = NULL,                         \
+                        .hw.init        = CLK_HW_INIT_NO_PARENT(_name,  \
+                                                      &owl_gate_ops,    \
+                                                      _flags),          \
+                },                                                      \
+        }                                                               \
+
+static inline struct owl_gate *hw_to_owl_gate(const struct clk_hw *hw)
+{
+        struct owl_clk_common *common = hw_to_owl_clk_common(hw);
+
+        return container_of(common, struct owl_gate, common);
+}
+
+void owl_gate_set(const struct owl_clk_common *common,
+                 const struct owl_gate_hw *gate_hw, bool enable);
+int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
+                   const struct owl_gate_hw *gate_hw);
+
+extern const struct clk_ops owl_gate_ops;
+
+#endif /* _OWL_GATE_H_ */
diff --git a/drivers/clk/actions/owl-mux.c b/drivers/clk/actions/owl-mux.c
new file mode 100644
index 000000000000..f9c6cf2540e4
--- /dev/null
+++ b/drivers/clk/actions/owl-mux.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL mux clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include "owl-mux.h"
+
+u8 owl_mux_helper_get_parent(const struct owl_clk_common *common,
+                             const struct owl_mux_hw *mux_hw)
+{
+        u32 reg;
+        u8 parent;
+
+        regmap_read(common->regmap, mux_hw->reg, &reg);
+        parent = reg >> mux_hw->shift;
+        parent &= BIT(mux_hw->width) - 1;
+
+        return parent;
+}
+
+static u8 owl_mux_get_parent(struct clk_hw *hw)
+{
+        struct owl_mux *mux = hw_to_owl_mux(hw);
+
+        return owl_mux_helper_get_parent(&mux->common, &mux->mux_hw);
+}
+
+int owl_mux_helper_set_parent(const struct owl_clk_common *common,
+                              struct owl_mux_hw *mux_hw, u8 index)
+{
+        u32 reg;
+
+        regmap_read(common->regmap, mux_hw->reg, &reg);
+        reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift);
+        regmap_write(common->regmap, mux_hw->reg,
+                        reg | (index << mux_hw->shift));
+
+        return 0;
+}
+
+static int owl_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct owl_mux *mux = hw_to_owl_mux(hw);
+
+        return owl_mux_helper_set_parent(&mux->common, &mux->mux_hw, index);
+}
+
+const struct clk_ops owl_mux_ops = {
+        .get_parent = owl_mux_get_parent,
+        .set_parent = owl_mux_set_parent,
+        .determine_rate = __clk_mux_determine_rate,
+};
diff --git a/drivers/clk/actions/owl-mux.h b/drivers/clk/actions/owl-mux.h
new file mode 100644
index 000000000000..834284c8c3ae
--- /dev/null
+++ b/drivers/clk/actions/owl-mux.h
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL mux clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_MUX_H_
+#define _OWL_MUX_H_
+
+#include "owl-common.h"
+
+struct owl_mux_hw {
+        u32                     reg;
+        u8                      shift;
+        u8                      width;
+};
+
+struct owl_mux {
+        struct owl_mux_hw       mux_hw;
+        struct owl_clk_common   common;
+};
+
+#define OWL_MUX_HW(_reg, _shift, _width)                \
+        {                                               \
+                .reg    = _reg,                         \
+                .shift  = _shift,                       \
+                .width  = _width,                       \
+        }
+
+#define OWL_MUX(_struct, _name, _parents, _reg,                         \
+                _shift, _width, _flags)                                 \
+        struct owl_mux _struct = {                                      \
+                .mux_hw = OWL_MUX_HW(_reg, _shift, _width),             \
+                .common = {                                             \
+                        .regmap = NULL,                                 \
+                        .hw.init = CLK_HW_INIT_PARENTS(_name,           \
+                                                       _parents,        \
+                                                       &owl_mux_ops,    \
+                                                       _flags),         \
+                },                                                      \
+        }
+
+static inline struct owl_mux *hw_to_owl_mux(const struct clk_hw *hw)
+{
+        struct owl_clk_common *common = hw_to_owl_clk_common(hw);
+
+        return container_of(common, struct owl_mux, common);
+}
+
+u8 owl_mux_helper_get_parent(const struct owl_clk_common *common,
+                             const struct owl_mux_hw *mux_hw);
+int owl_mux_helper_set_parent(const struct owl_clk_common *common,
+                              struct owl_mux_hw *mux_hw, u8 index);
+
+extern const struct clk_ops owl_mux_ops;
+
+#endif /* _OWL_MUX_H_ */
diff --git a/drivers/clk/actions/owl-pll.c b/drivers/clk/actions/owl-pll.c
new file mode 100644
index 000000000000..058e06d7099f
--- /dev/null
+++ b/drivers/clk/actions/owl-pll.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL pll clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include "owl-pll.h"
+
+static u32 owl_pll_calculate_mul(struct owl_pll_hw *pll_hw, unsigned long rate)
+{
+        u32 mul;
+
+        mul = DIV_ROUND_CLOSEST(rate, pll_hw->bfreq);
+        if (mul < pll_hw->min_mul)
+                mul = pll_hw->min_mul;
+        else if (mul > pll_hw->max_mul)
+                mul = pll_hw->max_mul;
+
+        return mul &= mul_mask(pll_hw);
+}
+
+static unsigned long _get_table_rate(const struct clk_pll_table *table,
+                unsigned int val)
+{
+        const struct clk_pll_table *clkt;
+
+        for (clkt = table; clkt->rate; clkt++)
+                if (clkt->val == val)
+                        return clkt->rate;
+
+        return 0;
+}
+
+static const struct clk_pll_table *_get_pll_table(
+                const struct clk_pll_table *table, unsigned long rate)
+{
+        const struct clk_pll_table *clkt;
+
+        for (clkt = table; clkt->rate; clkt++) {
+                if (clkt->rate == rate) {
+                        table = clkt;
+                        break;
+                } else if (clkt->rate < rate)
+                        table = clkt;
+        }
+
+        return table;
+}
+
+static long owl_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long *parent_rate)
+{
+        struct owl_pll *pll = hw_to_owl_pll(hw);
+        struct owl_pll_hw *pll_hw = &pll->pll_hw;
+        const struct clk_pll_table *clkt;
+        u32 mul;
+
+        if (pll_hw->table) {
+                clkt = _get_pll_table(pll_hw->table, rate);
+                return clkt->rate;
+        }
+
+        /* fixed frequency */
+        if (pll_hw->width == 0)
+                return pll_hw->bfreq;
+
+        mul = owl_pll_calculate_mul(pll_hw, rate);
+
+        return pll_hw->bfreq * mul;
+}
+
+static unsigned long owl_pll_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct owl_pll *pll = hw_to_owl_pll(hw);
+        struct owl_pll_hw *pll_hw = &pll->pll_hw;
+        const struct owl_clk_common *common = &pll->common;
+        u32 val;
+
+        if (pll_hw->table) {
+                regmap_read(common->regmap, pll_hw->reg, &val);
+
+                val = val >> pll_hw->shift;
+                val &= mul_mask(pll_hw);
+
+                return _get_table_rate(pll_hw->table, val);
+        }
+
+        /* fixed frequency */
+        if (pll_hw->width == 0)
+                return pll_hw->bfreq;
+
+        regmap_read(common->regmap, pll_hw->reg, &val);
+
+        val = val >> pll_hw->shift;
+        val &= mul_mask(pll_hw);
+
+        return pll_hw->bfreq * val;
+}
+
+static int owl_pll_is_enabled(struct clk_hw *hw)
+{
+        struct owl_pll *pll = hw_to_owl_pll(hw);
+        struct owl_pll_hw *pll_hw = &pll->pll_hw;
+        const struct owl_clk_common *common = &pll->common;
+        u32 reg;
+
+        regmap_read(common->regmap, pll_hw->reg, &reg);
+
+        return !!(reg & BIT(pll_hw->bit_idx));
+}
+
+static void owl_pll_set(const struct owl_clk_common *common,
+                       const struct owl_pll_hw *pll_hw, bool enable)
+{
+        u32 reg;
+
+        regmap_read(common->regmap, pll_hw->reg, &reg);
+
+        if (enable)
+                reg |= BIT(pll_hw->bit_idx);
+        else
+                reg &= ~BIT(pll_hw->bit_idx);
+
+        regmap_write(common->regmap, pll_hw->reg, reg);
+}
+
+static int owl_pll_enable(struct clk_hw *hw)
+{
+        struct owl_pll *pll = hw_to_owl_pll(hw);
+        const struct owl_clk_common *common = &pll->common;
+
+        owl_pll_set(common, &pll->pll_hw, true);
+
+        return 0;
+}
+
+static void owl_pll_disable(struct clk_hw *hw)
+{
+        struct owl_pll *pll = hw_to_owl_pll(hw);
+        const struct owl_clk_common *common = &pll->common;
+
+        owl_pll_set(common, &pll->pll_hw, false);
+}
+
+static int owl_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct owl_pll *pll = hw_to_owl_pll(hw);
+        struct owl_pll_hw *pll_hw = &pll->pll_hw;
+        const struct owl_clk_common *common = &pll->common;
+        const struct clk_pll_table *clkt;
+        u32 val, reg;
+
+        /* fixed frequency */
+        if (pll_hw->width == 0)
+                return 0;
+
+        if (pll_hw->table) {
+                clkt = _get_pll_table(pll_hw->table, rate);
+                val = clkt->val;
+        } else {
+                val = owl_pll_calculate_mul(pll_hw, rate);
+        }
+
+        regmap_read(common->regmap, pll_hw->reg, &reg);
+
+        reg &= ~mul_mask(pll_hw);
+        reg |= val << pll_hw->shift;
+
+        regmap_write(common->regmap, pll_hw->reg, reg);
+
+        udelay(PLL_STABILITY_WAIT_US);
+
+        return 0;
+}
+
+const struct clk_ops owl_pll_ops = {
+        .enable = owl_pll_enable,
+        .disable = owl_pll_disable,
+        .is_enabled = owl_pll_is_enabled,
+        .round_rate = owl_pll_round_rate,
+        .recalc_rate = owl_pll_recalc_rate,
+        .set_rate = owl_pll_set_rate,
+};
diff --git a/drivers/clk/actions/owl-pll.h b/drivers/clk/actions/owl-pll.h
new file mode 100644
index 000000000000..0aae30abd5dc
--- /dev/null
+++ b/drivers/clk/actions/owl-pll.h
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL pll clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#ifndef _OWL_PLL_H_
+#define _OWL_PLL_H_
+
+#include "owl-common.h"
+
+/* last entry should have rate = 0 */
+struct clk_pll_table {
+        unsigned int            val;
+        unsigned long           rate;
+};
+
+struct owl_pll_hw {
+        u32                     reg;
+        u32                     bfreq;
+        u8                      bit_idx;
+        u8                      shift;
+        u8                      width;
+        u8                      min_mul;
+        u8                      max_mul;
+        const struct clk_pll_table *table;
+};
+
+struct owl_pll {
+        struct owl_pll_hw       pll_hw;
+        struct owl_clk_common   common;
+};
+
+#define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,                      \
+                   _width, _min_mul, _max_mul, _table)                  \
+        {                                                               \
+                .reg            = _reg,                                 \
+                .bfreq          = _bfreq,                               \
+                .bit_idx        = _bit_idx,                             \
+                .shift          = _shift,                               \
+                .width          = _width,                               \
+                .min_mul        = _min_mul,                             \
+                .max_mul        = _max_mul,                             \
+                .table          = _table,                               \
+        }
+
+#define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx,        \
+                _shift, _width, _min_mul, _max_mul, _table, _flags)     \
+        struct owl_pll _struct = {                                      \
+                .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,    \
+                                     _width, _min_mul,                  \
+                                     _max_mul, _table),                 \
+                .common = {                                             \
+                        .regmap = NULL,                                 \
+                        .hw.init = CLK_HW_INIT(_name,                   \
+                                               _parent,                 \
+                                               &owl_pll_ops,            \
+                                               _flags),                 \
+                },                                                      \
+        }
+
+#define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx,       \
+                _shift, _width, _min_mul, _max_mul, _table, _flags)     \
+        struct owl_pll _struct = {                                      \
+                .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,    \
+                                     _width, _min_mul,                  \
+                                     _max_mul, _table),                 \
+                .common = {                                             \
+                        .regmap = NULL,                                 \
+                        .hw.init = CLK_HW_INIT_NO_PARENT(_name,         \
+                                               &owl_pll_ops,            \
+                                               _flags),                 \
+                },                                                      \
+        }
+
+#define mul_mask(m)             ((1 << ((m)->width)) - 1)
+#define PLL_STABILITY_WAIT_US   (50)
+
+static inline struct owl_pll *hw_to_owl_pll(const struct clk_hw *hw)
+{
+        struct owl_clk_common *common = hw_to_owl_clk_common(hw);
+
+        return container_of(common, struct owl_pll, common);
+}
+
+extern const struct clk_ops owl_pll_ops;
+
+#endif /* _OWL_PLL_H_ */
diff --git a/drivers/clk/actions/owl-s900.c b/drivers/clk/actions/owl-s900.c
new file mode 100644
index 000000000000..7f60ed6afe63
--- /dev/null
+++ b/drivers/clk/actions/owl-s900.c
@@ -0,0 +1,721 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// OWL S900 SoC clock driver
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Author: David Liu <liuwei@actions-semi.com>
+//
+// Copyright (c) 2018 Linaro Ltd.
+// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "owl-common.h"
+#include "owl-composite.h"
+#include "owl-divider.h"
+#include "owl-factor.h"
+#include "owl-fixed-factor.h"
+#include "owl-gate.h"
+#include "owl-mux.h"
+#include "owl-pll.h"
+
+#include <dt-bindings/clock/actions,s900-cmu.h>
+
+#define CMU_COREPLL             (0x0000)
+#define CMU_DEVPLL              (0x0004)
+#define CMU_DDRPLL              (0x0008)
+#define CMU_NANDPLL             (0x000C)
+#define CMU_DISPLAYPLL          (0x0010)
+#define CMU_AUDIOPLL            (0x0014)
+#define CMU_TVOUTPLL            (0x0018)
+#define CMU_BUSCLK              (0x001C)
+#define CMU_SENSORCLK           (0x0020)
+#define CMU_LCDCLK              (0x0024)
+#define CMU_DSICLK              (0x0028)
+#define CMU_CSICLK              (0x002C)
+#define CMU_DECLK               (0x0030)
+#define CMU_BISPCLK             (0x0034)
+#define CMU_IMXCLK              (0x0038)
+#define CMU_HDECLK              (0x003C)
+#define CMU_VDECLK              (0x0040)
+#define CMU_VCECLK              (0x0044)
+#define CMU_NANDCCLK            (0x004C)
+#define CMU_SD0CLK              (0x0050)
+#define CMU_SD1CLK              (0x0054)
+#define CMU_SD2CLK              (0x0058)
+#define CMU_UART0CLK            (0x005C)
+#define CMU_UART1CLK            (0x0060)
+#define CMU_UART2CLK            (0x0064)
+#define CMU_PWM0CLK             (0x0070)
+#define CMU_PWM1CLK             (0x0074)
+#define CMU_PWM2CLK             (0x0078)
+#define CMU_PWM3CLK             (0x007C)
+#define CMU_USBPLL              (0x0080)
+#define CMU_ASSISTPLL           (0x0084)
+#define CMU_EDPCLK              (0x0088)
+#define CMU_GPU3DCLK            (0x0090)
+#define CMU_CORECTL             (0x009C)
+#define CMU_DEVCLKEN0           (0x00A0)
+#define CMU_DEVCLKEN1           (0x00A4)
+#define CMU_DEVRST0             (0x00A8)
+#define CMU_DEVRST1             (0x00AC)
+#define CMU_UART3CLK            (0x00B0)
+#define CMU_UART4CLK            (0x00B4)
+#define CMU_UART5CLK            (0x00B8)
+#define CMU_UART6CLK            (0x00BC)
+#define CMU_TLSCLK              (0x00C0)
+#define CMU_SD3CLK              (0x00C4)
+#define CMU_PWM4CLK             (0x00C8)
+#define CMU_PWM5CLK             (0x00CC)
+
+static struct clk_pll_table clk_audio_pll_table[] = {
+        { 0, 45158400 }, { 1, 49152000 },
+        { 0, 0 },
+};
+
+static struct clk_pll_table clk_edp_pll_table[] = {
+        { 0, 810000000 }, { 1, 135000000 }, { 2, 270000000 },
+        { 0, 0 },
+};
+
+/* pll clocks */
+static OWL_PLL_NO_PARENT(core_pll_clk, "core_pll_clk", CMU_COREPLL, 24000000, 9, 0, 8, 5, 107, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(dev_pll_clk, "dev_pll_clk", CMU_DEVPLL, 6000000, 8, 0, 8, 20, 180, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(ddr_pll_clk, "ddr_pll_clk", CMU_DDRPLL, 24000000, 8, 0, 8, 5, 45, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(nand_pll_clk, "nand_pll_clk", CMU_NANDPLL, 6000000, 8, 0, 8, 4, 100, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(display_pll_clk, "display_pll_clk", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 20, 180, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(assist_pll_clk, "assist_pll_clk", CMU_ASSISTPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED);
+static OWL_PLL_NO_PARENT(audio_pll_clk, "audio_pll_clk", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED);
+static OWL_PLL(edp_pll_clk, "edp_pll_clk", "edp24M_clk", CMU_EDPCLK, 0, 9, 0, 2, 0, 0, clk_edp_pll_table, CLK_IGNORE_UNUSED);
+
+static const char *cpu_clk_mux_p[] = { "losc", "hosc", "core_pll_clk", };
+static const char *dev_clk_p[] = { "hosc", "dev_pll_clk", };
+static const char *noc_clk_mux_p[] = { "dev_clk", "assist_pll_clk", };
+static const char *dmm_clk_mux_p[] = { "dev_clk", "nand_pll_clk", "assist_pll_clk", "ddr_clk_src", };
+static const char *bisp_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
+static const char *csi_clk_mux_p[] = { "display_pll_clk", "dev_clk", };
+static const char *de_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
+static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll_clk", "ddr_clk_src", };
+static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll_clk", "ddr_clk_src", };
+static const char *imx_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
+static const char *lcd_clk_mux_p[] = { "display_pll_clk", "nand_pll_clk", };
+static const char *nand_clk_mux_p[] = { "dev_clk", "nand_pll_clk", };
+static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk", };
+static const char *sensor_clk_mux_p[] = { "hosc", "bisp_clk", };
+static const char *uart_clk_mux_p[] = { "hosc", "dev_pll_clk", };
+static const char *vce_clk_mux_p[] = { "dev_clk", "display_pll_clk", "assist_pll_clk", "ddr_clk_src", };
+static const char *i2s_clk_mux_p[] = { "audio_pll_clk", };
+static const char *edp_clk_mux_p[] = { "assist_pll_clk", "display_pll_clk", };
+
+/* mux clocks */
+static OWL_MUX(cpu_clk, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
+static OWL_MUX(dev_clk, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
+static OWL_MUX(noc_clk_mux, "noc_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 7, 1, CLK_SET_RATE_PARENT);
+
+static struct clk_div_table nand_div_table[] = {
+        { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 },
+        { 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 },
+        { 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 },
+        { 12, 24 }, { 13, 26 }, { 14, 28 }, { 15, 30 },
+        { 0, 0 },
+};
+
+static struct clk_div_table apb_div_table[] = {
+        { 1, 2 }, { 2, 3 }, { 3, 4 },
+        { 0, 0 },
+};
+
+static struct clk_div_table eth_mac_div_table[] = {
+        { 0, 2 }, { 1, 4 },
+        { 0, 0 },
+};
+
+static struct clk_div_table rmii_ref_div_table[] = {
+        { 0, 4 },         { 1, 10 },
+        { 0, 0 },
+};
+
+static struct clk_div_table usb3_mac_div_table[] = {
+        { 1, 2 }, { 2, 3 }, { 3, 4 },
+        { 0, 8 },
+};
+
+static struct clk_div_table i2s_div_table[] = {
+        { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
+        { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
+        { 8, 24 },
+        { 0, 0 },
+};
+
+static struct clk_div_table hdmia_div_table[] = {
+        { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
+        { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
+        { 8, 24 },
+        { 0, 0 },
+};
+
+/* divider clocks */
+static OWL_DIVIDER(noc_clk_div, "noc_clk_div", "noc_clk", CMU_BUSCLK, 19, 1, NULL, 0, 0);
+static OWL_DIVIDER(ahb_clk, "ahb_clk", "noc_clk_div", CMU_BUSCLK, 4, 1, NULL, 0, 0);
+static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK, 8, 2, apb_div_table, 0, 0);
+static OWL_DIVIDER(usb3_mac_clk, "usb3_mac_clk", "assist_pll_clk", CMU_ASSISTPLL, 12, 2, usb3_mac_div_table, 0, 0);
+static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "assist_pll_clk", CMU_ASSISTPLL, 8, 1, rmii_ref_div_table, 0, 0);
+
+static struct clk_factor_table sd_factor_table[] = {
+        /* bit0 ~ 4 */
+        { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
+        { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
+        { 8, 1, 9 }, { 9, 1, 10 }, { 10, 1, 11 }, { 11, 1, 12 },
+        { 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
+        { 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
+        { 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
+        { 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 },
+        { 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 },
+
+        /* bit8: /128 */
+        { 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
+        { 260, 1, 5 * 128 }, { 261, 1, 6 * 128 }, { 262, 1, 7 * 128 }, { 263, 1, 8 * 128 },
+        { 264, 1, 9 * 128 }, { 265, 1, 10 * 128 }, { 266, 1, 11 * 128 }, { 267, 1, 12 * 128 },
+        { 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
+        { 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
+        { 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
+        { 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 },
+        { 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 },
+
+        { 0, 0 },
+};
+
+static struct clk_factor_table dmm_factor_table[] = {
+        { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 },
+        { 4, 1, 4 },
+        { 0, 0, 0 },
+};
+
+static struct clk_factor_table noc_factor_table[] = {
+        { 0, 1, 1 },   { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 }, { 4, 1, 4 },
+        { 0, 0, 0 },
+};
+
+static struct clk_factor_table bisp_factor_table[] = {
+        { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
+        { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
+        { 0, 0, 0 },
+};
+
+/* factor clocks */
+static OWL_FACTOR(noc_clk, "noc_clk", "noc_clk_mux", CMU_BUSCLK, 16, 3, noc_factor_table, 0, 0);
+static OWL_FACTOR(de_clk1, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0);
+static OWL_FACTOR(de_clk2, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0);
+static OWL_FACTOR(de_clk3, "de_clk3", "de_clk", CMU_DECLK, 8, 3, bisp_factor_table, 0, 0);
+
+/* gate clocks */
+static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
+static OWL_GATE_NO_PARENT(gpu_clk, "gpu_clk", CMU_DEVCLKEN0, 30, 0, 0);
+static OWL_GATE(dmac_clk, "dmac_clk", "noc_clk_div", CMU_DEVCLKEN0, 1, 0, 0);
+static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
+static OWL_GATE_NO_PARENT(dsi_clk, "dsi_clk", CMU_DEVCLKEN0, 12, 0, 0);
+static OWL_GATE(ddr0_clk, "ddr0_clk", "ddr_pll_clk", CMU_DEVCLKEN0, 31, 0, CLK_IGNORE_UNUSED);
+static OWL_GATE(ddr1_clk, "ddr1_clk", "ddr_pll_clk", CMU_DEVCLKEN0, 29, 0, CLK_IGNORE_UNUSED);
+static OWL_GATE_NO_PARENT(usb3_480mpll0_clk, "usb3_480mpll0_clk", CMU_USBPLL, 3, 0, 0);
+static OWL_GATE_NO_PARENT(usb3_480mphy0_clk, "usb3_480mphy0_clk", CMU_USBPLL, 2, 0, 0);
+static OWL_GATE_NO_PARENT(usb3_5gphy_clk, "usb3_5gphy_clk", CMU_USBPLL, 1, 0, 0);
+static OWL_GATE_NO_PARENT(usb3_cce_clk, "usb3_cce_clk", CMU_USBPLL, 0, 0, 0);
+static OWL_GATE(edp24M_clk, "edp24M_clk", "diff24M", CMU_EDPCLK, 8, 0, 0);
+static OWL_GATE(edp_link_clk, "edp_link_clk", "edp_pll_clk", CMU_DEVCLKEN0, 10, 0, 0);
+static OWL_GATE_NO_PARENT(usbh0_pllen_clk, "usbh0_pllen_clk", CMU_USBPLL, 12, 0, 0);
+static OWL_GATE_NO_PARENT(usbh0_phy_clk, "usbh0_phy_clk", CMU_USBPLL, 10, 0, 0);
+static OWL_GATE_NO_PARENT(usbh0_cce_clk, "usbh0_cce_clk", CMU_USBPLL, 8, 0, 0);
+static OWL_GATE_NO_PARENT(usbh1_pllen_clk, "usbh1_pllen_clk", CMU_USBPLL, 13, 0, 0);
+static OWL_GATE_NO_PARENT(usbh1_phy_clk, "usbh1_phy_clk", CMU_USBPLL, 11, 0, 0);
+static OWL_GATE_NO_PARENT(usbh1_cce_clk, "usbh1_cce_clk", CMU_USBPLL, 9, 0, 0);
+static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
+static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
+static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
+static OWL_GATE(spi3_clk, "spi3_clk", "ahb_clk", CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED);
+
+/* composite clocks */
+static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p,
+                        OWL_MUX_HW(CMU_BISPCLK, 4, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
+                        OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table),
+                        0);
+
+static OWL_COMP_DIV(csi0_clk, "csi0_clk", csi_clk_mux_p,
+                        OWL_MUX_HW(CMU_CSICLK, 4, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
+                        OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
+                        0);
+
+static OWL_COMP_DIV(csi1_clk, "csi1_clk", csi_clk_mux_p,
+                        OWL_MUX_HW(CMU_CSICLK, 20, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 15, 0),
+                        OWL_DIVIDER_HW(CMU_CSICLK, 16, 4, 0, NULL),
+                        0);
+
+static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p,
+                        OWL_MUX_HW(CMU_DECLK, 12, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
+                        0);
+
+static OWL_COMP_FACTOR(dmm_clk, "dmm_clk", dmm_clk_mux_p,
+                        OWL_MUX_HW(CMU_BUSCLK, 10, 2),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 19, 0),
+                        OWL_FACTOR_HW(CMU_BUSCLK, 12, 3, 0, dmm_factor_table),
+                        CLK_IGNORE_UNUSED);
+
+static OWL_COMP_FACTOR(edp_clk, "edp_clk", edp_clk_mux_p,
+                        OWL_MUX_HW(CMU_EDPCLK, 19, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
+                        OWL_FACTOR_HW(CMU_EDPCLK, 16, 3, 0, bisp_factor_table),
+                        0);
+
+static OWL_COMP_DIV_FIXED(eth_mac_clk, "eth_mac_clk", "assist_pll_clk",
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0),
+                        OWL_DIVIDER_HW(CMU_ASSISTPLL, 10, 1, 0, eth_mac_div_table),
+                        0);
+
+static OWL_COMP_FACTOR(gpu_core_clk, "gpu_core_clk", gpu_clk_mux_p,
+                        OWL_MUX_HW(CMU_GPU3DCLK, 4, 2),
+                        OWL_GATE_HW(CMU_GPU3DCLK, 15, 0),
+                        OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, bisp_factor_table),
+                        0);
+
+static OWL_COMP_FACTOR(gpu_mem_clk, "gpu_mem_clk", gpu_clk_mux_p,
+                        OWL_MUX_HW(CMU_GPU3DCLK, 20, 2),
+                        OWL_GATE_HW(CMU_GPU3DCLK, 14, 0),
+                        OWL_FACTOR_HW(CMU_GPU3DCLK, 16, 3, 0, bisp_factor_table),
+                        0);
+
+static OWL_COMP_FACTOR(gpu_sys_clk, "gpu_sys_clk", gpu_clk_mux_p,
+                        OWL_MUX_HW(CMU_GPU3DCLK, 28, 2),
+                        OWL_GATE_HW(CMU_GPU3DCLK, 13, 0),
+                        OWL_FACTOR_HW(CMU_GPU3DCLK, 24, 3, 0, bisp_factor_table),
+                        0);
+
+static OWL_COMP_FACTOR(hde_clk, "hde_clk", hde_clk_mux_p,
+                        OWL_MUX_HW(CMU_HDECLK, 4, 2),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 27, 0),
+                        OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, bisp_factor_table),
+                        0);
+
+static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p,
+                        OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
+                        OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
+                        0);
+
+static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "assist_pll_clk",
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
+                        1, 5, 0);
+
+static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "assist_pll_clk",
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0),
+                        1, 5, 0);
+
+static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "assist_pll_clk",
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0),
+                        1, 5, 0);
+
+static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "assist_pll_clk",
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
+                        1, 5, 0);
+
+static OWL_COMP_FIXED_FACTOR(i2c4_clk, "i2c4_clk", "assist_pll_clk",
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 17, 0),
+                        1, 5, 0);
+
+static OWL_COMP_FIXED_FACTOR(i2c5_clk, "i2c5_clk", "assist_pll_clk",
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 1, 0),
+                        1, 5, 0);
+
+static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
+                        OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
+                        OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
+                        0);
+
+static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p,
+                        OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0),
+                        OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
+                        0);
+
+static OWL_COMP_FACTOR(imx_clk, "imx_clk", imx_clk_mux_p,
+                        OWL_MUX_HW(CMU_IMXCLK, 4, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
+                        OWL_FACTOR_HW(CMU_IMXCLK, 0, 3, 0, bisp_factor_table),
+                        0);
+
+static OWL_COMP_DIV(lcd_clk, "lcd_clk", lcd_clk_mux_p,
+                        OWL_MUX_HW(CMU_LCDCLK, 12, 2),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
+                        OWL_DIVIDER_HW(CMU_LCDCLK, 0, 5, 0, NULL),
+                        0);
+
+static OWL_COMP_DIV(nand0_clk, "nand0_clk", nand_clk_mux_p,
+                        OWL_MUX_HW(CMU_NANDCCLK, 8, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
+                        OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 4, 0, nand_div_table),
+                        CLK_SET_RATE_PARENT);
+
+static OWL_COMP_DIV(nand1_clk, "nand1_clk", nand_clk_mux_p,
+                        OWL_MUX_HW(CMU_NANDCCLK, 24, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
+                        OWL_DIVIDER_HW(CMU_NANDCCLK, 16, 4, 0, nand_div_table),
+                        CLK_SET_RATE_PARENT);
+
+static OWL_COMP_DIV_FIXED(pwm0_clk, "pwm0_clk", "hosc",
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
+                        OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 6, 0, NULL),
+                        0);
+
+static OWL_COMP_DIV_FIXED(pwm1_clk, "pwm1_clk", "hosc",
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0),
+                        OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 6, 0, NULL),
+                        0);
+/*
+ * pwm2 may be for backlight, do not gate it
+ * even it is "unused", because it may be
+ * enabled at boot stage, and in kernel, driver
+ * has no effective method to know the real status,
+ * so, the best way is keeping it as what it was.
+ */
+static OWL_COMP_DIV_FIXED(pwm2_clk, "pwm2_clk", "hosc",
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0),
+                        OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 6, 0, NULL),
+                        CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV_FIXED(pwm3_clk, "pwm3_clk", "hosc",
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
+                        OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 6, 0, NULL),
+                        0);
+
+static OWL_COMP_DIV_FIXED(pwm4_clk, "pwm4_clk", "hosc",
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 4, 0),
+                        OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 6, 0, NULL),
+                        0);
+
+static OWL_COMP_DIV_FIXED(pwm5_clk, "pwm5_clk", "hosc",
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 5, 0),
+                        OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 6, 0, NULL),
+                        0);
+
+static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
+                        OWL_MUX_HW(CMU_SD0CLK, 9, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0),
+                        OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
+                        0);
+
+static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p,
+                        OWL_MUX_HW(CMU_SD1CLK, 9, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0),
+                        OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
+                        0);
+
+static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p,
+                        OWL_MUX_HW(CMU_SD2CLK, 9, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0),
+                        OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
+                        0);
+
+static OWL_COMP_FACTOR(sd3_clk, "sd3_clk", sd_clk_mux_p,
+                        OWL_MUX_HW(CMU_SD3CLK, 9, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 16, 0),
+                        OWL_FACTOR_HW(CMU_SD3CLK, 0, 9, 0, sd_factor_table),
+                        0);
+
+static OWL_COMP_DIV(sensor_clk, "sensor_clk", sensor_clk_mux_p,
+                        OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
+                        OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, NULL),
+                        0);
+
+static OWL_COMP_DIV_FIXED(speed_sensor_clk, "speed_sensor_clk",
+                        "hosc",
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 0, 0),
+                        OWL_DIVIDER_HW(CMU_TLSCLK, 0, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
+                        0);
+
+static OWL_COMP_DIV_FIXED(thermal_sensor_clk, "thermal_sensor_clk",
+                        "hosc",
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 2, 0),
+                        OWL_DIVIDER_HW(CMU_TLSCLK, 8, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
+                        0);
+
+static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
+                        OWL_MUX_HW(CMU_UART0CLK, 16, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
+                        OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+                        CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
+                        OWL_MUX_HW(CMU_UART1CLK, 16, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0),
+                        OWL_DIVIDER_HW(CMU_UART1CLK, 1, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+                        CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
+                        OWL_MUX_HW(CMU_UART2CLK, 16, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
+                        OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+                        CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
+                        OWL_MUX_HW(CMU_UART3CLK, 16, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
+                        OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+                        CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
+                        OWL_MUX_HW(CMU_UART4CLK, 16, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
+                        OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+                        CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
+                        OWL_MUX_HW(CMU_UART5CLK, 16, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
+                        OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+                        CLK_IGNORE_UNUSED);
+
+static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
+                        OWL_MUX_HW(CMU_UART6CLK, 16, 1),
+                        OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
+                        OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+                        CLK_IGNORE_UNUSED);
+
+static OWL_COMP_FACTOR(vce_clk, "vce_clk", vce_clk_mux_p,
+                        OWL_MUX_HW(CMU_VCECLK, 4, 2),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
+                        OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table),
+                        0);
+
+static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
+                        OWL_MUX_HW(CMU_VDECLK, 4, 2),
+                        OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
+                        OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table),
+                        0);
+
+static struct owl_clk_common *s900_clks[] = {
+        &core_pll_clk.common,
+        &dev_pll_clk.common,
+        &ddr_pll_clk.common,
+        &nand_pll_clk.common,
+        &display_pll_clk.common,
+        &assist_pll_clk.common,
+        &audio_pll_clk.common,
+        &edp_pll_clk.common,
+        &cpu_clk.common,
+        &dev_clk.common,
+        &noc_clk_mux.common,
+        &noc_clk_div.common,
+        &ahb_clk.common,
+        &apb_clk.common,
+        &usb3_mac_clk.common,
+        &rmii_ref_clk.common,
+        &noc_clk.common,
+        &de_clk1.common,
+        &de_clk2.common,
+        &de_clk3.common,
+        &gpio_clk.common,
+        &gpu_clk.common,
+        &dmac_clk.common,
+        &timer_clk.common,
+        &dsi_clk.common,
+        &ddr0_clk.common,
+        &ddr1_clk.common,
+        &usb3_480mpll0_clk.common,
+        &usb3_480mphy0_clk.common,
+        &usb3_5gphy_clk.common,
+        &usb3_cce_clk.common,
+        &edp24M_clk.common,
+        &edp_link_clk.common,
+        &usbh0_pllen_clk.common,
+        &usbh0_phy_clk.common,
+        &usbh0_cce_clk.common,
+        &usbh1_pllen_clk.common,
+        &usbh1_phy_clk.common,
+        &usbh1_cce_clk.common,
+        &i2c0_clk.common,
+        &i2c1_clk.common,
+        &i2c2_clk.common,
+        &i2c3_clk.common,
+        &i2c4_clk.common,
+        &i2c5_clk.common,
+        &spi0_clk.common,
+        &spi1_clk.common,
+        &spi2_clk.common,
+        &spi3_clk.common,
+        &bisp_clk.common,
+        &csi0_clk.common,
+        &csi1_clk.common,
+        &de_clk.common,
+        &dmm_clk.common,
+        &edp_clk.common,
+        &eth_mac_clk.common,
+        &gpu_core_clk.common,
+        &gpu_mem_clk.common,
+        &gpu_sys_clk.common,
+        &hde_clk.common,
+        &hdmia_clk.common,
+        &i2srx_clk.common,
+        &i2stx_clk.common,
+        &imx_clk.common,
+        &lcd_clk.common,
+        &nand0_clk.common,
+        &nand1_clk.common,
+        &pwm0_clk.common,
+        &pwm1_clk.common,
+        &pwm2_clk.common,
+        &pwm3_clk.common,
+        &pwm4_clk.common,
+        &pwm5_clk.common,
+        &sd0_clk.common,
+        &sd1_clk.common,
+        &sd2_clk.common,
+        &sd3_clk.common,
+        &sensor_clk.common,
+        &speed_sensor_clk.common,
+        &thermal_sensor_clk.common,
+        &uart0_clk.common,
+        &uart1_clk.common,
+        &uart2_clk.common,
+        &uart3_clk.common,
+        &uart4_clk.common,
+        &uart5_clk.common,
+        &uart6_clk.common,
+        &vce_clk.common,
+        &vde_clk.common,
+};
+
+static struct clk_hw_onecell_data s900_hw_clks = {
+        .hws    = {
+                [CLK_CORE_PLL]          = &core_pll_clk.common.hw,
+                [CLK_DEV_PLL]           = &dev_pll_clk.common.hw,
+                [CLK_DDR_PLL]           = &ddr_pll_clk.common.hw,
+                [CLK_NAND_PLL]          = &nand_pll_clk.common.hw,
+                [CLK_DISPLAY_PLL]       = &display_pll_clk.common.hw,
+                [CLK_ASSIST_PLL]        = &assist_pll_clk.common.hw,
+                [CLK_AUDIO_PLL]         = &audio_pll_clk.common.hw,
+                [CLK_EDP_PLL]           = &edp_pll_clk.common.hw,
+                [CLK_CPU]               = &cpu_clk.common.hw,
+                [CLK_DEV]               = &dev_clk.common.hw,
+                [CLK_NOC_MUX]           = &noc_clk_mux.common.hw,
+                [CLK_NOC_DIV]           = &noc_clk_div.common.hw,
+                [CLK_AHB]               = &ahb_clk.common.hw,
+                [CLK_APB]               = &apb_clk.common.hw,
+                [CLK_USB3_MAC]          = &usb3_mac_clk.common.hw,
+                [CLK_RMII_REF]          = &rmii_ref_clk.common.hw,
+                [CLK_NOC]               = &noc_clk.common.hw,
+                [CLK_DE1]               = &de_clk1.common.hw,
+                [CLK_DE2]               = &de_clk2.common.hw,
+                [CLK_DE3]               = &de_clk3.common.hw,
+                [CLK_GPIO]              = &gpio_clk.common.hw,
+                [CLK_GPU]               = &gpu_clk.common.hw,
+                [CLK_DMAC]              = &dmac_clk.common.hw,
+                [CLK_TIMER]             = &timer_clk.common.hw,
+                [CLK_DSI]               = &dsi_clk.common.hw,
+                [CLK_DDR0]              = &ddr0_clk.common.hw,
+                [CLK_DDR1]              = &ddr1_clk.common.hw,
+                [CLK_USB3_480MPLL0]     = &usb3_480mpll0_clk.common.hw,
+                [CLK_USB3_480MPHY0]     = &usb3_480mphy0_clk.common.hw,
+                [CLK_USB3_5GPHY]        = &usb3_5gphy_clk.common.hw,
+                [CLK_USB3_CCE]          = &usb3_cce_clk.common.hw,
+                [CLK_24M_EDP]           = &edp24M_clk.common.hw,
+                [CLK_EDP_LINK]          = &edp_link_clk.common.hw,
+                [CLK_USB2H0_PLLEN]      = &usbh0_pllen_clk.common.hw,
+                [CLK_USB2H0_PHY]        = &usbh0_phy_clk.common.hw,
+                [CLK_USB2H0_CCE]        = &usbh0_cce_clk.common.hw,
+                [CLK_USB2H1_PLLEN]      = &usbh1_pllen_clk.common.hw,
+                [CLK_USB2H1_PHY]        = &usbh1_phy_clk.common.hw,
+                [CLK_USB2H1_CCE]        = &usbh1_cce_clk.common.hw,
+                [CLK_I2C0]              = &i2c0_clk.common.hw,
+                [CLK_I2C1]              = &i2c1_clk.common.hw,
+                [CLK_I2C2]              = &i2c2_clk.common.hw,
+                [CLK_I2C3]              = &i2c3_clk.common.hw,
+                [CLK_I2C4]              = &i2c4_clk.common.hw,
+                [CLK_I2C5]              = &i2c5_clk.common.hw,
+                [CLK_SPI0]              = &spi0_clk.common.hw,
+                [CLK_SPI1]              = &spi1_clk.common.hw,
+                [CLK_SPI2]              = &spi2_clk.common.hw,
+                [CLK_SPI3]              = &spi3_clk.common.hw,
+                [CLK_BISP]              = &bisp_clk.common.hw,
+                [CLK_CSI0]              = &csi0_clk.common.hw,
+                [CLK_CSI1]              = &csi1_clk.common.hw,
+                [CLK_DE0]               = &de_clk.common.hw,
+                [CLK_DMM]               = &dmm_clk.common.hw,
+                [CLK_EDP]               = &edp_clk.common.hw,
+                [CLK_ETH_MAC]           = &eth_mac_clk.common.hw,
+                [CLK_GPU_CORE]          = &gpu_core_clk.common.hw,
+                [CLK_GPU_MEM]           = &gpu_mem_clk.common.hw,
+                [CLK_GPU_SYS]           = &gpu_sys_clk.common.hw,
+                [CLK_HDE]               = &hde_clk.common.hw,
+                [CLK_HDMI_AUDIO]        = &hdmia_clk.common.hw,
+                [CLK_I2SRX]             = &i2srx_clk.common.hw,
+                [CLK_I2STX]             = &i2stx_clk.common.hw,
+                [CLK_IMX]               = &imx_clk.common.hw,
+                [CLK_LCD]               = &lcd_clk.common.hw,
+                [CLK_NAND0]             = &nand0_clk.common.hw,
+                [CLK_NAND1]             = &nand1_clk.common.hw,
+                [CLK_PWM0]              = &pwm0_clk.common.hw,
+                [CLK_PWM1]              = &pwm1_clk.common.hw,
+                [CLK_PWM2]              = &pwm2_clk.common.hw,
+                [CLK_PWM3]              = &pwm3_clk.common.hw,
+                [CLK_PWM4]              = &pwm4_clk.common.hw,
+                [CLK_PWM5]              = &pwm5_clk.common.hw,
+                [CLK_SD0]               = &sd0_clk.common.hw,
+                [CLK_SD1]               = &sd1_clk.common.hw,
+                [CLK_SD2]               = &sd2_clk.common.hw,
+                [CLK_SD3]               = &sd3_clk.common.hw,
+                [CLK_SENSOR]            = &sensor_clk.common.hw,
+                [CLK_SPEED_SENSOR]      = &speed_sensor_clk.common.hw,
+                [CLK_THERMAL_SENSOR]    = &thermal_sensor_clk.common.hw,
+                [CLK_UART0]             = &uart0_clk.common.hw,
+                [CLK_UART1]             = &uart1_clk.common.hw,
+                [CLK_UART2]             = &uart2_clk.common.hw,
+                [CLK_UART3]             = &uart3_clk.common.hw,
+                [CLK_UART4]             = &uart4_clk.common.hw,
+                [CLK_UART5]             = &uart5_clk.common.hw,
+                [CLK_UART6]             = &uart6_clk.common.hw,
+                [CLK_VCE]               = &vce_clk.common.hw,
+                [CLK_VDE]               = &vde_clk.common.hw,
+        },
+        .num    = CLK_NR_CLKS,
+};
+
+static const struct owl_clk_desc s900_clk_desc = {
+        .clks       = s900_clks,
+        .num_clks   = ARRAY_SIZE(s900_clks),
+
+        .hw_clks    = &s900_hw_clks,
+};
+
+static int s900_clk_probe(struct platform_device *pdev)
+{
+        const struct owl_clk_desc *desc;
+
+        desc = &s900_clk_desc;
+        owl_clk_regmap_init(pdev, desc);
+
+        return owl_clk_probe(&pdev->dev, desc->hw_clks);
+}
+
+static const struct of_device_id s900_clk_of_match[] = {
+        { .compatible = "actions,s900-cmu", },
+        { /* sentinel */ }
+};
+
+static struct platform_driver s900_clk_driver = {
+        .probe = s900_clk_probe,
+        .driver = {
+                .name = "s900-cmu",
+                .of_match_table = s900_clk_of_match,
+        },
+};
+
+static int __init s900_clk_init(void)
+{
+        return platform_driver_register(&s900_clk_driver);
+}
+core_initcall(s900_clk_init);
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
index 7d3223fc7161..72b6091eb7b9 100644
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -132,19 +132,8 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
                                          unsigned long parent_rate)
 {
         struct clk_pll *pll = to_clk_pll(hw);
-        unsigned int pllr;
-        u16 mul;
-        u8 div;
-
-        regmap_read(pll->regmap, PLL_REG(pll->id), &pllr);
-
-        div = PLL_DIV(pllr);
-        mul = PLL_MUL(pllr, pll->layout);
-
-        if (!div || !mul)
-                return 0;
 
-        return (parent_rate / div) * (mul + 1);
+        return (parent_rate / pll->div) * (pll->mul + 1);
 }
 
 static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 6d4e69edfb36..9e0b2f2b48e7 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -394,25 +394,21 @@ out:
         return count * 1000;
 }
 
-static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
+static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
                                   struct debugfs_reg32 *regs, size_t nregs,
                                   struct dentry *dentry)
 {
-        struct dentry *regdump;
         struct debugfs_regset32 *regset;
 
         regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
         if (!regset)
-                return -ENOMEM;
+                return;
 
         regset->regs = regs;
         regset->nregs = nregs;
         regset->base = cprman->regs + base;
 
-        regdump = debugfs_create_regset32("regdump", S_IRUGO, dentry,
-                                          regset);
-
-        return regdump ? 0 : -ENOMEM;
+        debugfs_create_regset32("regdump", S_IRUGO, dentry, regset);
 }
 
 struct bcm2835_pll_data {
@@ -730,7 +726,7 @@ static int bcm2835_pll_set_rate(struct clk_hw *hw,
         return 0;
 }
 
-static int bcm2835_pll_debug_init(struct clk_hw *hw,
+static void bcm2835_pll_debug_init(struct clk_hw *hw,
                                   struct dentry *dentry)
 {
         struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
@@ -740,7 +736,7 @@ static int bcm2835_pll_debug_init(struct clk_hw *hw,
 
         regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
         if (!regs)
-                return -ENOMEM;
+                return;
 
         regs[0].name = "cm_ctrl";
         regs[0].offset = data->cm_ctrl_reg;
@@ -757,7 +753,7 @@ static int bcm2835_pll_debug_init(struct clk_hw *hw,
         regs[6].name = "ana3";
         regs[6].offset = data->ana_reg_base + 3 * 4;
 
-        return bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
+        bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
 }
 
 static const struct clk_ops bcm2835_pll_clk_ops = {
@@ -861,8 +857,8 @@ static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
         return 0;
 }
 
-static int bcm2835_pll_divider_debug_init(struct clk_hw *hw,
-                                          struct dentry *dentry)
+static void bcm2835_pll_divider_debug_init(struct clk_hw *hw,
+                                           struct dentry *dentry)
 {
         struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
         struct bcm2835_cprman *cprman = divider->cprman;
@@ -871,14 +867,14 @@ static int bcm2835_pll_divider_debug_init(struct clk_hw *hw,
 
         regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
         if (!regs)
-                return -ENOMEM;
+                return;
 
         regs[0].name = "cm";
         regs[0].offset = data->cm_reg;
         regs[1].name = "a2w";
         regs[1].offset = data->a2w_reg;
 
-        return bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
+        bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
 }
 
 static const struct clk_ops bcm2835_pll_divider_clk_ops = {
@@ -1254,15 +1250,14 @@ static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
         },
 };
 
-static int bcm2835_clock_debug_init(struct clk_hw *hw,
+static void bcm2835_clock_debug_init(struct clk_hw *hw,
                                     struct dentry *dentry)
 {
         struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
         struct bcm2835_cprman *cprman = clock->cprman;
         const struct bcm2835_clock_data *data = clock->data;
 
-        return bcm2835_debugfs_regset(
-                cprman, data->ctl_reg,
+        bcm2835_debugfs_regset(cprman, data->ctl_reg,
                 bcm2835_debugfs_clock_reg32,
                 ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
                 dentry);
@@ -1395,7 +1390,7 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
         struct bcm2835_clock *clock;
         struct clk_init_data init;
         const char *parents[1 << CM_SRC_BITS];
-        size_t i, j;
+        size_t i;
         int ret;
 
         /*
@@ -1405,12 +1400,11 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
         for (i = 0; i < data->num_mux_parents; i++) {
                 parents[i] = data->parents[i];
 
-                for (j = 0; j < ARRAY_SIZE(cprman_parent_names); j++) {
-                        if (strcmp(parents[i], cprman_parent_names[j]) == 0) {
-                                parents[i] = cprman->real_parent_names[j];
-                                break;
-                        }
-                }
+                ret = match_string(cprman_parent_names,
+                                   ARRAY_SIZE(cprman_parent_names),
+                                   parents[i]);
+                if (ret >= 0)
+                        parents[i] = cprman->real_parent_names[ret];
         }
 
         memset(&init, 0, sizeof(init));
diff --git a/drivers/clk/bcm/clk-sr.c b/drivers/clk/bcm/clk-sr.c
index adc74f4584cf..7b9efc0212a8 100644
--- a/drivers/clk/bcm/clk-sr.c
+++ b/drivers/clk/bcm/clk-sr.c
@@ -56,8 +56,8 @@ static const struct iproc_pll_ctrl sr_genpll0 = {
 };
 
 static const struct iproc_clk_ctrl sr_genpll0_clk[] = {
-        [BCM_SR_GENPLL0_SATA_CLK] = {
-                .channel = BCM_SR_GENPLL0_SATA_CLK,
+        [BCM_SR_GENPLL0_125M_CLK] = {
+                .channel = BCM_SR_GENPLL0_125M_CLK,
                 .flags = IPROC_CLK_AON,
                 .enable = ENABLE_VAL(0x4, 6, 0, 12),
                 .mdiv = REG_VAL(0x18, 0, 9),
@@ -102,6 +102,65 @@ static int sr_genpll0_clk_init(struct platform_device *pdev)
         return 0;
 }
 
+static const struct iproc_pll_ctrl sr_genpll2 = {
+        .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
+                IPROC_CLK_PLL_NEEDS_SW_CFG,
+        .aon = AON_VAL(0x0, 1, 13, 12),
+        .reset = RESET_VAL(0x0, 12, 11),
+        .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
+        .sw_ctrl = SW_CTRL_VAL(0x10, 31),
+        .ndiv_int = REG_VAL(0x10, 20, 10),
+        .ndiv_frac = REG_VAL(0x10, 0, 20),
+        .pdiv = REG_VAL(0x14, 0, 4),
+        .status = REG_VAL(0x30, 12, 1),
+};
+
+static const struct iproc_clk_ctrl sr_genpll2_clk[] = {
+        [BCM_SR_GENPLL2_NIC_CLK] = {
+                .channel = BCM_SR_GENPLL2_NIC_CLK,
+                .flags = IPROC_CLK_AON,
+                .enable = ENABLE_VAL(0x4, 6, 0, 12),
+                .mdiv = REG_VAL(0x18, 0, 9),
+        },
+        [BCM_SR_GENPLL2_TS_500_CLK] = {
+                .channel = BCM_SR_GENPLL2_TS_500_CLK,
+                .flags = IPROC_CLK_AON,
+                .enable = ENABLE_VAL(0x4, 7, 1, 13),
+                .mdiv = REG_VAL(0x18, 10, 9),
+        },
+        [BCM_SR_GENPLL2_125_NITRO_CLK] = {
+                .channel = BCM_SR_GENPLL2_125_NITRO_CLK,
+                .flags = IPROC_CLK_AON,
+                .enable = ENABLE_VAL(0x4, 8, 2, 14),
+                .mdiv = REG_VAL(0x18, 20, 9),
+        },
+        [BCM_SR_GENPLL2_CHIMP_CLK] = {
+                .channel = BCM_SR_GENPLL2_CHIMP_CLK,
+                .flags = IPROC_CLK_AON,
+                .enable = ENABLE_VAL(0x4, 9, 3, 15),
+                .mdiv = REG_VAL(0x1c, 0, 9),
+        },
+        [BCM_SR_GENPLL2_NIC_FLASH_CLK] = {
+                .channel = BCM_SR_GENPLL2_NIC_FLASH_CLK,
+                .flags = IPROC_CLK_AON,
+                .enable = ENABLE_VAL(0x4, 10, 4, 16),
+                .mdiv = REG_VAL(0x1c, 10, 9),
+        },
+        [BCM_SR_GENPLL2_FS4_CLK] = {
+                .channel = BCM_SR_GENPLL2_FS4_CLK,
+                .enable = ENABLE_VAL(0x4, 11, 5, 17),
+                .mdiv = REG_VAL(0x1c, 20, 9),
+        },
+};
+
+static int sr_genpll2_clk_init(struct platform_device *pdev)
+{
+        iproc_pll_clk_setup(pdev->dev.of_node,
+                            &sr_genpll2, NULL, 0, sr_genpll2_clk,
+                            ARRAY_SIZE(sr_genpll2_clk));
+        return 0;
+}
+
 static const struct iproc_pll_ctrl sr_genpll3 = {
         .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
                 IPROC_CLK_PLL_NEEDS_SW_CFG,
@@ -157,6 +216,30 @@ static const struct iproc_clk_ctrl sr_genpll4_clk[] = {
                 .enable = ENABLE_VAL(0x4, 6, 0, 12),
                 .mdiv = REG_VAL(0x18, 0, 9),
         },
+        [BCM_SR_GENPLL4_TPIU_PLL_CLK] = {
+                .channel = BCM_SR_GENPLL4_TPIU_PLL_CLK,
+                .flags = IPROC_CLK_AON,
+                .enable = ENABLE_VAL(0x4, 7, 1, 13),
+                .mdiv = REG_VAL(0x18, 10, 9),
+        },
+        [BCM_SR_GENPLL4_NOC_CLK] = {
+                .channel = BCM_SR_GENPLL4_NOC_CLK,
+                .flags = IPROC_CLK_AON,
+                .enable = ENABLE_VAL(0x4, 8, 2, 14),
+                .mdiv = REG_VAL(0x18, 20, 9),
+        },
+        [BCM_SR_GENPLL4_CHCLK_FS4_CLK] = {
+                .channel = BCM_SR_GENPLL4_CHCLK_FS4_CLK,
+                .flags = IPROC_CLK_AON,
+                .enable = ENABLE_VAL(0x4, 9, 3, 15),
+                .mdiv = REG_VAL(0x1c, 0, 9),
+        },
+        [BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK] = {
+                .channel = BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK,
+                .flags = IPROC_CLK_AON,
+                .enable = ENABLE_VAL(0x4, 10, 4, 16),
+                .mdiv = REG_VAL(0x1c, 10, 9),
+        },
 };
 
 static int sr_genpll4_clk_init(struct platform_device *pdev)
@@ -181,18 +264,21 @@ static const struct iproc_pll_ctrl sr_genpll5 = {
 };
 
 static const struct iproc_clk_ctrl sr_genpll5_clk[] = {
-        [BCM_SR_GENPLL5_FS_CLK] = {
-                .channel = BCM_SR_GENPLL5_FS_CLK,
-                .flags = IPROC_CLK_AON,
+        [BCM_SR_GENPLL5_FS4_HF_CLK] = {
+                .channel = BCM_SR_GENPLL5_FS4_HF_CLK,
                 .enable = ENABLE_VAL(0x4, 6, 0, 12),
                 .mdiv = REG_VAL(0x18, 0, 9),
         },
-        [BCM_SR_GENPLL5_SPU_CLK] = {
-                .channel = BCM_SR_GENPLL5_SPU_CLK,
-                .flags = IPROC_CLK_AON,
-                .enable = ENABLE_VAL(0x4, 6, 0, 12),
+        [BCM_SR_GENPLL5_CRYPTO_AE_CLK] = {
+                .channel = BCM_SR_GENPLL5_CRYPTO_AE_CLK,
+                .enable = ENABLE_VAL(0x4, 7, 1, 12),
                 .mdiv = REG_VAL(0x18, 10, 9),
         },
+        [BCM_SR_GENPLL5_RAID_AE_CLK] = {
+                .channel = BCM_SR_GENPLL5_RAID_AE_CLK,
+                .enable = ENABLE_VAL(0x4, 8, 2, 14),
+                .mdiv = REG_VAL(0x18, 20, 9),
+        },
 };
 
 static int sr_genpll5_clk_init(struct platform_device *pdev)
@@ -214,24 +300,30 @@ static const struct iproc_pll_ctrl sr_lcpll0 = {
 };
 
 static const struct iproc_clk_ctrl sr_lcpll0_clk[] = {
-        [BCM_SR_LCPLL0_SATA_REF_CLK] = {
-                .channel = BCM_SR_LCPLL0_SATA_REF_CLK,
+        [BCM_SR_LCPLL0_SATA_REFP_CLK] = {
+                .channel = BCM_SR_LCPLL0_SATA_REFP_CLK,
                 .flags = IPROC_CLK_AON,
                 .enable = ENABLE_VAL(0x0, 7, 1, 13),
                 .mdiv = REG_VAL(0x14, 0, 9),
         },
-        [BCM_SR_LCPLL0_USB_REF_CLK] = {
-                .channel = BCM_SR_LCPLL0_USB_REF_CLK,
+        [BCM_SR_LCPLL0_SATA_REFN_CLK] = {
+                .channel = BCM_SR_LCPLL0_SATA_REFN_CLK,
                 .flags = IPROC_CLK_AON,
                 .enable = ENABLE_VAL(0x0, 8, 2, 14),
                 .mdiv = REG_VAL(0x14, 10, 9),
         },
-        [BCM_SR_LCPLL0_SATA_REFPN_CLK] = {
-                .channel = BCM_SR_LCPLL0_SATA_REFPN_CLK,
+        [BCM_SR_LCPLL0_SATA_350_CLK] = {
+                .channel = BCM_SR_LCPLL0_SATA_350_CLK,
                 .flags = IPROC_CLK_AON,
                 .enable = ENABLE_VAL(0x0, 9, 3, 15),
                 .mdiv = REG_VAL(0x14, 20, 9),
         },
+        [BCM_SR_LCPLL0_SATA_500_CLK] = {
+                .channel = BCM_SR_LCPLL0_SATA_500_CLK,
+                .flags = IPROC_CLK_AON,
+                .enable = ENABLE_VAL(0x0, 10, 4, 16),
+                .mdiv = REG_VAL(0x18, 0, 9),
+        },
 };
 
 static int sr_lcpll0_clk_init(struct platform_device *pdev)
@@ -259,6 +351,18 @@ static const struct iproc_clk_ctrl sr_lcpll1_clk[] = {
                 .enable = ENABLE_VAL(0x0, 7, 1, 13),
                 .mdiv = REG_VAL(0x14, 0, 9),
         },
+        [BCM_SR_LCPLL1_USB_REF_CLK] = {
+                .channel = BCM_SR_LCPLL1_USB_REF_CLK,
+                .flags = IPROC_CLK_AON,
+                .enable = ENABLE_VAL(0x0, 8, 2, 14),
+                .mdiv = REG_VAL(0x14, 10, 9),
+        },
+        [BCM_SR_LCPLL1_CRMU_TS_CLK] = {
+                .channel = BCM_SR_LCPLL1_CRMU_TS_CLK,
+                .flags = IPROC_CLK_AON,
+                .enable = ENABLE_VAL(0x0, 9, 3, 15),
+                .mdiv = REG_VAL(0x14, 20, 9),
+        },
 };
 
 static int sr_lcpll1_clk_init(struct platform_device *pdev)
@@ -298,6 +402,7 @@ static int sr_lcpll_pcie_clk_init(struct platform_device *pdev)
 
 static const struct of_device_id sr_clk_dt_ids[] = {
         { .compatible = "brcm,sr-genpll0", .data = sr_genpll0_clk_init },
+        { .compatible = "brcm,sr-genpll2", .data = sr_genpll2_clk_init },
         { .compatible = "brcm,sr-genpll4", .data = sr_genpll4_clk_init },
         { .compatible = "brcm,sr-genpll5", .data = sr_genpll5_clk_init },
         { .compatible = "brcm,sr-lcpll0", .data = sr_lcpll0_clk_init },
diff --git a/drivers/clk/berlin/berlin2-avpll.c b/drivers/clk/berlin/berlin2-avpll.c
index cfcae468e989..aa89b4c9464e 100644
--- a/drivers/clk/berlin/berlin2-avpll.c
+++ b/drivers/clk/berlin/berlin2-avpll.c
@@ -1,20 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2014 Marvell Technology Group Ltd.
  *
  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  * Alexandre Belloni <alexandre.belloni@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #include <linux/clk-provider.h>
 #include <linux/io.h>
diff --git a/drivers/clk/berlin/berlin2-avpll.h b/drivers/clk/berlin/berlin2-avpll.h
index 17e311153b42..f3af34dc2bee 100644
--- a/drivers/clk/berlin/berlin2-avpll.h
+++ b/drivers/clk/berlin/berlin2-avpll.h
@@ -1,20 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (c) 2014 Marvell Technology Group Ltd.
  *
  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  * Alexandre Belloni <alexandre.belloni@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #ifndef __BERLIN2_AVPLL_H
 #define __BERLIN2_AVPLL_H
diff --git a/drivers/clk/berlin/berlin2-div.c b/drivers/clk/berlin/berlin2-div.c
index 41ab2d392c57..4d0be66aa6a8 100644
--- a/drivers/clk/berlin/berlin2-div.c
+++ b/drivers/clk/berlin/berlin2-div.c
@@ -1,20 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2014 Marvell Technology Group Ltd.
  *
  * Alexandre Belloni <alexandre.belloni@free-electrons.com>
  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #include <linux/bitops.h>
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/berlin/berlin2-div.h b/drivers/clk/berlin/berlin2-div.h
index e835ddf8374a..d4da64325190 100644
--- a/drivers/clk/berlin/berlin2-div.h
+++ b/drivers/clk/berlin/berlin2-div.h
@@ -1,20 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (c) 2014 Marvell Technology Group Ltd.
  *
  * Alexandre Belloni <alexandre.belloni@free-electrons.com>
  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #ifndef __BERLIN2_DIV_H
 #define __BERLIN2_DIV_H
diff --git a/drivers/clk/berlin/berlin2-pll.c b/drivers/clk/berlin/berlin2-pll.c
index 4ffbe80f6323..9661820717a5 100644
--- a/drivers/clk/berlin/berlin2-pll.c
+++ b/drivers/clk/berlin/berlin2-pll.c
@@ -1,20 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2014 Marvell Technology Group Ltd.
  *
  * Alexandre Belloni <alexandre.belloni@free-electrons.com>
  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #include <linux/clk-provider.h>
 #include <linux/io.h>
diff --git a/drivers/clk/berlin/berlin2-pll.h b/drivers/clk/berlin/berlin2-pll.h
index 583e024b9bed..3757fb25c4e8 100644
--- a/drivers/clk/berlin/berlin2-pll.h
+++ b/drivers/clk/berlin/berlin2-pll.h
@@ -1,20 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (c) 2014 Marvell Technology Group Ltd.
  *
  * Alexandre Belloni <alexandre.belloni@free-electrons.com>
  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #ifndef __BERLIN2_PLL_H
 #define __BERLIN2_PLL_H
diff --git a/drivers/clk/berlin/bg2.c b/drivers/clk/berlin/bg2.c
index 45fb888bf0a0..0b4b44a2579e 100644
--- a/drivers/clk/berlin/bg2.c
+++ b/drivers/clk/berlin/bg2.c
@@ -1,20 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2014 Marvell Technology Group Ltd.
  *
  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  * Alexandre Belloni <alexandre.belloni@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c
index db7364e15c8b..9b9db743df25 100644
--- a/drivers/clk/berlin/bg2q.c
+++ b/drivers/clk/berlin/bg2q.c
@@ -1,20 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2014 Marvell Technology Group Ltd.
  *
  * Alexandre Belloni <alexandre.belloni@free-electrons.com>
  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/clk/berlin/common.h b/drivers/clk/berlin/common.h
index bc68a14c4550..1afb3c29b796 100644
--- a/drivers/clk/berlin/common.h
+++ b/drivers/clk/berlin/common.h
@@ -1,20 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (c) 2014 Marvell Technology Group Ltd.
  *
  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  * Alexandre Belloni <alexandre.belloni@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #ifndef __BERLIN2_COMMON_H
 #define __BERLIN2_COMMON_H
diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
index 7abe4232d282..38b366b00c57 100644
--- a/drivers/clk/clk-aspeed.c
+++ b/drivers/clk/clk-aspeed.c
@@ -14,7 +14,9 @@
 
 #include <dt-bindings/clock/aspeed-clock.h>
 
-#define ASPEED_NUM_CLKS         35
+#define ASPEED_NUM_CLKS         36
+
+#define ASPEED_RESET2_OFFSET    32
 
 #define ASPEED_RESET_CTRL       0x04
 #define ASPEED_CLK_SELECTION    0x08
@@ -30,6 +32,7 @@
 #define  CLKIN_25MHZ_EN         BIT(23)
 #define  AST2400_CLK_SOURCE_SEL BIT(18)
 #define ASPEED_CLK_SELECTION_2  0xd8
+#define ASPEED_RESET_CTRL2      0xd4
 
 /* Globally visible clocks */
 static DEFINE_SPINLOCK(aspeed_clk_lock);
@@ -88,7 +91,7 @@ static const struct aspeed_gate_data aspeed_gates[] = {
         [ASPEED_CLK_GATE_GCLK] =        {  1,  7, "gclk-gate",          NULL,   0 }, /* 2D engine */
         [ASPEED_CLK_GATE_MCLK] =        {  2, -1, "mclk-gate",          "mpll", CLK_IS_CRITICAL }, /* SDRAM */
         [ASPEED_CLK_GATE_VCLK] =        {  3,  6, "vclk-gate",          NULL,   0 }, /* Video Capture */
-        [ASPEED_CLK_GATE_BCLK] =        {  4, 10, "bclk-gate",          "bclk", 0 }, /* PCIe/PCI */
+        [ASPEED_CLK_GATE_BCLK] =        {  4,  8, "bclk-gate",          "bclk", 0 }, /* PCIe/PCI */
         [ASPEED_CLK_GATE_DCLK] =        {  5, -1, "dclk-gate",          NULL,   0 }, /* DAC */
         [ASPEED_CLK_GATE_REFCLK] =      {  6, -1, "refclk-gate",        "clkin", CLK_IS_CRITICAL },
         [ASPEED_CLK_GATE_USBPORT2CLK] = {  7,  3, "usb-port2-gate",     NULL,   0 }, /* USB2.0 Host port 2 */
@@ -291,47 +294,72 @@ struct aspeed_reset {
 #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
 
 static const u8 aspeed_resets[] = {
+        /* SCU04 resets */
         [ASPEED_RESET_XDMA]     = 25,
         [ASPEED_RESET_MCTP]     = 24,
         [ASPEED_RESET_ADC]      = 23,
         [ASPEED_RESET_JTAG_MASTER] = 22,
         [ASPEED_RESET_MIC]      = 18,
         [ASPEED_RESET_PWM]      =  9,
-        [ASPEED_RESET_PCIVGA]   =  8,
+        [ASPEED_RESET_PECI]     = 10,
         [ASPEED_RESET_I2C]      =  2,
         [ASPEED_RESET_AHB]      =  1,
+
+        /*
+         * SCUD4 resets start at an offset to separate them from
+         * the SCU04 resets.
+         */
+        [ASPEED_RESET_CRT1]     = ASPEED_RESET2_OFFSET + 5,
 };
 
 static int aspeed_reset_deassert(struct reset_controller_dev *rcdev,
                                  unsigned long id)
 {
         struct aspeed_reset *ar = to_aspeed_reset(rcdev);
-        u32 rst = BIT(aspeed_resets[id]);
+        u32 reg = ASPEED_RESET_CTRL;
+        u32 bit = aspeed_resets[id];
 
-        return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0);
+        if (bit >= ASPEED_RESET2_OFFSET) {
+                bit -= ASPEED_RESET2_OFFSET;
+                reg = ASPEED_RESET_CTRL2;
+        }
+
+        return regmap_update_bits(ar->map, reg, BIT(bit), 0);
 }
 
 static int aspeed_reset_assert(struct reset_controller_dev *rcdev,
                                unsigned long id)
 {
         struct aspeed_reset *ar = to_aspeed_reset(rcdev);
-        u32 rst = BIT(aspeed_resets[id]);
+        u32 reg = ASPEED_RESET_CTRL;
+        u32 bit = aspeed_resets[id];
+
+        if (bit >= ASPEED_RESET2_OFFSET) {
+                bit -= ASPEED_RESET2_OFFSET;
+                reg = ASPEED_RESET_CTRL2;
+        }
 
-        return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst);
+        return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit));
 }
 
 static int aspeed_reset_status(struct reset_controller_dev *rcdev,
                                unsigned long id)
 {
         struct aspeed_reset *ar = to_aspeed_reset(rcdev);
-        u32 val, rst = BIT(aspeed_resets[id]);
-        int ret;
+        u32 reg = ASPEED_RESET_CTRL;
+        u32 bit = aspeed_resets[id];
+        int ret, val;
+
+        if (bit >= ASPEED_RESET2_OFFSET) {
+                bit -= ASPEED_RESET2_OFFSET;
+                reg = ASPEED_RESET_CTRL2;
+        }
 
-        ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val);
+        ret = regmap_read(ar->map, reg, &val);
         if (ret)
                 return ret;
 
-        return !!(val & rst);
+        return !!(val & BIT(bit));
 }
 
 static const struct reset_control_ops aspeed_reset_ops = {
@@ -474,6 +502,13 @@ static int aspeed_clk_probe(struct platform_device *pdev)
                 return PTR_ERR(hw);
         aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;
 
+        /* Fixed 24MHz clock */
+        hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin",
+                                        0, 24000000);
+        if (IS_ERR(hw))
+                return PTR_ERR(hw);
+        aspeed_clk_data->hws[ASPEED_CLK_24M] = hw;
+
         /*
          * TODO: There are a number of clocks that not included in this driver
          * as more information is required:
diff --git a/drivers/clk/clk-bulk.c b/drivers/clk/clk-bulk.c
index 4c10456f8a32..6904ed6da504 100644
--- a/drivers/clk/clk-bulk.c
+++ b/drivers/clk/clk-bulk.c
@@ -42,8 +42,9 @@ int __must_check clk_bulk_get(struct device *dev, int num_clks,
                 clks[i].clk = clk_get(dev, clks[i].id);
                 if (IS_ERR(clks[i].clk)) {
                         ret = PTR_ERR(clks[i].clk);
-                        dev_err(dev, "Failed to get clk '%s': %d\n",
-                                clks[i].id, ret);
+                        if (ret != -EPROBE_DEFER)
+                                dev_err(dev, "Failed to get clk '%s': %d\n",
+                                        clks[i].id, ret);
                         clks[i].clk = NULL;
                         goto err;
                 }
diff --git a/drivers/clk/clk-npcm7xx.c b/drivers/clk/clk-npcm7xx.c
new file mode 100644
index 000000000000..740af90a9508
--- /dev/null
+++ b/drivers/clk/clk-npcm7xx.c
@@ -0,0 +1,656 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Nuvoton NPCM7xx Clock Generator
+ * All the clocks are initialized by the bootloader, so this driver allow only
+ * reading of current settings directly from the hardware.
+ *
+ * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
+ */
+
+#include <linux/module.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/bitfield.h>
+
+#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
+
+struct npcm7xx_clk_pll {
+        struct clk_hw   hw;
+        void __iomem    *pllcon;
+        u8              flags;
+};
+
+#define to_npcm7xx_clk_pll(_hw) container_of(_hw, struct npcm7xx_clk_pll, hw)
+
+#define PLLCON_LOKI     BIT(31)
+#define PLLCON_LOKS     BIT(30)
+#define PLLCON_FBDV     GENMASK(27, 16)
+#define PLLCON_OTDV2    GENMASK(15, 13)
+#define PLLCON_PWDEN    BIT(12)
+#define PLLCON_OTDV1    GENMASK(10, 8)
+#define PLLCON_INDV     GENMASK(5, 0)
+
+static unsigned long npcm7xx_clk_pll_recalc_rate(struct clk_hw *hw,
+                                                 unsigned long parent_rate)
+{
+        struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw);
+        unsigned long fbdv, indv, otdv1, otdv2;
+        unsigned int val;
+        u64 ret;
+
+        if (parent_rate == 0) {
+                pr_err("%s: parent rate is zero", __func__);
+                return 0;
+        }
+
+        val = readl_relaxed(pll->pllcon);
+
+        indv = FIELD_GET(PLLCON_INDV, val);
+        fbdv = FIELD_GET(PLLCON_FBDV, val);
+        otdv1 = FIELD_GET(PLLCON_OTDV1, val);
+        otdv2 = FIELD_GET(PLLCON_OTDV2, val);
+
+        ret = (u64)parent_rate * fbdv;
+        do_div(ret, indv * otdv1 * otdv2);
+
+        return ret;
+}
+
+static const struct clk_ops npcm7xx_clk_pll_ops = {
+        .recalc_rate = npcm7xx_clk_pll_recalc_rate,
+};
+
+static struct clk_hw *
+npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name,
+                         const char *parent_name, unsigned long flags)
+{
+        struct npcm7xx_clk_pll *pll;
+        struct clk_init_data init;
+        struct clk_hw *hw;
+        int ret;
+
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll)
+                return ERR_PTR(-ENOMEM);
+
+        pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
+
+        init.name = name;
+        init.ops = &npcm7xx_clk_pll_ops;
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+        init.flags = flags;
+
+        pll->pllcon = pllcon;
+        pll->hw.init = &init;
+
+        hw = &pll->hw;
+
+        ret = clk_hw_register(NULL, hw);
+        if (ret) {
+                kfree(pll);
+                hw = ERR_PTR(ret);
+        }
+
+        return hw;
+}
+
+#define NPCM7XX_CLKEN1          (0x00)
+#define NPCM7XX_CLKEN2          (0x28)
+#define NPCM7XX_CLKEN3          (0x30)
+#define NPCM7XX_CLKSEL          (0x04)
+#define NPCM7XX_CLKDIV1         (0x08)
+#define NPCM7XX_CLKDIV2         (0x2C)
+#define NPCM7XX_CLKDIV3         (0x58)
+#define NPCM7XX_PLLCON0         (0x0C)
+#define NPCM7XX_PLLCON1         (0x10)
+#define NPCM7XX_PLLCON2         (0x54)
+#define NPCM7XX_SWRSTR          (0x14)
+#define NPCM7XX_IRQWAKECON      (0x18)
+#define NPCM7XX_IRQWAKEFLAG     (0x1C)
+#define NPCM7XX_IPSRST1         (0x20)
+#define NPCM7XX_IPSRST2         (0x24)
+#define NPCM7XX_IPSRST3         (0x34)
+#define NPCM7XX_WD0RCR          (0x38)
+#define NPCM7XX_WD1RCR          (0x3C)
+#define NPCM7XX_WD2RCR          (0x40)
+#define NPCM7XX_SWRSTC1         (0x44)
+#define NPCM7XX_SWRSTC2         (0x48)
+#define NPCM7XX_SWRSTC3         (0x4C)
+#define NPCM7XX_SWRSTC4         (0x50)
+#define NPCM7XX_CORSTC          (0x5C)
+#define NPCM7XX_PLLCONG         (0x60)
+#define NPCM7XX_AHBCKFI         (0x64)
+#define NPCM7XX_SECCNT          (0x68)
+#define NPCM7XX_CNTR25M         (0x6C)
+
+struct npcm7xx_clk_gate_data {
+        u32 reg;
+        u8 bit_idx;
+        const char *name;
+        const char *parent_name;
+        unsigned long flags;
+        /*
+         * If this clock is exported via DT, set onecell_idx to constant
+         * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
+         * this specific clock.  Otherwise, set to -1.
+         */
+        int onecell_idx;
+};
+
+struct npcm7xx_clk_mux_data {
+        u8 shift;
+        u8 mask;
+        u32 *table;
+        const char *name;
+        const char * const *parent_names;
+        u8 num_parents;
+        unsigned long flags;
+        /*
+         * If this clock is exported via DT, set onecell_idx to constant
+         * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
+         * this specific clock.  Otherwise, set to -1.
+         */
+        int onecell_idx;
+
+};
+
+struct npcm7xx_clk_div_fixed_data {
+        u8 mult;
+        u8 div;
+        const char *name;
+        const char *parent_name;
+        u8 clk_divider_flags;
+        /*
+         * If this clock is exported via DT, set onecell_idx to constant
+         * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
+         * this specific clock.  Otherwise, set to -1.
+         */
+        int onecell_idx;
+};
+
+
+struct npcm7xx_clk_div_data {
+        u32 reg;
+        u8 shift;
+        u8 width;
+        const char *name;
+        const char *parent_name;
+        u8 clk_divider_flags;
+        unsigned long flags;
+        /*
+         * If this clock is exported via DT, set onecell_idx to constant
+         * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
+         * this specific clock.  Otherwise, set to -1.
+         */
+        int onecell_idx;
+};
+
+struct npcm7xx_clk_pll_data {
+        u32 reg;
+        const char *name;
+        const char *parent_name;
+        unsigned long flags;
+        /*
+         * If this clock is exported via DT, set onecell_idx to constant
+         * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
+         * this specific clock.  Otherwise, set to -1.
+         */
+        int onecell_idx;
+};
+
+/*
+ * Single copy of strings used to refer to clocks within this driver indexed by
+ * above enum.
+ */
+#define NPCM7XX_CLK_S_REFCLK      "refclk"
+#define NPCM7XX_CLK_S_SYSBYPCK    "sysbypck"
+#define NPCM7XX_CLK_S_MCBYPCK     "mcbypck"
+#define NPCM7XX_CLK_S_GFXBYPCK    "gfxbypck"
+#define NPCM7XX_CLK_S_PLL0        "pll0"
+#define NPCM7XX_CLK_S_PLL1        "pll1"
+#define NPCM7XX_CLK_S_PLL1_DIV2   "pll1_div2"
+#define NPCM7XX_CLK_S_PLL2        "pll2"
+#define NPCM7XX_CLK_S_PLL_GFX     "pll_gfx"
+#define NPCM7XX_CLK_S_PLL2_DIV2   "pll2_div2"
+#define NPCM7XX_CLK_S_PIX_MUX     "gfx_pixel"
+#define NPCM7XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
+#define NPCM7XX_CLK_S_MC_MUX      "mc_phy"
+#define NPCM7XX_CLK_S_CPU_MUX     "cpu"  /*AKA system clock.*/
+#define NPCM7XX_CLK_S_MC          "mc"
+#define NPCM7XX_CLK_S_AXI         "axi"  /*AKA CLK2*/
+#define NPCM7XX_CLK_S_AHB         "ahb"  /*AKA CLK4*/
+#define NPCM7XX_CLK_S_CLKOUT_MUX  "clkout_mux"
+#define NPCM7XX_CLK_S_UART_MUX    "uart_mux"
+#define NPCM7XX_CLK_S_TIM_MUX     "timer_mux"
+#define NPCM7XX_CLK_S_SD_MUX      "sd_mux"
+#define NPCM7XX_CLK_S_GFXM_MUX    "gfxm_mux"
+#define NPCM7XX_CLK_S_SU_MUX      "serial_usb_mux"
+#define NPCM7XX_CLK_S_DVC_MUX     "dvc_mux"
+#define NPCM7XX_CLK_S_GFX_MUX     "gfx_mux"
+#define NPCM7XX_CLK_S_GFX_PIXEL   "gfx_pixel"
+#define NPCM7XX_CLK_S_SPI0        "spi0"
+#define NPCM7XX_CLK_S_SPI3        "spi3"
+#define NPCM7XX_CLK_S_SPIX        "spix"
+#define NPCM7XX_CLK_S_APB1        "apb1"
+#define NPCM7XX_CLK_S_APB2        "apb2"
+#define NPCM7XX_CLK_S_APB3        "apb3"
+#define NPCM7XX_CLK_S_APB4        "apb4"
+#define NPCM7XX_CLK_S_APB5        "apb5"
+#define NPCM7XX_CLK_S_TOCK        "tock"
+#define NPCM7XX_CLK_S_CLKOUT      "clkout"
+#define NPCM7XX_CLK_S_UART        "uart"
+#define NPCM7XX_CLK_S_TIMER       "timer"
+#define NPCM7XX_CLK_S_MMC         "mmc"
+#define NPCM7XX_CLK_S_SDHC        "sdhc"
+#define NPCM7XX_CLK_S_ADC         "adc"
+#define NPCM7XX_CLK_S_GFX         "gfx0_gfx1_mem"
+#define NPCM7XX_CLK_S_USBIF       "serial_usbif"
+#define NPCM7XX_CLK_S_USB_HOST    "usb_host"
+#define NPCM7XX_CLK_S_USB_BRIDGE  "usb_bridge"
+#define NPCM7XX_CLK_S_PCI         "pci"
+
+static u32 pll_mux_table[] = {0, 1, 2, 3};
+static const char * const pll_mux_parents[] __initconst = {
+        NPCM7XX_CLK_S_PLL0,
+        NPCM7XX_CLK_S_PLL1_DIV2,
+        NPCM7XX_CLK_S_REFCLK,
+        NPCM7XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 cpuck_mux_table[] = {0, 1, 2, 3};
+static const char * const cpuck_mux_parents[] __initconst = {
+        NPCM7XX_CLK_S_PLL0,
+        NPCM7XX_CLK_S_PLL1_DIV2,
+        NPCM7XX_CLK_S_REFCLK,
+        NPCM7XX_CLK_S_SYSBYPCK,
+};
+
+static u32 pixcksel_mux_table[] = {0, 2};
+static const char * const pixcksel_mux_parents[] __initconst = {
+        NPCM7XX_CLK_S_PLL_GFX,
+        NPCM7XX_CLK_S_REFCLK,
+};
+
+static u32 sucksel_mux_table[] = {2, 3};
+static const char * const sucksel_mux_parents[] __initconst = {
+        NPCM7XX_CLK_S_REFCLK,
+        NPCM7XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 mccksel_mux_table[] = {0, 2, 3};
+static const char * const mccksel_mux_parents[] __initconst = {
+        NPCM7XX_CLK_S_PLL1_DIV2,
+        NPCM7XX_CLK_S_REFCLK,
+        NPCM7XX_CLK_S_MCBYPCK,
+};
+
+static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4};
+static const char * const clkoutsel_mux_parents[] __initconst = {
+        NPCM7XX_CLK_S_PLL0,
+        NPCM7XX_CLK_S_PLL1_DIV2,
+        NPCM7XX_CLK_S_REFCLK,
+        NPCM7XX_CLK_S_PLL_GFX, // divided by 2
+        NPCM7XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 gfxmsel_mux_table[] = {2, 3};
+static const char * const gfxmsel_mux_parents[] __initconst = {
+        NPCM7XX_CLK_S_REFCLK,
+        NPCM7XX_CLK_S_PLL2_DIV2,
+};
+
+static u32 dvcssel_mux_table[] = {2, 3};
+static const char * const dvcssel_mux_parents[] __initconst = {
+        NPCM7XX_CLK_S_REFCLK,
+        NPCM7XX_CLK_S_PLL2,
+};
+
+static const struct npcm7xx_clk_pll_data npcm7xx_plls[] __initconst = {
+        {NPCM7XX_PLLCON0, NPCM7XX_CLK_S_PLL0, NPCM7XX_CLK_S_REFCLK, 0, -1},
+
+        {NPCM7XX_PLLCON1, NPCM7XX_CLK_S_PLL1,
+        NPCM7XX_CLK_S_REFCLK, 0, -1},
+
+        {NPCM7XX_PLLCON2, NPCM7XX_CLK_S_PLL2,
+        NPCM7XX_CLK_S_REFCLK, 0, -1},
+
+        {NPCM7XX_PLLCONG, NPCM7XX_CLK_S_PLL_GFX,
+        NPCM7XX_CLK_S_REFCLK, 0, -1},
+};
+
+static const struct npcm7xx_clk_mux_data npcm7xx_muxes[] __initconst = {
+        {0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX,
+        cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL,
+        NPCM7XX_CLK_CPU},
+
+        {4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX,
+        pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0,
+        NPCM7XX_CLK_GFX_PIXEL},
+
+        {6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX,
+        pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+        {8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX,
+        pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+        {10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX,
+        sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1},
+
+        {12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX,
+        mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1},
+
+        {14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX,
+        pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+        {16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX,
+        pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
+
+        {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX,
+        clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1},
+
+        {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX,
+        gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1},
+
+        {23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX,
+        dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
+};
+
+/* fixed ratio dividers (no register): */
+static const struct npcm7xx_clk_div_fixed_data npcm7xx_divs_fx[] __initconst = {
+        { 1, 2, NPCM7XX_CLK_S_MC, NPCM7XX_CLK_S_MC_MUX, 0, NPCM7XX_CLK_MC},
+        { 1, 2, NPCM7XX_CLK_S_PLL1_DIV2, NPCM7XX_CLK_S_PLL1, 0, -1},
+        { 1, 2, NPCM7XX_CLK_S_PLL2_DIV2, NPCM7XX_CLK_S_PLL2, 0, -1},
+};
+
+/* configurable dividers: */
+static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = {
+        {NPCM7XX_CLKDIV1, 28, 3, NPCM7XX_CLK_S_ADC,
+        NPCM7XX_CLK_S_TIMER, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_ADC},
+        /*30-28 ADCCKDIV*/
+        {NPCM7XX_CLKDIV1, 26, 2, NPCM7XX_CLK_S_AHB,
+        NPCM7XX_CLK_S_AXI, 0, CLK_IS_CRITICAL, NPCM7XX_CLK_AHB},
+        /*27-26 CLK4DIV*/
+        {NPCM7XX_CLKDIV1, 21, 5, NPCM7XX_CLK_S_TIMER,
+        NPCM7XX_CLK_S_TIM_MUX, 0, 0, NPCM7XX_CLK_TIMER},
+        /*25-21 TIMCKDIV*/
+        {NPCM7XX_CLKDIV1, 16, 5, NPCM7XX_CLK_S_UART,
+        NPCM7XX_CLK_S_UART_MUX, 0, 0, NPCM7XX_CLK_UART},
+        /*20-16 UARTDIV*/
+        {NPCM7XX_CLKDIV1, 11, 5, NPCM7XX_CLK_S_MMC,
+        NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_MMC},
+        /*15-11 MMCCKDIV*/
+        {NPCM7XX_CLKDIV1, 6, 5, NPCM7XX_CLK_S_SPI3,
+        NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI3},
+        /*10-6 AHB3CKDIV*/
+        {NPCM7XX_CLKDIV1, 2, 4, NPCM7XX_CLK_S_PCI,
+        NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_PCI},
+        /*5-2 PCICKDIV*/
+        {NPCM7XX_CLKDIV1, 0, 1, NPCM7XX_CLK_S_AXI,
+        NPCM7XX_CLK_S_CPU_MUX, CLK_DIVIDER_POWER_OF_TWO, CLK_IS_CRITICAL,
+        NPCM7XX_CLK_AXI},/*0 CLK2DIV*/
+
+        {NPCM7XX_CLKDIV2, 30, 2, NPCM7XX_CLK_S_APB4,
+        NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB4},
+        /*31-30 APB4CKDIV*/
+        {NPCM7XX_CLKDIV2, 28, 2, NPCM7XX_CLK_S_APB3,
+        NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB3},
+        /*29-28 APB3CKDIV*/
+        {NPCM7XX_CLKDIV2, 26, 2, NPCM7XX_CLK_S_APB2,
+        NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB2},
+        /*27-26 APB2CKDIV*/
+        {NPCM7XX_CLKDIV2, 24, 2, NPCM7XX_CLK_S_APB1,
+        NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB1},
+        /*25-24 APB1CKDIV*/
+        {NPCM7XX_CLKDIV2, 22, 2, NPCM7XX_CLK_S_APB5,
+        NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB5},
+        /*23-22 APB5CKDIV*/
+        {NPCM7XX_CLKDIV2, 16, 5, NPCM7XX_CLK_S_CLKOUT,
+        NPCM7XX_CLK_S_CLKOUT_MUX, 0, 0, NPCM7XX_CLK_CLKOUT},
+        /*20-16 CLKOUTDIV*/
+        {NPCM7XX_CLKDIV2, 13, 3, NPCM7XX_CLK_S_GFX,
+        NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_GFX},
+        /*15-13 GFXCKDIV*/
+        {NPCM7XX_CLKDIV2, 8, 5, NPCM7XX_CLK_S_USB_BRIDGE,
+        NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU},
+        /*12-8 SUCKDIV*/
+        {NPCM7XX_CLKDIV2, 4, 4, NPCM7XX_CLK_S_USB_HOST,
+        NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU48},
+        /*7-4 SU48CKDIV*/
+        {NPCM7XX_CLKDIV2, 0, 4, NPCM7XX_CLK_S_SDHC,
+        NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_SDHC}
+        ,/*3-0 SD1CKDIV*/
+
+        {NPCM7XX_CLKDIV3, 6, 5, NPCM7XX_CLK_S_SPI0,
+        NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI0},
+        /*10-6 SPI0CKDV*/
+        {NPCM7XX_CLKDIV3, 1, 5, NPCM7XX_CLK_S_SPIX,
+        NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPIX},
+        /*5-1 SPIXCKDV*/
+
+};
+
+static const struct npcm7xx_clk_gate_data npcm7xx_gates[] __initconst = {
+        {NPCM7XX_CLKEN1, 31, "smb1-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN1, 30, "smb0-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN1, 29, "smb7-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN1, 28, "smb6-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN1, 27, "adc-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN1, 26, "wdt-gate", NPCM7XX_CLK_S_TIMER, 0},
+        {NPCM7XX_CLKEN1, 25, "usbdev3-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN1, 24, "usbdev6-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN1, 23, "usbdev5-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN1, 22, "usbdev4-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN1, 21, "emc2-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN1, 20, "timer5_9-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN1, 19, "timer0_4-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN1, 18, "pwmm0-gate", NPCM7XX_CLK_S_APB3, 0},
+        {NPCM7XX_CLKEN1, 17, "huart-gate", NPCM7XX_CLK_S_UART, 0},
+        {NPCM7XX_CLKEN1, 16, "smb5-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN1, 15, "smb4-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN1, 14, "smb3-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN1, 13, "smb2-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN1, 12, "mc-gate", NPCM7XX_CLK_S_MC, 0},
+        {NPCM7XX_CLKEN1, 11, "uart01-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN1, 10, "aes-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN1, 9, "peci-gate", NPCM7XX_CLK_S_APB3, 0},
+        {NPCM7XX_CLKEN1, 8, "usbdev2-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN1, 7, "uart23-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN1, 6, "emc1-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN1, 5, "usbdev1-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN1, 4, "shm-gate", NPCM7XX_CLK_S_AHB, 0},
+        /* bit 3 is reserved */
+        {NPCM7XX_CLKEN1, 2, "kcs-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN1, 1, "spi3-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN1, 0, "spi0-gate", NPCM7XX_CLK_S_AHB, 0},
+
+        {NPCM7XX_CLKEN2, 31, "cp-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN2, 30, "tock-gate", NPCM7XX_CLK_S_TOCK, 0},
+        /* bit 29 is reserved */
+        {NPCM7XX_CLKEN2, 28, "gmac1-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN2, 27, "usbif-gate", NPCM7XX_CLK_S_USBIF, 0},
+        {NPCM7XX_CLKEN2, 26, "usbhost-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN2, 25, "gmac2-gate", NPCM7XX_CLK_S_AHB, 0},
+        /* bit 24 is reserved */
+        {NPCM7XX_CLKEN2, 23, "pspi2-gate", NPCM7XX_CLK_S_APB5, 0},
+        {NPCM7XX_CLKEN2, 22, "pspi1-gate", NPCM7XX_CLK_S_APB5, 0},
+        {NPCM7XX_CLKEN2, 21, "3des-gate", NPCM7XX_CLK_S_AHB, 0},
+        /* bit 20 is reserved */
+        {NPCM7XX_CLKEN2, 19, "siox2-gate", NPCM7XX_CLK_S_APB3, 0},
+        {NPCM7XX_CLKEN2, 18, "siox1-gate", NPCM7XX_CLK_S_APB3, 0},
+        /* bit 17 is reserved */
+        {NPCM7XX_CLKEN2, 16, "fuse-gate", NPCM7XX_CLK_S_APB4, 0},
+        /*  bit 15 is reserved */
+        {NPCM7XX_CLKEN2, 14, "vcd-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN2, 13, "ece-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN2, 12, "vdma-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN2, 10, "gfxsys-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN2, 9, "sdhc-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN2, 8, "mmc-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN2, 7, "mft7-gate", NPCM7XX_CLK_S_APB4, 0},
+        {NPCM7XX_CLKEN2, 6, "mft6-gate", NPCM7XX_CLK_S_APB4, 0},
+        {NPCM7XX_CLKEN2, 5, "mft5-gate", NPCM7XX_CLK_S_APB4, 0},
+        {NPCM7XX_CLKEN2, 4, "mft4-gate", NPCM7XX_CLK_S_APB4, 0},
+        {NPCM7XX_CLKEN2, 3, "mft3-gate", NPCM7XX_CLK_S_APB4, 0},
+        {NPCM7XX_CLKEN2, 2, "mft2-gate", NPCM7XX_CLK_S_APB4, 0},
+        {NPCM7XX_CLKEN2, 1, "mft1-gate", NPCM7XX_CLK_S_APB4, 0},
+        {NPCM7XX_CLKEN2, 0, "mft0-gate", NPCM7XX_CLK_S_APB4, 0},
+
+        {NPCM7XX_CLKEN3, 31, "gpiom7-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN3, 30, "gpiom6-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN3, 29, "gpiom5-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN3, 28, "gpiom4-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN3, 27, "gpiom3-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN3, 26, "gpiom2-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN3, 25, "gpiom1-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN3, 24, "gpiom0-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN3, 23, "espi-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN3, 22, "smb11-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN3, 21, "smb10-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN3, 20, "smb9-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN3, 19, "smb8-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN3, 18, "smb15-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN3, 17, "rng-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN3, 16, "timer10_14-gate", NPCM7XX_CLK_S_APB1, 0},
+        {NPCM7XX_CLKEN3, 15, "pcirc-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN3, 14, "sececc-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN3, 13, "sha-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN3, 12, "smb14-gate", NPCM7XX_CLK_S_APB2, 0},
+        /* bit 11 is reserved */
+        /* bit 10 is reserved */
+        {NPCM7XX_CLKEN3, 9, "pcimbx-gate", NPCM7XX_CLK_S_AHB, 0},
+        /* bit 8 is reserved */
+        {NPCM7XX_CLKEN3, 7, "usbdev9-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN3, 6, "usbdev8-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN3, 5, "usbdev7-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN3, 4, "usbdev0-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN3, 3, "smb13-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN3, 2, "spix-gate", NPCM7XX_CLK_S_AHB, 0},
+        {NPCM7XX_CLKEN3, 1, "smb12-gate", NPCM7XX_CLK_S_APB2, 0},
+        {NPCM7XX_CLKEN3, 0, "pwmm1-gate", NPCM7XX_CLK_S_APB3, 0},
+};
+
+static DEFINE_SPINLOCK(npcm7xx_clk_lock);
+
+static void __init npcm7xx_clk_init(struct device_node *clk_np)
+{
+        struct clk_hw_onecell_data *npcm7xx_clk_data;
+        void __iomem *clk_base;
+        struct resource res;
+        struct clk_hw *hw;
+        int ret;
+        int i;
+
+        ret = of_address_to_resource(clk_np, 0, &res);
+        if (ret) {
+                pr_err("%s: failed to get resource, ret %d\n", clk_np->name,
+                        ret);
+                return;
+        }
+
+        clk_base = ioremap(res.start, resource_size(&res));
+        if (!clk_base)
+                goto npcm7xx_init_error;
+
+        npcm7xx_clk_data = kzalloc(sizeof(*npcm7xx_clk_data->hws) *
+                NPCM7XX_NUM_CLOCKS + sizeof(npcm7xx_clk_data), GFP_KERNEL);
+        if (!npcm7xx_clk_data)
+                goto npcm7xx_init_np_err;
+
+        npcm7xx_clk_data->num = NPCM7XX_NUM_CLOCKS;
+
+        for (i = 0; i < NPCM7XX_NUM_CLOCKS; i++)
+                npcm7xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
+
+        /* Register plls */
+        for (i = 0; i < ARRAY_SIZE(npcm7xx_plls); i++) {
+                const struct npcm7xx_clk_pll_data *pll_data = &npcm7xx_plls[i];
+
+                hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg,
+                        pll_data->name, pll_data->parent_name, pll_data->flags);
+                if (IS_ERR(hw)) {
+                        pr_err("npcm7xx_clk: Can't register pll\n");
+                        goto npcm7xx_init_fail;
+                }
+
+                if (pll_data->onecell_idx >= 0)
+                        npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw;
+        }
+
+        /* Register fixed dividers */
+        hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL1_DIV2,
+                        NPCM7XX_CLK_S_PLL1, 0, 1, 2);
+        if (IS_ERR(hw)) {
+                pr_err("npcm7xx_clk: Can't register fixed div\n");
+                goto npcm7xx_init_fail;
+        }
+
+        hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL2_DIV2,
+                        NPCM7XX_CLK_S_PLL2, 0, 1, 2);
+        if (IS_ERR(hw)) {
+                pr_err("npcm7xx_clk: Can't register div2\n");
+                goto npcm7xx_init_fail;
+        }
+
+        /* Register muxes */
+        for (i = 0; i < ARRAY_SIZE(npcm7xx_muxes); i++) {
+                const struct npcm7xx_clk_mux_data *mux_data = &npcm7xx_muxes[i];
+
+                hw = clk_hw_register_mux_table(NULL,
+                        mux_data->name,
+                        mux_data->parent_names, mux_data->num_parents,
+                        mux_data->flags, clk_base + NPCM7XX_CLKSEL,
+                        mux_data->shift, mux_data->mask, 0,
+                        mux_data->table, &npcm7xx_clk_lock);
+
+                if (IS_ERR(hw)) {
+                        pr_err("npcm7xx_clk: Can't register mux\n");
+                        goto npcm7xx_init_fail;
+                }
+
+                if (mux_data->onecell_idx >= 0)
+                        npcm7xx_clk_data->hws[mux_data->onecell_idx] = hw;
+        }
+
+        /* Register clock dividers specified in npcm7xx_divs */
+        for (i = 0; i < ARRAY_SIZE(npcm7xx_divs); i++) {
+                const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i];
+
+                hw = clk_hw_register_divider(NULL, div_data->name,
+                                div_data->parent_name,
+                                div_data->flags,
+                                clk_base + div_data->reg,
+                                div_data->shift, div_data->width,
+                                div_data->clk_divider_flags, &npcm7xx_clk_lock);
+                if (IS_ERR(hw)) {
+                        pr_err("npcm7xx_clk: Can't register div table\n");
+                        goto npcm7xx_init_fail;
+                }
+
+                if (div_data->onecell_idx >= 0)
+                        npcm7xx_clk_data->hws[div_data->onecell_idx] = hw;
+        }
+
+        ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
+                                        npcm7xx_clk_data);
+        if (ret)
+                pr_err("failed to add DT provider: %d\n", ret);
+
+        of_node_put(clk_np);
+
+        return;
+
+npcm7xx_init_fail:
+        kfree(npcm7xx_clk_data->hws);
+npcm7xx_init_np_err:
+        iounmap(clk_base);
+npcm7xx_init_error:
+        of_node_put(clk_np);
+}
+CLK_OF_DECLARE(npcm7xx_clk_init, "nuvoton,npcm750-clk", npcm7xx_clk_init);
diff --git a/drivers/clk/clk-si544.c b/drivers/clk/clk-si544.c
index 1c96a9f6c022..1e2a3b8f9454 100644
--- a/drivers/clk/clk-si544.c
+++ b/drivers/clk/clk-si544.c
@@ -207,6 +207,7 @@ static int si544_calc_muldiv(struct clk_si544_muldiv *settings,
 
         /* And the fractional bits using the remainder */
         vco = (u64)tmp << 32;
+        vco += FXO / 2; /* Round to nearest multiple */
         do_div(vco, FXO);
         settings->fb_div_frac = vco;
 
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 83e8cd81674f..a907555b2a3d 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -579,14 +579,9 @@ clk_stm32_register_gate_ops(struct device *dev,
                             spinlock_t *lock)
 {
         struct clk_init_data init = { NULL };
-        struct clk_gate *gate;
         struct clk_hw *hw;
         int ret;
 
-        gate = kzalloc(sizeof(*gate), GFP_KERNEL);
-        if (!gate)
-                return ERR_PTR(-ENOMEM);
-
         init.name = name;
         init.parent_names = &parent_name;
         init.num_parents = 1;
@@ -604,10 +599,8 @@ clk_stm32_register_gate_ops(struct device *dev,
         hw->init = &init;
 
         ret = clk_hw_register(dev, hw);
-        if (ret) {
-                kfree(gate);
+        if (ret)
                 hw = ERR_PTR(ret);
-        }
 
         return hw;
 }
@@ -1988,7 +1981,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
                   _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
 
         /* Debug clocks */
-        GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
+        GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED,
+             RCC_DBGCFGR, 8, 0),
 
         COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
                   _GATE(RCC_DBGCFGR, 9, 0),
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 7af555f0e60c..a24a6afb50b6 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -549,7 +549,8 @@ static void clk_core_rate_unprotect(struct clk_core *core)
         if (!core)
                 return;
 
-        if (WARN_ON(core->protect_count == 0))
+        if (WARN(core->protect_count == 0,
+            "%s already unprotected\n", core->name))
                 return;
 
         if (--core->protect_count > 0)
@@ -682,16 +683,18 @@ static void clk_core_unprepare(struct clk_core *core)
         if (!core)
                 return;
 
-        if (WARN_ON(core->prepare_count == 0))
+        if (WARN(core->prepare_count == 0,
+            "%s already unprepared\n", core->name))
                 return;
 
-        if (WARN_ON(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL))
+        if (WARN(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL,
+            "Unpreparing critical %s\n", core->name))
                 return;
 
         if (--core->prepare_count > 0)
                 return;
 
-        WARN_ON(core->enable_count > 0);
+        WARN(core->enable_count > 0, "Unpreparing enabled %s\n", core->name);
 
         trace_clk_unprepare(core);
 
@@ -809,10 +812,11 @@ static void clk_core_disable(struct clk_core *core)
         if (!core)
                 return;
 
-        if (WARN_ON(core->enable_count == 0))
+        if (WARN(core->enable_count == 0, "%s already disabled\n", core->name))
                 return;
 
-        if (WARN_ON(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL))
+        if (WARN(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL,
+            "Disabling critical %s\n", core->name))
                 return;
 
         if (--core->enable_count > 0)
@@ -867,7 +871,8 @@ static int clk_core_enable(struct clk_core *core)
         if (!core)
                 return 0;
 
-        if (WARN_ON(core->prepare_count == 0))
+        if (WARN(core->prepare_count == 0,
+            "Enabling unprepared %s\n", core->name))
                 return -ESHUTDOWN;
 
         if (core->enable_count == 0) {
@@ -2171,7 +2176,6 @@ void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent)
 bool clk_has_parent(struct clk *clk, struct clk *parent)
 {
         struct clk_core *core, *parent_core;
-        unsigned int i;
 
         /* NULL clocks should be nops, so return success if either is NULL. */
         if (!clk || !parent)
@@ -2184,11 +2188,8 @@ bool clk_has_parent(struct clk *clk, struct clk *parent)
         if (core->parent == parent_core)
                 return true;
 
-        for (i = 0; i < core->num_parents; i++)
-                if (strcmp(core->parent_names[i], parent_core->name) == 0)
-                        return true;
-
-        return false;
+        return match_string(core->parent_names, core->num_parents,
+                            parent_core->name) >= 0;
 }
 EXPORT_SYMBOL_GPL(clk_has_parent);
 
@@ -2609,81 +2610,31 @@ static int possible_parents_show(struct seq_file *s, void *data)
 }
 DEFINE_SHOW_ATTRIBUTE(possible_parents);
 
-static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
+static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
 {
-        struct dentry *d;
-        int ret = -ENOMEM;
-
-        if (!core || !pdentry) {
-                ret = -EINVAL;
-                goto out;
-        }
-
-        d = debugfs_create_dir(core->name, pdentry);
-        if (!d)
-                goto out;
+        struct dentry *root;
 
-        core->dentry = d;
-
-        d = debugfs_create_ulong("clk_rate", 0444, core->dentry, &core->rate);
-        if (!d)
-                goto err_out;
-
-        d = debugfs_create_ulong("clk_accuracy", 0444, core->dentry,
-                                 &core->accuracy);
-        if (!d)
-                goto err_out;
-
-        d = debugfs_create_u32("clk_phase", 0444, core->dentry, &core->phase);
-        if (!d)
-                goto err_out;
-
-        d = debugfs_create_file("clk_flags", 0444, core->dentry, core,
-                                &clk_flags_fops);
-        if (!d)
-                goto err_out;
-
-        d = debugfs_create_u32("clk_prepare_count", 0444, core->dentry,
-                               &core->prepare_count);
-        if (!d)
-                goto err_out;
-
-        d = debugfs_create_u32("clk_enable_count", 0444, core->dentry,
-                               &core->enable_count);
-        if (!d)
-                goto err_out;
-
-        d = debugfs_create_u32("clk_protect_count", 0444, core->dentry,
-                               &core->protect_count);
-        if (!d)
-                goto err_out;
-
-        d = debugfs_create_u32("clk_notifier_count", 0444, core->dentry,
-                               &core->notifier_count);
-        if (!d)
-                goto err_out;
+        if (!core || !pdentry)
+                return;
 
-        if (core->num_parents > 1) {
-                d = debugfs_create_file("clk_possible_parents", 0444,
-                                core->dentry, core, &possible_parents_fops);
-                if (!d)
-                        goto err_out;
-        }
+        root = debugfs_create_dir(core->name, pdentry);
+        core->dentry = root;
 
-        if (core->ops->debug_init) {
-                ret = core->ops->debug_init(core->hw, core->dentry);
-                if (ret)
-                        goto err_out;
-        }
+        debugfs_create_ulong("clk_rate", 0444, root, &core->rate);
+        debugfs_create_ulong("clk_accuracy", 0444, root, &core->accuracy);
+        debugfs_create_u32("clk_phase", 0444, root, &core->phase);
+        debugfs_create_file("clk_flags", 0444, root, core, &clk_flags_fops);
+        debugfs_create_u32("clk_prepare_count", 0444, root, &core->prepare_count);
+        debugfs_create_u32("clk_enable_count", 0444, root, &core->enable_count);
+        debugfs_create_u32("clk_protect_count", 0444, root, &core->protect_count);
+        debugfs_create_u32("clk_notifier_count", 0444, root, &core->notifier_count);
 
-        ret = 0;
-        goto out;
+        if (core->num_parents > 1)
+                debugfs_create_file("clk_possible_parents", 0444, root, core,
+                                    &possible_parents_fops);
 
-err_out:
-        debugfs_remove_recursive(core->dentry);
-        core->dentry = NULL;
-out:
-        return ret;
+        if (core->ops->debug_init)
+                core->ops->debug_init(core->hw, core->dentry);
 }
 
 /**
@@ -2694,17 +2645,13 @@ out:
  * initialized.  Otherwise it bails out early since the debugfs clk directory
  * will be created lazily by clk_debug_init as part of a late_initcall.
  */
-static int clk_debug_register(struct clk_core *core)
+static void clk_debug_register(struct clk_core *core)
 {
-        int ret = 0;
-
         mutex_lock(&clk_debug_lock);
         hlist_add_head(&core->debug_node, &clk_debug_list);
         if (inited)
-                ret = clk_debug_create_one(core, rootdir);
+                clk_debug_create_one(core, rootdir);
         mutex_unlock(&clk_debug_lock);
-
-        return ret;
 }
 
  /**
@@ -2724,19 +2671,6 @@ static void clk_debug_unregister(struct clk_core *core)
         mutex_unlock(&clk_debug_lock);
 }
 
-struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
-                                void *data, const struct file_operations *fops)
-{
-        struct dentry *d = NULL;
-
-        if (hw->core->dentry)
-                d = debugfs_create_file(name, mode, hw->core->dentry, data,
-                                        fops);
-
-        return d;
-}
-EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
-
 /**
  * clk_debug_init - lazily populate the debugfs clk directory
  *
@@ -2749,32 +2683,17 @@ EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
 static int __init clk_debug_init(void)
 {
         struct clk_core *core;
-        struct dentry *d;
 
         rootdir = debugfs_create_dir("clk", NULL);
 
-        if (!rootdir)
-                return -ENOMEM;
-
-        d = debugfs_create_file("clk_summary", 0444, rootdir, &all_lists,
-                                &clk_summary_fops);
-        if (!d)
-                return -ENOMEM;
-
-        d = debugfs_create_file("clk_dump", 0444, rootdir, &all_lists,
-                                &clk_dump_fops);
-        if (!d)
-                return -ENOMEM;
-
-        d = debugfs_create_file("clk_orphan_summary", 0444, rootdir,
-                                &orphan_list, &clk_summary_fops);
-        if (!d)
-                return -ENOMEM;
-
-        d = debugfs_create_file("clk_orphan_dump", 0444, rootdir,
-                                &orphan_list, &clk_dump_fops);
-        if (!d)
-                return -ENOMEM;
+        debugfs_create_file("clk_summary", 0444, rootdir, &all_lists,
+                            &clk_summary_fops);
+        debugfs_create_file("clk_dump", 0444, rootdir, &all_lists,
+                            &clk_dump_fops);
+        debugfs_create_file("clk_orphan_summary", 0444, rootdir, &orphan_list,
+                            &clk_summary_fops);
+        debugfs_create_file("clk_orphan_dump", 0444, rootdir, &orphan_list,
+                            &clk_dump_fops);
 
         mutex_lock(&clk_debug_lock);
         hlist_for_each_entry(core, &clk_debug_list, debug_node)
@@ -2787,7 +2706,7 @@ static int __init clk_debug_init(void)
 }
 late_initcall(clk_debug_init);
 #else
-static inline int clk_debug_register(struct clk_core *core) { return 0; }
+static inline void clk_debug_register(struct clk_core *core) { }
 static inline void clk_debug_reparent(struct clk_core *core,
                                       struct clk_core *new_parent)
 {
@@ -3907,7 +3826,7 @@ int of_clk_parent_fill(struct device_node *np, const char **parents,
 EXPORT_SYMBOL_GPL(of_clk_parent_fill);
 
 struct clock_provider {
-        of_clk_init_cb_t clk_init_cb;
+        void (*clk_init_cb)(struct device_node *);
         struct device_node *np;
         struct list_head node;
 };
diff --git a/drivers/clk/davinci/pll-da830.c b/drivers/clk/davinci/pll-da830.c
index 929a3d3a9adb..0a0d06fb25fd 100644
--- a/drivers/clk/davinci/pll-da830.c
+++ b/drivers/clk/davinci/pll-da830.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/clkdev.h>
+#include <linux/clk/davinci.h>
 #include <linux/bitops.h>
 #include <linux/init.h>
 #include <linux/types.h>
@@ -36,11 +37,11 @@ SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
 SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV);
 SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
 
-int da830_pll_init(struct device *dev, void __iomem *base)
+int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
 {
         struct clk *clk;
 
-        davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base);
+        davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, cfgchip);
 
         clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
         clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0");
diff --git a/drivers/clk/davinci/pll-da850.c b/drivers/clk/davinci/pll-da850.c
index 2a038b7908cc..0f7198191ea2 100644
--- a/drivers/clk/davinci/pll-da850.c
+++ b/drivers/clk/davinci/pll-da850.c
@@ -7,10 +7,14 @@
 
 #include <linux/bitops.h>
 #include <linux/clk-provider.h>
+#include <linux/clk/davinci.h>
 #include <linux/clkdev.h>
+#include <linux/device.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/mfd/da8xx-cfgchip.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
 #include <linux/of.h>
 #include <linux/types.h>
 
@@ -81,11 +85,11 @@ static const struct davinci_pll_obsclk_info da850_pll0_obsclk_info = {
         .ocsrc_mask = GENMASK(4, 0),
 };
 
-int da850_pll0_init(struct device *dev, void __iomem *base)
+int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
 {
         struct clk *clk;
 
-        davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base);
+        davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip);
 
         clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base);
         clk_register_clkdev(clk, "pll0_sysclk1", "da850-psc0");
@@ -134,11 +138,22 @@ static const struct davinci_pll_sysclk_info *da850_pll0_sysclk_info[] = {
         NULL
 };
 
-int of_da850_pll0_init(struct device *dev, void __iomem *base)
+void of_da850_pll0_init(struct device_node *node)
 {
-        return of_davinci_pll_init(dev, &da850_pll0_info,
-                                   &da850_pll0_obsclk_info,
-                                   da850_pll0_sysclk_info, 7, base);
+        void __iomem *base;
+        struct regmap *cfgchip;
+
+        base = of_iomap(node, 0);
+        if (!base) {
+                pr_err("%s: ioremap failed\n", __func__);
+                return;
+        }
+
+        cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
+
+        of_davinci_pll_init(NULL, node, &da850_pll0_info,
+                            &da850_pll0_obsclk_info,
+                            da850_pll0_sysclk_info, 7, base, cfgchip);
 }
 
 static const struct davinci_pll_clk_info da850_pll1_info = {
@@ -179,11 +194,11 @@ static const struct davinci_pll_obsclk_info da850_pll1_obsclk_info = {
         .ocsrc_mask = GENMASK(4, 0),
 };
 
-int da850_pll1_init(struct device *dev, void __iomem *base)
+int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
 {
         struct clk *clk;
 
-        davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base);
+        davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base, cfgchip);
 
         davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
 
@@ -204,9 +219,9 @@ static const struct davinci_pll_sysclk_info *da850_pll1_sysclk_info[] = {
         NULL
 };
 
-int of_da850_pll1_init(struct device *dev, void __iomem *base)
+int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
 {
-        return of_davinci_pll_init(dev, &da850_pll1_info,
+        return of_davinci_pll_init(dev, dev->of_node, &da850_pll1_info,
                                    &da850_pll1_obsclk_info,
-                                   da850_pll1_sysclk_info, 3, base);
+                                   da850_pll1_sysclk_info, 3, base, cfgchip);
 }
diff --git a/drivers/clk/davinci/pll-dm355.c b/drivers/clk/davinci/pll-dm355.c
index 5345f8286c50..505aed80be9a 100644
--- a/drivers/clk/davinci/pll-dm355.c
+++ b/drivers/clk/davinci/pll-dm355.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/bitops.h>
+#include <linux/clk/davinci.h>
 #include <linux/clkdev.h>
 #include <linux/init.h>
 #include <linux/types.h>
@@ -22,16 +23,16 @@ static const struct davinci_pll_clk_info dm355_pll1_info = {
                  PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
 };
 
-SYSCLK(1, pll1_sysclk1, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
-SYSCLK(2, pll1_sysclk2, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
-SYSCLK(3, pll1_sysclk3, pll1, 5, SYSCLK_ALWAYS_ENABLED);
-SYSCLK(4, pll1_sysclk4, pll1, 5, SYSCLK_ALWAYS_ENABLED);
+SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
+SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
 
-int dm355_pll1_init(struct device *dev, void __iomem *base)
+int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
 {
         struct clk *clk;
 
-        davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base);
+        davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base, cfgchip);
 
         clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
         clk_register_clkdev(clk, "pll1_sysclk1", "dm355-psc");
@@ -62,17 +63,14 @@ static const struct davinci_pll_clk_info dm355_pll2_info = {
                  PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
 };
 
-SYSCLK(1, pll2_sysclk1, pll2, 5, SYSCLK_FIXED_DIV);
-SYSCLK(2, pll2_sysclk2, pll2, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
+SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
 
-int dm355_pll2_init(struct device *dev, void __iomem *base)
+int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
 {
-        davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base);
+        davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base, cfgchip);
 
         davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
 
-        davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
-
         davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);
 
         return 0;
diff --git a/drivers/clk/davinci/pll-dm365.c b/drivers/clk/davinci/pll-dm365.c
index 5f8d9f42d0f3..2d29712753a3 100644
--- a/drivers/clk/davinci/pll-dm365.c
+++ b/drivers/clk/davinci/pll-dm365.c
@@ -7,6 +7,7 @@
 
 #include <linux/bitops.h>
 #include <linux/clkdev.h>
+#include <linux/clk/davinci.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
@@ -56,11 +57,11 @@ static const struct davinci_pll_obsclk_info dm365_pll1_obsclk_info = {
         .ocsrc_mask = BIT(4),
 };
 
-int dm365_pll1_init(struct device *dev, void __iomem *base)
+int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
 {
         struct clk *clk;
 
-        davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base);
+        davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base, cfgchip);
 
         clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
         clk_register_clkdev(clk, "pll1_sysclk1", "dm365-psc");
@@ -119,11 +120,11 @@ static const struct davinci_pll_obsclk_info dm365_pll2_obsclk_info = {
         .ocsrc_mask = BIT(4),
 };
 
-int dm365_pll2_init(struct device *dev, void __iomem *base)
+int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
 {
         struct clk *clk;
 
-        davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base);
+        davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base, cfgchip);
 
         davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
 
diff --git a/drivers/clk/davinci/pll-dm644x.c b/drivers/clk/davinci/pll-dm644x.c
index 69bf785377cf..7650fadfaac8 100644
--- a/drivers/clk/davinci/pll-dm644x.c
+++ b/drivers/clk/davinci/pll-dm644x.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/bitops.h>
+#include <linux/clk/davinci.h>
 #include <linux/clkdev.h>
 #include <linux/init.h>
 #include <linux/types.h>
@@ -27,11 +28,11 @@ SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV);
 SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV);
 SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, SYSCLK_FIXED_DIV);
 
-int dm644x_pll1_init(struct device *dev, void __iomem *base)
+int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
 {
         struct clk *clk;
 
-        davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base);
+        davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base, cfgchip);
 
         clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
         clk_register_clkdev(clk, "pll1_sysclk1", "dm644x-psc");
@@ -66,9 +67,9 @@ static const struct davinci_pll_clk_info dm644x_pll2_info = {
 SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
 SYSCLK(2, pll2_sysclk2, pll2_pllen, 4, 0);
 
-int dm644x_pll2_init(struct device *dev, void __iomem *base)
+int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
 {
-        davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base);
+        davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base, cfgchip);
 
         davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
 
diff --git a/drivers/clk/davinci/pll-dm646x.c b/drivers/clk/davinci/pll-dm646x.c
index a61cc3256418..26982970df0e 100644
--- a/drivers/clk/davinci/pll-dm646x.c
+++ b/drivers/clk/davinci/pll-dm646x.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/clk/davinci.h>
 #include <linux/clkdev.h>
 #include <linux/init.h>
 #include <linux/types.h>
@@ -29,11 +30,11 @@ SYSCLK(6, pll1_sysclk6, pll1_pllen, 4, 0);
 SYSCLK(8, pll1_sysclk8, pll1_pllen, 4, 0);
 SYSCLK(9, pll1_sysclk9, pll1_pllen, 4, 0);
 
-int dm646x_pll1_init(struct device *dev, void __iomem *base)
+int dm646x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
 {
         struct clk *clk;
 
-        davinci_pll_clk_register(dev, &dm646x_pll1_info, "ref_clk", base);
+        davinci_pll_clk_register(dev, &dm646x_pll1_info, "ref_clk", base, cfgchip);
 
         clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
         clk_register_clkdev(clk, "pll1_sysclk1", "dm646x-psc");
@@ -72,11 +73,11 @@ static const struct davinci_pll_clk_info dm646x_pll2_info = {
         .flags = 0,
 };
 
-SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
+SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, SYSCLK_ALWAYS_ENABLED);
 
-int dm646x_pll2_init(struct device *dev, void __iomem *base)
+int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
 {
-        davinci_pll_clk_register(dev, &dm646x_pll2_info, "oscin", base);
+        davinci_pll_clk_register(dev, &dm646x_pll2_info, "oscin", base, cfgchip);
 
         davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
 
diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c
index 23a24c944f1d..1c99e992d638 100644
--- a/drivers/clk/davinci/pll.c
+++ b/drivers/clk/davinci/pll.c
@@ -11,6 +11,7 @@
 
 #include <linux/clk-provider.h>
 #include <linux/clk.h>
+#include <linux/clk/davinci.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/io.h>
@@ -190,7 +191,7 @@ static int davinci_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 }
 
 #ifdef CONFIG_DEBUG_FS
-static int davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry);
+static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry);
 #else
 #define davinci_pll_debug_init NULL
 #endif
@@ -223,6 +224,7 @@ static const struct clk_ops dm365_pll_ops = {
 
 /**
  * davinci_pll_div_register - common *DIV clock implementation
+ * @dev: The PLL platform device or NULL
  * @name: the clock name
  * @parent_name: the parent clock name
  * @reg: the *DIV register
@@ -240,17 +242,21 @@ static struct clk *davinci_pll_div_register(struct device *dev,
         const struct clk_ops *divider_ops = &clk_divider_ops;
         struct clk_gate *gate;
         struct clk_divider *divider;
+        struct clk *clk;
+        int ret;
 
-        gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
+        gate = kzalloc(sizeof(*gate), GFP_KERNEL);
         if (!gate)
                 return ERR_PTR(-ENOMEM);
 
         gate->reg = reg;
         gate->bit_idx = DIV_ENABLE_SHIFT;
 
-        divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL);
-        if (!divider)
-                return ERR_PTR(-ENOMEM);
+        divider = kzalloc(sizeof(*divider), GFP_KERNEL);
+        if (!divider) {
+                ret = -ENOMEM;
+                goto err_free_gate;
+        }
 
         divider->reg = reg;
         divider->shift = DIV_RATIO_SHIFT;
@@ -261,9 +267,22 @@ static struct clk *davinci_pll_div_register(struct device *dev,
                 divider_ops = &clk_divider_ro_ops;
         }
 
-        return clk_register_composite(dev, name, parent_names, num_parents,
-                                      NULL, NULL, &divider->hw, divider_ops,
-                                      &gate->hw, &clk_gate_ops, flags);
+        clk = clk_register_composite(dev, name, parent_names, num_parents,
+                                     NULL, NULL, &divider->hw, divider_ops,
+                                     &gate->hw, &clk_gate_ops, flags);
+        if (IS_ERR(clk)) {
+                ret = PTR_ERR(clk);
+                goto err_free_divider;
+        }
+
+        return clk;
+
+err_free_divider:
+        kfree(divider);
+err_free_gate:
+        kfree(gate);
+
+        return ERR_PTR(ret);
 }
 
 struct davinci_pllen_clk {
@@ -321,36 +340,17 @@ static int davinci_pllen_rate_change(struct notifier_block *nb,
         return NOTIFY_OK;
 }
 
-static struct davinci_pll_platform_data *davinci_pll_get_pdata(struct device *dev)
-{
-        struct davinci_pll_platform_data *pdata = dev_get_platdata(dev);
-
-        /*
-         * Platform data is optional, so allocate a new struct if one was not
-         * provided. For device tree, this will always be the case.
-         */
-        if (!pdata)
-                pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
-        if (!pdata)
-                return NULL;
-
-        /* for device tree, we need to fill in the struct */
-        if (dev->of_node)
-                pdata->cfgchip =
-                        syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
-
-        return pdata;
-}
-
 static struct notifier_block davinci_pllen_notifier = {
         .notifier_call = davinci_pllen_rate_change,
 };
 
 /**
  * davinci_pll_clk_register - Register a PLL clock
+ * @dev: The PLL platform device or NULL
  * @info: The device-specific clock info
  * @parent_name: The parent clock name
  * @base: The PLL's memory region
+ * @cfgchip: CFGCHIP syscon regmap for info->unlock_reg or NULL
  *
  * This creates a series of clocks that represent the PLL.
  *
@@ -366,9 +366,9 @@ static struct notifier_block davinci_pllen_notifier = {
 struct clk *davinci_pll_clk_register(struct device *dev,
                                      const struct davinci_pll_clk_info *info,
                                      const char *parent_name,
-                                     void __iomem *base)
+                                     void __iomem *base,
+                                     struct regmap *cfgchip)
 {
-        struct davinci_pll_platform_data *pdata;
         char prediv_name[MAX_NAME_SIZE];
         char pllout_name[MAX_NAME_SIZE];
         char postdiv_name[MAX_NAME_SIZE];
@@ -376,11 +376,12 @@ struct clk *davinci_pll_clk_register(struct device *dev,
         struct clk_init_data init;
         struct davinci_pll_clk *pllout;
         struct davinci_pllen_clk *pllen;
-        struct clk *pllout_clk, *clk;
-
-        pdata = davinci_pll_get_pdata(dev);
-        if (!pdata)
-                return ERR_PTR(-ENOMEM);
+        struct clk *oscin_clk = NULL;
+        struct clk *prediv_clk = NULL;
+        struct clk *pllout_clk;
+        struct clk *postdiv_clk = NULL;
+        struct clk *pllen_clk;
+        int ret;
 
         if (info->flags & PLL_HAS_CLKMODE) {
                 /*
@@ -392,10 +393,10 @@ struct clk *davinci_pll_clk_register(struct device *dev,
                  * a number of different things. In this driver we use it to
                  * mean the signal after the PLLCTL[CLKMODE] switch.
                  */
-                clk = clk_register_fixed_factor(dev, OSCIN_CLK_NAME,
-                                                parent_name, 0, 1, 1);
-                if (IS_ERR(clk))
-                        return clk;
+                oscin_clk = clk_register_fixed_factor(dev, OSCIN_CLK_NAME,
+                                                      parent_name, 0, 1, 1);
+                if (IS_ERR(oscin_clk))
+                        return oscin_clk;
 
                 parent_name = OSCIN_CLK_NAME;
         }
@@ -411,30 +412,34 @@ struct clk *davinci_pll_clk_register(struct device *dev,
 
                 /* Some? DM355 chips don't correctly report the PREDIV value */
                 if (info->flags & PLL_PREDIV_FIXED8)
-                        clk = clk_register_fixed_factor(dev, prediv_name,
-                                                parent_name, flags, 1, 8);
+                        prediv_clk = clk_register_fixed_factor(dev, prediv_name,
+                                                        parent_name, flags, 1, 8);
                 else
-                        clk = davinci_pll_div_register(dev, prediv_name,
+                        prediv_clk = davinci_pll_div_register(dev, prediv_name,
                                 parent_name, base + PREDIV, fixed, flags);
-                if (IS_ERR(clk))
-                        return clk;
+                if (IS_ERR(prediv_clk)) {
+                        ret = PTR_ERR(prediv_clk);
+                        goto err_unregister_oscin;
+                }
 
                 parent_name = prediv_name;
         }
 
         /* Unlock writing to PLL registers */
         if (info->unlock_reg) {
-                if (IS_ERR_OR_NULL(pdata->cfgchip))
+                if (IS_ERR_OR_NULL(cfgchip))
                         dev_warn(dev, "Failed to get CFGCHIP (%ld)\n",
-                                 PTR_ERR(pdata->cfgchip));
+                                 PTR_ERR(cfgchip));
                 else
-                        regmap_write_bits(pdata->cfgchip, info->unlock_reg,
+                        regmap_write_bits(cfgchip, info->unlock_reg,
                                           info->unlock_mask, 0);
         }
 
-        pllout = devm_kzalloc(dev, sizeof(*pllout), GFP_KERNEL);
-        if (!pllout)
-                return ERR_PTR(-ENOMEM);
+        pllout = kzalloc(sizeof(*pllout), GFP_KERNEL);
+        if (!pllout) {
+                ret = -ENOMEM;
+                goto err_unregister_prediv;
+        }
 
         snprintf(pllout_name, MAX_NAME_SIZE, "%s_pllout", info->name);
 
@@ -456,9 +461,11 @@ struct clk *davinci_pll_clk_register(struct device *dev,
         pllout->pllm_min = info->pllm_min;
         pllout->pllm_max = info->pllm_max;
 
-        pllout_clk = devm_clk_register(dev, &pllout->hw);
-        if (IS_ERR(pllout_clk))
-                return pllout_clk;
+        pllout_clk = clk_register(dev, &pllout->hw);
+        if (IS_ERR(pllout_clk)) {
+                ret = PTR_ERR(pllout_clk);
+                goto err_free_pllout;
+        }
 
         clk_hw_set_rate_range(&pllout->hw, info->pllout_min_rate,
                               info->pllout_max_rate);
@@ -474,17 +481,21 @@ struct clk *davinci_pll_clk_register(struct device *dev,
                 if (info->flags & PLL_POSTDIV_ALWAYS_ENABLED)
                         flags |= CLK_IS_CRITICAL;
 
-                clk = davinci_pll_div_register(dev, postdiv_name, parent_name,
-                                               base + POSTDIV, fixed, flags);
-                if (IS_ERR(clk))
-                        return clk;
+                postdiv_clk = davinci_pll_div_register(dev, postdiv_name,
+                                parent_name, base + POSTDIV, fixed, flags);
+                if (IS_ERR(postdiv_clk)) {
+                        ret = PTR_ERR(postdiv_clk);
+                        goto err_unregister_pllout;
+                }
 
                 parent_name = postdiv_name;
         }
 
-        pllen = devm_kzalloc(dev, sizeof(*pllout), GFP_KERNEL);
-        if (!pllen)
-                return ERR_PTR(-ENOMEM);
+        pllen = kzalloc(sizeof(*pllout), GFP_KERNEL);
+        if (!pllen) {
+                ret = -ENOMEM;
+                goto err_unregister_postdiv;
+        }
 
         snprintf(pllen_name, MAX_NAME_SIZE, "%s_pllen", info->name);
 
@@ -497,17 +508,35 @@ struct clk *davinci_pll_clk_register(struct device *dev,
         pllen->hw.init = &init;
         pllen->base = base;
 
-        clk = devm_clk_register(dev, &pllen->hw);
-        if (IS_ERR(clk))
-                return clk;
+        pllen_clk = clk_register(dev, &pllen->hw);
+        if (IS_ERR(pllen_clk)) {
+                ret = PTR_ERR(pllen_clk);
+                goto err_free_pllen;
+        }
 
-        clk_notifier_register(clk, &davinci_pllen_notifier);
+        clk_notifier_register(pllen_clk, &davinci_pllen_notifier);
 
         return pllout_clk;
+
+err_free_pllen:
+        kfree(pllen);
+err_unregister_postdiv:
+        clk_unregister(postdiv_clk);
+err_unregister_pllout:
+        clk_unregister(pllout_clk);
+err_free_pllout:
+        kfree(pllout);
+err_unregister_prediv:
+        clk_unregister(prediv_clk);
+err_unregister_oscin:
+        clk_unregister(oscin_clk);
+
+        return ERR_PTR(ret);
 }
 
 /**
  * davinci_pll_auxclk_register - Register bypass clock (AUXCLK)
+ * @dev: The PLL platform device or NULL
  * @name: The clock name
  * @base: The PLL memory region
  */
@@ -521,6 +550,7 @@ struct clk *davinci_pll_auxclk_register(struct device *dev,
 
 /**
  * davinci_pll_sysclkbp_clk_register - Register bypass divider clock (SYSCLKBP)
+ * @dev: The PLL platform device or NULL
  * @name: The clock name
  * @base: The PLL memory region
  */
@@ -535,6 +565,7 @@ struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev,
 
 /**
  * davinci_pll_obsclk_register - Register oscillator divider clock (OBSCLK)
+ * @dev: The PLL platform device or NULL
  * @info: The clock info
  * @base: The PLL memory region
  */
@@ -546,9 +577,11 @@ davinci_pll_obsclk_register(struct device *dev,
         struct clk_mux *mux;
         struct clk_gate *gate;
         struct clk_divider *divider;
+        struct clk *clk;
         u32 oscdiv;
+        int ret;
 
-        mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+        mux = kzalloc(sizeof(*mux), GFP_KERNEL);
         if (!mux)
                 return ERR_PTR(-ENOMEM);
 
@@ -556,16 +589,20 @@ davinci_pll_obsclk_register(struct device *dev,
         mux->table = info->table;
         mux->mask = info->ocsrc_mask;
 
-        gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
-        if (!gate)
-                return ERR_PTR(-ENOMEM);
+        gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+        if (!gate) {
+                ret = -ENOMEM;
+                goto err_free_mux;
+        }
 
         gate->reg = base + CKEN;
         gate->bit_idx = CKEN_OBSCLK_SHIFT;
 
-        divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL);
-        if (!divider)
-                return ERR_PTR(-ENOMEM);
+        divider = kzalloc(sizeof(*divider), GFP_KERNEL);
+        if (!divider) {
+                ret = -ENOMEM;
+                goto err_free_gate;
+        }
 
         divider->reg = base + OSCDIV;
         divider->shift = DIV_RATIO_SHIFT;
@@ -576,11 +613,27 @@ davinci_pll_obsclk_register(struct device *dev,
         oscdiv |= BIT(DIV_ENABLE_SHIFT);
         writel(oscdiv, base + OSCDIV);
 
-        return clk_register_composite(dev, info->name, info->parent_names,
-                                      info->num_parents,
-                                      &mux->hw, &clk_mux_ops,
-                                      &divider->hw, &clk_divider_ops,
-                                      &gate->hw, &clk_gate_ops, 0);
+        clk = clk_register_composite(dev, info->name, info->parent_names,
+                                     info->num_parents,
+                                     &mux->hw, &clk_mux_ops,
+                                     &divider->hw, &clk_divider_ops,
+                                     &gate->hw, &clk_gate_ops, 0);
+
+        if (IS_ERR(clk)) {
+                ret = PTR_ERR(clk);
+                goto err_free_divider;
+        }
+
+        return clk;
+
+err_free_divider:
+        kfree(divider);
+err_free_gate:
+        kfree(gate);
+err_free_mux:
+        kfree(mux);
+
+        return ERR_PTR(ret);
 }
 
 /* The PLL SYSCLKn clocks have a mechanism for synchronizing rate changes. */
@@ -616,6 +669,7 @@ static struct notifier_block davinci_pll_sysclk_notifier = {
 
 /**
  * davinci_pll_sysclk_register - Register divider clocks (SYSCLKn)
+ * @dev: The PLL platform device or NULL
  * @info: The clock info
  * @base: The PLL memory region
  */
@@ -630,6 +684,7 @@ davinci_pll_sysclk_register(struct device *dev,
         struct clk *clk;
         u32 reg;
         u32 flags = 0;
+        int ret;
 
         /* PLLDIVn registers are not entirely consecutive */
         if (info->id < 4)
@@ -637,16 +692,18 @@ davinci_pll_sysclk_register(struct device *dev,
         else
                 reg = PLLDIV4 + 4 * (info->id - 4);
 
-        gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
+        gate = kzalloc(sizeof(*gate), GFP_KERNEL);
         if (!gate)
                 return ERR_PTR(-ENOMEM);
 
         gate->reg = base + reg;
         gate->bit_idx = DIV_ENABLE_SHIFT;
 
-        divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL);
-        if (!divider)
-                return ERR_PTR(-ENOMEM);
+        divider = kzalloc(sizeof(*divider), GFP_KERNEL);
+        if (!divider) {
+                ret = -ENOMEM;
+                goto err_free_gate;
+        }
 
         divider->reg = base + reg;
         divider->shift = DIV_RATIO_SHIFT;
@@ -668,22 +725,31 @@ davinci_pll_sysclk_register(struct device *dev,
         clk = clk_register_composite(dev, info->name, &info->parent_name, 1,
                                      NULL, NULL, &divider->hw, divider_ops,
                                      &gate->hw, &clk_gate_ops, flags);
-        if (IS_ERR(clk))
-                return clk;
+        if (IS_ERR(clk)) {
+                ret = PTR_ERR(clk);
+                goto err_free_divider;
+        }
 
         clk_notifier_register(clk, &davinci_pll_sysclk_notifier);
 
         return clk;
+
+err_free_divider:
+        kfree(divider);
+err_free_gate:
+        kfree(gate);
+
+        return ERR_PTR(ret);
 }
 
-int of_davinci_pll_init(struct device *dev,
+int of_davinci_pll_init(struct device *dev, struct device_node *node,
                         const struct davinci_pll_clk_info *info,
                         const struct davinci_pll_obsclk_info *obsclk_info,
                         const struct davinci_pll_sysclk_info **div_info,
                         u8 max_sysclk_id,
-                        void __iomem *base)
+                        void __iomem *base,
+                        struct regmap *cfgchip)
 {
-        struct device_node *node = dev->of_node;
         struct device_node *child;
         const char *parent_name;
         struct clk *clk;
@@ -693,7 +759,7 @@ int of_davinci_pll_init(struct device *dev,
         else
                 parent_name = OSCIN_CLK_NAME;
 
-        clk = davinci_pll_clk_register(dev, info, parent_name, base);
+        clk = davinci_pll_clk_register(dev, info, parent_name, base, cfgchip);
         if (IS_ERR(clk)) {
                 dev_err(dev, "failed to register %s\n", info->name);
                 return PTR_ERR(clk);
@@ -711,13 +777,15 @@ int of_davinci_pll_init(struct device *dev,
                 int n_clks =  max_sysclk_id + 1;
                 int i;
 
-                clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
+                clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
                 if (!clk_data)
                         return -ENOMEM;
 
-                clks = devm_kmalloc_array(dev, n_clks, sizeof(*clks), GFP_KERNEL);
-                if (!clks)
+                clks = kmalloc_array(n_clks, sizeof(*clks), GFP_KERNEL);
+                if (!clks) {
+                        kfree(clk_data);
                         return -ENOMEM;
+                }
 
                 clk_data->clks = clks;
                 clk_data->clk_num = n_clks;
@@ -770,32 +838,73 @@ int of_davinci_pll_init(struct device *dev,
         return 0;
 }
 
+static struct davinci_pll_platform_data *davinci_pll_get_pdata(struct device *dev)
+{
+        struct davinci_pll_platform_data *pdata = dev_get_platdata(dev);
+
+        /*
+         * Platform data is optional, so allocate a new struct if one was not
+         * provided. For device tree, this will always be the case.
+         */
+        if (!pdata)
+                pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+        if (!pdata)
+                return NULL;
+
+        /* for device tree, we need to fill in the struct */
+        if (dev->of_node)
+                pdata->cfgchip =
+                        syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
+
+        return pdata;
+}
+
+/* needed in early boot for clocksource/clockevent */
+#ifdef CONFIG_ARCH_DAVINCI_DA850
+CLK_OF_DECLARE(da850_pll0, "ti,da850-pll0", of_da850_pll0_init);
+#endif
+
 static const struct of_device_id davinci_pll_of_match[] = {
-        { .compatible = "ti,da850-pll0", .data = of_da850_pll0_init },
+#ifdef CONFIG_ARCH_DAVINCI_DA850
         { .compatible = "ti,da850-pll1", .data = of_da850_pll1_init },
+#endif
         { }
 };
 
 static const struct platform_device_id davinci_pll_id_table[] = {
+#ifdef CONFIG_ARCH_DAVINCI_DA830
         { .name = "da830-pll",   .driver_data = (kernel_ulong_t)da830_pll_init   },
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DA850
         { .name = "da850-pll0",  .driver_data = (kernel_ulong_t)da850_pll0_init  },
         { .name = "da850-pll1",  .driver_data = (kernel_ulong_t)da850_pll1_init  },
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM355
         { .name = "dm355-pll1",  .driver_data = (kernel_ulong_t)dm355_pll1_init  },
         { .name = "dm355-pll2",  .driver_data = (kernel_ulong_t)dm355_pll2_init  },
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM365
         { .name = "dm365-pll1",  .driver_data = (kernel_ulong_t)dm365_pll1_init  },
         { .name = "dm365-pll2",  .driver_data = (kernel_ulong_t)dm365_pll2_init  },
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM644x
         { .name = "dm644x-pll1", .driver_data = (kernel_ulong_t)dm644x_pll1_init },
         { .name = "dm644x-pll2", .driver_data = (kernel_ulong_t)dm644x_pll2_init },
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM646x
         { .name = "dm646x-pll1", .driver_data = (kernel_ulong_t)dm646x_pll1_init },
         { .name = "dm646x-pll2", .driver_data = (kernel_ulong_t)dm646x_pll2_init },
+#endif
         { }
 };
 
-typedef int (*davinci_pll_init)(struct device *dev, void __iomem *base);
+typedef int (*davinci_pll_init)(struct device *dev, void __iomem *base,
+                                struct regmap *cfgchip);
 
 static int davinci_pll_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
+        struct davinci_pll_platform_data *pdata;
         const struct of_device_id *of_id;
         davinci_pll_init pll_init = NULL;
         struct resource *res;
@@ -812,12 +921,18 @@ static int davinci_pll_probe(struct platform_device *pdev)
                 return -EINVAL;
         }
 
+        pdata = davinci_pll_get_pdata(dev);
+        if (!pdata) {
+                dev_err(dev, "missing platform data\n");
+                return -EINVAL;
+        }
+
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         base = devm_ioremap_resource(dev, res);
         if (IS_ERR(base))
                 return PTR_ERR(base);
 
-        return pll_init(dev, base);
+        return pll_init(dev, base, pdata->cfgchip);
 }
 
 static struct platform_driver davinci_pll_driver = {
@@ -874,26 +989,19 @@ static const struct debugfs_reg32 davinci_pll_regs[] = {
         DEBUG_REG(PLLDIV9),
 };
 
-static int davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
+static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
 {
         struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
         struct debugfs_regset32 *regset;
-        struct dentry *d;
 
         regset = kzalloc(sizeof(*regset), GFP_KERNEL);
         if (!regset)
-                return -ENOMEM;
+                return;
 
         regset->regs = davinci_pll_regs;
         regset->nregs = ARRAY_SIZE(davinci_pll_regs);
         regset->base = pll->base;
 
-        d = debugfs_create_regset32("registers", 0400, dentry, regset);
-        if (IS_ERR(d)) {
-                kfree(regset);
-                return PTR_ERR(d);
-        }
-
-        return 0;
+        debugfs_create_regset32("registers", 0400, dentry, regset);
 }
 #endif
diff --git a/drivers/clk/davinci/pll.h b/drivers/clk/davinci/pll.h
index b1b6fb23f972..7cc354dd29e2 100644
--- a/drivers/clk/davinci/pll.h
+++ b/drivers/clk/davinci/pll.h
@@ -11,6 +11,7 @@
 #include <linux/bitops.h>
 #include <linux/clk-provider.h>
 #include <linux/of.h>
+#include <linux/regmap.h>
 #include <linux/types.h>
 
 #define PLL_HAS_CLKMODE                 BIT(0) /* PLL has PLLCTL[CLKMODE] */
@@ -94,7 +95,8 @@ struct davinci_pll_obsclk_info {
 struct clk *davinci_pll_clk_register(struct device *dev,
                                      const struct davinci_pll_clk_info *info,
                                      const char *parent_name,
-                                     void __iomem *base);
+                                     void __iomem *base,
+                                     struct regmap *cfgchip);
 struct clk *davinci_pll_auxclk_register(struct device *dev,
                                         const char *name,
                                         void __iomem *base);
@@ -110,32 +112,29 @@ davinci_pll_sysclk_register(struct device *dev,
                             const struct davinci_pll_sysclk_info *info,
                             void __iomem *base);
 
-int of_davinci_pll_init(struct device *dev,
+int of_davinci_pll_init(struct device *dev, struct device_node *node,
                         const struct davinci_pll_clk_info *info,
                         const struct davinci_pll_obsclk_info *obsclk_info,
                         const struct davinci_pll_sysclk_info **div_info,
                         u8 max_sysclk_id,
-                        void __iomem *base);
+                        void __iomem *base,
+                        struct regmap *cfgchip);
 
 /* Platform-specific callbacks */
 
-int da830_pll_init(struct device *dev, void __iomem *base);
-
-int da850_pll0_init(struct device *dev, void __iomem *base);
-int da850_pll1_init(struct device *dev, void __iomem *base);
-int of_da850_pll0_init(struct device *dev, void __iomem *base);
-int of_da850_pll1_init(struct device *dev, void __iomem *base);
-
-int dm355_pll1_init(struct device *dev, void __iomem *base);
-int dm355_pll2_init(struct device *dev, void __iomem *base);
-
-int dm365_pll1_init(struct device *dev, void __iomem *base);
-int dm365_pll2_init(struct device *dev, void __iomem *base);
-
-int dm644x_pll1_init(struct device *dev, void __iomem *base);
-int dm644x_pll2_init(struct device *dev, void __iomem *base);
-
-int dm646x_pll1_init(struct device *dev, void __iomem *base);
-int dm646x_pll2_init(struct device *dev, void __iomem *base);
+#ifdef CONFIG_ARCH_DAVINCI_DA850
+int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
+void of_da850_pll0_init(struct device_node *node);
+int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM355
+int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM644x
+int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM646x
+int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
+#endif
 
 #endif /* __CLK_DAVINCI_PLL_H___ */
diff --git a/drivers/clk/davinci/psc-da830.c b/drivers/clk/davinci/psc-da830.c
index f61abf5632ff..081b039fcb02 100644
--- a/drivers/clk/davinci/psc-da830.c
+++ b/drivers/clk/davinci/psc-da830.c
@@ -55,7 +55,8 @@ const struct davinci_psc_init_data da830_psc0_init_data = {
         .psc_init               = &da830_psc0_init,
 };
 
-LPSC_CLKDEV2(usb0_clkdev,       NULL,   "musb-da8xx",
+LPSC_CLKDEV3(usb0_clkdev,       "fck",  "da830-usb-phy-clks",
+                                NULL,   "musb-da8xx",
                                 NULL,   "cppi41-dmaengine");
 LPSC_CLKDEV1(usb1_clkdev,       NULL,   "ohci-da8xx");
 /* REVISIT: gpio-davinci.c should be modified to drop con_id */
diff --git a/drivers/clk/davinci/psc-dm355.c b/drivers/clk/davinci/psc-dm355.c
index 6995ecea2677..ddd250107c4e 100644
--- a/drivers/clk/davinci/psc-dm355.c
+++ b/drivers/clk/davinci/psc-dm355.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/clk/davinci.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/init.h>
@@ -41,14 +42,14 @@ static const struct davinci_lpsc_clk_info dm355_psc_info[] = {
         LPSC(5,  0, timer3,      pll1_auxclk,  NULL,               0),
         LPSC(6,  0, spi1,        pll1_sysclk2, spi1_clkdev,        0),
         LPSC(7,  0, mmcsd1,      pll1_sysclk2, mmcsd1_clkdev,      0),
-        LPSC(8,  0, asp1,        pll1_sysclk2, NULL,               0),
+        LPSC(8,  0, asp1,        pll1_sysclk2, mcbsp1_clkdev,      0),
         LPSC(9,  0, usb,         pll1_sysclk2, usb_clkdev,         0),
         LPSC(10, 0, pwm3,        pll1_auxclk,  NULL,               0),
         LPSC(11, 0, spi2,        pll1_sysclk2, spi2_clkdev,        0),
         LPSC(12, 0, rto,         pll1_auxclk,  NULL,               0),
         LPSC(14, 0, aemif,       pll1_sysclk2, aemif_clkdev,       0),
         LPSC(15, 0, mmcsd0,      pll1_sysclk2, mmcsd0_clkdev,      0),
-        LPSC(17, 0, asp0,        pll1_sysclk2, NULL,               0),
+        LPSC(17, 0, asp0,        pll1_sysclk2, mcbsp0_clkdev,      0),
         LPSC(18, 0, i2c,         pll1_auxclk,  i2c_clkdev,         0),
         LPSC(19, 0, uart0,       pll1_auxclk,  uart0_clkdev,       0),
         LPSC(20, 0, uart1,       pll1_auxclk,  uart1_clkdev,       0),
@@ -68,7 +69,7 @@ static const struct davinci_lpsc_clk_info dm355_psc_info[] = {
         { }
 };
 
-static int dm355_psc_init(struct device *dev, void __iomem *base)
+int dm355_psc_init(struct device *dev, void __iomem *base)
 {
         return davinci_psc_register_clocks(dev, dm355_psc_info, 42, base);
 }
diff --git a/drivers/clk/davinci/psc-dm365.c b/drivers/clk/davinci/psc-dm365.c
index 3ad915f37376..8c73086cc676 100644
--- a/drivers/clk/davinci/psc-dm365.c
+++ b/drivers/clk/davinci/psc-dm365.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/clk/davinci.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/init.h>
@@ -65,15 +66,28 @@ static const struct davinci_lpsc_clk_info dm365_psc_info[] = {
         LPSC(31, 0, arm,         pll2_sysclk2, NULL,               LPSC_ALWAYS_ENABLED),
         LPSC(38, 0, spi3,        pll1_sysclk4, spi3_clkdev,        0),
         LPSC(39, 0, spi4,        pll1_auxclk,  spi4_clkdev,        0),
-        LPSC(40, 0, emac,        pll2_sysclk4, emac_clkdev,        0),
-        LPSC(44, 1, voice_codec, pll1_sysclk3, voice_codec_clkdev, 0),
-        LPSC(46, 1, vpss_dac,    pll1_sysclk3, vpss_dac_clkdev,    0),
+        LPSC(40, 0, emac,        pll1_sysclk4, emac_clkdev,        0),
+        /*
+         * The TRM (ARM Subsystem User's Guide) shows two clocks input into
+         * voice codec module (PLL2 SYSCLK4 with a DIV2 and PLL1 SYSCLK4). Its
+         * not fully clear from documentation which clock should be considered
+         * as parent for PSC. The clock chosen here is to maintain
+         * compatibility with existing code in arch/arm/mach-davinci/dm365.c
+         */
+        LPSC(44, 0, voice_codec, pll2_sysclk4, voice_codec_clkdev, 0),
+        /*
+         * Its not fully clear from TRM (ARM Subsystem User's Guide) as to what
+         * the parent of VPSS DAC LPSC should actually be. PLL1 SYSCLK3 feeds
+         * into HDVICP and MJCP. The clock chosen here is to remain compatible
+         * with code existing in arch/arm/mach-davinci/dm365.c
+         */
+        LPSC(46, 0, vpss_dac,    pll1_sysclk3, vpss_dac_clkdev,    0),
         LPSC(47, 0, vpss_master, pll1_sysclk5, vpss_master_clkdev, 0),
         LPSC(50, 0, mjcp,        pll1_sysclk3, NULL,               0),
         { }
 };
 
-static int dm365_psc_init(struct device *dev, void __iomem *base)
+int dm365_psc_init(struct device *dev, void __iomem *base)
 {
         return davinci_psc_register_clocks(dev, dm365_psc_info, 52, base);
 }
diff --git a/drivers/clk/davinci/psc-dm644x.c b/drivers/clk/davinci/psc-dm644x.c
index c22367baa46f..fc0230e3a3d6 100644
--- a/drivers/clk/davinci/psc-dm644x.c
+++ b/drivers/clk/davinci/psc-dm644x.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/clk/davinci.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/init.h>
@@ -63,7 +64,7 @@ static const struct davinci_lpsc_clk_info dm644x_psc_info[] = {
         { }
 };
 
-static int dm644x_psc_init(struct device *dev, void __iomem *base)
+int dm644x_psc_init(struct device *dev, void __iomem *base)
 {
         return davinci_psc_register_clocks(dev, dm644x_psc_info, 41, base);
 }
diff --git a/drivers/clk/davinci/psc-dm646x.c b/drivers/clk/davinci/psc-dm646x.c
index 468ef86ea40b..c3f82ed70a80 100644
--- a/drivers/clk/davinci/psc-dm646x.c
+++ b/drivers/clk/davinci/psc-dm646x.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/clk/davinci.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/init.h>
@@ -58,7 +59,7 @@ static const struct davinci_lpsc_clk_info dm646x_psc_info[] = {
         { }
 };
 
-static int dm646x_psc_init(struct device *dev, void __iomem *base)
+int dm646x_psc_init(struct device *dev, void __iomem *base)
 {
         return davinci_psc_register_clocks(dev, dm646x_psc_info, 46, base);
 }
diff --git a/drivers/clk/davinci/psc.c b/drivers/clk/davinci/psc.c
index ce170e600f09..fffbed5e263b 100644
--- a/drivers/clk/davinci/psc.c
+++ b/drivers/clk/davinci/psc.c
@@ -15,6 +15,7 @@
 
 #include <linux/clk-provider.h>
 #include <linux/clk.h>
+#include <linux/clk/davinci.h>
 #include <linux/clkdev.h>
 #include <linux/err.h>
 #include <linux/of_address.h>
@@ -63,7 +64,7 @@ struct davinci_psc_data {
 
 /**
  * struct davinci_lpsc_clk - LPSC clock structure
- * @dev: the device that provides this LPSC
+ * @dev: the device that provides this LPSC or NULL
  * @hw: clk_hw for the LPSC
  * @pm_domain: power domain for the LPSC
  * @genpd_clk: clock reference owned by @pm_domain
@@ -221,6 +222,7 @@ static void davinci_psc_genpd_detach_dev(struct generic_pm_domain *pm_domain,
 
 /**
  * davinci_lpsc_clk_register - register LPSC clock
+ * @dev: the clocks's device or NULL
  * @name: name of this clock
  * @parent_name: name of clock's parent
  * @regmap: PSC MMIO region
@@ -238,7 +240,7 @@ davinci_lpsc_clk_register(struct device *dev, const char *name,
         int ret;
         bool is_on;
 
-        lpsc = devm_kzalloc(dev, sizeof(*lpsc), GFP_KERNEL);
+        lpsc = kzalloc(sizeof(*lpsc), GFP_KERNEL);
         if (!lpsc)
                 return ERR_PTR(-ENOMEM);
 
@@ -261,9 +263,15 @@ davinci_lpsc_clk_register(struct device *dev, const char *name,
         lpsc->pd = pd;
         lpsc->flags = flags;
 
-        ret = devm_clk_hw_register(dev, &lpsc->hw);
-        if (ret < 0)
+        ret = clk_hw_register(dev, &lpsc->hw);
+        if (ret < 0) {
+                kfree(lpsc);
                 return ERR_PTR(ret);
+        }
+
+        /* for now, genpd is only registered when using device-tree */
+        if (!dev || !dev->of_node)
+                return lpsc;
 
         /* genpd attach needs a way to look up this clock */
         ret = clk_hw_register_clkdev(&lpsc->hw, name, best_dev_name(dev));
@@ -378,13 +386,15 @@ __davinci_psc_register_clocks(struct device *dev,
         struct regmap *regmap;
         int i, ret;
 
-        psc = devm_kzalloc(dev, sizeof(*psc), GFP_KERNEL);
+        psc = kzalloc(sizeof(*psc), GFP_KERNEL);
         if (!psc)
                 return ERR_PTR(-ENOMEM);
 
-        clks = devm_kmalloc_array(dev, num_clks, sizeof(*clks), GFP_KERNEL);
-        if (!clks)
-                return ERR_PTR(-ENOMEM);
+        clks = kmalloc_array(num_clks, sizeof(*clks), GFP_KERNEL);
+        if (!clks) {
+                ret = -ENOMEM;
+                goto err_free_psc;
+        }
 
         psc->clk_data.clks = clks;
         psc->clk_data.clk_num = num_clks;
@@ -396,16 +406,20 @@ __davinci_psc_register_clocks(struct device *dev,
         for (i = 0; i < num_clks; i++)
                 clks[i] = ERR_PTR(-ENOENT);
 
-        pm_domains = devm_kcalloc(dev, num_clks, sizeof(*pm_domains), GFP_KERNEL);
-        if (!pm_domains)
-                return ERR_PTR(-ENOMEM);
+        pm_domains = kcalloc(num_clks, sizeof(*pm_domains), GFP_KERNEL);
+        if (!pm_domains) {
+                ret = -ENOMEM;
+                goto err_free_clks;
+        }
 
         psc->pm_data.domains = pm_domains;
         psc->pm_data.num_domains = num_clks;
 
-        regmap = devm_regmap_init_mmio(dev, base, &davinci_psc_regmap_config);
-        if (IS_ERR(regmap))
-                return ERR_CAST(regmap);
+        regmap = regmap_init_mmio(dev, base, &davinci_psc_regmap_config);
+        if (IS_ERR(regmap)) {
+                ret = PTR_ERR(regmap);
+                goto err_free_pm_domains;
+        }
 
         for (; info->name; info++) {
                 struct davinci_lpsc_clk *lpsc;
@@ -423,6 +437,13 @@ __davinci_psc_register_clocks(struct device *dev,
                 pm_domains[info->md] = &lpsc->pm_domain;
         }
 
+        /*
+         * for now, a reset controller is only registered when there is a device
+         * to associate it with.
+         */
+        if (!dev)
+                return psc;
+
         psc->rcdev.ops = &davinci_psc_reset_ops;
         psc->rcdev.owner = THIS_MODULE;
         psc->rcdev.dev = dev;
@@ -436,6 +457,15 @@ __davinci_psc_register_clocks(struct device *dev,
                 dev_warn(dev, "Failed to register reset controller (%d)\n", ret);
 
         return psc;
+
+err_free_pm_domains:
+        kfree(pm_domains);
+err_free_clks:
+        kfree(clks);
+err_free_psc:
+        kfree(psc);
+
+        return ERR_PTR(ret);
 }
 
 int davinci_psc_register_clocks(struct device *dev,
@@ -483,20 +513,34 @@ int of_davinci_psc_clk_init(struct device *dev,
 }
 
 static const struct of_device_id davinci_psc_of_match[] = {
+#ifdef CONFIG_ARCH_DAVINCI_DA850
         { .compatible = "ti,da850-psc0", .data = &of_da850_psc0_init_data },
         { .compatible = "ti,da850-psc1", .data = &of_da850_psc1_init_data },
+#endif
         { }
 };
 
 static const struct platform_device_id davinci_psc_id_table[] = {
+#ifdef CONFIG_ARCH_DAVINCI_DA830
         { .name = "da830-psc0", .driver_data = (kernel_ulong_t)&da830_psc0_init_data },
         { .name = "da830-psc1", .driver_data = (kernel_ulong_t)&da830_psc1_init_data },
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DA850
         { .name = "da850-psc0", .driver_data = (kernel_ulong_t)&da850_psc0_init_data },
         { .name = "da850-psc1", .driver_data = (kernel_ulong_t)&da850_psc1_init_data },
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM355
         { .name = "dm355-psc",  .driver_data = (kernel_ulong_t)&dm355_psc_init_data  },
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM365
         { .name = "dm365-psc",  .driver_data = (kernel_ulong_t)&dm365_psc_init_data  },
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM644x
         { .name = "dm644x-psc", .driver_data = (kernel_ulong_t)&dm644x_psc_init_data },
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM646x
         { .name = "dm646x-psc", .driver_data = (kernel_ulong_t)&dm646x_psc_init_data },
+#endif
         { }
 };
 
diff --git a/drivers/clk/davinci/psc.h b/drivers/clk/davinci/psc.h
index c2a7df6413fe..6a42529d31a9 100644
--- a/drivers/clk/davinci/psc.h
+++ b/drivers/clk/davinci/psc.h
@@ -94,15 +94,27 @@ struct davinci_psc_init_data {
         int (*psc_init)(struct device *dev, void __iomem *base);
 };
 
+#ifdef CONFIG_ARCH_DAVINCI_DA830
 extern const struct davinci_psc_init_data da830_psc0_init_data;
 extern const struct davinci_psc_init_data da830_psc1_init_data;
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DA850
 extern const struct davinci_psc_init_data da850_psc0_init_data;
 extern const struct davinci_psc_init_data da850_psc1_init_data;
 extern const struct davinci_psc_init_data of_da850_psc0_init_data;
 extern const struct davinci_psc_init_data of_da850_psc1_init_data;
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM355
 extern const struct davinci_psc_init_data dm355_psc_init_data;
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM356
 extern const struct davinci_psc_init_data dm365_psc_init_data;
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM644x
 extern const struct davinci_psc_init_data dm644x_psc_init_data;
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM646x
 extern const struct davinci_psc_init_data dm646x_psc_init_data;
+#endif
 
 #endif /* __CLK_DAVINCI_PSC_H__ */
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index 1bd43550e4c8..becdb1dd21b5 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -44,14 +44,17 @@ config RESET_HISI
           Build reset controller driver for HiSilicon device chipsets.
 
 config STUB_CLK_HI6220
-        bool "Hi6220 Stub Clock Driver"
-        depends on COMMON_CLK_HI6220 && MAILBOX
-        default ARCH_HISI
+        bool "Hi6220 Stub Clock Driver" if EXPERT
+        depends on (COMMON_CLK_HI6220 || COMPILE_TEST)
+        depends on MAILBOX
+        default COMMON_CLK_HI6220
         help
           Build the Hisilicon Hi6220 stub clock driver.
 
 config STUB_CLK_HI3660
-        bool "Hi3660 Stub Clock Driver"
-        depends on COMMON_CLK_HI3660 && MAILBOX
+        bool "Hi3660 Stub Clock Driver" if EXPERT
+        depends on (COMMON_CLK_HI3660 || COMPILE_TEST)
+        depends on MAILBOX
+        default COMMON_CLK_HI3660
         help
           Build the Hisilicon Hi3660 stub clock driver.
diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c
index 743eec131528..4fe0b2a9baf1 100644
--- a/drivers/clk/hisilicon/crg-hi3798cv200.c
+++ b/drivers/clk/hisilicon/crg-hi3798cv200.c
@@ -186,6 +186,23 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
                 CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
         { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
                 CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
+        /* USB3 */
+        { HISTB_USB3_BUS_CLK, "clk_u3_bus", NULL,
+                CLK_SET_RATE_PARENT, 0xb0, 0, 0 },
+        { HISTB_USB3_UTMI_CLK, "clk_u3_utmi", NULL,
+                CLK_SET_RATE_PARENT, 0xb0, 4, 0 },
+        { HISTB_USB3_PIPE_CLK, "clk_u3_pipe", NULL,
+                CLK_SET_RATE_PARENT, 0xb0, 3, 0 },
+        { HISTB_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL,
+                CLK_SET_RATE_PARENT, 0xb0, 2, 0 },
+        { HISTB_USB3_BUS_CLK1, "clk_u3_bus1", NULL,
+                CLK_SET_RATE_PARENT, 0xb0, 16, 0 },
+        { HISTB_USB3_UTMI_CLK1, "clk_u3_utmi1", NULL,
+                CLK_SET_RATE_PARENT, 0xb0, 20, 0 },
+        { HISTB_USB3_PIPE_CLK1, "clk_u3_pipe1", NULL,
+                CLK_SET_RATE_PARENT, 0xb0, 19, 0 },
+        { HISTB_USB3_SUSPEND_CLK1, "clk_u3_suspend1", NULL,
+                CLK_SET_RATE_PARENT, 0xb0, 18, 0 },
 };
 
 static struct hisi_clock_data *hi3798cv200_clk_register(
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 8d518ad5dc13..b9ea7037e193 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -753,6 +753,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         else
                 clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5",        "ecspi_root",        base + 0x6c, 8);
         clk[IMX6QDL_CLK_ENET]         = imx_clk_gate2("enet",          "ipg",               base + 0x6c, 10);
+        clk[IMX6QDL_CLK_EPIT1]        = imx_clk_gate2("epit1",         "ipg",               base + 0x6c, 12);
+        clk[IMX6QDL_CLK_EPIT2]        = imx_clk_gate2("epit2",         "ipg",               base + 0x6c, 14);
         clk[IMX6QDL_CLK_ESAI_EXTAL]   = imx_clk_gate2_shared("esai_extal",   "esai_podf",   base + 0x6c, 16, &share_count_esai);
         clk[IMX6QDL_CLK_ESAI_IPG]     = imx_clk_gate2_shared("esai_ipg",   "ahb",           base + 0x6c, 16, &share_count_esai);
         clk[IMX6QDL_CLK_ESAI_MEM]     = imx_clk_gate2_shared("esai_mem", "ahb",             base + 0x6c, 16, &share_count_esai);
diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
index 9642cdf0fb88..66b1dd1cfad0 100644
--- a/drivers/clk/imx/clk-imx6sl.c
+++ b/drivers/clk/imx/clk-imx6sl.c
@@ -330,7 +330,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26,  1,   base + 0x48, 3,  periph2_sels, ARRAY_SIZE(periph2_sels));
 
         /*                                                   name                 parent_name          reg       shift width */
-        clks[IMX6SL_CLK_OCRAM_PODF]        = imx_clk_divider("ocram_podf",        "ocram_sel",         base + 0x14, 16, 3);
+        clks[IMX6SL_CLK_OCRAM_PODF]        = imx_clk_busy_divider("ocram_podf",   "ocram_sel",         base + 0x14, 16, 3, base + 0x48, 0);
         clks[IMX6SL_CLK_PERIPH_CLK2_PODF]  = imx_clk_divider("periph_clk2_podf",  "periph_clk2_sel",   base + 0x14, 27, 3);
         clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel",  base + 0x14, 0,  3);
         clks[IMX6SL_CLK_IPG]               = imx_clk_divider("ipg",               "ahb",               base + 0x14, 8,  2);
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
index bc3f9ebf2d9e..10c771b91ef6 100644
--- a/drivers/clk/imx/clk-imx6sx.c
+++ b/drivers/clk/imx/clk-imx6sx.c
@@ -80,7 +80,7 @@ static const char *lvds_sels[]	= {
         "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
         "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2",
 };
-static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
+static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
 static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
 static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
 static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
@@ -97,12 +97,7 @@ static int const clks_init_on[] __initconst = {
         IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3,
         IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG,
         IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM,
-        IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_M4,
-        IMX6SX_CLK_QSPI1, IMX6SX_CLK_QSPI2, IMX6SX_CLK_UART_IPG,
-        IMX6SX_CLK_UART_SERIAL, IMX6SX_CLK_I2C3, IMX6SX_CLK_ECSPI5,
-        IMX6SX_CLK_CAN1_IPG, IMX6SX_CLK_CAN1_SERIAL, IMX6SX_CLK_CAN2_IPG,
-        IMX6SX_CLK_CAN2_SERIAL, IMX6SX_CLK_CANFD, IMX6SX_CLK_EPIT1,
-        IMX6SX_CLK_EPIT2,
+        IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_TZASC1,
 };
 
 static const struct clk_div_table clk_enet_ref_table[] = {
@@ -158,8 +153,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
         clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
         clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
 
-        /* Clock source from external clock via CLK1 PAD */
-        clks[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
+        /* Clock source from external clock via CLK1/2 PAD */
+        clks[IMX6SX_CLK_ANACLK1] = of_clk_get_by_name(ccm_node, "anaclk1");
+        clks[IMX6SX_CLK_ANACLK2] = of_clk_get_by_name(ccm_node, "anaclk2");
 
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
         base = of_iomap(np, 0);
@@ -228,7 +224,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
         clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
 
         clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
+        clks[IMX6SX_CLK_LVDS2_OUT] = imx_clk_gate_exclusive("lvds2_out", "lvds2_sel", base + 0x160, 11, BIT(13));
         clks[IMX6SX_CLK_LVDS1_IN]  = imx_clk_gate_exclusive("lvds1_in",  "anaclk1",   base + 0x160, 12, BIT(10));
+        clks[IMX6SX_CLK_LVDS2_IN]  = imx_clk_gate_exclusive("lvds2_in",  "anaclk2",   base + 0x160, 13, BIT(11));
 
         clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
                         base + 0xe0, 0, 2, 0, clk_enet_ref_table,
@@ -270,6 +268,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
 
         /*                                                name                reg           shift   width   parent_names       num_parents */
         clks[IMX6SX_CLK_LVDS1_SEL]          = imx_clk_mux("lvds1_sel",        base + 0x160, 0,      5,      lvds_sels,         ARRAY_SIZE(lvds_sels));
+        clks[IMX6SX_CLK_LVDS2_SEL]          = imx_clk_mux("lvds2_sel",        base + 0x160, 5,      5,      lvds_sels,         ARRAY_SIZE(lvds_sels));
 
         np = ccm_node;
         base = of_iomap(np, 0);
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 12320118f8de..ba563ba50b40 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -40,7 +40,7 @@ static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", };
 static const char *axi_sels[] = {"periph", "axi_alt_sel", };
 static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
 static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };
-static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", };
+static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "pll2_bypass_src", };
 static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", };
 static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
 static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
@@ -68,6 +68,13 @@ static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "
 static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
 static const char *esai_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
 static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
+static const char *cko1_sels[] = { "dummy", "dummy", "dummy", "dummy", "dummy", "axi", "enfc", "dummy", "dummy",
+                                   "dummy", "lcdif_pix", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
+static const char *cko2_sels[] = { "dummy", "dummy", "dummy", "usdhc1", "dummy", "dummy", "ecspi_root", "dummy",
+                                   "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "osc", "dummy",
+                                   "dummy", "usdhc2", "sai1", "sai2", "sai3", "dummy", "dummy", "can_root",
+                                   "dummy", "dummy", "dummy", "dummy", "uart_serial", "spdif", "dummy", "dummy", };
+static const char *cko_sels[] = { "cko1", "cko2", };
 
 static struct clk *clks[IMX6UL_CLK_END];
 static struct clk_onecell_data clk_data;
@@ -273,6 +280,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
         clks[IMX6UL_CLK_LDB_DI0_DIV_SEL]  = imx_clk_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));
         clks[IMX6UL_CLK_LDB_DI1_DIV_SEL]  = imx_clk_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));
 
+        clks[IMX6UL_CLK_CKO1_SEL]         = imx_clk_mux("cko1_sel", base + 0x60, 0,  4, cko1_sels, ARRAY_SIZE(cko1_sels));
+        clks[IMX6UL_CLK_CKO2_SEL]         = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
+        clks[IMX6UL_CLK_CKO]              = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
+
         clks[IMX6UL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
         clks[IMX6UL_CLK_LDB_DI0_DIV_7]   = imx_clk_fixed_factor("ldb_di0_div_7",   "ldb_di0_sel", 1, 7);
         clks[IMX6UL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "qspi1_sel", 2, 7);
@@ -316,6 +327,9 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
         clks[IMX6UL_CLK_LCDIF_PRED]     = imx_clk_divider("lcdif_pred",    "lcdif_pre_sel",     base + 0x38, 12, 3);
         clks[IMX6UL_CLK_CSI_PODF]       = imx_clk_divider("csi_podf",      "csi_sel",           base + 0x3c, 11, 3);
 
+        clks[IMX6UL_CLK_CKO1_PODF]      = imx_clk_divider("cko1_podf",     "cko1_sel",          base + 0x60, 4,  3);
+        clks[IMX6UL_CLK_CKO2_PODF]      = imx_clk_divider("cko2_podf",     "cko2_sel",          base + 0x60, 21, 3);
+
         clks[IMX6UL_CLK_ARM]            = imx_clk_busy_divider("arm",       "pll1_sw",  base +  0x10, 0,  3,  base + 0x48, 16);
         clks[IMX6UL_CLK_MMDC_PODF]      = imx_clk_busy_divider("mmdc_podf", "periph2",  base +  0x14, 3,  3,  base + 0x48, 2);
         clks[IMX6UL_CLK_AXI_PODF]       = imx_clk_busy_divider("axi_podf",  "axi_sel",  base +  0x14, 16, 3,  base + 0x48, 0);
@@ -445,6 +459,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
         clks[IMX6UL_CLK_PWM6]           = imx_clk_gate2("pwm6",         "perclk",        base + 0x80,   28);
         clks[IMX6UL_CLK_PWM7]           = imx_clk_gate2("pwm7",         "perclk",        base + 0x80,   30);
 
+        /* CCOSR */
+        clks[IMX6UL_CLK_CKO1]           = imx_clk_gate("cko1",          "cko1_podf",     base + 0x60,   7);
+        clks[IMX6UL_CLK_CKO2]           = imx_clk_gate("cko2",          "cko2_podf",     base + 0x60,   24);
+
         /* mask handshake of mmdc */
         writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
 
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 975a20d3cc94..27217a7ea17e 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -26,6 +26,8 @@ static u32 share_count_sai1;
 static u32 share_count_sai2;
 static u32 share_count_sai3;
 static u32 share_count_nand;
+static u32 share_count_enet1;
+static u32 share_count_enet2;
 
 static const struct clk_div_table test_div_table[] = {
         { .val = 3, .div = 1, },
@@ -729,7 +731,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
         clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_divider2("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6);
         clks[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_divider2("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6);
         clks[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_divider2("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6);
-        clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div", "mipi_csi_dphy_div", base + 0xa480, 0, 6);
+        clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div", "mipi_dphy_pre_div", base + 0xa480, 0, 6);
         clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider2("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6);
         clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider2("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6);
         clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider2("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6);
@@ -738,7 +740,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
         clks[IMX7D_ENET1_TIME_ROOT_DIV] = imx_clk_divider2("enet1_time_post_div", "enet1_time_pre_div", base + 0xa780, 0, 6);
         clks[IMX7D_ENET2_REF_ROOT_DIV] = imx_clk_divider2("enet2_ref_post_div", "enet2_ref_pre_div", base + 0xa800, 0, 6);
         clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6);
-        clks[IMX7D_ENET_PHY_REF_ROOT_DIV] = imx_clk_divider2("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base + 0xa900, 0, 6);
+        clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_divider2("enet_phy_ref_root_clk", "enet_phy_ref_pre_div", base + 0xa900, 0, 6);
         clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider2("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6);
         clks[IMX7D_NAND_ROOT_CLK] = imx_clk_divider2("nand_root_clk", "nand_pre_div", base + 0xaa00, 0, 6);
         clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider2("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6);
@@ -805,6 +807,10 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
         clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate4("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0);
         clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate4("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0);
         clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate4("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0);
+        clks[IMX7D_ENET1_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet1_ipg_root_clk", "enet_axi_post_div", base + 0x4700, 0, &share_count_enet1);
+        clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet1_time_root_clk", "enet1_time_post_div", base + 0x4700, 0, &share_count_enet1);
+        clks[IMX7D_ENET2_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet2_ipg_root_clk", "enet_axi_post_div", base + 0x4710, 0, &share_count_enet2);
+        clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet2_time_root_clk", "enet2_time_post_div", base + 0x4710, 0, &share_count_enet2);
         clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2_shared2("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0, &share_count_sai1);
         clks[IMX7D_SAI1_IPG_CLK]  = imx_clk_gate2_shared2("sai1_ipg_clk",  "ipg_root_clk",  base + 0x48c0, 0, &share_count_sai1);
         clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate2_shared2("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0, &share_count_sai2);
@@ -812,11 +818,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
         clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate2_shared2("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0, &share_count_sai3);
         clks[IMX7D_SAI3_IPG_CLK]  = imx_clk_gate2_shared2("sai3_ipg_clk",  "ipg_root_clk",  base + 0x48e0, 0, &share_count_sai3);
         clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate4("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0);
-        clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate4("enet1_ref_root_clk", "enet1_ref_post_div", base + 0x44e0, 0);
-        clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate4("enet1_time_root_clk", "enet1_time_post_div", base + 0x44f0, 0);
-        clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate4("enet2_ref_root_clk", "enet2_ref_post_div", base + 0x4500, 0);
-        clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate4("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0);
-        clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0);
         clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0);
         clks[IMX7D_NAND_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0, &share_count_nand);
         clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base + 0x4140, 0, &share_count_nand);
@@ -891,6 +892,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
         clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
         clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
 
+        clk_set_parent(clks[IMX7D_MIPI_CSI_ROOT_SRC], clks[IMX7D_PLL_SYS_PFD3_CLK]);
+
         /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
         clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
 
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index 56a712c9075f..5ef7d9ba2195 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -43,7 +43,8 @@ static inline bool
 ingenic_cgu_gate_get(struct ingenic_cgu *cgu,
                      const struct ingenic_cgu_gate_info *info)
 {
-        return readl(cgu->base + info->reg) & BIT(info->bit);
+        return !!(readl(cgu->base + info->reg) & BIT(info->bit))
+                ^ info->clear_to_gate;
 }
 
 /**
@@ -62,7 +63,7 @@ ingenic_cgu_gate_set(struct ingenic_cgu *cgu,
 {
         u32 clkgr = readl(cgu->base + info->reg);
 
-        if (val)
+        if (val ^ info->clear_to_gate)
                 clkgr |= BIT(info->bit);
         else
                 clkgr &= ~BIT(info->bit);
@@ -511,6 +512,9 @@ static int ingenic_clk_enable(struct clk_hw *hw)
                 spin_lock_irqsave(&cgu->lock, flags);
                 ingenic_cgu_gate_set(cgu, &clk_info->gate, false);
                 spin_unlock_irqrestore(&cgu->lock, flags);
+
+                if (clk_info->gate.delay_us)
+                        udelay(clk_info->gate.delay_us);
         }
 
         return 0;
diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h
index 9da34910bd80..542192376ebf 100644
--- a/drivers/clk/ingenic/cgu.h
+++ b/drivers/clk/ingenic/cgu.h
@@ -111,10 +111,14 @@ struct ingenic_cgu_fixdiv_info {
  * struct ingenic_cgu_gate_info - information about a clock gate
  * @reg: offset of the gate control register within the CGU
  * @bit: offset of the bit in the register that controls the gate
+ * @clear_to_gate: if set, the clock is gated when the bit is cleared
+ * @delay_us: delay in microseconds after which the clock is considered stable
  */
 struct ingenic_cgu_gate_info {
         unsigned reg;
         u8 bit;
+        bool clear_to_gate;
+        u16 delay_us;
 };
 
 /**
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
index c78d369b9403..bf46a0df2004 100644
--- a/drivers/clk/ingenic/jz4770-cgu.c
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -42,7 +42,6 @@
 
 /* bits within the OPCR register */
 #define OPCR_SPENDH             BIT(5)          /* UHC PHY suspend */
-#define OPCR_SPENDN             BIT(7)          /* OTG PHY suspend */
 
 /* bits within the USBPCR1 register */
 #define USBPCR1_UHC_POWER       BIT(5)          /* UHC PHY power down */
@@ -83,37 +82,6 @@ static const struct clk_ops jz4770_uhc_phy_ops = {
         .is_enabled = jz4770_uhc_phy_is_enabled,
 };
 
-static int jz4770_otg_phy_enable(struct clk_hw *hw)
-{
-        void __iomem *reg_opcr          = cgu->base + CGU_REG_OPCR;
-
-        writel(readl(reg_opcr) | OPCR_SPENDN, reg_opcr);
-
-        /* Wait for the clock to be stable */
-        udelay(50);
-        return 0;
-}
-
-static void jz4770_otg_phy_disable(struct clk_hw *hw)
-{
-        void __iomem *reg_opcr          = cgu->base + CGU_REG_OPCR;
-
-        writel(readl(reg_opcr) & ~OPCR_SPENDN, reg_opcr);
-}
-
-static int jz4770_otg_phy_is_enabled(struct clk_hw *hw)
-{
-        void __iomem *reg_opcr          = cgu->base + CGU_REG_OPCR;
-
-        return !!(readl(reg_opcr) & OPCR_SPENDN);
-}
-
-static const struct clk_ops jz4770_otg_phy_ops = {
-        .enable = jz4770_otg_phy_enable,
-        .disable = jz4770_otg_phy_disable,
-        .is_enabled = jz4770_otg_phy_is_enabled,
-};
-
 static const s8 pll_od_encoding[8] = {
         0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
 };
@@ -186,7 +154,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
                 "h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
                 .parents = { JZ4770_CLK_PLL0, },
                 .div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1 },
-                .gate = { CGU_REG_LCR, 30 },
+                .gate = { CGU_REG_CLKGR1, 7 },
         },
         [JZ4770_CLK_H2CLK] = {
                 "h2clk", CGU_CLK_DIV,
@@ -194,9 +162,10 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
                 .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 },
         },
         [JZ4770_CLK_C1CLK] = {
-                "c1clk", CGU_CLK_DIV,
+                "c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
                 .parents = { JZ4770_CLK_PLL0, },
                 .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 },
+                .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
         },
         [JZ4770_CLK_PCLK] = {
                 "pclk", CGU_CLK_DIV,
@@ -393,7 +362,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
         [JZ4770_CLK_VPU] = {
                 "vpu", CGU_CLK_GATE,
                 .parents = { JZ4770_CLK_H1CLK, },
-                .gate = { CGU_REG_CLKGR1, 7 },
+                .gate = { CGU_REG_LCR, 30, false, 150 },
         },
         [JZ4770_CLK_MMC0] = {
                 "mmc0", CGU_CLK_GATE,
@@ -410,6 +379,11 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
                 .parents = { JZ4770_CLK_MMC2_MUX, },
                 .gate = { CGU_REG_CLKGR0, 12 },
         },
+        [JZ4770_CLK_OTG_PHY] = {
+                "usb_phy", CGU_CLK_GATE,
+                .parents = { JZ4770_CLK_OTG },
+                .gate = { CGU_REG_OPCR, 7, true, 50 },
+        },
 
         /* Custom clocks */
 
@@ -418,11 +392,6 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
                 .parents = { JZ4770_CLK_UHC, -1, -1, -1 },
                 .custom = { &jz4770_uhc_phy_ops },
         },
-        [JZ4770_CLK_OTG_PHY] = {
-                "usb_phy", CGU_CLK_CUSTOM,
-                .parents = { JZ4770_CLK_OTG, -1, -1, -1 },
-                .custom = { &jz4770_otg_phy_ops },
-        },
 
         [JZ4770_CLK_EXT512] = {
                 "ext/512", CGU_CLK_FIXDIV,
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 92afe5989e97..3dd1dab92223 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -60,6 +60,12 @@ config COMMON_CLK_MT2701_AUDSYS
         ---help---
           This driver supports Mediatek MT2701 audsys clocks.
 
+config COMMON_CLK_MT2701_G3DSYS
+        bool "Clock driver for MediaTek MT2701 g3dsys"
+        depends on COMMON_CLK_MT2701
+        ---help---
+          This driver supports MediaTek MT2701 g3dsys clocks.
+
 config COMMON_CLK_MT2712
         bool "Clock driver for MediaTek MT2712"
         depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index b80eff2abb31..844b55d2770d 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
 obj-$(CONFIG_COMMON_CLK_MT2701_AUDSYS) += clk-mt2701-aud.o
 obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
 obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o
+obj-$(CONFIG_COMMON_CLK_MT2701_G3DSYS) += clk-mt2701-g3d.o
 obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
 obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
 obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
new file mode 100644
index 000000000000..1328c112a38f
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Sean Wang <sean.wang@mediatek.com>
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2701-clk.h>
+
+#define GATE_G3D(_id, _name, _parent, _shift) { \
+                .id = _id,                              \
+                .name = _name,                          \
+                .parent_name = _parent,                 \
+                .regs = &g3d_cg_regs,                   \
+                .shift = _shift,                        \
+                .ops = &mtk_clk_gate_ops_setclr,        \
+        }
+
+static const struct mtk_gate_regs g3d_cg_regs = {
+        .sta_ofs = 0x0,
+        .set_ofs = 0x4,
+        .clr_ofs = 0x8,
+};
+
+static const struct mtk_gate g3d_clks[] = {
+        GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
+};
+
+static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
+{
+        struct clk_onecell_data *clk_data;
+        struct device_node *node = pdev->dev.of_node;
+        int r;
+
+        clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
+
+        mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
+                               clk_data);
+
+        r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+        if (r)
+                dev_err(&pdev->dev,
+                        "could not register clock provider: %s: %d\n",
+                        pdev->name, r);
+
+        mtk_register_reset_controller(node, 1, 0xc);
+
+        return r;
+}
+
+static const struct of_device_id of_match_clk_mt2701_g3d[] = {
+        {
+                .compatible = "mediatek,mt2701-g3dsys",
+                .data = clk_mt2701_g3dsys_init,
+        }, {
+                /* sentinel */
+        }
+};
+
+static int clk_mt2701_g3d_probe(struct platform_device *pdev)
+{
+        int (*clk_init)(struct platform_device *);
+        int r;
+
+        clk_init = of_device_get_match_data(&pdev->dev);
+        if (!clk_init)
+                return -EINVAL;
+
+        r = clk_init(pdev);
+        if (r)
+                dev_err(&pdev->dev,
+                        "could not register clock provider: %s: %d\n",
+                        pdev->name, r);
+
+        return r;
+}
+
+static struct platform_driver clk_mt2701_g3d_drv = {
+        .probe = clk_mt2701_g3d_probe,
+        .driver = {
+                .name = "clk-mt2701-g3d",
+                .of_match_table = of_match_clk_mt2701_g3d,
+        },
+};
+
+builtin_platform_driver(clk_mt2701_g3d_drv);
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index deca7527f92f..4dda8988b2f0 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -46,8 +46,6 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
                 340 * MHZ),
         FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m",
                 340 * MHZ),
-        FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_dig_cts", "clk26m",
-                300 * MHZ),
         FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m",
                 27 * MHZ),
         FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m",
@@ -977,6 +975,10 @@ static const struct mtk_pll_data apmixed_plls[] = {
                                 21, 0x2d0, 4, 0x0, 0x2d4, 0),
 };
 
+static const struct mtk_fixed_factor apmixed_fixed_divs[] = {
+        FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1),
+};
+
 static int mtk_apmixedsys_init(struct platform_device *pdev)
 {
         struct clk_onecell_data *clk_data;
@@ -988,6 +990,8 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
 
         mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
                                                                 clk_data);
+        mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
+                                                                clk_data);
 
         return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 }
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index d5cbec522aec..815659eebea3 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -3,6 +3,12 @@ config COMMON_CLK_AMLOGIC
         depends on OF
         depends on ARCH_MESON || COMPILE_TEST
 
+config COMMON_CLK_MESON_AO
+        bool
+        depends on OF
+        depends on ARCH_MESON || COMPILE_TEST
+        select COMMON_CLK_REGMAP_MESON
+
 config COMMON_CLK_REGMAP_MESON
         bool
         select REGMAP
@@ -21,6 +27,7 @@ config COMMON_CLK_GXBB
         bool
         depends on COMMON_CLK_AMLOGIC
         select RESET_CONTROLLER
+        select COMMON_CLK_MESON_AO
         select COMMON_CLK_REGMAP_MESON
         select MFD_SYSCON
         help
@@ -31,6 +38,7 @@ config COMMON_CLK_AXG
         bool
         depends on COMMON_CLK_AMLOGIC
         select RESET_CONTROLLER
+        select COMMON_CLK_MESON_AO
         select COMMON_CLK_REGMAP_MESON
         select MFD_SYSCON
         help
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index ffee82e60b7a..d0d13aeb369a 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -3,7 +3,8 @@
 #
 
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
+obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)    += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
-obj-$(CONFIG_COMMON_CLK_AXG)     += axg.o
+obj-$(CONFIG_COMMON_CLK_AXG)     += axg.o axg-aoclk.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)   += clk-regmap.o
diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
new file mode 100644
index 000000000000..29e088542387
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-AXG Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette <mturquette@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/mfd/syscon.h>
+#include "clk-regmap.h"
+#include "meson-aoclk.h"
+#include "axg-aoclk.h"
+
+#define AXG_AO_GATE(_name, _bit)                                        \
+static struct clk_regmap axg_aoclk_##_name = {                          \
+        .data = &(struct clk_regmap_gate_data) {                        \
+                .offset = (AO_RTI_GEN_CNTL_REG0),                       \
+                .bit_idx = (_bit),                                      \
+        },                                                              \
+        .hw.init = &(struct clk_init_data) {                            \
+                .name =  "axg_ao_" #_name,                              \
+                .ops = &clk_regmap_gate_ops,                            \
+                .parent_names = (const char *[]){ "clk81" },            \
+                .num_parents = 1,                                       \
+                .flags = CLK_IGNORE_UNUSED,                             \
+        },                                                              \
+}
+
+AXG_AO_GATE(remote, 0);
+AXG_AO_GATE(i2c_master, 1);
+AXG_AO_GATE(i2c_slave, 2);
+AXG_AO_GATE(uart1, 3);
+AXG_AO_GATE(uart2, 5);
+AXG_AO_GATE(ir_blaster, 6);
+AXG_AO_GATE(saradc, 7);
+
+static struct clk_regmap axg_aoclk_clk81 = {
+        .data = &(struct clk_regmap_mux_data) {
+                .offset = AO_RTI_PWR_CNTL_REG0,
+                .mask = 0x1,
+                .shift = 8,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "axg_ao_clk81",
+                .ops = &clk_regmap_mux_ro_ops,
+                .parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
+                .num_parents = 2,
+        },
+};
+
+static struct clk_regmap axg_aoclk_saradc_mux = {
+        .data = &(struct clk_regmap_mux_data) {
+                .offset = AO_SAR_CLK,
+                .mask = 0x3,
+                .shift = 9,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "axg_ao_saradc_mux",
+                .ops = &clk_regmap_mux_ops,
+                .parent_names = (const char *[]){ "xtal", "axg_ao_clk81" },
+                .num_parents = 2,
+        },
+};
+
+static struct clk_regmap axg_aoclk_saradc_div = {
+        .data = &(struct clk_regmap_div_data) {
+                .offset = AO_SAR_CLK,
+                .shift = 0,
+                .width = 8,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "axg_ao_saradc_div",
+                .ops = &clk_regmap_divider_ops,
+                .parent_names = (const char *[]){ "axg_ao_saradc_mux" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_regmap axg_aoclk_saradc_gate = {
+        .data = &(struct clk_regmap_gate_data) {
+                .offset = AO_SAR_CLK,
+                .bit_idx = 8,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "axg_ao_saradc_gate",
+                .ops = &clk_regmap_gate_ops,
+                .parent_names = (const char *[]){ "axg_ao_saradc_div" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static const unsigned int axg_aoclk_reset[] = {
+        [RESET_AO_REMOTE]       = 16,
+        [RESET_AO_I2C_MASTER]   = 18,
+        [RESET_AO_I2C_SLAVE]    = 19,
+        [RESET_AO_UART1]        = 17,
+        [RESET_AO_UART2]        = 22,
+        [RESET_AO_IR_BLASTER]   = 23,
+};
+
+static struct clk_regmap *axg_aoclk_regmap[] = {
+        [CLKID_AO_REMOTE]       = &axg_aoclk_remote,
+        [CLKID_AO_I2C_MASTER]   = &axg_aoclk_i2c_master,
+        [CLKID_AO_I2C_SLAVE]    = &axg_aoclk_i2c_slave,
+        [CLKID_AO_UART1]        = &axg_aoclk_uart1,
+        [CLKID_AO_UART2]        = &axg_aoclk_uart2,
+        [CLKID_AO_IR_BLASTER]   = &axg_aoclk_ir_blaster,
+        [CLKID_AO_SAR_ADC]      = &axg_aoclk_saradc,
+        [CLKID_AO_CLK81]        = &axg_aoclk_clk81,
+        [CLKID_AO_SAR_ADC_SEL]  = &axg_aoclk_saradc_mux,
+        [CLKID_AO_SAR_ADC_DIV]  = &axg_aoclk_saradc_div,
+        [CLKID_AO_SAR_ADC_CLK]  = &axg_aoclk_saradc_gate,
+};
+
+static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
+        .hws = {
+                [CLKID_AO_REMOTE]       = &axg_aoclk_remote.hw,
+                [CLKID_AO_I2C_MASTER]   = &axg_aoclk_i2c_master.hw,
+                [CLKID_AO_I2C_SLAVE]    = &axg_aoclk_i2c_slave.hw,
+                [CLKID_AO_UART1]        = &axg_aoclk_uart1.hw,
+                [CLKID_AO_UART2]        = &axg_aoclk_uart2.hw,
+                [CLKID_AO_IR_BLASTER]   = &axg_aoclk_ir_blaster.hw,
+                [CLKID_AO_SAR_ADC]      = &axg_aoclk_saradc.hw,
+                [CLKID_AO_CLK81]        = &axg_aoclk_clk81.hw,
+                [CLKID_AO_SAR_ADC_SEL]  = &axg_aoclk_saradc_mux.hw,
+                [CLKID_AO_SAR_ADC_DIV]  = &axg_aoclk_saradc_div.hw,
+                [CLKID_AO_SAR_ADC_CLK]  = &axg_aoclk_saradc_gate.hw,
+        },
+        .num = NR_CLKS,
+};
+
+static const struct meson_aoclk_data axg_aoclkc_data = {
+        .reset_reg      = AO_RTI_GEN_CNTL_REG0,
+        .num_reset      = ARRAY_SIZE(axg_aoclk_reset),
+        .reset          = axg_aoclk_reset,
+        .num_clks       = ARRAY_SIZE(axg_aoclk_regmap),
+        .clks           = axg_aoclk_regmap,
+        .hw_data        = &axg_aoclk_onecell_data,
+};
+
+static const struct of_device_id axg_aoclkc_match_table[] = {
+        {
+                .compatible     = "amlogic,meson-axg-aoclkc",
+                .data           = &axg_aoclkc_data,
+        },
+        { }
+};
+
+static struct platform_driver axg_aoclkc_driver = {
+        .probe          = meson_aoclkc_probe,
+        .driver         = {
+                .name   = "axg-aoclkc",
+                .of_match_table = axg_aoclkc_match_table,
+        },
+};
+
+builtin_platform_driver(axg_aoclkc_driver);
diff --git a/drivers/clk/meson/axg-aoclk.h b/drivers/clk/meson/axg-aoclk.h
new file mode 100644
index 000000000000..91384d8dd844
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2017 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef __AXG_AOCLKC_H
+#define __AXG_AOCLKC_H
+
+#define NR_CLKS 11
+/* AO Configuration Clock registers offsets
+ * Register offsets from the data sheet must be multiplied by 4.
+ */
+#define AO_RTI_PWR_CNTL_REG1    0x0C
+#define AO_RTI_PWR_CNTL_REG0    0x10
+#define AO_RTI_GEN_CNTL_REG0    0x40
+#define AO_OSCIN_CNTL           0x58
+#define AO_CRT_CLK_CNTL1        0x68
+#define AO_SAR_CLK              0x90
+#define AO_RTC_ALT_CLK_CNTL0    0x94
+#define AO_RTC_ALT_CLK_CNTL1    0x98
+
+#include <dt-bindings/clock/axg-aoclkc.h>
+#include <dt-bindings/reset/axg-aoclkc.h>
+
+#endif /* __AXG_AOCLKC_H */
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 5f5d468c1efe..bd4dbc696b88 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -461,6 +461,7 @@ static struct clk_regmap axg_mpll0_div = {
                         .width   = 1,
                 },
                 .lock = &meson_clk_lock,
+                .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
         },
         .hw.init = &(struct clk_init_data){
                 .name = "mpll0_div",
@@ -507,6 +508,7 @@ static struct clk_regmap axg_mpll1_div = {
                         .width   = 1,
                 },
                 .lock = &meson_clk_lock,
+                .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
         },
         .hw.init = &(struct clk_init_data){
                 .name = "mpll1_div",
@@ -553,6 +555,7 @@ static struct clk_regmap axg_mpll2_div = {
                         .width   = 1,
                 },
                 .lock = &meson_clk_lock,
+                .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
         },
         .hw.init = &(struct clk_init_data){
                 .name = "mpll2_div",
@@ -599,6 +602,7 @@ static struct clk_regmap axg_mpll3_div = {
                         .width   = 1,
                 },
                 .lock = &meson_clk_lock,
+                .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
         },
         .hw.init = &(struct clk_init_data){
                 .name = "mpll3_div",
diff --git a/drivers/clk/meson/clk-audio-divider.c b/drivers/clk/meson/clk-audio-divider.c
index f7ab5b1db342..58f546e04807 100644
--- a/drivers/clk/meson/clk-audio-divider.c
+++ b/drivers/clk/meson/clk-audio-divider.c
@@ -1,18 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2017 AmLogic, Inc.
  * Author: Jerome Brunet <jbrunet@baylibre.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 /*
diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c
index 0df1227b65b3..650f75cc15a9 100644
--- a/drivers/clk/meson/clk-mpll.c
+++ b/drivers/clk/meson/clk-mpll.c
@@ -1,57 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
 /*
- * This file is provided under a dual BSD/GPLv2 license.  When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright (c) 2016 AmLogic, Inc.
- * Author: Michael Turquette <mturquette@baylibre.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
- * in the file called COPYING
- *
- * BSD LICENSE
- *
  * Copyright (c) 2016 AmLogic, Inc.
  * Author: Michael Turquette <mturquette@baylibre.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *   * Neither the name of Intel Corporation nor the names of its
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 /*
@@ -89,10 +39,23 @@ static long rate_from_params(unsigned long parent_rate,
 static void params_from_rate(unsigned long requested_rate,
                              unsigned long parent_rate,
                              unsigned int *sdm,
-                             unsigned int *n2)
+                             unsigned int *n2,
+                             u8 flags)
 {
         uint64_t div = parent_rate;
-        unsigned long rem = do_div(div, requested_rate);
+        uint64_t frac = do_div(div, requested_rate);
+
+        frac *= SDM_DEN;
+
+        if (flags & CLK_MESON_MPLL_ROUND_CLOSEST)
+                *sdm = DIV_ROUND_CLOSEST_ULL(frac, requested_rate);
+        else
+                *sdm = DIV_ROUND_UP_ULL(frac, requested_rate);
+
+        if (*sdm == SDM_DEN) {
+                *sdm = 0;
+                div += 1;
+        }
 
         if (div < N2_MIN) {
                 *n2 = N2_MIN;
@@ -102,7 +65,6 @@ static void params_from_rate(unsigned long requested_rate,
                 *sdm = SDM_DEN - 1;
         } else {
                 *n2 = div;
-                *sdm = DIV_ROUND_UP_ULL((u64)rem * SDM_DEN, requested_rate);
         }
 }
 
@@ -125,9 +87,11 @@ static long mpll_round_rate(struct clk_hw *hw,
                             unsigned long rate,
                             unsigned long *parent_rate)
 {
+        struct clk_regmap *clk = to_clk_regmap(hw);
+        struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
         unsigned int sdm, n2;
 
-        params_from_rate(rate, *parent_rate, &sdm, &n2);
+        params_from_rate(rate, *parent_rate, &sdm, &n2, mpll->flags);
         return rate_from_params(*parent_rate, sdm, n2);
 }
 
@@ -140,7 +104,7 @@ static int mpll_set_rate(struct clk_hw *hw,
         unsigned int sdm, n2;
         unsigned long flags = 0;
 
-        params_from_rate(rate, parent_rate, &sdm, &n2);
+        params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags);
 
         if (mpll->lock)
                 spin_lock_irqsave(mpll->lock, flags);
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 65a7bd903551..3e04617ac47f 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -1,21 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2015 Endless Mobile, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
  *
  * Copyright (c) 2018 Baylibre, SAS.
  * Author: Jerome Brunet <jbrunet@baylibre.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 /*
diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c
index ab7a3556f5b2..305ee307c003 100644
--- a/drivers/clk/meson/clk-regmap.c
+++ b/drivers/clk/meson/clk-regmap.c
@@ -1,6 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
-// Copyright (c) 2018 BayLibre, SAS.
-// Author: Jerome Brunet <jbrunet@baylibre.com>
+/*
+ * Copyright (c) 2018 BayLibre, SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
 
 #include "clk-regmap.h"
 
diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h
index 627c888026d7..ed2d4348dbe2 100644
--- a/drivers/clk/meson/clk-regmap.h
+++ b/drivers/clk/meson/clk-regmap.h
@@ -1,6 +1,8 @@
-// SPDX-License-Identifier: GPL-2.0
-// Copyright (c) 2018 BayLibre, SAS.
-// Author: Jerome Brunet <jbrunet@baylibre.com>
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 BayLibre, SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
 
 #ifndef __CLK_REGMAP_H
 #define __CLK_REGMAP_H
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 8fe73c4edca8..2fb084330ee9 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -1,18 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (c) 2015 Endless Mobile, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #ifndef __CLKC_H
@@ -97,8 +86,11 @@ struct meson_clk_mpll_data {
         struct parm ssen;
         struct parm misc;
         spinlock_t *lock;
+        u8 flags;
 };
 
+#define CLK_MESON_MPLL_ROUND_CLOSEST    BIT(0)
+
 struct meson_clk_audio_div_data {
         struct parm div;
         u8 flags;
diff --git a/drivers/clk/meson/gxbb-aoclk-32k.c b/drivers/clk/meson/gxbb-aoclk-32k.c
index 491634dbc985..680467141a1d 100644
--- a/drivers/clk/meson/gxbb-aoclk-32k.c
+++ b/drivers/clk/meson/gxbb-aoclk-32k.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2017 BayLibre, SAS.
  * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
  */
 
 #include <linux/clk-provider.h>
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 9ec23ae9a219..42ed61d3c3fb 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -1,90 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
 /*
- * This file is provided under a dual BSD/GPLv2 license.  When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
  * Copyright (c) 2016 BayLibre, SAS.
  * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
- * The full GNU General Public License is included in this distribution
- * in the file called COPYING.
- *
- * BSD LICENSE
- *
- * Copyright (c) 2016 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *   * Neither the name of Intel Corporation nor the names of its
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-#include <linux/clk-provider.h>
-#include <linux/of_address.h>
 #include <linux/platform_device.h>
-#include <linux/reset-controller.h>
 #include <linux/mfd/syscon.h>
-#include <linux/regmap.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <dt-bindings/clock/gxbb-aoclkc.h>
-#include <dt-bindings/reset/gxbb-aoclkc.h>
 #include "clk-regmap.h"
+#include "meson-aoclk.h"
 #include "gxbb-aoclk.h"
 
-struct gxbb_aoclk_reset_controller {
-        struct reset_controller_dev reset;
-        unsigned int *data;
-        struct regmap *regmap;
-};
-
-static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
-                               unsigned long id)
-{
-        struct gxbb_aoclk_reset_controller *reset =
-                container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
-
-        return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
-                            BIT(reset->data[id]));
-}
-
-static const struct reset_control_ops gxbb_aoclk_reset_ops = {
-        .reset = gxbb_aoclk_do_reset,
-};
-
 #define GXBB_AO_GATE(_name, _bit)                                       \
 static struct clk_regmap _name##_ao = {                                 \
         .data = &(struct clk_regmap_gate_data) {                        \
@@ -96,7 +20,7 @@ static struct clk_regmap _name##_ao = {					\
                 .ops = &clk_regmap_gate_ops,                            \
                 .parent_names = (const char *[]){ "clk81" },            \
                 .num_parents = 1,                                       \
-                .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),     \
+                .flags = CLK_IGNORE_UNUSED,                             \
         },                                                              \
 }
 
@@ -117,7 +41,7 @@ static struct aoclk_cec_32k cec_32k_ao = {
         },
 };
 
-static unsigned int gxbb_aoclk_reset[] = {
+static const unsigned int gxbb_aoclk_reset[] = {
         [RESET_AO_REMOTE] = 16,
         [RESET_AO_I2C_MASTER] = 18,
         [RESET_AO_I2C_SLAVE] = 19,
@@ -135,7 +59,7 @@ static struct clk_regmap *gxbb_aoclk_gate[] = {
         [CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
 };
 
-static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
+static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
         .hws = {
                 [CLKID_AO_REMOTE] = &remote_ao.hw,
                 [CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
@@ -145,58 +69,55 @@ static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
                 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
                 [CLKID_AO_CEC_32K] = &cec_32k_ao.hw,
         },
-        .num = 7,
+        .num = NR_CLKS,
 };
 
-static int gxbb_aoclkc_probe(struct platform_device *pdev)
+static int gxbb_register_cec_ao_32k(struct platform_device *pdev)
 {
-        struct gxbb_aoclk_reset_controller *rstc;
         struct device *dev = &pdev->dev;
         struct regmap *regmap;
-        int ret, clkid;
-
-        rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
-        if (!rstc)
-                return -ENOMEM;
+        int ret;
 
         regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
         if (IS_ERR(regmap)) {
                 dev_err(dev, "failed to get regmap\n");
-                return -ENODEV;
-        }
-
-        /* Reset Controller */
-        rstc->regmap = regmap;
-        rstc->data = gxbb_aoclk_reset;
-        rstc->reset.ops = &gxbb_aoclk_reset_ops;
-        rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
-        rstc->reset.of_node = dev->of_node;
-        ret = devm_reset_controller_register(dev, &rstc->reset);
-
-        /*
-         * Populate regmap and register all clks
-         */
-        for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
-                gxbb_aoclk_gate[clkid]->map = regmap;
-
-                ret = devm_clk_hw_register(dev,
-                                           gxbb_aoclk_onecell_data.hws[clkid]);
-                if (ret)
-                        return ret;
+                return PTR_ERR(regmap);
         }
 
         /* Specific clocks */
         cec_32k_ao.regmap = regmap;
         ret = devm_clk_hw_register(dev, &cec_32k_ao.hw);
+        if (ret) {
+                dev_err(&pdev->dev, "clk cec_32k_ao register failed.\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static const struct meson_aoclk_data gxbb_aoclkc_data = {
+        .reset_reg      = AO_RTI_GEN_CNTL_REG0,
+        .num_reset      = ARRAY_SIZE(gxbb_aoclk_reset),
+        .reset          = gxbb_aoclk_reset,
+        .num_clks       = ARRAY_SIZE(gxbb_aoclk_gate),
+        .clks           = gxbb_aoclk_gate,
+        .hw_data        = &gxbb_aoclk_onecell_data,
+};
+
+static int gxbb_aoclkc_probe(struct platform_device *pdev)
+{
+        int ret = gxbb_register_cec_ao_32k(pdev);
         if (ret)
                 return ret;
 
-        return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
-                        &gxbb_aoclk_onecell_data);
+        return meson_aoclkc_probe(pdev);
 }
 
 static const struct of_device_id gxbb_aoclkc_match_table[] = {
-        { .compatible = "amlogic,meson-gx-aoclkc" },
+        {
+                .compatible     = "amlogic,meson-gx-aoclkc",
+                .data           = &gxbb_aoclkc_data,
+        },
         { }
 };
 
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
index badc4c22b4ee..c514493d989a 100644
--- a/drivers/clk/meson/gxbb-aoclk.h
+++ b/drivers/clk/meson/gxbb-aoclk.h
@@ -1,13 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (c) 2017 BayLibre, SAS
  * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
  */
 
 #ifndef __GXBB_AOCLKC_H
 #define __GXBB_AOCLKC_H
 
+#define NR_CLKS 7
+
 /* AO Configuration Clock registers offsets */
 #define AO_RTI_PWR_CNTL_REG1    0x0c
 #define AO_RTI_PWR_CNTL_REG0    0x10
@@ -26,4 +27,7 @@ struct aoclk_cec_32k {
 
 extern const struct clk_ops meson_aoclk_cec_32k_ops;
 
+#include <dt-bindings/clock/gxbb-aoclkc.h>
+#include <dt-bindings/reset/gxbb-aoclkc.h>
+
 #endif /* __GXBB_AOCLKC_H */
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index b1e4d9557610..240658404367 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -1,20 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * AmLogic S905 / GXBB Clock Controller Driver
- *
  * Copyright (c) 2016 AmLogic, Inc.
  * Michael Turquette <mturquette@baylibre.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <linux/clk.h>
@@ -1543,6 +1530,102 @@ static struct clk_regmap gxbb_vapb = {
         },
 };
 
+/* VDEC clocks */
+
+static const char * const gxbb_vdec_parent_names[] = {
+        "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
+};
+
+static struct clk_regmap gxbb_vdec_1_sel = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_VDEC_CLK_CNTL,
+                .mask = 0x3,
+                .shift = 9,
+                .flags = CLK_MUX_ROUND_CLOSEST,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "vdec_1_sel",
+                .ops = &clk_regmap_mux_ops,
+                .parent_names = gxbb_vdec_parent_names,
+                .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_regmap gxbb_vdec_1_div = {
+        .data = &(struct clk_regmap_div_data){
+                .offset = HHI_VDEC_CLK_CNTL,
+                .shift = 0,
+                .width = 7,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "vdec_1_div",
+                .ops = &clk_regmap_divider_ops,
+                .parent_names = (const char *[]){ "vdec_1_sel" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_regmap gxbb_vdec_1 = {
+        .data = &(struct clk_regmap_gate_data){
+                .offset = HHI_VDEC_CLK_CNTL,
+                .bit_idx = 8,
+        },
+        .hw.init = &(struct clk_init_data) {
+                .name = "vdec_1",
+                .ops = &clk_regmap_gate_ops,
+                .parent_names = (const char *[]){ "vdec_1_div" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_regmap gxbb_vdec_hevc_sel = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_VDEC2_CLK_CNTL,
+                .mask = 0x3,
+                .shift = 25,
+                .flags = CLK_MUX_ROUND_CLOSEST,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "vdec_hevc_sel",
+                .ops = &clk_regmap_mux_ops,
+                .parent_names = gxbb_vdec_parent_names,
+                .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_regmap gxbb_vdec_hevc_div = {
+        .data = &(struct clk_regmap_div_data){
+                .offset = HHI_VDEC2_CLK_CNTL,
+                .shift = 16,
+                .width = 7,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "vdec_hevc_div",
+                .ops = &clk_regmap_divider_ops,
+                .parent_names = (const char *[]){ "vdec_hevc_sel" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_regmap gxbb_vdec_hevc = {
+        .data = &(struct clk_regmap_gate_data){
+                .offset = HHI_VDEC2_CLK_CNTL,
+                .bit_idx = 24,
+        },
+        .hw.init = &(struct clk_init_data) {
+                .name = "vdec_hevc",
+                .ops = &clk_regmap_gate_ops,
+                .parent_names = (const char *[]){ "vdec_hevc_div" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -1786,6 +1869,12 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
+                [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
+                [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
+                [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
+                [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
+                [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
+                [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
                 [NR_CLKS]                   = NULL,
         },
         .num = NR_CLKS,
@@ -1942,6 +2031,12 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
+                [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
+                [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
+                [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
+                [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
+                [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
+                [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
                 [NR_CLKS]                   = NULL,
         },
         .num = NR_CLKS,
@@ -2100,6 +2195,12 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
         &gxbb_fclk_div4,
         &gxbb_fclk_div5,
         &gxbb_fclk_div7,
+        &gxbb_vdec_1_sel,
+        &gxbb_vdec_1_div,
+        &gxbb_vdec_1,
+        &gxbb_vdec_hevc_sel,
+        &gxbb_vdec_hevc_div,
+        &gxbb_vdec_hevc,
 };
 
 struct clkc_data {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 9febf3f03739..ec1a812bf1fd 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -1,57 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
 /*
- * This file is provided under a dual BSD/GPLv2 license.  When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
  * Copyright (c) 2016 AmLogic, Inc.
  * Author: Michael Turquette <mturquette@baylibre.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
- * in the file called COPYING
- *
- * BSD LICENSE
- *
- * Copyright (c) 2016 BayLibre, Inc.
- * Author: Michael Turquette <mturquette@baylibre.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *   * Neither the name of Intel Corporation nor the names of its
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef __GXBB_H
@@ -204,8 +154,12 @@
 #define CLKID_FCLK_DIV4_DIV       148
 #define CLKID_FCLK_DIV5_DIV       149
 #define CLKID_FCLK_DIV7_DIV       150
+#define CLKID_VDEC_1_SEL          151
+#define CLKID_VDEC_1_DIV          152
+#define CLKID_VDEC_HEVC_SEL       154
+#define CLKID_VDEC_HEVC_DIV       155
 
-#define NR_CLKS                   151
+#define NR_CLKS                   157
 
 /* include the CLKIDs that have been made part of the DT binding */
 #include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
new file mode 100644
index 000000000000..f965845917e3
--- /dev/null
+++ b/drivers/clk/meson/meson-aoclk.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-AXG Clock Controller Driver
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ * Author: Yixun Lan <yixun.lan@amlogic.com>
+ */
+
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include "clk-regmap.h"
+#include "meson-aoclk.h"
+
+static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
+                               unsigned long id)
+{
+        struct meson_aoclk_reset_controller *rstc =
+                container_of(rcdev, struct meson_aoclk_reset_controller, reset);
+
+        return regmap_write(rstc->regmap, rstc->data->reset_reg,
+                            BIT(rstc->data->reset[id]));
+}
+
+static const struct reset_control_ops meson_aoclk_reset_ops = {
+        .reset = meson_aoclk_do_reset,
+};
+
+int meson_aoclkc_probe(struct platform_device *pdev)
+{
+        struct meson_aoclk_reset_controller *rstc;
+        struct meson_aoclk_data *data;
+        struct device *dev = &pdev->dev;
+        struct regmap *regmap;
+        int ret, clkid;
+
+        data = (struct meson_aoclk_data *) of_device_get_match_data(dev);
+        if (!data)
+                return -ENODEV;
+
+        rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
+        if (!rstc)
+                return -ENOMEM;
+
+        regmap = syscon_node_to_regmap(of_get_parent(dev->of_node));
+        if (IS_ERR(regmap)) {
+                dev_err(dev, "failed to get regmap\n");
+                return PTR_ERR(regmap);
+        }
+
+        /* Reset Controller */
+        rstc->data = data;
+        rstc->regmap = regmap;
+        rstc->reset.ops = &meson_aoclk_reset_ops;
+        rstc->reset.nr_resets = data->num_reset,
+        rstc->reset.of_node = dev->of_node;
+        ret = devm_reset_controller_register(dev, &rstc->reset);
+        if (ret) {
+                dev_err(dev, "failed to register reset controller\n");
+                return ret;
+        }
+
+        /*
+         * Populate regmap and register all clks
+         */
+        for (clkid = 0; clkid < data->num_clks; clkid++) {
+                data->clks[clkid]->map = regmap;
+
+                ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
+                if (ret)
+                        return ret;
+        }
+
+        return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+                (void *) data->hw_data);
+}
diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
new file mode 100644
index 000000000000..ab2819e88922
--- /dev/null
+++ b/drivers/clk/meson/meson-aoclk.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2017 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ * Author: Yixun Lan <yixun.lan@amlogic.com>
+ */
+
+#ifndef __MESON_AOCLK_H__
+#define __MESON_AOCLK_H__
+
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include "clk-regmap.h"
+
+struct meson_aoclk_data {
+        const unsigned int                      reset_reg;
+        const int                               num_reset;
+        const unsigned int                      *reset;
+        int                                     num_clks;
+        struct clk_regmap                       **clks;
+        const struct clk_hw_onecell_data        *hw_data;
+};
+
+struct meson_aoclk_reset_controller {
+        struct reset_controller_dev             reset;
+        const struct meson_aoclk_data           *data;
+        struct regmap                           *regmap;
+};
+
+int meson_aoclkc_probe(struct platform_device *pdev);
+#endif
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index d0524ec71aad..7447d96a265f 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1,24 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
- * Driver
- *
  * Copyright (c) 2015 Endless Mobile, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
  *
  * Copyright (c) 2016 BayLibre, Inc.
  * Michael Turquette <mturquette@baylibre.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <linux/clk.h>
@@ -246,6 +232,13 @@ static struct clk_regmap meson8b_fclk_div2 = {
                 .ops = &clk_regmap_gate_ops,
                 .parent_names = (const char *[]){ "fclk_div2_div" },
                 .num_parents = 1,
+                /*
+                 * FIXME: Ethernet with a RGMII PHYs is not working if
+                 * fclk_div2 is disabled. it is currently unclear why this
+                 * is. keep it enabled until the Ethernet driver knows how
+                 * to manage this clock.
+                 */
+                .flags = CLK_IS_CRITICAL,
         },
 };
 
@@ -640,6 +633,54 @@ static struct clk_regmap meson8b_cpu_clk = {
         },
 };
 
+static struct clk_regmap meson8b_nand_clk_sel = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_NAND_CLK_CNTL,
+                .mask = 0x7,
+                .shift = 9,
+                .flags = CLK_MUX_ROUND_CLOSEST,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "nand_clk_sel",
+                .ops = &clk_regmap_mux_ops,
+                /* FIXME all other parents are unknown: */
+                .parent_names = (const char *[]){ "fclk_div4", "fclk_div3",
+                        "fclk_div5", "fclk_div7", "xtal" },
+                .num_parents = 5,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_regmap meson8b_nand_clk_div = {
+        .data = &(struct clk_regmap_div_data){
+                .offset =  HHI_NAND_CLK_CNTL,
+                .shift = 0,
+                .width = 7,
+                .flags = CLK_DIVIDER_ROUND_CLOSEST,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "nand_clk_div",
+                .ops = &clk_regmap_divider_ops,
+                .parent_names = (const char *[]){ "nand_clk_sel" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_regmap meson8b_nand_clk_gate = {
+        .data = &(struct clk_regmap_gate_data){
+                .offset = HHI_NAND_CLK_CNTL,
+                .bit_idx = 8,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "nand_clk_gate",
+                .ops = &clk_regmap_gate_ops,
+                .parent_names = (const char *[]){ "nand_clk_div" },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
 /* Everything Else (EE) domain gates */
 
 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
@@ -835,6 +876,9 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
                 [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
                 [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
                 [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
+                [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
+                [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
+                [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
                 [CLK_NR_CLKS]               = NULL,
         },
         .num = CLK_NR_CLKS,
@@ -940,6 +984,9 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
         &meson8b_fclk_div4,
         &meson8b_fclk_div5,
         &meson8b_fclk_div7,
+        &meson8b_nand_clk_sel,
+        &meson8b_nand_clk_div,
+        &meson8b_nand_clk_gate,
 };
 
 static const struct meson8b_clk_reset_line {
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 6e414bd36981..5d09412b5084 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -1,21 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (c) 2015 Endless Mobile, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
  *
  * Copyright (c) 2016 BayLibre, Inc.
  * Michael Turquette <mturquette@baylibre.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #ifndef __MESON8B_H
@@ -40,6 +29,7 @@
 #define HHI_VID_CLK_CNTL                0x17c /* 0x5f offset in data sheet */
 #define HHI_VID_DIVIDER_CNTL            0x198 /* 0x66 offset in data sheet */
 #define HHI_SYS_CPU_CLK_CNTL0           0x19c /* 0x67 offset in data sheet */
+#define HHI_NAND_CLK_CNTL               0x25c /* 0x97 offset in data sheet */
 #define HHI_MPLL_CNTL                   0x280 /* 0xa0 offset in data sheet */
 #define HHI_SYS_PLL_CNTL                0x300 /* 0xc0 offset in data sheet */
 #define HHI_VID_PLL_CNTL                0x320 /* 0xc8 offset in data sheet */
@@ -83,8 +73,10 @@
 #define CLKID_FCLK_DIV4_DIV     107
 #define CLKID_FCLK_DIV5_DIV     108
 #define CLKID_FCLK_DIV7_DIV     109
+#define CLKID_NAND_SEL          110
+#define CLKID_NAND_DIV          111
 
-#define CLK_NR_CLKS             110
+#define CLK_NR_CLKS             113
 
 /*
  * include the CLKID and RESETID that have
diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c
index 8491979f4096..68f05c53d40e 100644
--- a/drivers/clk/mvebu/clk-corediv.c
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -72,7 +72,7 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = {
 };
 
 static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = {
-        { .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */
+        { .mask = 0x0f, .offset = 6, .fieldbit = 27 }, /* NAND clock */
 };
 
 #define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index fbf4532f94b8..9c3480dcc38a 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -218,6 +218,33 @@ config MSM_MMCC_8996
           Say Y if you want to support multimedia devices such as display,
           graphics, video encode/decode, camera, etc.
 
+config MSM_GCC_8998
+        tristate "MSM8998 Global Clock Controller"
+        depends on COMMON_CLK_QCOM
+        help
+          Support for the global clock controller on msm8998 devices.
+          Say Y if you want to use peripheral devices such as UART, SPI,
+          i2c, USB, UFS, SD/eMMC, PCIe, etc.
+
+config SDM_GCC_845
+        tristate "SDM845 Global Clock Controller"
+        select QCOM_GDSC
+        depends on COMMON_CLK_QCOM
+        help
+          Support for the global clock controller on SDM845 devices.
+          Say Y if you want to use peripheral devices such as UART, SPI,
+          i2C, USB, UFS, SDDC, PCIe, etc.
+
+config SDM_VIDEOCC_845
+        tristate "SDM845 Video Clock Controller"
+        depends on COMMON_CLK_QCOM
+        select SDM_GCC_845
+        select QCOM_GDSC
+        help
+          Support for the video clock controller on SDM845 devices.
+          Say Y if you want to support video devices and functionality such as
+          video encode and decode.
+
 config SPMI_PMIC_CLKDIV
         tristate "SPMI PMIC clkdiv Support"
         depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 230332cf317e..762c01137c2f 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
 obj-$(CONFIG_MSM_GCC_8994) += gcc-msm8994.o
 obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
 obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
+obj-$(CONFIG_MSM_GCC_8998) += gcc-msm8998.o
 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
 obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
@@ -37,4 +38,6 @@ obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
 obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
 obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
 obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
+obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
+obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 6d04cd96482a..3c49a60072f1 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -58,6 +58,8 @@
 #define PLL_TEST_CTL(p)         ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
 #define PLL_TEST_CTL_U(p)       ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
 #define PLL_STATUS(p)           ((p)->offset + (p)->regs[PLL_OFF_STATUS])
+#define PLL_OPMODE(p)           ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
+#define PLL_FRAC(p)             ((p)->offset + (p)->regs[PLL_OFF_FRAC])
 
 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
         [CLK_ALPHA_PLL_TYPE_DEFAULT] =  {
@@ -90,6 +92,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
                 [PLL_OFF_TEST_CTL] = 0x1c,
                 [PLL_OFF_STATUS] = 0x24,
         },
+        [CLK_ALPHA_PLL_TYPE_FABIA] =  {
+                [PLL_OFF_L_VAL] = 0x04,
+                [PLL_OFF_USER_CTL] = 0x0c,
+                [PLL_OFF_USER_CTL_U] = 0x10,
+                [PLL_OFF_CONFIG_CTL] = 0x14,
+                [PLL_OFF_CONFIG_CTL_U] = 0x18,
+                [PLL_OFF_TEST_CTL] = 0x1c,
+                [PLL_OFF_TEST_CTL_U] = 0x20,
+                [PLL_OFF_STATUS] = 0x24,
+                [PLL_OFF_OPMODE] = 0x2c,
+                [PLL_OFF_FRAC] = 0x38,
+        },
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 
@@ -108,6 +122,12 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 #define PLL_HUAYRA_N_MASK               0xff
 #define PLL_HUAYRA_ALPHA_WIDTH          16
 
+#define FABIA_OPMODE_STANDBY    0x0
+#define FABIA_OPMODE_RUN        0x1
+
+#define FABIA_PLL_OUT_MASK      0x7
+#define FABIA_PLL_RATE_MARGIN   500
+
 #define pll_alpha_width(p)                                      \
                 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
                                  ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
@@ -441,16 +461,12 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
         return alpha_pll_calc_rate(prate, l, a, alpha_width);
 }
 
-static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
-                                      int (*is_enabled)(struct clk_hw *))
+
+static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
 {
         int ret;
         u32 mode;
 
-        if (!is_enabled(&pll->clkr.hw) ||
-            !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
-                return 0;
-
         regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
 
         /* Latch the input to the PLL */
@@ -489,6 +505,16 @@ static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
         return 0;
 }
 
+static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
+                                      int (*is_enabled)(struct clk_hw *))
+{
+        if (!is_enabled(&pll->clkr.hw) ||
+            !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
+                return 0;
+
+        return __clk_alpha_pll_update_latch(pll);
+}
+
 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
                                     unsigned long prate,
                                     int (*is_enabled)(struct clk_hw *))
@@ -832,3 +858,265 @@ const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
         .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
+
+void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+                             const struct alpha_pll_config *config)
+{
+        u32 val, mask;
+
+        if (config->l)
+                regmap_write(regmap, PLL_L_VAL(pll), config->l);
+
+        if (config->alpha)
+                regmap_write(regmap, PLL_FRAC(pll), config->alpha);
+
+        if (config->config_ctl_val)
+                regmap_write(regmap, PLL_CONFIG_CTL(pll),
+                                                config->config_ctl_val);
+
+        if (config->post_div_mask) {
+                mask = config->post_div_mask;
+                val = config->post_div_val;
+                regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
+        }
+
+        regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
+                                                        PLL_UPDATE_BYPASS);
+
+        regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
+}
+EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
+
+static int alpha_pll_fabia_enable(struct clk_hw *hw)
+{
+        int ret;
+        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+        u32 val, opmode_val;
+        struct regmap *regmap = pll->clkr.regmap;
+
+        ret = regmap_read(regmap, PLL_MODE(pll), &val);
+        if (ret)
+                return ret;
+
+        /* If in FSM mode, just vote for it */
+        if (val & PLL_VOTE_FSM_ENA) {
+                ret = clk_enable_regmap(hw);
+                if (ret)
+                        return ret;
+                return wait_for_pll_enable_active(pll);
+        }
+
+        ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
+        if (ret)
+                return ret;
+
+        /* Skip If PLL is already running */
+        if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL))
+                return 0;
+
+        ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
+        if (ret)
+                return ret;
+
+        ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
+        if (ret)
+                return ret;
+
+        ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
+                                 PLL_RESET_N);
+        if (ret)
+                return ret;
+
+        ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN);
+        if (ret)
+                return ret;
+
+        ret = wait_for_pll_enable_lock(pll);
+        if (ret)
+                return ret;
+
+        ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
+                                 FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK);
+        if (ret)
+                return ret;
+
+        return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
+                                 PLL_OUTCTRL);
+}
+
+static void alpha_pll_fabia_disable(struct clk_hw *hw)
+{
+        int ret;
+        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+        u32 val;
+        struct regmap *regmap = pll->clkr.regmap;
+
+        ret = regmap_read(regmap, PLL_MODE(pll), &val);
+        if (ret)
+                return;
+
+        /* If in FSM mode, just unvote it */
+        if (val & PLL_FSM_ENA) {
+                clk_disable_regmap(hw);
+                return;
+        }
+
+        ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
+        if (ret)
+                return;
+
+        /* Disable main outputs */
+        ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK,
+                                 0);
+        if (ret)
+                return;
+
+        /* Place the PLL in STANDBY */
+        regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
+}
+
+static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
+                                                unsigned long parent_rate)
+{
+        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+        u32 l, frac, alpha_width = pll_alpha_width(pll);
+
+        regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
+        regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
+
+        return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
+}
+
+static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
+                                                unsigned long prate)
+{
+        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+        u32 val, l, alpha_width = pll_alpha_width(pll);
+        u64 a;
+        unsigned long rrate;
+        int ret = 0;
+
+        ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
+        if (ret)
+                return ret;
+
+        rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
+
+        /*
+         * Due to limited number of bits for fractional rate programming, the
+         * rounded up rate could be marginally higher than the requested rate.
+         */
+        if (rrate > (rate + FABIA_PLL_RATE_MARGIN) || rrate < rate) {
+                pr_err("Call set rate on the PLL with rounded rates!\n");
+                return -EINVAL;
+        }
+
+        regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
+        regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
+
+        return __clk_alpha_pll_update_latch(pll);
+}
+
+const struct clk_ops clk_alpha_pll_fabia_ops = {
+        .enable = alpha_pll_fabia_enable,
+        .disable = alpha_pll_fabia_disable,
+        .is_enabled = clk_alpha_pll_is_enabled,
+        .set_rate = alpha_pll_fabia_set_rate,
+        .recalc_rate = alpha_pll_fabia_recalc_rate,
+        .round_rate = clk_alpha_pll_round_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
+
+const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
+        .enable = alpha_pll_fabia_enable,
+        .disable = alpha_pll_fabia_disable,
+        .is_enabled = clk_alpha_pll_is_enabled,
+        .recalc_rate = alpha_pll_fabia_recalc_rate,
+        .round_rate = clk_alpha_pll_round_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
+
+static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
+                                        unsigned long parent_rate)
+{
+        struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+        u32 i, div = 1, val;
+        int ret;
+
+        if (!pll->post_div_table) {
+                pr_err("Missing the post_div_table for the PLL\n");
+                return -EINVAL;
+        }
+
+        ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
+        if (ret)
+                return ret;
+
+        val >>= pll->post_div_shift;
+        val &= BIT(pll->width) - 1;
+
+        for (i = 0; i < pll->num_post_div; i++) {
+                if (pll->post_div_table[i].val == val) {
+                        div = pll->post_div_table[i].div;
+                        break;
+                }
+        }
+
+        return (parent_rate / div);
+}
+
+static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
+                                unsigned long rate, unsigned long *prate)
+{
+        struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+
+        if (!pll->post_div_table) {
+                pr_err("Missing the post_div_table for the PLL\n");
+                return -EINVAL;
+        }
+
+        return divider_round_rate(hw, rate, prate, pll->post_div_table,
+                                pll->width, CLK_DIVIDER_ROUND_CLOSEST);
+}
+
+static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
+                                unsigned long rate, unsigned long parent_rate)
+{
+        struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+        int i, val = 0, div, ret;
+
+        /*
+         * If the PLL is in FSM mode, then treat set_rate callback as a
+         * no-operation.
+         */
+        ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
+        if (ret)
+                return ret;
+
+        if (val & PLL_VOTE_FSM_ENA)
+                return 0;
+
+        if (!pll->post_div_table) {
+                pr_err("Missing the post_div_table for the PLL\n");
+                return -EINVAL;
+        }
+
+        div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+        for (i = 0; i < pll->num_post_div; i++) {
+                if (pll->post_div_table[i].div == div) {
+                        val = pll->post_div_table[i].val;
+                        break;
+                }
+        }
+
+        return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+                                (BIT(pll->width) - 1) << pll->post_div_shift,
+                                val << pll->post_div_shift);
+}
+
+const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
+        .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
+        .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
+        .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 7593e8a56cf2..f981b486c468 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -22,6 +22,7 @@ enum {
         CLK_ALPHA_PLL_TYPE_DEFAULT,
         CLK_ALPHA_PLL_TYPE_HUAYRA,
         CLK_ALPHA_PLL_TYPE_BRAMMO,
+        CLK_ALPHA_PLL_TYPE_FABIA,
         CLK_ALPHA_PLL_TYPE_MAX,
 };
 
@@ -36,6 +37,8 @@ enum {
         PLL_OFF_TEST_CTL,
         PLL_OFF_TEST_CTL_U,
         PLL_OFF_STATUS,
+        PLL_OFF_OPMODE,
+        PLL_OFF_FRAC,
         PLL_OFF_MAX_REGS
 };
 
@@ -73,6 +76,10 @@ struct clk_alpha_pll {
  * @offset: base address of registers
  * @regs: alpha pll register map (see @clk_alpha_pll_regs)
  * @width: width of post-divider
+ * @post_div_shift: shift to differentiate between odd & even post-divider
+ * @post_div_table: table with PLL odd and even post-divider settings
+ * @num_post_div: Number of PLL post-divider settings
+ *
  * @clkr: regmap clock handle
  */
 struct clk_alpha_pll_postdiv {
@@ -81,6 +88,9 @@ struct clk_alpha_pll_postdiv {
         const u8 *regs;
 
         struct clk_regmap clkr;
+        int post_div_shift;
+        const struct clk_div_table *post_div_table;
+        size_t num_post_div;
 };
 
 struct alpha_pll_config {
@@ -109,7 +119,13 @@ extern const struct clk_ops clk_alpha_pll_postdiv_ops;
 extern const struct clk_ops clk_alpha_pll_huayra_ops;
 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
 
+extern const struct clk_ops clk_alpha_pll_fabia_ops;
+extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
+extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
+
 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
                              const struct alpha_pll_config *config);
+void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+                                const struct alpha_pll_config *config);
 
 #endif
diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c
index 26f7af315066..c58c5538b1b6 100644
--- a/drivers/clk/qcom/clk-branch.c
+++ b/drivers/clk/qcom/clk-branch.c
@@ -77,8 +77,11 @@ static int clk_branch_wait(const struct clk_branch *br, bool enabling,
         bool voted = br->halt_check & BRANCH_VOTED;
         const char *name = clk_hw_get_name(&br->clkr.hw);
 
-        /* Skip checking halt bit if the clock is in hardware gated mode */
-        if (clk_branch_in_hwcg_mode(br))
+        /*
+         * Skip checking halt bit if we're explicitly ignoring the bit or the
+         * clock is in hardware gated mode
+         */
+        if (br->halt_check == BRANCH_HALT_SKIP || clk_branch_in_hwcg_mode(br))
                 return 0;
 
         if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) {
diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h
index 284df3f3c55f..1702efb1c511 100644
--- a/drivers/clk/qcom/clk-branch.h
+++ b/drivers/clk/qcom/clk-branch.h
@@ -42,6 +42,7 @@ struct clk_branch {
 #define BRANCH_HALT_ENABLE              1 /* pol: 0 = halt */
 #define BRANCH_HALT_ENABLE_VOTED        (BRANCH_HALT_ENABLE | BRANCH_VOTED)
 #define BRANCH_HALT_DELAY               2 /* No bit to check; just delay */
+#define BRANCH_HALT_SKIP                3 /* Don't check halt bit */
 
         struct clk_regmap clkr;
 };
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 2a7489a84e69..b209a2fe86b9 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -1,15 +1,5 @@
-/*
- * Copyright (c) 2013, The Linux Foundation. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. */
 
 #ifndef __QCOM_CLK_RCG_H__
 #define __QCOM_CLK_RCG_H__
@@ -144,6 +134,7 @@ extern const struct clk_ops clk_dyn_rcg_ops;
  * @cmd_rcgr: corresponds to *_CMD_RCGR
  * @mnd_width: number of bits in m/n/d values
  * @hid_width: number of bits in half integer divider
+ * @safe_src_index: safe src index value
  * @parent_map: map from software's parent index to hardware's src_sel field
  * @freq_tbl: frequency table
  * @clkr: regmap clock handle
@@ -153,6 +144,7 @@ struct clk_rcg2 {
         u32                     cmd_rcgr;
         u8                      mnd_width;
         u8                      hid_width;
+        u8                      safe_src_index;
         const struct parent_map *parent_map;
         const struct freq_tbl   *freq_tbl;
         struct clk_regmap       clkr;
@@ -167,5 +159,6 @@ extern const struct clk_ops clk_byte_ops;
 extern const struct clk_ops clk_byte2_ops;
 extern const struct clk_ops clk_pixel_ops;
 extern const struct clk_ops clk_gfx3d_ops;
+extern const struct clk_ops clk_rcg2_shared_ops;
 
 #endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index bbeaf9c09dbb..52208d4165f4 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -1,14 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2013, The Linux Foundation. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/kernel.h>
@@ -42,6 +34,7 @@
 #define CFG_MODE_SHIFT          12
 #define CFG_MODE_MASK           (0x3 << CFG_MODE_SHIFT)
 #define CFG_MODE_DUAL_EDGE      (0x2 << CFG_MODE_SHIFT)
+#define CFG_HW_CLK_CTRL_MASK    BIT(20)
 
 #define M_REG                   0x8
 #define N_REG                   0xc
@@ -211,6 +204,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
         clk_flags = clk_hw_get_flags(hw);
         p = clk_hw_get_parent_by_index(hw, index);
         if (clk_flags & CLK_SET_RATE_PARENT) {
+                rate = f->freq;
                 if (f->pre_div) {
                         rate /= 2;
                         rate *= f->pre_div + 1;
@@ -248,7 +242,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
         return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
 }
 
-static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
+static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
 {
         u32 cfg, mask;
         struct clk_hw *hw = &rcg->clkr.hw;
@@ -276,13 +270,21 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
         }
 
         mask = BIT(rcg->hid_width) - 1;
-        mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
+        mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK;
         cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
         cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
         if (rcg->mnd_width && f->n && (f->m != f->n))
                 cfg |= CFG_MODE_DUAL_EDGE;
-        ret = regmap_update_bits(rcg->clkr.regmap,
-                        rcg->cmd_rcgr + CFG_REG, mask, cfg);
+
+        return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
+                                        mask, cfg);
+}
+
+static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
+{
+        int ret;
+
+        ret = __clk_rcg2_configure(rcg, f);
         if (ret)
                 return ret;
 
@@ -789,3 +791,141 @@ const struct clk_ops clk_gfx3d_ops = {
         .determine_rate = clk_gfx3d_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_gfx3d_ops);
+
+static int clk_rcg2_set_force_enable(struct clk_hw *hw)
+{
+        struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+        const char *name = clk_hw_get_name(hw);
+        int ret, count;
+
+        ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
+                                 CMD_ROOT_EN, CMD_ROOT_EN);
+        if (ret)
+                return ret;
+
+        /* wait for RCG to turn ON */
+        for (count = 500; count > 0; count--) {
+                if (clk_rcg2_is_enabled(hw))
+                        return 0;
+
+                udelay(1);
+        }
+
+        pr_err("%s: RCG did not turn on\n", name);
+        return -ETIMEDOUT;
+}
+
+static int clk_rcg2_clear_force_enable(struct clk_hw *hw)
+{
+        struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+
+        return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
+                                        CMD_ROOT_EN, 0);
+}
+
+static int
+clk_rcg2_shared_force_enable_clear(struct clk_hw *hw, const struct freq_tbl *f)
+{
+        struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+        int ret;
+
+        ret = clk_rcg2_set_force_enable(hw);
+        if (ret)
+                return ret;
+
+        ret = clk_rcg2_configure(rcg, f);
+        if (ret)
+                return ret;
+
+        return clk_rcg2_clear_force_enable(hw);
+}
+
+static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,
+                                    unsigned long parent_rate)
+{
+        struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+        const struct freq_tbl *f;
+
+        f = qcom_find_freq(rcg->freq_tbl, rate);
+        if (!f)
+                return -EINVAL;
+
+        /*
+         * In case clock is disabled, update the CFG, M, N and D registers
+         * and don't hit the update bit of CMD register.
+         */
+        if (!__clk_is_enabled(hw->clk))
+                return __clk_rcg2_configure(rcg, f);
+
+        return clk_rcg2_shared_force_enable_clear(hw, f);
+}
+
+static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw,
+                unsigned long rate, unsigned long parent_rate, u8 index)
+{
+        return clk_rcg2_shared_set_rate(hw, rate, parent_rate);
+}
+
+static int clk_rcg2_shared_enable(struct clk_hw *hw)
+{
+        struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+        int ret;
+
+        /*
+         * Set the update bit because required configuration has already
+         * been written in clk_rcg2_shared_set_rate()
+         */
+        ret = clk_rcg2_set_force_enable(hw);
+        if (ret)
+                return ret;
+
+        ret = update_config(rcg);
+        if (ret)
+                return ret;
+
+        return clk_rcg2_clear_force_enable(hw);
+}
+
+static void clk_rcg2_shared_disable(struct clk_hw *hw)
+{
+        struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+        u32 cfg;
+
+        /*
+         * Store current configuration as switching to safe source would clear
+         * the SRC and DIV of CFG register
+         */
+        regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
+
+        /*
+         * Park the RCG at a safe configuration - sourced off of safe source.
+         * Force enable and disable the RCG while configuring it to safeguard
+         * against any update signal coming from the downstream clock.
+         * The current parent is still prepared and enabled at this point, and
+         * the safe source is always on while application processor subsystem
+         * is online. Therefore, the RCG can safely switch its parent.
+         */
+        clk_rcg2_set_force_enable(hw);
+
+        regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
+                     rcg->safe_src_index << CFG_SRC_SEL_SHIFT);
+
+        update_config(rcg);
+
+        clk_rcg2_clear_force_enable(hw);
+
+        /* Write back the stored configuration corresponding to current rate */
+        regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
+}
+
+const struct clk_ops clk_rcg2_shared_ops = {
+        .enable = clk_rcg2_shared_enable,
+        .disable = clk_rcg2_shared_disable,
+        .get_parent = clk_rcg2_get_parent,
+        .set_parent = clk_rcg2_set_parent,
+        .recalc_rate = clk_rcg2_recalc_rate,
+        .determine_rate = clk_rcg2_determine_rate,
+        .set_rate = clk_rcg2_shared_set_rate,
+        .set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
+};
+EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index b8064a336d46..39ce64c2783b 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -228,22 +228,6 @@ int qcom_cc_really_probe(struct platform_device *pdev,
         if (!cc)
                 return -ENOMEM;
 
-        cc->rclks = rclks;
-        cc->num_rclks = num_clks;
-
-        for (i = 0; i < num_clks; i++) {
-                if (!rclks[i])
-                        continue;
-
-                ret = devm_clk_register_regmap(dev, rclks[i]);
-                if (ret)
-                        return ret;
-        }
-
-        ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
-        if (ret)
-                return ret;
-
         reset = &cc->reset;
         reset->rcdev.of_node = dev->of_node;
         reset->rcdev.ops = &qcom_reset_ops;
@@ -272,6 +256,22 @@ int qcom_cc_really_probe(struct platform_device *pdev,
                         return ret;
         }
 
+        cc->rclks = rclks;
+        cc->num_rclks = num_clks;
+
+        for (i = 0; i < num_clks; i++) {
+                if (!rclks[i])
+                        continue;
+
+                ret = devm_clk_register_regmap(dev, rclks[i]);
+                if (ret)
+                        return ret;
+        }
+
+        ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
+        if (ret)
+                return ret;
+
         return 0;
 }
 EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 3d6452932797..9f35b3fe1d97 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -1418,6 +1418,7 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
 
 static struct clk_branch gcc_usb3_phy_pipe_clk = {
         .halt_reg = 0x50004,
+        .halt_check = BRANCH_HALT_SKIP,
         .clkr = {
                 .enable_reg = 0x50004,
                 .enable_mask = BIT(0),
@@ -2472,6 +2473,7 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
 
 static struct clk_branch gcc_pcie_0_pipe_clk = {
         .halt_reg = 0x6b018,
+        .halt_check = BRANCH_HALT_SKIP,
         .clkr = {
                 .enable_reg = 0x6b018,
                 .enable_mask = BIT(0),
@@ -2547,6 +2549,7 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
 
 static struct clk_branch gcc_pcie_1_pipe_clk = {
         .halt_reg = 0x6d018,
+        .halt_check = BRANCH_HALT_SKIP,
         .clkr = {
                 .enable_reg = 0x6d018,
                 .enable_mask = BIT(0),
@@ -2622,6 +2625,7 @@ static struct clk_branch gcc_pcie_2_aux_clk = {
 
 static struct clk_branch gcc_pcie_2_pipe_clk = {
         .halt_reg = 0x6e018,
+        .halt_check = BRANCH_HALT_SKIP,
         .clkr = {
                 .enable_reg = 0x6e018,
                 .enable_mask = BIT(0),
@@ -2792,6 +2796,7 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
 
 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
         .halt_reg = 0x7501c,
+        .halt_check = BRANCH_HALT_SKIP,
         .clkr = {
                 .enable_reg = 0x7501c,
                 .enable_mask = BIT(0),
@@ -2807,6 +2812,7 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
 
 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
         .halt_reg = 0x75020,
+        .halt_check = BRANCH_HALT_SKIP,
         .clkr = {
                 .enable_reg = 0x75020,
                 .enable_mask = BIT(0),
@@ -3105,7 +3111,7 @@ static struct gdsc aggre0_noc_gdsc = {
                 .name = "aggre0_noc",
         },
         .pwrsts = PWRSTS_OFF_ON,
-        .flags = VOTABLE,
+        .flags = VOTABLE | ALWAYS_ON,
 };
 
 static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
new file mode 100644
index 000000000000..78d87f5c7098
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -0,0 +1,2834 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/qcom,gcc-msm8998.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-alpha-pll.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+#include "gdsc.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+        P_AUD_REF_CLK,
+        P_CORE_BI_PLL_TEST_SE,
+        P_GPLL0_OUT_MAIN,
+        P_GPLL4_OUT_MAIN,
+        P_PLL0_EARLY_DIV_CLK_SRC,
+        P_SLEEP_CLK,
+        P_XO,
+};
+
+static const struct parent_map gcc_parent_map_0[] = {
+        { P_XO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_0[] = {
+        "xo",
+        "gpll0_out_main",
+        "gpll0_out_main",
+        "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_1[] = {
+        { P_XO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_1[] = {
+        "xo",
+        "gpll0_out_main",
+        "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_2[] = {
+        { P_XO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_SLEEP_CLK, 5 },
+        { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_2[] = {
+        "xo",
+        "gpll0_out_main",
+        "core_pi_sleep_clk",
+        "gpll0_out_main",
+        "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_3[] = {
+        { P_XO, 0 },
+        { P_SLEEP_CLK, 5 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_3[] = {
+        "xo",
+        "core_pi_sleep_clk",
+        "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_4[] = {
+        { P_XO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_GPLL4_OUT_MAIN, 5 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_4[] = {
+        "xo",
+        "gpll0_out_main",
+        "gpll4_out_main",
+        "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_5[] = {
+        { P_XO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_AUD_REF_CLK, 2 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_5[] = {
+        "xo",
+        "gpll0_out_main",
+        "aud_ref_clk",
+        "core_bi_pll_test_se",
+};
+
+static struct pll_vco fabia_vco[] = {
+        { 250000000, 2000000000, 0 },
+        { 125000000, 1000000000, 1 },
+};
+
+static struct clk_alpha_pll gpll0 = {
+        .offset = 0x0,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .vco_table = fabia_vco,
+        .num_vco = ARRAY_SIZE(fabia_vco),
+        .clkr = {
+                .enable_reg = 0x52000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpll0",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_alpha_pll_ops,
+                }
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll0_out_even = {
+        .offset = 0x0,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll0_out_even",
+                .parent_names = (const char *[]){ "gpll0" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll0_out_main = {
+        .offset = 0x0,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll0_out_main",
+                .parent_names = (const char *[]){ "gpll0" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll0_out_odd = {
+        .offset = 0x0,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll0_out_odd",
+                .parent_names = (const char *[]){ "gpll0" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll0_out_test = {
+        .offset = 0x0,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll0_out_test",
+                .parent_names = (const char *[]){ "gpll0" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll gpll1 = {
+        .offset = 0x1000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .vco_table = fabia_vco,
+        .num_vco = ARRAY_SIZE(fabia_vco),
+        .clkr = {
+                .enable_reg = 0x52000,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpll1",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_alpha_pll_ops,
+                }
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll1_out_even = {
+        .offset = 0x1000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll1_out_even",
+                .parent_names = (const char *[]){ "gpll1" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll1_out_main = {
+        .offset = 0x1000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll1_out_main",
+                .parent_names = (const char *[]){ "gpll1" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll1_out_odd = {
+        .offset = 0x1000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll1_out_odd",
+                .parent_names = (const char *[]){ "gpll1" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll1_out_test = {
+        .offset = 0x1000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll1_out_test",
+                .parent_names = (const char *[]){ "gpll1" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll gpll2 = {
+        .offset = 0x2000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .vco_table = fabia_vco,
+        .num_vco = ARRAY_SIZE(fabia_vco),
+        .clkr = {
+                .enable_reg = 0x52000,
+                .enable_mask = BIT(2),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpll2",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_alpha_pll_ops,
+                }
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll2_out_even = {
+        .offset = 0x2000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll2_out_even",
+                .parent_names = (const char *[]){ "gpll2" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll2_out_main = {
+        .offset = 0x2000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll2_out_main",
+                .parent_names = (const char *[]){ "gpll2" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll2_out_odd = {
+        .offset = 0x2000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll2_out_odd",
+                .parent_names = (const char *[]){ "gpll2" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll2_out_test = {
+        .offset = 0x2000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll2_out_test",
+                .parent_names = (const char *[]){ "gpll2" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll gpll3 = {
+        .offset = 0x3000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .vco_table = fabia_vco,
+        .num_vco = ARRAY_SIZE(fabia_vco),
+        .clkr = {
+                .enable_reg = 0x52000,
+                .enable_mask = BIT(3),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpll3",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_alpha_pll_ops,
+                }
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll3_out_even = {
+        .offset = 0x3000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll3_out_even",
+                .parent_names = (const char *[]){ "gpll3" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll3_out_main = {
+        .offset = 0x3000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll3_out_main",
+                .parent_names = (const char *[]){ "gpll3" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll3_out_odd = {
+        .offset = 0x3000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll3_out_odd",
+                .parent_names = (const char *[]){ "gpll3" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll3_out_test = {
+        .offset = 0x3000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll3_out_test",
+                .parent_names = (const char *[]){ "gpll3" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll gpll4 = {
+        .offset = 0x77000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .vco_table = fabia_vco,
+        .num_vco = ARRAY_SIZE(fabia_vco),
+        .clkr = {
+                .enable_reg = 0x52000,
+                .enable_mask = BIT(4),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpll4",
+                        .parent_names = (const char *[]){ "xo" },
+                        .num_parents = 1,
+                        .ops = &clk_alpha_pll_ops,
+                }
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll4_out_even = {
+        .offset = 0x77000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll4_out_even",
+                .parent_names = (const char *[]){ "gpll4" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll4_out_main = {
+        .offset = 0x77000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll4_out_main",
+                .parent_names = (const char *[]){ "gpll4" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll4_out_odd = {
+        .offset = 0x77000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll4_out_odd",
+                .parent_names = (const char *[]){ "gpll4" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll_postdiv gpll4_out_test = {
+        .offset = 0x77000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll4_out_test",
+                .parent_names = (const char *[]){ "gpll4" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x19020,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup1_i2c_apps_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
+        F(960000, P_XO, 10, 1, 2),
+        F(4800000, P_XO, 4, 0, 0),
+        F(9600000, P_XO, 2, 0, 0),
+        F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
+        F(19200000, P_XO, 1, 0, 0),
+        F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
+        F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+        .cmd_rcgr = 0x1900c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup1_spi_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x1b020,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup2_i2c_apps_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+        .cmd_rcgr = 0x1b00c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup2_spi_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x1d020,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup3_i2c_apps_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+        .cmd_rcgr = 0x1d00c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup3_spi_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x1f020,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup4_i2c_apps_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
+        .cmd_rcgr = 0x1f00c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup4_spi_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x21020,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup5_i2c_apps_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
+        .cmd_rcgr = 0x2100c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup5_spi_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x23020,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup6_i2c_apps_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
+        .cmd_rcgr = 0x2300c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_qup6_spi_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
+        F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625),
+        F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625),
+        F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625),
+        F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15),
+        F(19200000, P_XO, 1, 0, 0),
+        F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
+        F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
+        F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
+        F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
+        F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
+        F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
+        F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
+        F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
+        F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
+        F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+        .cmd_rcgr = 0x1a00c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_uart1_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+        .cmd_rcgr = 0x1c00c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_uart2_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
+        .cmd_rcgr = 0x1e00c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp1_uart3_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x26020,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup1_i2c_apps_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
+        .cmd_rcgr = 0x2600c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup1_spi_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x28020,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup2_i2c_apps_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
+        .cmd_rcgr = 0x2800c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup2_spi_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x2a020,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup3_i2c_apps_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
+        .cmd_rcgr = 0x2a00c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup3_spi_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x2c020,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup4_i2c_apps_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
+        .cmd_rcgr = 0x2c00c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup4_spi_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x2e020,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup5_i2c_apps_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
+        .cmd_rcgr = 0x2e00c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup5_spi_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
+        .cmd_rcgr = 0x30020,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup6_i2c_apps_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
+        .cmd_rcgr = 0x3000c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_qup6_spi_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
+        .cmd_rcgr = 0x2700c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_uart1_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
+        .cmd_rcgr = 0x2900c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_uart2_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
+        .cmd_rcgr = 0x2b00c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "blsp2_uart3_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gp1_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gp1_clk_src = {
+        .cmd_rcgr = 0x64004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_2,
+        .freq_tbl = ftbl_gp1_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gp1_clk_src",
+                .parent_names = gcc_parent_names_2,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gp2_clk_src = {
+        .cmd_rcgr = 0x65004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_2,
+        .freq_tbl = ftbl_gp1_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gp2_clk_src",
+                .parent_names = gcc_parent_names_2,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gp3_clk_src = {
+        .cmd_rcgr = 0x66004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_2,
+        .freq_tbl = ftbl_gp1_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gp3_clk_src",
+                .parent_names = gcc_parent_names_2,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
+        F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 hmss_ahb_clk_src = {
+        .cmd_rcgr = 0x48014,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_hmss_ahb_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "hmss_ahb_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 hmss_rbcpr_clk_src = {
+        .cmd_rcgr = 0x48044,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_hmss_rbcpr_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "hmss_rbcpr_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
+        F(1010526, P_XO, 1, 1, 19),
+        { }
+};
+
+static struct clk_rcg2 pcie_aux_clk_src = {
+        .cmd_rcgr = 0x6c000,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_3,
+        .freq_tbl = ftbl_pcie_aux_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "pcie_aux_clk_src",
+                .parent_names = gcc_parent_names_3,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_pdm2_clk_src[] = {
+        F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 pdm2_clk_src = {
+        .cmd_rcgr = 0x33010,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_pdm2_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "pdm2_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
+        F(144000, P_XO, 16, 3, 25),
+        F(400000, P_XO, 12, 1, 4),
+        F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
+        F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
+        F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 sdcc2_apps_clk_src = {
+        .cmd_rcgr = 0x14010,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_4,
+        .freq_tbl = ftbl_sdcc2_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "sdcc2_apps_clk_src",
+                .parent_names = gcc_parent_names_4,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
+        F(144000, P_XO, 16, 3, 25),
+        F(400000, P_XO, 12, 1, 4),
+        F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
+        F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
+        F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 sdcc4_apps_clk_src = {
+        .cmd_rcgr = 0x16010,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_sdcc4_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "sdcc4_apps_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
+        F(105495, P_XO, 1, 1, 182),
+        { }
+};
+
+static struct clk_rcg2 tsif_ref_clk_src = {
+        .cmd_rcgr = 0x36010,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_5,
+        .freq_tbl = ftbl_tsif_ref_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "tsif_ref_clk_src",
+                .parent_names = gcc_parent_names_5,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+        F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 ufs_axi_clk_src = {
+        .cmd_rcgr = 0x75018,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_ufs_axi_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "ufs_axi_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
+        F(19200000, P_XO, 1, 0, 0),
+        F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
+        F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 usb30_master_clk_src = {
+        .cmd_rcgr = 0xf014,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_usb30_master_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "usb30_master_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 usb30_mock_utmi_clk_src = {
+        .cmd_rcgr = 0xf028,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_hmss_rbcpr_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "usb30_mock_utmi_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
+        F(1200000, P_XO, 16, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 usb3_phy_aux_clk_src = {
+        .cmd_rcgr = 0x5000c,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_3,
+        .freq_tbl = ftbl_usb3_phy_aux_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "usb3_phy_aux_clk_src",
+                .parent_names = gcc_parent_names_3,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_branch gcc_aggre1_noc_xo_clk = {
+        .halt_reg = 0x8202c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8202c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre1_noc_xo_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre1_ufs_axi_clk = {
+        .halt_reg = 0x82028,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x82028,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre1_ufs_axi_clk",
+                        .parent_names = (const char *[]){
+                                "ufs_axi_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre1_usb3_axi_clk = {
+        .halt_reg = 0x82024,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x82024,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre1_usb3_axi_clk",
+                        .parent_names = (const char *[]){
+                                "usb30_master_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = {
+        .halt_reg = 0x48090,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x48090,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_apss_qdss_tsctr_div2_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = {
+        .halt_reg = 0x48094,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x48094,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_apss_qdss_tsctr_div8_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_bimc_hmss_axi_clk = {
+        .halt_reg = 0x48004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(22),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_bimc_hmss_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
+        .halt_reg = 0x4401c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x4401c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_bimc_mss_q6_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+        .halt_reg = 0x17004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(17),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+        .halt_reg = 0x19008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x19008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup1_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup1_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+        .halt_reg = 0x19004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x19004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup1_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup1_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+        .halt_reg = 0x1b008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x1b008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup2_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup2_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+        .halt_reg = 0x1b004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x1b004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup2_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup2_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+        .halt_reg = 0x1d008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x1d008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup3_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup3_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+        .halt_reg = 0x1d004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x1d004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup3_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup3_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
+        .halt_reg = 0x1f008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x1f008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup4_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup4_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
+        .halt_reg = 0x1f004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x1f004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup4_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup4_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
+        .halt_reg = 0x21008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x21008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup5_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup5_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
+        .halt_reg = 0x21004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x21004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup5_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup5_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
+        .halt_reg = 0x23008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x23008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup6_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup6_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
+        .halt_reg = 0x23004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x23004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_qup6_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_qup6_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_sleep_clk = {
+        .halt_reg = 0x17008,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(16),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_sleep_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+        .halt_reg = 0x1a004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x1a004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_uart1_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_uart1_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+        .halt_reg = 0x1c004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x1c004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_uart2_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_uart2_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp1_uart3_apps_clk = {
+        .halt_reg = 0x1e004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x1e004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp1_uart3_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp1_uart3_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_ahb_clk = {
+        .halt_reg = 0x25004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(15),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
+        .halt_reg = 0x26008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x26008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup1_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp2_qup1_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
+        .halt_reg = 0x26004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x26004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup1_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp2_qup1_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
+        .halt_reg = 0x28008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x28008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup2_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp2_qup2_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
+        .halt_reg = 0x28004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x28004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup2_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp2_qup2_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
+        .halt_reg = 0x2a008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x2a008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup3_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp2_qup3_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
+        .halt_reg = 0x2a004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x2a004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup3_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp2_qup3_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
+        .halt_reg = 0x2c008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x2c008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup4_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp2_qup4_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
+        .halt_reg = 0x2c004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x2c004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup4_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp2_qup4_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
+        .halt_reg = 0x2e008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x2e008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup5_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp2_qup5_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
+        .halt_reg = 0x2e004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x2e004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup5_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp2_qup5_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
+        .halt_reg = 0x30008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x30008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup6_i2c_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp2_qup6_i2c_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
+        .halt_reg = 0x30004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x30004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_qup6_spi_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp2_qup6_spi_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_sleep_clk = {
+        .halt_reg = 0x25008,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(14),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_sleep_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_uart1_apps_clk = {
+        .halt_reg = 0x27004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x27004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_uart1_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp2_uart1_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_uart2_apps_clk = {
+        .halt_reg = 0x29004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x29004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_uart2_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp2_uart2_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_blsp2_uart3_apps_clk = {
+        .halt_reg = 0x2b004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x2b004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_blsp2_uart3_apps_clk",
+                        .parent_names = (const char *[]){
+                                "blsp2_uart3_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
+        .halt_reg = 0x5018,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x5018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_cfg_noc_usb3_axi_clk",
+                        .parent_names = (const char *[]){
+                                "usb30_master_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+        .halt_reg = 0x64000,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x64000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gp1_clk",
+                        .parent_names = (const char *[]){
+                                "gp1_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+        .halt_reg = 0x65000,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x65000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gp2_clk",
+                        .parent_names = (const char *[]){
+                                "gp2_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+        .halt_reg = 0x66000,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x66000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gp3_clk",
+                        .parent_names = (const char *[]){
+                                "gp3_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gpu_bimc_gfx_clk = {
+        .halt_reg = 0x71010,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x71010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gpu_bimc_gfx_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
+        .halt_reg = 0x7100c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x7100c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gpu_bimc_gfx_src_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gpu_cfg_ahb_clk = {
+        .halt_reg = 0x71004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x71004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gpu_cfg_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
+        .halt_reg = 0x71018,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x71018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gpu_snoc_dvm_gfx_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_hmss_ahb_clk = {
+        .halt_reg = 0x48000,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(21),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_hmss_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "hmss_ahb_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_hmss_at_clk = {
+        .halt_reg = 0x48010,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x48010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_hmss_at_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_hmss_dvm_bus_clk = {
+        .halt_reg = 0x4808c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x4808c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_hmss_dvm_bus_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_hmss_rbcpr_clk = {
+        .halt_reg = 0x48008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x48008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_hmss_rbcpr_clk",
+                        .parent_names = (const char *[]){
+                                "hmss_rbcpr_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_hmss_trig_clk = {
+        .halt_reg = 0x4800c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x4800c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_hmss_trig_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_lpass_at_clk = {
+        .halt_reg = 0x47020,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x47020,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_lpass_at_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_lpass_trig_clk = {
+        .halt_reg = 0x4701c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x4701c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_lpass_trig_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
+        .halt_reg = 0x9004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x9004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mmss_noc_cfg_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mmss_qm_ahb_clk = {
+        .halt_reg = 0x9030,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x9030,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mmss_qm_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mmss_qm_core_clk = {
+        .halt_reg = 0x900c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x900c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mmss_qm_core_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
+        .halt_reg = 0x9000,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x9000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mmss_sys_noc_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mss_at_clk = {
+        .halt_reg = 0x8a00c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8a00c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mss_at_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_aux_clk = {
+        .halt_reg = 0x6b014,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x6b014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_aux_clk",
+                        .parent_names = (const char *[]){
+                                "pcie_aux_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
+        .halt_reg = 0x6b010,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x6b010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_cfg_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
+        .halt_reg = 0x6b00c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x6b00c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_mstr_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_pipe_clk = {
+        .halt_reg = 0x6b018,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x6b018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_pipe_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_slv_axi_clk = {
+        .halt_reg = 0x6b008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x6b008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_slv_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_phy_aux_clk = {
+        .halt_reg = 0x6f004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x6f004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_phy_aux_clk",
+                        .parent_names = (const char *[]){
+                                "pcie_aux_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+        .halt_reg = 0x3300c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x3300c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pdm2_clk",
+                        .parent_names = (const char *[]){
+                                "pdm2_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pdm_ahb_clk = {
+        .halt_reg = 0x33004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x33004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pdm_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pdm_xo4_clk = {
+        .halt_reg = 0x33008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x33008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pdm_xo4_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+        .halt_reg = 0x34004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(13),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_prng_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc2_ahb_clk = {
+        .halt_reg = 0x14008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x14008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc2_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+        .halt_reg = 0x14004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x14004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc2_apps_clk",
+                        .parent_names = (const char *[]){
+                                "sdcc2_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc4_ahb_clk = {
+        .halt_reg = 0x16008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x16008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc4_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc4_apps_clk = {
+        .halt_reg = 0x16004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x16004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc4_apps_clk",
+                        .parent_names = (const char *[]){
+                                "sdcc4_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_tsif_ahb_clk = {
+        .halt_reg = 0x36004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x36004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_tsif_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_tsif_inactivity_timers_clk = {
+        .halt_reg = 0x3600c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x3600c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_tsif_inactivity_timers_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_tsif_ref_clk = {
+        .halt_reg = 0x36008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x36008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_tsif_ref_clk",
+                        .parent_names = (const char *[]){
+                                "tsif_ref_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_ahb_clk = {
+        .halt_reg = 0x7500c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x7500c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_axi_clk = {
+        .halt_reg = 0x75008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x75008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_axi_clk",
+                        .parent_names = (const char *[]){
+                                "ufs_axi_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_ice_core_clk = {
+        .halt_reg = 0x7600c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x7600c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_ice_core_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_aux_clk = {
+        .halt_reg = 0x76040,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x76040,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_aux_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
+        .halt_reg = 0x75014,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x75014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_rx_symbol_0_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
+        .halt_reg = 0x7605c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x7605c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_rx_symbol_1_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
+        .halt_reg = 0x75010,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x75010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_tx_symbol_0_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_unipro_core_clk = {
+        .halt_reg = 0x76008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x76008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_unipro_core_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_master_clk = {
+        .halt_reg = 0xf008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xf008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_master_clk",
+                        .parent_names = (const char *[]){
+                                "usb30_master_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_mock_utmi_clk = {
+        .halt_reg = 0xf010,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xf010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_mock_utmi_clk",
+                        .parent_names = (const char *[]){
+                                "usb30_mock_utmi_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_sleep_clk = {
+        .halt_reg = 0xf00c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xf00c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_sleep_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_phy_aux_clk = {
+        .halt_reg = 0x50000,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x50000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_phy_aux_clk",
+                        .parent_names = (const char *[]){
+                                "usb3_phy_aux_clk_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_phy_pipe_clk = {
+        .halt_reg = 0x50004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x50004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_phy_pipe_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
+        .halt_reg = 0x6a004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x6a004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb_phy_cfg_ahb2phy_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct gdsc pcie_0_gdsc = {
+        .gdscr = 0x6b004,
+        .gds_hw_ctrl = 0x0,
+        .pd = {
+                .name = "pcie_0_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+        .flags = VOTABLE,
+};
+
+static struct gdsc ufs_gdsc = {
+        .gdscr = 0x75004,
+        .gds_hw_ctrl = 0x0,
+        .pd = {
+                .name = "ufs_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+        .flags = VOTABLE,
+};
+
+static struct gdsc usb_30_gdsc = {
+        .gdscr = 0xf004,
+        .gds_hw_ctrl = 0x0,
+        .pd = {
+                .name = "usb_30_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+        .flags = VOTABLE,
+};
+
+static struct clk_regmap *gcc_msm8998_clocks[] = {
+        [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+        [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+        [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+        [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+        [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+        [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+        [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
+        [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
+        [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
+        [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
+        [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
+        [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
+        [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+        [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+        [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
+        [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
+        [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
+        [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
+        [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
+        [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
+        [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
+        [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
+        [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
+        [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
+        [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
+        [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
+        [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
+        [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
+        [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
+        [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
+        [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr,
+        [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr,
+        [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr,
+        [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr,
+        [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr,
+        [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
+        [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
+        [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+        [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+        [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+        [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+        [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
+        [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
+        [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
+        [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
+        [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
+        [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
+        [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+        [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+        [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
+        [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
+        [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
+        [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
+        [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
+        [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
+        [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
+        [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
+        [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
+        [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
+        [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
+        [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
+        [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
+        [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
+        [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
+        [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
+        [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
+        [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
+        [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
+        [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+        [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+        [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+        [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
+        [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
+        [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
+        [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
+        [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
+        [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
+        [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
+        [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
+        [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,
+        [GCC_LPASS_AT_CLK] = &gcc_lpass_at_clk.clkr,
+        [GCC_LPASS_TRIG_CLK] = &gcc_lpass_trig_clk.clkr,
+        [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
+        [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,
+        [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,
+        [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
+        [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr,
+        [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
+        [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
+        [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
+        [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
+        [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
+        [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
+        [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+        [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+        [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
+        [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+        [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+        [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+        [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
+        [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
+        [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
+        [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
+        [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
+        [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
+        [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
+        [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
+        [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
+        [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
+        [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
+        [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
+        [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
+        [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
+        [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
+        [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
+        [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
+        [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
+        [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
+        [GP1_CLK_SRC] = &gp1_clk_src.clkr,
+        [GP2_CLK_SRC] = &gp2_clk_src.clkr,
+        [GP3_CLK_SRC] = &gp3_clk_src.clkr,
+        [GPLL0] = &gpll0.clkr,
+        [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
+        [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
+        [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
+        [GPLL0_OUT_TEST] = &gpll0_out_test.clkr,
+        [GPLL1] = &gpll1.clkr,
+        [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr,
+        [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
+        [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr,
+        [GPLL1_OUT_TEST] = &gpll1_out_test.clkr,
+        [GPLL2] = &gpll2.clkr,
+        [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr,
+        [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
+        [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr,
+        [GPLL2_OUT_TEST] = &gpll2_out_test.clkr,
+        [GPLL3] = &gpll3.clkr,
+        [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
+        [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
+        [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr,
+        [GPLL3_OUT_TEST] = &gpll3_out_test.clkr,
+        [GPLL4] = &gpll4.clkr,
+        [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,
+        [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
+        [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr,
+        [GPLL4_OUT_TEST] = &gpll4_out_test.clkr,
+        [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr,
+        [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
+        [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
+        [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
+        [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
+        [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
+        [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
+        [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
+        [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
+        [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
+        [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
+};
+
+static struct gdsc *gcc_msm8998_gdscs[] = {
+        [PCIE_0_GDSC] = &pcie_0_gdsc,
+        [UFS_GDSC] = &ufs_gdsc,
+        [USB_30_GDSC] = &usb_30_gdsc,
+};
+
+static const struct qcom_reset_map gcc_msm8998_resets[] = {
+        [GCC_BLSP1_QUP1_BCR] = { 0x102400 },
+        [GCC_BLSP1_QUP2_BCR] = { 0x110592 },
+        [GCC_BLSP1_QUP3_BCR] = { 0x118784 },
+        [GCC_BLSP1_QUP4_BCR] = { 0x126976 },
+        [GCC_BLSP1_QUP5_BCR] = { 0x135168 },
+        [GCC_BLSP1_QUP6_BCR] = { 0x143360 },
+        [GCC_BLSP2_QUP1_BCR] = { 0x155648 },
+        [GCC_BLSP2_QUP2_BCR] = { 0x163840 },
+        [GCC_BLSP2_QUP3_BCR] = { 0x172032 },
+        [GCC_BLSP2_QUP4_BCR] = { 0x180224 },
+        [GCC_BLSP2_QUP5_BCR] = { 0x188416 },
+        [GCC_BLSP2_QUP6_BCR] = { 0x196608 },
+        [GCC_PCIE_0_BCR] = { 0x438272 },
+        [GCC_PDM_BCR] = { 0x208896 },
+        [GCC_SDCC2_BCR] = { 0x81920 },
+        [GCC_SDCC4_BCR] = { 0x90112 },
+        [GCC_TSIF_BCR] = { 0x221184 },
+        [GCC_UFS_BCR] = { 0x479232 },
+        [GCC_USB_30_BCR] = { 0x61440 },
+};
+
+static const struct regmap_config gcc_msm8998_regmap_config = {
+        .reg_bits       = 32,
+        .reg_stride     = 4,
+        .val_bits       = 32,
+        .max_register   = 0x8f000,
+        .fast_io        = true,
+};
+
+static const struct qcom_cc_desc gcc_msm8998_desc = {
+        .config = &gcc_msm8998_regmap_config,
+        .clks = gcc_msm8998_clocks,
+        .num_clks = ARRAY_SIZE(gcc_msm8998_clocks),
+        .resets = gcc_msm8998_resets,
+        .num_resets = ARRAY_SIZE(gcc_msm8998_resets),
+        .gdscs = gcc_msm8998_gdscs,
+        .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
+};
+
+static int gcc_msm8998_probe(struct platform_device *pdev)
+{
+        struct regmap *regmap;
+        int ret;
+
+        regmap = qcom_cc_map(pdev, &gcc_msm8998_desc);
+        if (IS_ERR(regmap))
+                return PTR_ERR(regmap);
+
+        /*
+         * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
+         * turned off by hardware during certain apps low power modes.
+         */
+        ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
+        if (ret)
+                return ret;
+
+        return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
+}
+
+static const struct of_device_id gcc_msm8998_match_table[] = {
+        { .compatible = "qcom,gcc-msm8998" },
+        { }
+};
+MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table);
+
+static struct platform_driver gcc_msm8998_driver = {
+        .probe          = gcc_msm8998_probe,
+        .driver         = {
+                .name   = "gcc-msm8998",
+                .of_match_table = gcc_msm8998_match_table,
+        },
+};
+
+static int __init gcc_msm8998_init(void)
+{
+        return platform_driver_register(&gcc_msm8998_driver);
+}
+core_initcall(gcc_msm8998_init);
+
+static void __exit gcc_msm8998_exit(void)
+{
+        platform_driver_unregister(&gcc_msm8998_driver);
+}
+module_exit(gcc_msm8998_exit);
+
+MODULE_DESCRIPTION("QCOM GCC msm8998 Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:gcc-msm8998");
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
new file mode 100644
index 000000000000..e78e6f5b99fc
--- /dev/null
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -0,0 +1,3465 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "clk-alpha-pll.h"
+#include "gdsc.h"
+#include "reset.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+        P_BI_TCXO,
+        P_AUD_REF_CLK,
+        P_CORE_BI_PLL_TEST_SE,
+        P_GPLL0_OUT_EVEN,
+        P_GPLL0_OUT_MAIN,
+        P_GPLL4_OUT_MAIN,
+        P_SLEEP_CLK,
+};
+
+static const struct parent_map gcc_parent_map_0[] = {
+        { P_BI_TCXO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_GPLL0_OUT_EVEN, 6 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_0[] = {
+        "bi_tcxo",
+        "gpll0",
+        "gpll0_out_even",
+        "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_1[] = {
+        { P_BI_TCXO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_SLEEP_CLK, 5 },
+        { P_GPLL0_OUT_EVEN, 6 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_1[] = {
+        "bi_tcxo",
+        "gpll0",
+        "core_pi_sleep_clk",
+        "gpll0_out_even",
+        "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_2[] = {
+        { P_BI_TCXO, 0 },
+        { P_SLEEP_CLK, 5 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_2[] = {
+        "bi_tcxo",
+        "core_pi_sleep_clk",
+        "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_3[] = {
+        { P_BI_TCXO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_3[] = {
+        "bi_tcxo",
+        "gpll0",
+        "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_4[] = {
+        { P_BI_TCXO, 0 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_4[] = {
+        "bi_tcxo",
+        "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_5[] = {
+        { P_BI_TCXO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_GPLL4_OUT_MAIN, 5 },
+        { P_GPLL0_OUT_EVEN, 6 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_5[] = {
+        "bi_tcxo",
+        "gpll0",
+        "gpll4",
+        "gpll0_out_even",
+        "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_6[] = {
+        { P_BI_TCXO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_AUD_REF_CLK, 2 },
+        { P_GPLL0_OUT_EVEN, 6 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_6[] = {
+        "bi_tcxo",
+        "gpll0",
+        "aud_ref_clk",
+        "gpll0_out_even",
+        "core_bi_pll_test_se",
+};
+
+static const char * const gcc_parent_names_7[] = {
+        "bi_tcxo",
+        "gpll0",
+        "gpll0_out_even",
+        "core_bi_pll_test_se",
+};
+
+static const char * const gcc_parent_names_8[] = {
+        "bi_tcxo",
+        "gpll0",
+        "core_bi_pll_test_se",
+};
+
+static const struct parent_map gcc_parent_map_10[] = {
+        { P_BI_TCXO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_GPLL4_OUT_MAIN, 5 },
+        { P_GPLL0_OUT_EVEN, 6 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const char * const gcc_parent_names_10[] = {
+        "bi_tcxo",
+        "gpll0",
+        "gpll4",
+        "gpll0_out_even",
+        "core_bi_pll_test_se",
+};
+
+static struct clk_alpha_pll gpll0 = {
+        .offset = 0x0,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+        .clkr = {
+                .enable_reg = 0x52000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpll0",
+                        .parent_names = (const char *[]){ "bi_tcxo" },
+                        .num_parents = 1,
+                        .ops = &clk_alpha_pll_fixed_fabia_ops,
+                },
+        },
+};
+
+static struct clk_alpha_pll gpll4 = {
+        .offset = 0x76000,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+        .clkr = {
+                .enable_reg = 0x52000,
+                .enable_mask = BIT(4),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpll4",
+                        .parent_names = (const char *[]){ "bi_tcxo" },
+                        .num_parents = 1,
+                        .ops = &clk_alpha_pll_fixed_fabia_ops,
+                },
+        },
+};
+
+static const struct clk_div_table post_div_table_fabia_even[] = {
+        { 0x0, 1 },
+        { 0x1, 2 },
+        { 0x3, 4 },
+        { 0x7, 8 },
+        { }
+};
+
+static struct clk_alpha_pll_postdiv gpll0_out_even = {
+        .offset = 0x0,
+        .post_div_shift = 8,
+        .post_div_table = post_div_table_fabia_even,
+        .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
+        .width = 4,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll0_out_even",
+                .parent_names = (const char *[]){ "gpll0" },
+                .num_parents = 1,
+                .ops = &clk_alpha_pll_postdiv_fabia_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
+        .cmd_rcgr = 0x48014,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_cpuss_ahb_clk_src",
+                .parent_names = gcc_parent_names_7,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
+        .cmd_rcgr = 0x4815c,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_3,
+        .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_cpuss_rbcpr_clk_src",
+                .parent_names = gcc_parent_names_8,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
+        F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_gp1_clk_src = {
+        .cmd_rcgr = 0x64004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_gcc_gp1_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_gp1_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_gp2_clk_src = {
+        .cmd_rcgr = 0x65004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_gcc_gp1_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_gp2_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_gp3_clk_src = {
+        .cmd_rcgr = 0x66004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_gcc_gp1_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_gp3_clk_src",
+                .parent_names = gcc_parent_names_1,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
+        F(9600000, P_BI_TCXO, 2, 0, 0),
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
+        .cmd_rcgr = 0x6b028,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_2,
+        .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_pcie_0_aux_clk_src",
+                .parent_names = gcc_parent_names_2,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
+        .cmd_rcgr = 0x8d028,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_2,
+        .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_pcie_1_aux_clk_src",
+                .parent_names = gcc_parent_names_2,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
+        .cmd_rcgr = 0x6f014,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_pcie_phy_refgen_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
+        F(9600000, P_BI_TCXO, 2, 0, 0),
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_pdm2_clk_src = {
+        .cmd_rcgr = 0x33010,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_pdm2_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_pdm2_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
+        F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
+        F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
+        F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
+        F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
+        F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
+        F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
+        F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
+        F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
+        F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
+        F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
+        F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
+        F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
+        F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
+        { }
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
+        .cmd_rcgr = 0x17034,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s0_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
+        .cmd_rcgr = 0x17164,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s1_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
+        .cmd_rcgr = 0x17294,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s2_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
+        .cmd_rcgr = 0x173c4,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s3_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
+        .cmd_rcgr = 0x174f4,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s4_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
+        .cmd_rcgr = 0x17624,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s5_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
+        .cmd_rcgr = 0x17754,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s6_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
+        .cmd_rcgr = 0x17884,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s7_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
+        .cmd_rcgr = 0x18018,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap1_s0_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
+        .cmd_rcgr = 0x18148,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap1_s1_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
+        .cmd_rcgr = 0x18278,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap1_s2_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
+        .cmd_rcgr = 0x183a8,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap1_s3_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
+        .cmd_rcgr = 0x184d8,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap1_s4_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
+        .cmd_rcgr = 0x18608,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap1_s5_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
+        .cmd_rcgr = 0x18738,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap1_s6_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
+        .cmd_rcgr = 0x18868,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap1_s7_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+        F(400000, P_BI_TCXO, 12, 1, 4),
+        F(9600000, P_BI_TCXO, 2, 0, 0),
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
+        F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
+        .cmd_rcgr = 0x1400c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_10,
+        .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_sdcc2_apps_clk_src",
+                .parent_names = gcc_parent_names_10,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
+        F(400000, P_BI_TCXO, 12, 1, 4),
+        F(9600000, P_BI_TCXO, 2, 0, 0),
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
+        F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
+        .cmd_rcgr = 0x1600c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_sdcc4_apps_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
+        F(105495, P_BI_TCXO, 2, 1, 91),
+        { }
+};
+
+static struct clk_rcg2 gcc_tsif_ref_clk_src = {
+        .cmd_rcgr = 0x36010,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_6,
+        .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_tsif_ref_clk_src",
+                .parent_names = gcc_parent_names_6,
+                .num_parents = 5,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
+        F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
+        F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+        F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
+        .cmd_rcgr = 0x7501c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_card_axi_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
+        F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
+        F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
+        F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+        F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
+        .cmd_rcgr = 0x7505c,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_card_ice_core_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
+        .cmd_rcgr = 0x75090,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_4,
+        .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_card_phy_aux_clk_src",
+                .parent_names = gcc_parent_names_4,
+                .num_parents = 2,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
+        F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
+        F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
+        F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
+        .cmd_rcgr = 0x75074,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_card_unipro_core_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
+        F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
+        F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+        F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
+        .cmd_rcgr = 0x7701c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_phy_axi_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
+        .cmd_rcgr = 0x7705c,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_phy_ice_core_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
+        .cmd_rcgr = 0x77090,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_4,
+        .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_phy_phy_aux_clk_src",
+                .parent_names = gcc_parent_names_4,
+                .num_parents = 2,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
+        .cmd_rcgr = 0x77074,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_phy_unipro_core_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+        F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
+        F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
+        F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
+        F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+        F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
+        .cmd_rcgr = 0xf018,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_usb30_prim_master_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
+        F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
+        F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
+        .cmd_rcgr = 0xf030,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_usb30_prim_mock_utmi_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
+        .cmd_rcgr = 0x10018,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_usb30_sec_master_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
+        .cmd_rcgr = 0x10030,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_usb30_sec_mock_utmi_clk_src",
+                .parent_names = gcc_parent_names_0,
+                .num_parents = 4,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
+        .cmd_rcgr = 0xf05c,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_2,
+        .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_usb3_prim_phy_aux_clk_src",
+                .parent_names = gcc_parent_names_2,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
+        .cmd_rcgr = 0x1005c,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_2,
+        .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_usb3_sec_phy_aux_clk_src",
+                .parent_names = gcc_parent_names_2,
+                .num_parents = 3,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
+        .cmd_rcgr = 0x7a030,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_3,
+        .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_vs_ctrl_clk_src",
+                .parent_names = gcc_parent_names_3,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
+        F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_vsensor_clk_src = {
+        .cmd_rcgr = 0x7a018,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_3,
+        .freq_tbl = ftbl_gcc_vsensor_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_vsensor_clk_src",
+                .parent_names = gcc_parent_names_8,
+                .num_parents = 3,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
+        .halt_reg = 0x90014,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x90014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre_noc_pcie_tbu_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
+        .halt_reg = 0x82028,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x82028,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x82028,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre_ufs_card_axi_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_ufs_card_axi_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
+        .halt_reg = 0x82024,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x82024,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x82024,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre_ufs_phy_axi_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_ufs_phy_axi_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
+        .halt_reg = 0x8201c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8201c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre_usb3_prim_axi_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_usb30_prim_master_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
+        .halt_reg = 0x82020,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x82020,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre_usb3_sec_axi_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_usb30_sec_master_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_apc_vs_clk = {
+        .halt_reg = 0x7a050,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x7a050,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_apc_vs_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_vsensor_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_boot_rom_ahb_clk = {
+        .halt_reg = 0x38004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x38004,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(10),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_boot_rom_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camera_ahb_clk = {
+        .halt_reg = 0xb008,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0xb008,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0xb008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camera_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camera_axi_clk = {
+        .halt_reg = 0xb020,
+        .halt_check = BRANCH_VOTED,
+        .clkr = {
+                .enable_reg = 0xb020,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camera_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camera_xo_clk = {
+        .halt_reg = 0xb02c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xb02c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camera_xo_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ce1_ahb_clk = {
+        .halt_reg = 0x4100c,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x4100c,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(3),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ce1_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ce1_axi_clk = {
+        .halt_reg = 0x41008,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(4),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ce1_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ce1_clk = {
+        .halt_reg = 0x41004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(5),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ce1_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
+        .halt_reg = 0x502c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x502c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_cfg_noc_usb3_prim_axi_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_usb30_prim_master_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
+        .halt_reg = 0x5030,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x5030,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_cfg_noc_usb3_sec_axi_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_usb30_sec_master_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_cpuss_ahb_clk = {
+        .halt_reg = 0x48000,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(21),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_cpuss_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_cpuss_ahb_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_cpuss_rbcpr_clk = {
+        .halt_reg = 0x48008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x48008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_cpuss_rbcpr_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_cpuss_rbcpr_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ddrss_gpu_axi_clk = {
+        .halt_reg = 0x44038,
+        .halt_check = BRANCH_VOTED,
+        .clkr = {
+                .enable_reg = 0x44038,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ddrss_gpu_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_disp_ahb_clk = {
+        .halt_reg = 0xb00c,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0xb00c,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0xb00c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_disp_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_disp_axi_clk = {
+        .halt_reg = 0xb024,
+        .halt_check = BRANCH_VOTED,
+        .clkr = {
+                .enable_reg = 0xb024,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_disp_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_disp_gpll0_clk_src = {
+        .halt_check = BRANCH_HALT_DELAY,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(18),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_disp_gpll0_clk_src",
+                        .parent_names = (const char *[]){
+                                "gpll0",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_disp_gpll0_div_clk_src = {
+        .halt_check = BRANCH_HALT_DELAY,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(19),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_disp_gpll0_div_clk_src",
+                        .parent_names = (const char *[]){
+                                "gpll0_out_even",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_disp_xo_clk = {
+        .halt_reg = 0xb030,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xb030,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_disp_xo_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+        .halt_reg = 0x64000,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x64000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gp1_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_gp1_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+        .halt_reg = 0x65000,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x65000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gp2_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_gp2_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+        .halt_reg = 0x66000,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x66000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gp3_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_gp3_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gpu_cfg_ahb_clk = {
+        .halt_reg = 0x71004,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x71004,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x71004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gpu_cfg_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gpu_gpll0_clk_src = {
+        .halt_check = BRANCH_HALT_DELAY,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(15),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gpu_gpll0_clk_src",
+                        .parent_names = (const char *[]){
+                                "gpll0",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
+        .halt_check = BRANCH_HALT_DELAY,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(16),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gpu_gpll0_div_clk_src",
+                        .parent_names = (const char *[]){
+                                "gpll0_out_even",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gpu_iref_clk = {
+        .halt_reg = 0x8c010,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8c010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gpu_iref_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
+        .halt_reg = 0x7100c,
+        .halt_check = BRANCH_VOTED,
+        .clkr = {
+                .enable_reg = 0x7100c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gpu_memnoc_gfx_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
+        .halt_reg = 0x71018,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x71018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gpu_snoc_dvm_gfx_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gpu_vs_clk = {
+        .halt_reg = 0x7a04c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x7a04c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gpu_vs_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_vsensor_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mss_axis2_clk = {
+        .halt_reg = 0x8a008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8a008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mss_axis2_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mss_cfg_ahb_clk = {
+        .halt_reg = 0x8a000,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x8a000,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x8a000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mss_cfg_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mss_gpll0_div_clk_src = {
+        .halt_check = BRANCH_HALT_DELAY,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(17),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mss_gpll0_div_clk_src",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mss_mfab_axis_clk = {
+        .halt_reg = 0x8a004,
+        .halt_check = BRANCH_VOTED,
+        .hwcg_reg = 0x8a004,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x8a004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mss_mfab_axis_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
+        .halt_reg = 0x8a154,
+        .halt_check = BRANCH_VOTED,
+        .clkr = {
+                .enable_reg = 0x8a154,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mss_q6_memnoc_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mss_snoc_axi_clk = {
+        .halt_reg = 0x8a150,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8a150,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mss_snoc_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_mss_vs_clk = {
+        .halt_reg = 0x7a048,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x7a048,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_mss_vs_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_vsensor_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_aux_clk = {
+        .halt_reg = 0x6b01c,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(3),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_aux_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_pcie_0_aux_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
+        .halt_reg = 0x6b018,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x6b018,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(2),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_cfg_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_clkref_clk = {
+        .halt_reg = 0x8c00c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8c00c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_clkref_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
+        .halt_reg = 0x6b014,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_mstr_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_pipe_clk = {
+        .halt_check = BRANCH_HALT_SKIP,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(4),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_pipe_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_slv_axi_clk = {
+        .halt_reg = 0x6b010,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x6b010,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_slv_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
+        .halt_reg = 0x6b00c,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(5),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_slv_q2a_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_aux_clk = {
+        .halt_reg = 0x8d01c,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(29),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_aux_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_pcie_1_aux_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
+        .halt_reg = 0x8d018,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x8d018,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(28),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_cfg_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_clkref_clk = {
+        .halt_reg = 0x8c02c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8c02c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_clkref_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
+        .halt_reg = 0x8d014,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(27),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_mstr_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_pipe_clk = {
+        .halt_check = BRANCH_HALT_SKIP,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(30),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_pipe_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_slv_axi_clk = {
+        .halt_reg = 0x8d010,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x8d010,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(26),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_slv_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
+        .halt_reg = 0x8d00c,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(25),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_slv_q2a_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_phy_aux_clk = {
+        .halt_reg = 0x6f004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x6f004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_phy_aux_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_pcie_0_aux_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_phy_refgen_clk = {
+        .halt_reg = 0x6f02c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x6f02c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_phy_refgen_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_pcie_phy_refgen_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+        .halt_reg = 0x3300c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x3300c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pdm2_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_pdm2_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pdm_ahb_clk = {
+        .halt_reg = 0x33004,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x33004,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x33004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pdm_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pdm_xo4_clk = {
+        .halt_reg = 0x33008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x33008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pdm_xo4_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+        .halt_reg = 0x34004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x34004,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(13),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_prng_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qmip_camera_ahb_clk = {
+        .halt_reg = 0xb014,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0xb014,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0xb014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qmip_camera_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qmip_disp_ahb_clk = {
+        .halt_reg = 0xb018,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0xb018,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0xb018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qmip_disp_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qmip_video_ahb_clk = {
+        .halt_reg = 0xb010,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0xb010,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0xb010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qmip_video_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
+        .halt_reg = 0x17030,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(10),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s0_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap0_s0_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
+        .halt_reg = 0x17160,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(11),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s1_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap0_s1_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
+        .halt_reg = 0x17290,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(12),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s2_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap0_s2_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
+        .halt_reg = 0x173c0,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(13),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s3_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap0_s3_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
+        .halt_reg = 0x174f0,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(14),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s4_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap0_s4_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
+        .halt_reg = 0x17620,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(15),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s5_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap0_s5_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
+        .halt_reg = 0x17750,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(16),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s6_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap0_s6_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
+        .halt_reg = 0x17880,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(17),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s7_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap0_s7_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
+        .halt_reg = 0x18014,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(22),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap1_s0_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap1_s0_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
+        .halt_reg = 0x18144,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(23),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap1_s1_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap1_s1_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
+        .halt_reg = 0x18274,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(24),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap1_s2_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap1_s2_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
+        .halt_reg = 0x183a4,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(25),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap1_s3_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap1_s3_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
+        .halt_reg = 0x184d4,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(26),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap1_s4_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap1_s4_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
+        .halt_reg = 0x18604,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(27),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap1_s5_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap1_s5_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
+        .halt_reg = 0x18734,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(28),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap1_s6_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap1_s6_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
+        .halt_reg = 0x18864,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(29),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap1_s7_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_qupv3_wrap1_s7_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
+        .halt_reg = 0x17004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(6),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap_0_m_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
+        .halt_reg = 0x17008,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x17008,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(7),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap_0_s_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
+        .halt_reg = 0x1800c,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(20),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap_1_m_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
+        .halt_reg = 0x18010,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x18010,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(21),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap_1_s_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc2_ahb_clk = {
+        .halt_reg = 0x14008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x14008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc2_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+        .halt_reg = 0x14004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x14004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc2_apps_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_sdcc2_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc4_ahb_clk = {
+        .halt_reg = 0x16008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x16008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc4_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc4_apps_clk = {
+        .halt_reg = 0x16004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x16004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc4_apps_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_sdcc4_apps_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
+        .halt_reg = 0x414c,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sys_noc_cpuss_ahb_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_cpuss_ahb_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_tsif_ahb_clk = {
+        .halt_reg = 0x36004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x36004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_tsif_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_tsif_inactivity_timers_clk = {
+        .halt_reg = 0x3600c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x3600c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_tsif_inactivity_timers_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_tsif_ref_clk = {
+        .halt_reg = 0x36008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x36008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_tsif_ref_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_tsif_ref_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_ahb_clk = {
+        .halt_reg = 0x75010,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x75010,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x75010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_axi_clk = {
+        .halt_reg = 0x7500c,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x7500c,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x7500c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_axi_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_ufs_card_axi_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_clkref_clk = {
+        .halt_reg = 0x8c004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8c004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_clkref_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_ice_core_clk = {
+        .halt_reg = 0x75058,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x75058,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x75058,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_ice_core_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_ufs_card_ice_core_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_phy_aux_clk = {
+        .halt_reg = 0x7508c,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x7508c,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x7508c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_phy_aux_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_ufs_card_phy_aux_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
+        .halt_check = BRANCH_HALT_SKIP,
+        .clkr = {
+                .enable_reg = 0x75018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_rx_symbol_0_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
+        .halt_check = BRANCH_HALT_SKIP,
+        .clkr = {
+                .enable_reg = 0x750a8,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_rx_symbol_1_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
+        .halt_check = BRANCH_HALT_SKIP,
+        .clkr = {
+                .enable_reg = 0x75014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_tx_symbol_0_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_unipro_core_clk = {
+        .halt_reg = 0x75054,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x75054,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x75054,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_unipro_core_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_ufs_card_unipro_core_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_mem_clkref_clk = {
+        .halt_reg = 0x8c000,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8c000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_mem_clkref_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_ahb_clk = {
+        .halt_reg = 0x77010,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x77010,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x77010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_axi_clk = {
+        .halt_reg = 0x7700c,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x7700c,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x7700c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_axi_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_ufs_phy_axi_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_ice_core_clk = {
+        .halt_reg = 0x77058,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x77058,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x77058,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_ice_core_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_ufs_phy_ice_core_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
+        .halt_reg = 0x7708c,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x7708c,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x7708c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_phy_aux_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_ufs_phy_phy_aux_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
+        .halt_check = BRANCH_HALT_SKIP,
+        .clkr = {
+                .enable_reg = 0x77018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_rx_symbol_0_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
+        .halt_check = BRANCH_HALT_SKIP,
+        .clkr = {
+                .enable_reg = 0x770a8,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_rx_symbol_1_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
+        .halt_check = BRANCH_HALT_SKIP,
+        .clkr = {
+                .enable_reg = 0x77014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_tx_symbol_0_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
+        .halt_reg = 0x77054,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x77054,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x77054,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_unipro_core_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_ufs_phy_unipro_core_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_prim_master_clk = {
+        .halt_reg = 0xf00c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xf00c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_prim_master_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_usb30_prim_master_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
+        .halt_reg = 0xf014,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xf014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_prim_mock_utmi_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_usb30_prim_mock_utmi_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_prim_sleep_clk = {
+        .halt_reg = 0xf010,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xf010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_prim_sleep_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_sec_master_clk = {
+        .halt_reg = 0x1000c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x1000c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_sec_master_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_usb30_sec_master_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
+        .halt_reg = 0x10014,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x10014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_sec_mock_utmi_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_usb30_sec_mock_utmi_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_sec_sleep_clk = {
+        .halt_reg = 0x10010,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x10010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_sec_sleep_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_prim_clkref_clk = {
+        .halt_reg = 0x8c008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8c008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_prim_clkref_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
+        .halt_reg = 0xf04c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xf04c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_prim_phy_aux_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_usb3_prim_phy_aux_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
+        .halt_reg = 0xf050,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xf050,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_prim_phy_com_aux_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_usb3_prim_phy_aux_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
+        .halt_check = BRANCH_HALT_SKIP,
+        .clkr = {
+                .enable_reg = 0xf054,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_prim_phy_pipe_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_sec_clkref_clk = {
+        .halt_reg = 0x8c028,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8c028,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_sec_clkref_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
+        .halt_reg = 0x1004c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x1004c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_sec_phy_aux_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_usb3_sec_phy_aux_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
+        .halt_reg = 0x10050,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x10050,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_sec_phy_com_aux_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_usb3_sec_phy_aux_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
+        .halt_check = BRANCH_HALT_SKIP,
+        .clkr = {
+                .enable_reg = 0x10054,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_sec_phy_pipe_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
+        .halt_reg = 0x6a004,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x6a004,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x6a004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb_phy_cfg_ahb2phy_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_vdda_vs_clk = {
+        .halt_reg = 0x7a00c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x7a00c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_vdda_vs_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_vsensor_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_vddcx_vs_clk = {
+        .halt_reg = 0x7a004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x7a004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_vddcx_vs_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_vsensor_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_vddmx_vs_clk = {
+        .halt_reg = 0x7a008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x7a008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_vddmx_vs_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_vsensor_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_video_ahb_clk = {
+        .halt_reg = 0xb004,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0xb004,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0xb004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_video_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_video_axi_clk = {
+        .halt_reg = 0xb01c,
+        .halt_check = BRANCH_VOTED,
+        .clkr = {
+                .enable_reg = 0xb01c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_video_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_video_xo_clk = {
+        .halt_reg = 0xb028,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xb028,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_video_xo_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_vs_ctrl_ahb_clk = {
+        .halt_reg = 0x7a014,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x7a014,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x7a014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_vs_ctrl_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_vs_ctrl_clk = {
+        .halt_reg = 0x7a010,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x7a010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_vs_ctrl_clk",
+                        .parent_names = (const char *[]){
+                                "gcc_vs_ctrl_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct gdsc pcie_0_gdsc = {
+        .gdscr = 0x6b004,
+        .pd = {
+                .name = "pcie_0_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+        .flags = POLL_CFG_GDSCR,
+};
+
+static struct gdsc pcie_1_gdsc = {
+        .gdscr = 0x8d004,
+        .pd = {
+                .name = "pcie_1_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+        .flags = POLL_CFG_GDSCR,
+};
+
+static struct gdsc ufs_card_gdsc = {
+        .gdscr = 0x75004,
+        .pd = {
+                .name = "ufs_card_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+        .flags = POLL_CFG_GDSCR,
+};
+
+static struct gdsc ufs_phy_gdsc = {
+        .gdscr = 0x77004,
+        .pd = {
+                .name = "ufs_phy_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+        .flags = POLL_CFG_GDSCR,
+};
+
+static struct gdsc usb30_prim_gdsc = {
+        .gdscr = 0xf004,
+        .pd = {
+                .name = "usb30_prim_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+        .flags = POLL_CFG_GDSCR,
+};
+
+static struct gdsc usb30_sec_gdsc = {
+        .gdscr = 0x10004,
+        .pd = {
+                .name = "usb30_sec_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+        .flags = POLL_CFG_GDSCR,
+};
+
+static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
+        .gdscr = 0x7d030,
+        .pd = {
+                .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
+        .gdscr = 0x7d03c,
+        .pd = {
+                .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
+        .gdscr = 0x7d034,
+        .pd = {
+                .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
+        .gdscr = 0x7d038,
+        .pd = {
+                .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
+        .gdscr = 0x7d040,
+        .pd = {
+                .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
+        .gdscr = 0x7d048,
+        .pd = {
+                .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
+        .gdscr = 0x7d044,
+        .pd = {
+                .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
+        },
+        .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct clk_regmap *gcc_sdm845_clocks[] = {
+        [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
+        [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
+        [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
+        [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
+        [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
+        [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
+        [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+        [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
+        [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
+        [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
+        [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
+        [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
+        [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
+        [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
+        [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
+        [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
+        [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
+        [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
+        [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
+        [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
+        [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
+        [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
+        [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
+        [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
+        [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
+        [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+        [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
+        [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+        [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
+        [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+        [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
+        [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
+        [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
+        [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
+        [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
+        [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
+        [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
+        [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
+        [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
+        [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
+        [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
+        [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
+        [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
+        [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
+        [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
+        [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
+        [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
+        [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
+        [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
+        [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
+        [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
+        [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
+        [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
+        [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
+        [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
+        [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
+        [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
+        [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
+        [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
+        [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
+        [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
+        [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
+        [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr,
+        [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
+        [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+        [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
+        [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+        [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
+        [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+        [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
+        [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
+        [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
+        [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
+        [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
+        [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
+        [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
+        [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
+        [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
+        [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
+        [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
+        [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
+        [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
+        [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
+        [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
+        [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
+        [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
+        [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
+        [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
+        [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
+        [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
+        [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
+        [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
+        [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
+        [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
+        [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
+        [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
+        [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
+        [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
+        [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
+        [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
+        [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
+        [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
+        [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
+        [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
+        [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
+        [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
+        [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
+        [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
+        [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+        [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+        [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
+        [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
+        [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
+        [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
+        [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
+        [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
+        [GCC_TSIF_INACTIVITY_TIMERS_CLK] =
+                                        &gcc_tsif_inactivity_timers_clk.clkr,
+        [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
+        [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
+        [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
+        [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
+        [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
+        [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
+        [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
+        [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
+        [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
+        [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
+        [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
+        [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
+        [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
+        [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
+        [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
+                                        &gcc_ufs_card_unipro_core_clk_src.clkr,
+        [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
+        [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
+        [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
+        [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
+        [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
+        [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
+        [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
+        [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
+        [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
+        [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
+        [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
+        [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
+        [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
+                                        &gcc_ufs_phy_unipro_core_clk_src.clkr,
+        [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
+        [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
+        [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
+        [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
+                                        &gcc_usb30_prim_mock_utmi_clk_src.clkr,
+        [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
+        [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
+        [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
+        [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
+        [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
+                                        &gcc_usb30_sec_mock_utmi_clk_src.clkr,
+        [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
+        [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
+        [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
+        [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
+        [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
+        [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
+        [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
+        [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
+        [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
+        [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
+        [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
+        [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
+        [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
+        [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
+        [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
+        [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
+        [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
+        [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
+        [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
+        [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
+        [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
+        [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
+        [GPLL0] = &gpll0.clkr,
+        [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
+        [GPLL4] = &gpll4.clkr,
+};
+
+static const struct qcom_reset_map gcc_sdm845_resets[] = {
+        [GCC_MMSS_BCR] = { 0xb000 },
+        [GCC_PCIE_0_BCR] = { 0x6b000 },
+        [GCC_PCIE_1_BCR] = { 0x8d000 },
+        [GCC_PCIE_PHY_BCR] = { 0x6f000 },
+        [GCC_PDM_BCR] = { 0x33000 },
+        [GCC_PRNG_BCR] = { 0x34000 },
+        [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
+        [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
+        [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
+        [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
+        [GCC_SDCC2_BCR] = { 0x14000 },
+        [GCC_SDCC4_BCR] = { 0x16000 },
+        [GCC_TSIF_BCR] = { 0x36000 },
+        [GCC_UFS_CARD_BCR] = { 0x75000 },
+        [GCC_UFS_PHY_BCR] = { 0x77000 },
+        [GCC_USB30_PRIM_BCR] = { 0xf000 },
+        [GCC_USB30_SEC_BCR] = { 0x10000 },
+        [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
+        [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
+        [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
+        [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
+        [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
+        [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
+        [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
+        [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
+        [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
+};
+
+static struct gdsc *gcc_sdm845_gdscs[] = {
+        [PCIE_0_GDSC] = &pcie_0_gdsc,
+        [PCIE_1_GDSC] = &pcie_1_gdsc,
+        [UFS_CARD_GDSC] = &ufs_card_gdsc,
+        [UFS_PHY_GDSC] = &ufs_phy_gdsc,
+        [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
+        [USB30_SEC_GDSC] = &usb30_sec_gdsc,
+        [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
+                        &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
+        [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] =
+                        &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc,
+        [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
+                        &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
+        [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
+                        &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
+        [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
+                        &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
+        [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
+                        &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
+        [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
+};
+
+static const struct regmap_config gcc_sdm845_regmap_config = {
+        .reg_bits       = 32,
+        .reg_stride     = 4,
+        .val_bits       = 32,
+        .max_register   = 0x182090,
+        .fast_io        = true,
+};
+
+static const struct qcom_cc_desc gcc_sdm845_desc = {
+        .config = &gcc_sdm845_regmap_config,
+        .clks = gcc_sdm845_clocks,
+        .num_clks = ARRAY_SIZE(gcc_sdm845_clocks),
+        .resets = gcc_sdm845_resets,
+        .num_resets = ARRAY_SIZE(gcc_sdm845_resets),
+        .gdscs = gcc_sdm845_gdscs,
+        .num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs),
+};
+
+static const struct of_device_id gcc_sdm845_match_table[] = {
+        { .compatible = "qcom,gcc-sdm845" },
+        { }
+};
+MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
+
+static int gcc_sdm845_probe(struct platform_device *pdev)
+{
+        struct regmap *regmap;
+
+        regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
+        if (IS_ERR(regmap))
+                return PTR_ERR(regmap);
+
+        /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
+        regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
+        regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
+
+        /* Enable CPUSS clocks */
+        regmap_update_bits(regmap, 0x48190, BIT(0), 0x1);
+        regmap_update_bits(regmap, 0x52004, BIT(22), 0x1);
+
+        return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
+}
+
+static struct platform_driver gcc_sdm845_driver = {
+        .probe          = gcc_sdm845_probe,
+        .driver         = {
+                .name   = "gcc-sdm845",
+                .of_match_table = gcc_sdm845_match_table,
+        },
+};
+
+static int __init gcc_sdm845_init(void)
+{
+        return platform_driver_register(&gcc_sdm845_driver);
+}
+subsys_initcall(gcc_sdm845_init);
+
+static void __exit gcc_sdm845_exit(void)
+{
+        platform_driver_unregister(&gcc_sdm845_driver);
+}
+module_exit(gcc_sdm845_exit);
+
+MODULE_DESCRIPTION("QTI GCC SDM845 Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:gcc-sdm845");
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index a4f3580587b7..a077133c7ce3 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -31,6 +31,12 @@
 #define HW_CONTROL_MASK         BIT(1)
 #define SW_COLLAPSE_MASK        BIT(0)
 #define GMEM_CLAMP_IO_MASK      BIT(0)
+#define GMEM_RESET_MASK         BIT(4)
+
+/* CFG_GDSCR */
+#define GDSC_POWER_UP_COMPLETE          BIT(16)
+#define GDSC_POWER_DOWN_COMPLETE        BIT(15)
+#define CFG_GDSCR_OFFSET                0x4
 
 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
 #define EN_REST_WAIT_VAL        (0x2 << 20)
@@ -40,20 +46,50 @@
 #define RETAIN_MEM              BIT(14)
 #define RETAIN_PERIPH           BIT(13)
 
-#define TIMEOUT_US              100
+#define TIMEOUT_US              500
 
 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
 
-static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
+enum gdsc_status {
+        GDSC_OFF,
+        GDSC_ON
+};
+
+/* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
+static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
 {
+        unsigned int reg;
         u32 val;
         int ret;
 
+        if (sc->flags & POLL_CFG_GDSCR)
+                reg = sc->gdscr + CFG_GDSCR_OFFSET;
+        else if (sc->gds_hw_ctrl)
+                reg = sc->gds_hw_ctrl;
+        else
+                reg = sc->gdscr;
+
         ret = regmap_read(sc->regmap, reg, &val);
         if (ret)
                 return ret;
 
-        return !!(val & PWR_ON_MASK);
+        if (sc->flags & POLL_CFG_GDSCR) {
+                switch (status) {
+                case GDSC_ON:
+                        return !!(val & GDSC_POWER_UP_COMPLETE);
+                case GDSC_OFF:
+                        return !!(val & GDSC_POWER_DOWN_COMPLETE);
+                }
+        }
+
+        switch (status) {
+        case GDSC_ON:
+                return !!(val & PWR_ON_MASK);
+        case GDSC_OFF:
+                return !(val & PWR_ON_MASK);
+        }
+
+        return -EINVAL;
 }
 
 static int gdsc_hwctrl(struct gdsc *sc, bool en)
@@ -63,34 +99,33 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en)
         return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
 }
 
-static int gdsc_poll_status(struct gdsc *sc, unsigned int reg, bool en)
+static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
 {
         ktime_t start;
 
         start = ktime_get();
         do {
-                if (gdsc_is_enabled(sc, reg) == en)
+                if (gdsc_check_status(sc, status))
                         return 0;
         } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
 
-        if (gdsc_is_enabled(sc, reg) == en)
+        if (gdsc_check_status(sc, status))
                 return 0;
 
         return -ETIMEDOUT;
 }
 
-static int gdsc_toggle_logic(struct gdsc *sc, bool en)
+static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
 {
         int ret;
-        u32 val = en ? 0 : SW_COLLAPSE_MASK;
-        unsigned int status_reg = sc->gdscr;
+        u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
 
         ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
         if (ret)
                 return ret;
 
         /* If disabling votable gdscs, don't poll on status */
-        if ((sc->flags & VOTABLE) && !en) {
+        if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
                 /*
                  * Add a short delay here to ensure that an enable
                  * right after it was disabled does not put it in an
@@ -101,7 +136,6 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
         }
 
         if (sc->gds_hw_ctrl) {
-                status_reg = sc->gds_hw_ctrl;
                 /*
                  * The gds hw controller asserts/de-asserts the status bit soon
                  * after it receives a power on/off request from a master.
@@ -115,7 +149,7 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)
                 udelay(1);
         }
 
-        return gdsc_poll_status(sc, status_reg, en);
+        return gdsc_poll_status(sc, status);
 }
 
 static inline int gdsc_deassert_reset(struct gdsc *sc)
@@ -166,6 +200,14 @@ static inline void gdsc_assert_clamp_io(struct gdsc *sc)
                            GMEM_CLAMP_IO_MASK, 1);
 }
 
+static inline void gdsc_assert_reset_aon(struct gdsc *sc)
+{
+        regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
+                           GMEM_RESET_MASK, 1);
+        udelay(1);
+        regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
+                           GMEM_RESET_MASK, 0);
+}
 static int gdsc_enable(struct generic_pm_domain *domain)
 {
         struct gdsc *sc = domain_to_gdsc(domain);
@@ -174,10 +216,19 @@ static int gdsc_enable(struct generic_pm_domain *domain)
         if (sc->pwrsts == PWRSTS_ON)
                 return gdsc_deassert_reset(sc);
 
-        if (sc->flags & CLAMP_IO)
+        if (sc->flags & SW_RESET) {
+                gdsc_assert_reset(sc);
+                udelay(1);
+                gdsc_deassert_reset(sc);
+        }
+
+        if (sc->flags & CLAMP_IO) {
+                if (sc->flags & AON_RESET)
+                        gdsc_assert_reset_aon(sc);
                 gdsc_deassert_clamp_io(sc);
+        }
 
-        ret = gdsc_toggle_logic(sc, true);
+        ret = gdsc_toggle_logic(sc, GDSC_ON);
         if (ret)
                 return ret;
 
@@ -222,8 +273,6 @@ static int gdsc_disable(struct generic_pm_domain *domain)
 
         /* Turn off HW trigger mode if supported */
         if (sc->flags & HW_CTRL) {
-                unsigned int reg;
-
                 ret = gdsc_hwctrl(sc, false);
                 if (ret < 0)
                         return ret;
@@ -235,8 +284,7 @@ static int gdsc_disable(struct generic_pm_domain *domain)
                  */
                 udelay(1);
 
-                reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
-                ret = gdsc_poll_status(sc, reg, true);
+                ret = gdsc_poll_status(sc, GDSC_ON);
                 if (ret)
                         return ret;
         }
@@ -244,7 +292,7 @@ static int gdsc_disable(struct generic_pm_domain *domain)
         if (sc->pwrsts & PWRSTS_OFF)
                 gdsc_clear_mem_on(sc);
 
-        ret = gdsc_toggle_logic(sc, false);
+        ret = gdsc_toggle_logic(sc, GDSC_OFF);
         if (ret)
                 return ret;
 
@@ -258,7 +306,6 @@ static int gdsc_init(struct gdsc *sc)
 {
         u32 mask, val;
         int on, ret;
-        unsigned int reg;
 
         /*
          * Disable HW trigger: collapse/restore occur based on registers writes.
@@ -274,13 +321,12 @@ static int gdsc_init(struct gdsc *sc)
 
         /* Force gdsc ON if only ON state is supported */
         if (sc->pwrsts == PWRSTS_ON) {
-                ret = gdsc_toggle_logic(sc, true);
+                ret = gdsc_toggle_logic(sc, GDSC_ON);
                 if (ret)
                         return ret;
         }
 
-        reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
-        on = gdsc_is_enabled(sc, reg);
+        on = gdsc_check_status(sc, GDSC_ON);
         if (on < 0)
                 return on;
 
@@ -291,6 +337,14 @@ static int gdsc_init(struct gdsc *sc)
         if ((sc->flags & VOTABLE) && on)
                 gdsc_enable(&sc->pd);
 
+        /* If ALWAYS_ON GDSCs are not ON, turn them ON */
+        if (sc->flags & ALWAYS_ON) {
+                if (!on)
+                        gdsc_enable(&sc->pd);
+                on = true;
+                sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
+        }
+
         if (on || (sc->pwrsts & PWRSTS_RET))
                 gdsc_force_mem_on(sc);
         else
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index 39648348e5ec..bd1f2c780d0a 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -53,6 +53,10 @@ struct gdsc {
 #define VOTABLE         BIT(0)
 #define CLAMP_IO        BIT(1)
 #define HW_CTRL         BIT(2)
+#define SW_RESET        BIT(3)
+#define AON_RESET       BIT(4)
+#define POLL_CFG_GDSCR  BIT(5)
+#define ALWAYS_ON       BIT(6)
         struct reset_controller_dev     *rcdev;
         unsigned int                    *resets;
         unsigned int                    reset_count;
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index 66a2fa4ec93c..1a25ee4f3658 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -1245,7 +1245,7 @@ static struct clk_branch mmss_mmagic_ahb_clk = {
                         .name = "mmss_mmagic_ahb_clk",
                         .parent_names = (const char *[]){ "ahb_clk_src" },
                         .num_parents = 1,
-                        .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+                        .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
                         .ops = &clk_branch2_ops,
                 },
         },
@@ -1260,7 +1260,7 @@ static struct clk_branch mmss_mmagic_cfg_ahb_clk = {
                         .name = "mmss_mmagic_cfg_ahb_clk",
                         .parent_names = (const char *[]){ "ahb_clk_src" },
                         .num_parents = 1,
-                        .flags = CLK_SET_RATE_PARENT,
+                        .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
                         .ops = &clk_branch2_ops,
                 },
         },
@@ -1319,7 +1319,7 @@ static struct clk_branch mmagic_camss_axi_clk = {
                         .name = "mmagic_camss_axi_clk",
                         .parent_names = (const char *[]){ "axi_clk_src" },
                         .num_parents = 1,
-                        .flags = CLK_SET_RATE_PARENT,
+                        .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
                         .ops = &clk_branch2_ops,
                 },
         },
@@ -1334,7 +1334,7 @@ static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = {
                         .name = "mmagic_camss_noc_cfg_ahb_clk",
                         .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
                         .num_parents = 1,
-                        .flags = CLK_SET_RATE_PARENT,
+                        .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
                         .ops = &clk_branch2_ops,
                 },
         },
@@ -1439,7 +1439,7 @@ static struct clk_branch mmagic_mdss_axi_clk = {
                         .name = "mmagic_mdss_axi_clk",
                         .parent_names = (const char *[]){ "axi_clk_src" },
                         .num_parents = 1,
-                        .flags = CLK_SET_RATE_PARENT,
+                        .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
                         .ops = &clk_branch2_ops,
                 },
         },
@@ -1454,7 +1454,7 @@ static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = {
                         .name = "mmagic_mdss_noc_cfg_ahb_clk",
                         .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
                         .num_parents = 1,
-                        .flags = CLK_SET_RATE_PARENT,
+                        .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
                         .ops = &clk_branch2_ops,
                 },
         },
@@ -1529,7 +1529,7 @@ static struct clk_branch mmagic_video_axi_clk = {
                         .name = "mmagic_video_axi_clk",
                         .parent_names = (const char *[]){ "axi_clk_src" },
                         .num_parents = 1,
-                        .flags = CLK_SET_RATE_PARENT,
+                        .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
                         .ops = &clk_branch2_ops,
                 },
         },
@@ -1544,7 +1544,7 @@ static struct clk_branch mmagic_video_noc_cfg_ahb_clk = {
                         .name = "mmagic_video_noc_cfg_ahb_clk",
                         .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
                         .num_parents = 1,
-                        .flags = CLK_SET_RATE_PARENT,
+                        .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
                         .ops = &clk_branch2_ops,
                 },
         },
@@ -2919,7 +2919,7 @@ static struct gdsc mmagic_video_gdsc = {
                 .name = "mmagic_video",
         },
         .pwrsts = PWRSTS_OFF_ON,
-        .flags = VOTABLE,
+        .flags = VOTABLE | ALWAYS_ON,
 };
 
 static struct gdsc mmagic_mdss_gdsc = {
@@ -2929,7 +2929,7 @@ static struct gdsc mmagic_mdss_gdsc = {
                 .name = "mmagic_mdss",
         },
         .pwrsts = PWRSTS_OFF_ON,
-        .flags = VOTABLE,
+        .flags = VOTABLE | ALWAYS_ON,
 };
 
 static struct gdsc mmagic_camss_gdsc = {
@@ -2939,7 +2939,7 @@ static struct gdsc mmagic_camss_gdsc = {
                 .name = "mmagic_camss",
         },
         .pwrsts = PWRSTS_OFF_ON,
-        .flags = VOTABLE,
+        .flags = VOTABLE | ALWAYS_ON,
 };
 
 static struct gdsc venus_gdsc = {
diff --git a/drivers/clk/qcom/videocc-sdm845.c b/drivers/clk/qcom/videocc-sdm845.c
new file mode 100644
index 000000000000..9073b7a710ac
--- /dev/null
+++ b/drivers/clk/qcom/videocc-sdm845.c
@@ -0,0 +1,358 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,videocc-sdm845.h>
+
+#include "common.h"
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "gdsc.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+        P_BI_TCXO,
+        P_CORE_BI_PLL_TEST_SE,
+        P_VIDEO_PLL0_OUT_EVEN,
+        P_VIDEO_PLL0_OUT_MAIN,
+        P_VIDEO_PLL0_OUT_ODD,
+};
+
+static const struct parent_map video_cc_parent_map_0[] = {
+        { P_BI_TCXO, 0 },
+        { P_VIDEO_PLL0_OUT_MAIN, 1 },
+        { P_VIDEO_PLL0_OUT_EVEN, 2 },
+        { P_VIDEO_PLL0_OUT_ODD, 3 },
+        { P_CORE_BI_PLL_TEST_SE, 4 },
+};
+
+static const char * const video_cc_parent_names_0[] = {
+        "bi_tcxo",
+        "video_pll0",
+        "video_pll0_out_even",
+        "video_pll0_out_odd",
+        "core_bi_pll_test_se",
+};
+
+static const struct alpha_pll_config video_pll0_config = {
+        .l = 0x10,
+        .alpha = 0xaaab,
+};
+
+static struct clk_alpha_pll video_pll0 = {
+        .offset = 0x42c,
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+        .clkr = {
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_pll0",
+                        .parent_names = (const char *[]){ "bi_tcxo" },
+                        .num_parents = 1,
+                        .ops = &clk_alpha_pll_fabia_ops,
+                },
+        },
+};
+
+static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
+        F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
+        F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
+        F(330000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+        F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+        F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+        F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 video_cc_venus_clk_src = {
+        .cmd_rcgr = 0x7f0,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = video_cc_parent_map_0,
+        .freq_tbl = ftbl_video_cc_venus_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "video_cc_venus_clk_src",
+                .parent_names = video_cc_parent_names_0,
+                .num_parents = 5,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_shared_ops,
+        },
+};
+
+static struct clk_branch video_cc_apb_clk = {
+        .halt_reg = 0x990,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x990,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_cc_apb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_cc_at_clk = {
+        .halt_reg = 0x9f0,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x9f0,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_cc_at_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_cc_qdss_trig_clk = {
+        .halt_reg = 0x970,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x970,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_cc_qdss_trig_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_cc_qdss_tsctr_div8_clk = {
+        .halt_reg = 0x9d0,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x9d0,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_cc_qdss_tsctr_div8_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_cc_vcodec0_axi_clk = {
+        .halt_reg = 0x930,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x930,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_cc_vcodec0_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_cc_vcodec0_core_clk = {
+        .halt_reg = 0x890,
+        .halt_check = BRANCH_VOTED,
+        .clkr = {
+                .enable_reg = 0x890,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_cc_vcodec0_core_clk",
+                        .parent_names = (const char *[]){
+                                "video_cc_venus_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_cc_vcodec1_axi_clk = {
+        .halt_reg = 0x950,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x950,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_cc_vcodec1_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_cc_vcodec1_core_clk = {
+        .halt_reg = 0x8d0,
+        .halt_check = BRANCH_VOTED,
+        .clkr = {
+                .enable_reg = 0x8d0,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_cc_vcodec1_core_clk",
+                        .parent_names = (const char *[]){
+                                "video_cc_venus_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_cc_venus_ahb_clk = {
+        .halt_reg = 0x9b0,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x9b0,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_cc_venus_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_cc_venus_ctl_axi_clk = {
+        .halt_reg = 0x910,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x910,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_cc_venus_ctl_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch video_cc_venus_ctl_core_clk = {
+        .halt_reg = 0x850,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x850,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "video_cc_venus_ctl_core_clk",
+                        .parent_names = (const char *[]){
+                                "video_cc_venus_clk_src",
+                        },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct gdsc venus_gdsc = {
+        .gdscr = 0x814,
+        .pd = {
+                .name = "venus_gdsc",
+        },
+        .cxcs = (unsigned int []){ 0x850, 0x910 },
+        .cxc_count = 2,
+        .pwrsts = PWRSTS_OFF_ON,
+        .flags = POLL_CFG_GDSCR,
+};
+
+static struct gdsc vcodec0_gdsc = {
+        .gdscr = 0x874,
+        .pd = {
+                .name = "vcodec0_gdsc",
+        },
+        .cxcs = (unsigned int []){ 0x890, 0x930 },
+        .cxc_count = 2,
+        .flags = HW_CTRL | POLL_CFG_GDSCR,
+        .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc vcodec1_gdsc = {
+        .gdscr = 0x8b4,
+        .pd = {
+                .name = "vcodec1_gdsc",
+        },
+        .cxcs = (unsigned int []){ 0x8d0, 0x950 },
+        .cxc_count = 2,
+        .flags = HW_CTRL | POLL_CFG_GDSCR,
+        .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct clk_regmap *video_cc_sdm845_clocks[] = {
+        [VIDEO_CC_APB_CLK] = &video_cc_apb_clk.clkr,
+        [VIDEO_CC_AT_CLK] = &video_cc_at_clk.clkr,
+        [VIDEO_CC_QDSS_TRIG_CLK] = &video_cc_qdss_trig_clk.clkr,
+        [VIDEO_CC_QDSS_TSCTR_DIV8_CLK] = &video_cc_qdss_tsctr_div8_clk.clkr,
+        [VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr,
+        [VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr,
+        [VIDEO_CC_VCODEC1_AXI_CLK] = &video_cc_vcodec1_axi_clk.clkr,
+        [VIDEO_CC_VCODEC1_CORE_CLK] = &video_cc_vcodec1_core_clk.clkr,
+        [VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
+        [VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr,
+        [VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr,
+        [VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr,
+        [VIDEO_PLL0] = &video_pll0.clkr,
+};
+
+static struct gdsc *video_cc_sdm845_gdscs[] = {
+        [VENUS_GDSC] = &venus_gdsc,
+        [VCODEC0_GDSC] = &vcodec0_gdsc,
+        [VCODEC1_GDSC] = &vcodec1_gdsc,
+};
+
+static const struct regmap_config video_cc_sdm845_regmap_config = {
+        .reg_bits       = 32,
+        .reg_stride     = 4,
+        .val_bits       = 32,
+        .max_register   = 0xb90,
+        .fast_io        = true,
+};
+
+static const struct qcom_cc_desc video_cc_sdm845_desc = {
+        .config = &video_cc_sdm845_regmap_config,
+        .clks = video_cc_sdm845_clocks,
+        .num_clks = ARRAY_SIZE(video_cc_sdm845_clocks),
+        .gdscs = video_cc_sdm845_gdscs,
+        .num_gdscs = ARRAY_SIZE(video_cc_sdm845_gdscs),
+};
+
+static const struct of_device_id video_cc_sdm845_match_table[] = {
+        { .compatible = "qcom,sdm845-videocc" },
+        { }
+};
+MODULE_DEVICE_TABLE(of, video_cc_sdm845_match_table);
+
+static int video_cc_sdm845_probe(struct platform_device *pdev)
+{
+        struct regmap *regmap;
+
+        regmap = qcom_cc_map(pdev, &video_cc_sdm845_desc);
+        if (IS_ERR(regmap))
+                return PTR_ERR(regmap);
+
+        clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
+
+        return qcom_cc_really_probe(pdev, &video_cc_sdm845_desc, regmap);
+}
+
+static struct platform_driver video_cc_sdm845_driver = {
+        .probe          = video_cc_sdm845_probe,
+        .driver         = {
+                .name   = "sdm845-videocc",
+                .of_match_table = video_cc_sdm845_match_table,
+        },
+};
+
+static int __init video_cc_sdm845_init(void)
+{
+        return platform_driver_register(&video_cc_sdm845_driver);
+}
+subsys_initcall(video_cc_sdm845_init);
+
+static void __exit video_cc_sdm845_exit(void)
+{
+        platform_driver_unregister(&video_cc_sdm845_driver);
+}
+module_exit(video_cc_sdm845_exit);
+
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index ef76c861ec84..f9ba71311727 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -7,6 +7,7 @@ config CLK_RENESAS
         select CLK_R8A7740 if ARCH_R8A7740
         select CLK_R8A7743 if ARCH_R8A7743
         select CLK_R8A7745 if ARCH_R8A7745
+        select CLK_R8A77470 if ARCH_R8A77470
         select CLK_R8A7778 if ARCH_R8A7778
         select CLK_R8A7779 if ARCH_R8A7779
         select CLK_R8A7790 if ARCH_R8A7790
@@ -18,6 +19,7 @@ config CLK_RENESAS
         select CLK_R8A77965 if ARCH_R8A77965
         select CLK_R8A77970 if ARCH_R8A77970
         select CLK_R8A77980 if ARCH_R8A77980
+        select CLK_R8A77990 if ARCH_R8A77990
         select CLK_R8A77995 if ARCH_R8A77995
         select CLK_SH73A0 if ARCH_SH73A0
 
@@ -60,6 +62,10 @@ config CLK_R8A7745
         bool "RZ/G1E clock support" if COMPILE_TEST
         select CLK_RCAR_GEN2_CPG
 
+config CLK_R8A77470
+        bool "RZ/G1C clock support" if COMPILE_TEST
+        select CLK_RCAR_GEN2_CPG
+
 config CLK_R8A7778
         bool "R-Car M1A clock support" if COMPILE_TEST
         select CLK_RENESAS_CPG_MSTP
@@ -111,6 +117,10 @@ config CLK_R8A77980
         bool "R-Car V3H clock support" if COMPILE_TEST
         select CLK_RCAR_GEN3_CPG
 
+config CLK_R8A77990
+        bool "R-Car E3 clock support" if COMPILE_TEST
+        select CLK_RCAR_GEN3_CPG
+
 config CLK_R8A77995
         bool "R-Car D3 clock support" if COMPILE_TEST
         select CLK_RCAR_GEN3_CPG
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 6c0f19636e3e..fe5bac9215e5 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_CLK_R8A73A4)		+= clk-r8a73a4.o
 obj-$(CONFIG_CLK_R8A7740)               += clk-r8a7740.o
 obj-$(CONFIG_CLK_R8A7743)               += r8a7743-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7745)               += r8a7745-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77470)              += r8a77470-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7778)               += clk-r8a7778.o
 obj-$(CONFIG_CLK_R8A7779)               += clk-r8a7779.o
 obj-$(CONFIG_CLK_R8A7790)               += r8a7790-cpg-mssr.o
@@ -17,6 +18,7 @@ obj-$(CONFIG_CLK_R8A7796)		+= r8a7796-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77965)              += r8a77965-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77970)              += r8a77970-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77980)              += r8a77980-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77990)              += r8a77990-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77995)              += r8a77995-cpg-mssr.o
 obj-$(CONFIG_CLK_SH73A0)                += clk-sh73a0.o
 
diff --git a/drivers/clk/renesas/r8a7743-cpg-mssr.c b/drivers/clk/renesas/r8a7743-cpg-mssr.c
index d3c8b1e2969f..011c170ec3f9 100644
--- a/drivers/clk/renesas/r8a7743-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7743-cpg-mssr.c
@@ -52,7 +52,6 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
 
         /* Core Clock Outputs */
         DEF_BASE("z",    R8A7743_CLK_Z,    CLK_TYPE_GEN2_Z,     CLK_PLL0),
-        DEF_BASE("lb",   R8A7743_CLK_LB,   CLK_TYPE_GEN2_LB,    CLK_PLL1),
         DEF_BASE("sdh",  R8A7743_CLK_SDH,  CLK_TYPE_GEN2_SDH,   CLK_PLL1),
         DEF_BASE("sd0",  R8A7743_CLK_SD0,  CLK_TYPE_GEN2_SD0,   CLK_PLL1),
         DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI,  CLK_PLL1_DIV2),
@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
         DEF_FIXED("zs",    R8A7743_CLK_ZS,      CLK_PLL1,           6, 1),
         DEF_FIXED("hp",    R8A7743_CLK_HP,      CLK_PLL1,          12, 1),
         DEF_FIXED("b",     R8A7743_CLK_B,       CLK_PLL1,          12, 1),
+        DEF_FIXED("lb",    R8A7743_CLK_LB,      CLK_PLL1,          24, 1),
         DEF_FIXED("p",     R8A7743_CLK_P,       CLK_PLL1,          24, 1),
         DEF_FIXED("cl",    R8A7743_CLK_CL,      CLK_PLL1,          48, 1),
         DEF_FIXED("m2",    R8A7743_CLK_M2,      CLK_PLL1,           8, 1),
diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
index 87f5a3619e4f..4b0a9243b748 100644
--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
@@ -51,7 +51,6 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
 
         /* Core Clock Outputs */
-        DEF_BASE("lb",   R8A7745_CLK_LB,   CLK_TYPE_GEN2_LB,    CLK_PLL1),
         DEF_BASE("sdh",  R8A7745_CLK_SDH,  CLK_TYPE_GEN2_SDH,   CLK_PLL1),
         DEF_BASE("sd0",  R8A7745_CLK_SD0,  CLK_TYPE_GEN2_SD0,   CLK_PLL1),
         DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI,  CLK_PLL1_DIV2),
@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
         DEF_FIXED("zs",    R8A7745_CLK_ZS,      CLK_PLL1,           6, 1),
         DEF_FIXED("hp",    R8A7745_CLK_HP,      CLK_PLL1,          12, 1),
         DEF_FIXED("b",     R8A7745_CLK_B,       CLK_PLL1,          12, 1),
+        DEF_FIXED("lb",    R8A7745_CLK_LB,      CLK_PLL1,          24, 1),
         DEF_FIXED("p",     R8A7745_CLK_P,       CLK_PLL1,          24, 1),
         DEF_FIXED("cl",    R8A7745_CLK_CL,      CLK_PLL1,          48, 1),
         DEF_FIXED("cp",    R8A7745_CLK_CP,      CLK_PLL1,          48, 1),
diff --git a/drivers/clk/renesas/r8a77470-cpg-mssr.c b/drivers/clk/renesas/r8a77470-cpg-mssr.c
new file mode 100644
index 000000000000..ab0fb10b6bf0
--- /dev/null
+++ b/drivers/clk/renesas/r8a77470-cpg-mssr.c
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a77470 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a77470-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+        /* Core Clock Outputs exported to DT */
+        LAST_DT_CORE_CLK = R8A77470_CLK_OSC,
+
+        /* External Input Clocks */
+        CLK_EXTAL,
+        CLK_USB_EXTAL,
+
+        /* Internal Core Clocks */
+        CLK_MAIN,
+        CLK_PLL0,
+        CLK_PLL1,
+        CLK_PLL3,
+        CLK_PLL1_DIV2,
+
+        /* Module Clocks */
+        MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77470_core_clks[] __initconst = {
+        /* External Clock Inputs */
+        DEF_INPUT("extal",      CLK_EXTAL),
+        DEF_INPUT("usb_extal",  CLK_USB_EXTAL),
+
+        /* Internal Core Clocks */
+        DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+        DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+        DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+        DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
+
+        DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+
+        /* Core Clock Outputs */
+        DEF_BASE("sdh",  R8A77470_CLK_SDH,  CLK_TYPE_GEN2_SDH,  CLK_PLL1),
+        DEF_BASE("sd0",  R8A77470_CLK_SD0,  CLK_TYPE_GEN2_SD0,  CLK_PLL1),
+        DEF_BASE("sd1",  R8A77470_CLK_SD1,  CLK_TYPE_GEN2_SD1,  CLK_PLL1),
+        DEF_BASE("qspi", R8A77470_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
+        DEF_BASE("rcan", R8A77470_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
+
+        DEF_FIXED("z2",    R8A77470_CLK_Z2,     CLK_PLL0,           1, 1),
+        DEF_FIXED("zx",    R8A77470_CLK_ZX,     CLK_PLL1,           3, 1),
+        DEF_FIXED("zs",    R8A77470_CLK_ZS,     CLK_PLL1,           6, 1),
+        DEF_FIXED("hp",    R8A77470_CLK_HP,     CLK_PLL1,          12, 1),
+        DEF_FIXED("b",     R8A77470_CLK_B,      CLK_PLL1,          12, 1),
+        DEF_FIXED("lb",    R8A77470_CLK_LB,     CLK_PLL1,          24, 1),
+        DEF_FIXED("p",     R8A77470_CLK_P,      CLK_PLL1,          24, 1),
+        DEF_FIXED("cl",    R8A77470_CLK_CL,     CLK_PLL1,          48, 1),
+        DEF_FIXED("cp",    R8A77470_CLK_CP,     CLK_PLL1,          48, 1),
+        DEF_FIXED("m2",    R8A77470_CLK_M2,     CLK_PLL1,           8, 1),
+        DEF_FIXED("zb3",   R8A77470_CLK_ZB3,    CLK_PLL3,           4, 1),
+        DEF_FIXED("mp",    R8A77470_CLK_MP,     CLK_PLL1_DIV2,     15, 1),
+        DEF_FIXED("cpex",  R8A77470_CLK_CPEX,   CLK_EXTAL,          2, 1),
+        DEF_FIXED("r",     R8A77470_CLK_R,      CLK_PLL1,       49152, 1),
+        DEF_FIXED("osc",   R8A77470_CLK_OSC,    CLK_PLL1,       12288, 1),
+
+        DEF_DIV6P1("sd2",  R8A77470_CLK_SD2,    CLK_PLL1_DIV2,  0x078),
+};
+
+static const struct mssr_mod_clk r8a77470_mod_clks[] __initconst = {
+        DEF_MOD("msiof0",                  0,   R8A77470_CLK_MP),
+        DEF_MOD("vcp0",                  101,   R8A77470_CLK_ZS),
+        DEF_MOD("vpc0",                  103,   R8A77470_CLK_ZS),
+        DEF_MOD("tmu1",                  111,   R8A77470_CLK_P),
+        DEF_MOD("3dg",                   112,   R8A77470_CLK_ZS),
+        DEF_MOD("2d-dmac",               115,   R8A77470_CLK_ZS),
+        DEF_MOD("fdp1-0",                119,   R8A77470_CLK_ZS),
+        DEF_MOD("tmu3",                  121,   R8A77470_CLK_P),
+        DEF_MOD("tmu2",                  122,   R8A77470_CLK_P),
+        DEF_MOD("cmt0",                  124,   R8A77470_CLK_R),
+        DEF_MOD("vsp1du0",               128,   R8A77470_CLK_ZS),
+        DEF_MOD("vsp1-sy",               131,   R8A77470_CLK_ZS),
+        DEF_MOD("msiof2",                205,   R8A77470_CLK_MP),
+        DEF_MOD("msiof1",                208,   R8A77470_CLK_MP),
+        DEF_MOD("sys-dmac1",             218,   R8A77470_CLK_ZS),
+        DEF_MOD("sys-dmac0",             219,   R8A77470_CLK_ZS),
+        DEF_MOD("sdhi2",                 312,   R8A77470_CLK_SD2),
+        DEF_MOD("sdhi1",                 313,   R8A77470_CLK_SD1),
+        DEF_MOD("sdhi0",                 314,   R8A77470_CLK_SD0),
+        DEF_MOD("usbhs-dmac0-ch1",       326,   R8A77470_CLK_HP),
+        DEF_MOD("usbhs-dmac1-ch1",       327,   R8A77470_CLK_HP),
+        DEF_MOD("cmt1",                  329,   R8A77470_CLK_R),
+        DEF_MOD("usbhs-dmac0-ch0",       330,   R8A77470_CLK_HP),
+        DEF_MOD("usbhs-dmac1-ch0",       331,   R8A77470_CLK_HP),
+        DEF_MOD("rwdt",                  402,   R8A77470_CLK_R),
+        DEF_MOD("irqc",                  407,   R8A77470_CLK_CP),
+        DEF_MOD("intc-sys",              408,   R8A77470_CLK_ZS),
+        DEF_MOD("audio-dmac0",           502,   R8A77470_CLK_HP),
+        DEF_MOD("pwm",                   523,   R8A77470_CLK_P),
+        DEF_MOD("usb-ehci-0",            703,   R8A77470_CLK_MP),
+        DEF_MOD("usbhs-0",               704,   R8A77470_CLK_HP),
+        DEF_MOD("usb-ehci-1",            705,   R8A77470_CLK_MP),
+        DEF_MOD("usbhs-1",               706,   R8A77470_CLK_HP),
+        DEF_MOD("hscif2",                713,   R8A77470_CLK_ZS),
+        DEF_MOD("scif5",                 714,   R8A77470_CLK_P),
+        DEF_MOD("scif4",                 715,   R8A77470_CLK_P),
+        DEF_MOD("hscif1",                716,   R8A77470_CLK_ZS),
+        DEF_MOD("hscif0",                717,   R8A77470_CLK_ZS),
+        DEF_MOD("scif3",                 718,   R8A77470_CLK_P),
+        DEF_MOD("scif2",                 719,   R8A77470_CLK_P),
+        DEF_MOD("scif1",                 720,   R8A77470_CLK_P),
+        DEF_MOD("scif0",                 721,   R8A77470_CLK_P),
+        DEF_MOD("du1",                   723,   R8A77470_CLK_ZX),
+        DEF_MOD("du0",                   724,   R8A77470_CLK_ZX),
+        DEF_MOD("ipmmu-sgx",             800,   R8A77470_CLK_ZX),
+        DEF_MOD("etheravb",              812,   R8A77470_CLK_HP),
+        DEF_MOD("ether",                 813,   R8A77470_CLK_P),
+        DEF_MOD("gpio5",                 907,   R8A77470_CLK_CP),
+        DEF_MOD("gpio4",                 908,   R8A77470_CLK_CP),
+        DEF_MOD("gpio3",                 909,   R8A77470_CLK_CP),
+        DEF_MOD("gpio2",                 910,   R8A77470_CLK_CP),
+        DEF_MOD("gpio1",                 911,   R8A77470_CLK_CP),
+        DEF_MOD("gpio0",                 912,   R8A77470_CLK_CP),
+        DEF_MOD("can1",                  915,   R8A77470_CLK_P),
+        DEF_MOD("can0",                  916,   R8A77470_CLK_P),
+        DEF_MOD("qspi_mod-1",            917,   R8A77470_CLK_QSPI),
+        DEF_MOD("qspi_mod-0",            918,   R8A77470_CLK_QSPI),
+        DEF_MOD("i2c4",                  927,   R8A77470_CLK_HP),
+        DEF_MOD("i2c3",                  928,   R8A77470_CLK_HP),
+        DEF_MOD("i2c2",                  929,   R8A77470_CLK_HP),
+        DEF_MOD("i2c1",                  930,   R8A77470_CLK_HP),
+        DEF_MOD("i2c0",                  931,   R8A77470_CLK_HP),
+        DEF_MOD("ssi-all",              1005,   R8A77470_CLK_P),
+        DEF_MOD("ssi9",                 1006,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi8",                 1007,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi7",                 1008,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi6",                 1009,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi5",                 1010,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi2",                 1013,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi1",                 1014,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi0",                 1015,   MOD_CLK_ID(1005)),
+        DEF_MOD("scu-all",              1017,   R8A77470_CLK_P),
+        DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-ctu1-mix1",        1020,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-ctu0-mix0",        1021,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src6",             1025,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src5",             1026,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src4",             1027,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src3",             1028,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src2",             1029,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src1",             1030,   MOD_CLK_ID(1017)),
+};
+
+static const unsigned int r8a77470_crit_mod_clks[] __initconst = {
+        MOD_CLK_ID(402),        /* RWDT */
+        MOD_CLK_ID(408),        /* INTC-SYS (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ *    MD        EXTAL           PLL0    PLL1    PLL3
+ * 14 13        (MHz)           *1      *2
+ *---------------------------------------------------
+ * 0  0         20              x80     x78     x50
+ * 0  1         26              x60     x60     x56
+ * 1  0         Prohibitted setting
+ * 1  1         30              x52     x52     x50
+ *
+ * *1 : Table 7.4 indicates VCO output (PLL0 = VCO)
+ * *2 : Table 7.4 indicates VCO output (PLL1 = VCO)
+ */
+#define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 13) | \
+                                         (((md) & BIT(13)) >> 13))
+
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
+        /* EXTAL div    PLL1 mult x2    PLL3 mult */
+        { 1,            156,            50,     },
+        { 1,            120,            56,     },
+        { /* Invalid*/                          },
+        { 1,            104,            50,     },
+};
+
+static int __init r8a77470_cpg_mssr_init(struct device *dev)
+{
+        const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
+        u32 cpg_mode;
+        int error;
+
+        error = rcar_rst_read_mode_pins(&cpg_mode);
+        if (error)
+                return error;
+
+        cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+        return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a77470_cpg_mssr_info __initconst = {
+        /* Core Clocks */
+        .core_clks = r8a77470_core_clks,
+        .num_core_clks = ARRAY_SIZE(r8a77470_core_clks),
+        .last_dt_core_clk = LAST_DT_CORE_CLK,
+        .num_total_core_clks = MOD_CLK_BASE,
+
+        /* Module Clocks */
+        .mod_clks = r8a77470_mod_clks,
+        .num_mod_clks = ARRAY_SIZE(r8a77470_mod_clks),
+        .num_hw_mod_clks = 12 * 32,
+
+        /* Critical Module Clocks */
+        .crit_mod_clks = r8a77470_crit_mod_clks,
+        .num_crit_mod_clks = ARRAY_SIZE(r8a77470_crit_mod_clks),
+
+        /* Callbacks */
+        .init = r8a77470_cpg_mssr_init,
+        .cpg_clk_register = rcar_gen2_cpg_clk_register,
+};
diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c
index 820b220b09cc..1b91f03b7598 100644
--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -57,7 +57,6 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
 
         /* Core Clock Outputs */
         DEF_BASE("z",    R8A7791_CLK_Z,    CLK_TYPE_GEN2_Z,    CLK_PLL0),
-        DEF_BASE("lb",   R8A7791_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
         DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
         DEF_BASE("sdh",  R8A7791_CLK_SDH,  CLK_TYPE_GEN2_SDH,  CLK_PLL1),
         DEF_BASE("sd0",  R8A7791_CLK_SD0,  CLK_TYPE_GEN2_SD0,  CLK_PLL1),
@@ -70,6 +69,7 @@ static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
         DEF_FIXED("hp",     R8A7791_CLK_HP,    CLK_PLL1,         12, 1),
         DEF_FIXED("i",      R8A7791_CLK_I,     CLK_PLL1,          2, 1),
         DEF_FIXED("b",      R8A7791_CLK_B,     CLK_PLL1,         12, 1),
+        DEF_FIXED("lb",     R8A7791_CLK_LB,    CLK_PLL1,         24, 1),
         DEF_FIXED("p",      R8A7791_CLK_P,     CLK_PLL1,         24, 1),
         DEF_FIXED("cl",     R8A7791_CLK_CL,    CLK_PLL1,         48, 1),
         DEF_FIXED("m2",     R8A7791_CLK_M2,    CLK_PLL1,          8, 1),
diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index 609a54080496..493e07859f5f 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -53,7 +53,6 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
 
         /* Core Clock Outputs */
-        DEF_BASE("lb",   R8A7792_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
         DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
 
         DEF_FIXED("z",      R8A7792_CLK_Z,     CLK_PLL0,          1, 1),
@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
         DEF_FIXED("hp",     R8A7792_CLK_HP,    CLK_PLL1,         12, 1),
         DEF_FIXED("i",      R8A7792_CLK_I,     CLK_PLL1,          3, 1),
         DEF_FIXED("b",      R8A7792_CLK_B,     CLK_PLL1,         12, 1),
+        DEF_FIXED("lb",     R8A7792_CLK_LB,    CLK_PLL1,         24, 1),
         DEF_FIXED("p",      R8A7792_CLK_P,     CLK_PLL1,         24, 1),
         DEF_FIXED("cl",     R8A7792_CLK_CL,    CLK_PLL1,         48, 1),
         DEF_FIXED("m2",     R8A7792_CLK_M2,    CLK_PLL1,          8, 1),
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index 2a40bbeaeeaf..088f4b79fdfc 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -55,7 +55,6 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
 
         /* Core Clock Outputs */
-        DEF_BASE("lb",   R8A7794_CLK_LB,   CLK_TYPE_GEN2_LB,   CLK_PLL1),
         DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
         DEF_BASE("sdh",  R8A7794_CLK_SDH,  CLK_TYPE_GEN2_SDH,  CLK_PLL1),
         DEF_BASE("sd0",  R8A7794_CLK_SD0,  CLK_TYPE_GEN2_SD0,  CLK_PLL1),
@@ -69,6 +68,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
         DEF_FIXED("hp",     R8A7794_CLK_HP,    CLK_PLL1,         12, 1),
         DEF_FIXED("i",      R8A7794_CLK_I,     CLK_PLL1,          2, 1),
         DEF_FIXED("b",      R8A7794_CLK_B,     CLK_PLL1,         12, 1),
+        DEF_FIXED("lb",     R8A7794_CLK_LB,    CLK_PLL1,         24, 1),
         DEF_FIXED("p",      R8A7794_CLK_P,     CLK_PLL1,         24, 1),
         DEF_FIXED("cl",     R8A7794_CLK_CL,    CLK_PLL1,         48, 1),
         DEF_FIXED("cp",     R8A7794_CLK_CP,    CLK_PLL1,         48, 1),
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index b1acfb60351c..8fae5e9c4a77 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -116,6 +116,10 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
         DEF_MOD("scif3",                204,    R8A77965_CLK_S3D4),
         DEF_MOD("scif1",                206,    R8A77965_CLK_S3D4),
         DEF_MOD("scif0",                207,    R8A77965_CLK_S3D4),
+        DEF_MOD("msiof3",               208,    R8A77965_CLK_MSO),
+        DEF_MOD("msiof2",               209,    R8A77965_CLK_MSO),
+        DEF_MOD("msiof1",               210,    R8A77965_CLK_MSO),
+        DEF_MOD("msiof0",               211,    R8A77965_CLK_MSO),
         DEF_MOD("sys-dmac2",            217,    R8A77965_CLK_S0D3),
         DEF_MOD("sys-dmac1",            218,    R8A77965_CLK_S0D3),
         DEF_MOD("sys-dmac0",            219,    R8A77965_CLK_S0D3),
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c
index 7aaae73a321a..d7ebd9ec0059 100644
--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -116,7 +116,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
         DEF_MOD("sys-dmac1",             218,   R8A77980_CLK_S0D3),
         DEF_MOD("tpu0",                  304,   R8A77980_CLK_S3D4),
         DEF_MOD("sdif",                  314,   R8A77980_CLK_SD0),
-        DEF_MOD("pciec0",                319,   R8A77980_CLK_S3D1),
+        DEF_MOD("pciec0",                319,   R8A77980_CLK_S2D2),
         DEF_MOD("intc-ex",               407,   R8A77980_CLK_CP),
         DEF_MOD("intc-ap",               408,   R8A77980_CLK_S0D3),
         DEF_MOD("hscif3",                517,   R8A77980_CLK_S3D1),
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
new file mode 100644
index 000000000000..9e14f1486fbb
--- /dev/null
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a77990 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * Based on r8a7795-cpg-mssr.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+        /* Core Clock Outputs exported to DT */
+        LAST_DT_CORE_CLK = R8A77990_CLK_CPEX,
+
+        /* External Input Clocks */
+        CLK_EXTAL,
+
+        /* Internal Core Clocks */
+        CLK_MAIN,
+        CLK_PLL0,
+        CLK_PLL1,
+        CLK_PLL3,
+        CLK_PLL0D4,
+        CLK_PLL0D6,
+        CLK_PLL0D8,
+        CLK_PLL0D20,
+        CLK_PLL0D24,
+        CLK_PLL1D2,
+        CLK_PE,
+        CLK_S0,
+        CLK_S1,
+        CLK_S2,
+        CLK_S3,
+        CLK_SDSRC,
+
+        /* Module Clocks */
+        MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
+        /* External Clock Inputs */
+        DEF_INPUT("extal",     CLK_EXTAL),
+
+        /* Internal Core Clocks */
+        DEF_BASE(".main",      CLK_MAIN, CLK_TYPE_GEN3_MAIN,       CLK_EXTAL),
+        DEF_BASE(".pll1",      CLK_PLL1, CLK_TYPE_GEN3_PLL1,       CLK_MAIN),
+        DEF_BASE(".pll3",      CLK_PLL3, CLK_TYPE_GEN3_PLL3,       CLK_MAIN),
+
+        DEF_FIXED(".pll0",     CLK_PLL0,           CLK_MAIN,       1, 100),
+        DEF_FIXED(".pll0d4",   CLK_PLL0D4,         CLK_PLL0,       4, 1),
+        DEF_FIXED(".pll0d6",   CLK_PLL0D6,         CLK_PLL0,       6, 1),
+        DEF_FIXED(".pll0d8",   CLK_PLL0D8,         CLK_PLL0,       8, 1),
+        DEF_FIXED(".pll0d20",  CLK_PLL0D20,        CLK_PLL0,      20, 1),
+        DEF_FIXED(".pll0d24",  CLK_PLL0D24,        CLK_PLL0,      24, 1),
+        DEF_FIXED(".pll1d2",   CLK_PLL1D2,         CLK_PLL1,       2, 1),
+        DEF_FIXED(".pe",       CLK_PE,             CLK_PLL0D20,    1, 1),
+        DEF_FIXED(".s0",       CLK_S0,             CLK_PLL1,       2, 1),
+        DEF_FIXED(".s1",       CLK_S1,             CLK_PLL1,       3, 1),
+        DEF_FIXED(".s2",       CLK_S2,             CLK_PLL1,       4, 1),
+        DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),
+        DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),
+
+        /* Core Clock Outputs */
+        DEF_FIXED("za2",       R8A77990_CLK_ZA2,   CLK_PLL0D24,    1, 1),
+        DEF_FIXED("za8",       R8A77990_CLK_ZA8,   CLK_PLL0D8,     1, 1),
+        DEF_FIXED("ztr",       R8A77990_CLK_ZTR,   CLK_PLL1,       6, 1),
+        DEF_FIXED("zt",        R8A77990_CLK_ZT,    CLK_PLL1,       4, 1),
+        DEF_FIXED("zx",        R8A77990_CLK_ZX,    CLK_PLL1,       3, 1),
+        DEF_FIXED("s0d1",      R8A77990_CLK_S0D1,  CLK_S0,         1, 1),
+        DEF_FIXED("s0d3",      R8A77990_CLK_S0D3,  CLK_S0,         3, 1),
+        DEF_FIXED("s0d6",      R8A77990_CLK_S0D6,  CLK_S0,         6, 1),
+        DEF_FIXED("s0d12",     R8A77990_CLK_S0D12, CLK_S0,        12, 1),
+        DEF_FIXED("s0d24",     R8A77990_CLK_S0D24, CLK_S0,        24, 1),
+        DEF_FIXED("s1d1",      R8A77990_CLK_S1D1,  CLK_S1,         1, 1),
+        DEF_FIXED("s1d2",      R8A77990_CLK_S1D2,  CLK_S1,         2, 1),
+        DEF_FIXED("s1d4",      R8A77990_CLK_S1D4,  CLK_S1,         4, 1),
+        DEF_FIXED("s2d1",      R8A77990_CLK_S2D1,  CLK_S2,         1, 1),
+        DEF_FIXED("s2d2",      R8A77990_CLK_S2D2,  CLK_S2,         2, 1),
+        DEF_FIXED("s2d4",      R8A77990_CLK_S2D4,  CLK_S2,         4, 1),
+        DEF_FIXED("s3d1",      R8A77990_CLK_S3D1,  CLK_S3,         1, 1),
+        DEF_FIXED("s3d2",      R8A77990_CLK_S3D2,  CLK_S3,         2, 1),
+        DEF_FIXED("s3d4",      R8A77990_CLK_S3D4,  CLK_S3,         4, 1),
+
+        DEF_GEN3_SD("sd0",     R8A77990_CLK_SD0,   CLK_SDSRC,     0x0074),
+        DEF_GEN3_SD("sd1",     R8A77990_CLK_SD1,   CLK_SDSRC,     0x0078),
+        DEF_GEN3_SD("sd3",     R8A77990_CLK_SD3,   CLK_SDSRC,     0x026c),
+
+        DEF_FIXED("cl",        R8A77990_CLK_CL,    CLK_PLL1,      48, 1),
+        DEF_FIXED("cp",        R8A77990_CLK_CP,    CLK_EXTAL,      2, 1),
+        DEF_FIXED("cpex",      R8A77990_CLK_CPEX,  CLK_EXTAL,      4, 1),
+        DEF_FIXED("osc",       R8A77990_CLK_OSC,   CLK_EXTAL,    384, 1),
+        DEF_FIXED("r",         R8A77990_CLK_R,     CLK_EXTAL,   1536, 1),
+
+        DEF_GEN3_PE("s0d6c",   R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
+        DEF_GEN3_PE("s3d1c",   R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
+        DEF_GEN3_PE("s3d2c",   R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
+        DEF_GEN3_PE("s3d4c",   R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
+
+        DEF_DIV6P1("canfd",    R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
+        DEF_DIV6P1("csi0",     R8A77990_CLK_CSI0,  CLK_PLL1D2, 0x00c),
+        DEF_DIV6P1("mso",      R8A77990_CLK_MSO,   CLK_PLL1D2, 0x014),
+};
+
+static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
+        DEF_MOD("scif5",                 202,   R8A77990_CLK_S3D4C),
+        DEF_MOD("scif4",                 203,   R8A77990_CLK_S3D4C),
+        DEF_MOD("scif3",                 204,   R8A77990_CLK_S3D4C),
+        DEF_MOD("scif1",                 206,   R8A77990_CLK_S3D4C),
+        DEF_MOD("scif0",                 207,   R8A77990_CLK_S3D4C),
+        DEF_MOD("msiof3",                208,   R8A77990_CLK_MSO),
+        DEF_MOD("msiof2",                209,   R8A77990_CLK_MSO),
+        DEF_MOD("msiof1",                210,   R8A77990_CLK_MSO),
+        DEF_MOD("msiof0",                211,   R8A77990_CLK_MSO),
+        DEF_MOD("sys-dmac2",             217,   R8A77990_CLK_S3D1),
+        DEF_MOD("sys-dmac1",             218,   R8A77990_CLK_S3D1),
+        DEF_MOD("sys-dmac0",             219,   R8A77990_CLK_S3D1),
+
+        DEF_MOD("cmt3",                  300,   R8A77990_CLK_R),
+        DEF_MOD("cmt2",                  301,   R8A77990_CLK_R),
+        DEF_MOD("cmt1",                  302,   R8A77990_CLK_R),
+        DEF_MOD("cmt0",                  303,   R8A77990_CLK_R),
+        DEF_MOD("scif2",                 310,   R8A77990_CLK_S3D4C),
+        DEF_MOD("sdif3",                 311,   R8A77990_CLK_SD3),
+        DEF_MOD("sdif1",                 313,   R8A77990_CLK_SD1),
+        DEF_MOD("sdif0",                 314,   R8A77990_CLK_SD0),
+        DEF_MOD("pcie0",                 319,   R8A77990_CLK_S3D1),
+        DEF_MOD("usb3-if0",              328,   R8A77990_CLK_S3D1),
+        DEF_MOD("usb-dmac0",             330,   R8A77990_CLK_S3D1),
+        DEF_MOD("usb-dmac1",             331,   R8A77990_CLK_S3D1),
+
+        DEF_MOD("rwdt",                  402,   R8A77990_CLK_R),
+        DEF_MOD("intc-ex",               407,   R8A77990_CLK_CP),
+        DEF_MOD("intc-ap",               408,   R8A77990_CLK_S0D3),
+
+        DEF_MOD("audmac0",               502,   R8A77990_CLK_S3D4),
+        DEF_MOD("drif7",                 508,   R8A77990_CLK_S3D2),
+        DEF_MOD("drif6",                 509,   R8A77990_CLK_S3D2),
+        DEF_MOD("drif5",                 510,   R8A77990_CLK_S3D2),
+        DEF_MOD("drif4",                 511,   R8A77990_CLK_S3D2),
+        DEF_MOD("drif3",                 512,   R8A77990_CLK_S3D2),
+        DEF_MOD("drif2",                 513,   R8A77990_CLK_S3D2),
+        DEF_MOD("drif1",                 514,   R8A77990_CLK_S3D2),
+        DEF_MOD("drif0",                 515,   R8A77990_CLK_S3D2),
+        DEF_MOD("hscif4",                516,   R8A77990_CLK_S3D1C),
+        DEF_MOD("hscif3",                517,   R8A77990_CLK_S3D1C),
+        DEF_MOD("hscif2",                518,   R8A77990_CLK_S3D1C),
+        DEF_MOD("hscif1",                519,   R8A77990_CLK_S3D1C),
+        DEF_MOD("hscif0",                520,   R8A77990_CLK_S3D1C),
+        DEF_MOD("thermal",               522,   R8A77990_CLK_CP),
+        DEF_MOD("pwm",                   523,   R8A77990_CLK_S3D4C),
+
+        DEF_MOD("fcpvd1",                602,   R8A77990_CLK_S1D2),
+        DEF_MOD("fcpvd0",                603,   R8A77990_CLK_S1D2),
+        DEF_MOD("fcpvb0",                607,   R8A77990_CLK_S0D1),
+        DEF_MOD("fcpvi0",                611,   R8A77990_CLK_S0D1),
+        DEF_MOD("fcpf0",                 615,   R8A77990_CLK_S0D1),
+        DEF_MOD("fcpcs",                 619,   R8A77990_CLK_S0D1),
+        DEF_MOD("vspd1",                 622,   R8A77990_CLK_S1D2),
+        DEF_MOD("vspd0",                 623,   R8A77990_CLK_S1D2),
+        DEF_MOD("vspb",                  626,   R8A77990_CLK_S0D1),
+        DEF_MOD("vspi0",                 631,   R8A77990_CLK_S0D1),
+
+        DEF_MOD("ehci0",                 703,   R8A77990_CLK_S3D4),
+        DEF_MOD("hsusb",                 704,   R8A77990_CLK_S3D4),
+        DEF_MOD("csi40",                 716,   R8A77990_CLK_CSI0),
+        DEF_MOD("du1",                   723,   R8A77990_CLK_S2D1),
+        DEF_MOD("du0",                   724,   R8A77990_CLK_S2D1),
+        DEF_MOD("lvds",                  727,   R8A77990_CLK_S2D1),
+
+        DEF_MOD("vin5",                  806,   R8A77990_CLK_S1D2),
+        DEF_MOD("vin4",                  807,   R8A77990_CLK_S1D2),
+        DEF_MOD("etheravb",              812,   R8A77990_CLK_S3D2),
+
+        DEF_MOD("gpio6",                 906,   R8A77990_CLK_S3D4),
+        DEF_MOD("gpio5",                 907,   R8A77990_CLK_S3D4),
+        DEF_MOD("gpio4",                 908,   R8A77990_CLK_S3D4),
+        DEF_MOD("gpio3",                 909,   R8A77990_CLK_S3D4),
+        DEF_MOD("gpio2",                 910,   R8A77990_CLK_S3D4),
+        DEF_MOD("gpio1",                 911,   R8A77990_CLK_S3D4),
+        DEF_MOD("gpio0",                 912,   R8A77990_CLK_S3D4),
+        DEF_MOD("can-fd",                914,   R8A77990_CLK_S3D2),
+        DEF_MOD("can-if1",               915,   R8A77990_CLK_S3D4),
+        DEF_MOD("can-if0",               916,   R8A77990_CLK_S3D4),
+        DEF_MOD("i2c6",                  918,   R8A77990_CLK_S3D2),
+        DEF_MOD("i2c5",                  919,   R8A77990_CLK_S3D2),
+        DEF_MOD("i2c-dvfs",              926,   R8A77990_CLK_CP),
+        DEF_MOD("i2c4",                  927,   R8A77990_CLK_S3D2),
+        DEF_MOD("i2c3",                  928,   R8A77990_CLK_S3D2),
+        DEF_MOD("i2c2",                  929,   R8A77990_CLK_S3D2),
+        DEF_MOD("i2c1",                  930,   R8A77990_CLK_S3D2),
+        DEF_MOD("i2c0",                  931,   R8A77990_CLK_S3D2),
+
+        DEF_MOD("ssi-all",              1005,   R8A77990_CLK_S3D4),
+        DEF_MOD("ssi9",                 1006,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi8",                 1007,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi7",                 1008,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi6",                 1009,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi5",                 1010,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi2",                 1013,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi1",                 1014,   MOD_CLK_ID(1005)),
+        DEF_MOD("ssi0",                 1015,   MOD_CLK_ID(1005)),
+        DEF_MOD("scu-all",              1017,   R8A77990_CLK_S3D4),
+        DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-ctu1-mix1",        1020,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-ctu0-mix0",        1021,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src9",             1022,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src8",             1023,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src7",             1024,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src6",             1025,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src5",             1026,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src4",             1027,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src3",             1028,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src2",             1029,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src1",             1030,   MOD_CLK_ID(1017)),
+        DEF_MOD("scu-src0",             1031,   MOD_CLK_ID(1017)),
+};
+
+static const unsigned int r8a77990_crit_mod_clks[] __initconst = {
+        MOD_CLK_ID(408),        /* INTC-AP (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD19         EXTAL (MHz)     PLL0            PLL1            PLL3
+ *--------------------------------------------------------------------
+ * 0            48 x 1          x100/4          x100/3          x100/3
+ * 1            48 x 1          x100/4          x100/3           x58/3
+ */
+#define CPG_PLL_CONFIG_INDEX(md)        (((md) & BIT(19)) >> 19)
+
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
+        /* EXTAL div    PLL1 mult/div   PLL3 mult/div */
+        { 1,            100,    3,      100,    3,      },
+        { 1,            100,    3,       58,    3,      },
+};
+
+static int __init r8a77990_cpg_mssr_init(struct device *dev)
+{
+        const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
+        u32 cpg_mode;
+        int error;
+
+        error = rcar_rst_read_mode_pins(&cpg_mode);
+        if (error)
+                return error;
+
+        cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+        return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a77990_cpg_mssr_info __initconst = {
+        /* Core Clocks */
+        .core_clks = r8a77990_core_clks,
+        .num_core_clks = ARRAY_SIZE(r8a77990_core_clks),
+        .last_dt_core_clk = LAST_DT_CORE_CLK,
+        .num_total_core_clks = MOD_CLK_BASE,
+
+        /* Module Clocks */
+        .mod_clks = r8a77990_mod_clks,
+        .num_mod_clks = ARRAY_SIZE(r8a77990_mod_clks),
+        .num_hw_mod_clks = 12 * 32,
+
+        /* Critical Module Clocks */
+        .crit_mod_clks = r8a77990_crit_mod_clks,
+        .num_crit_mod_clks = ARRAY_SIZE(r8a77990_crit_mod_clks),
+
+        /* Callbacks */
+        .init = r8a77990_cpg_mssr_init,
+        .cpg_clk_register = rcar_gen3_cpg_clk_register,
+};
diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar-gen2-cpg.c
index feb14579a71b..daf88bc2cdae 100644
--- a/drivers/clk/renesas/rcar-gen2-cpg.c
+++ b/drivers/clk/renesas/rcar-gen2-cpg.c
@@ -16,6 +16,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/sys_soc.h>
 
 #include "renesas-cpg-mssr.h"
 #include "rcar-gen2-cpg.h"
@@ -260,6 +261,17 @@ static const struct clk_div_table cpg_sd01_div_table[] = {
 static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata;
 static unsigned int cpg_pll0_div __initdata;
 static u32 cpg_mode __initdata;
+static u32 cpg_quirks __initdata;
+
+#define SD_SKIP_FIRST   BIT(0)          /* Skip first clock in SD table */
+
+static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
+        {
+                .soc_id = "r8a77470",
+                .data = (void *)SD_SKIP_FIRST,
+        },
+        { /* sentinel */ }
+};
 
 struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
         const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
@@ -327,11 +339,17 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
 
         case CLK_TYPE_GEN2_SD0:
                 table = cpg_sd01_div_table;
+                if (cpg_quirks & SD_SKIP_FIRST)
+                        table++;
+
                 shift = 4;
                 break;
 
         case CLK_TYPE_GEN2_SD1:
                 table = cpg_sd01_div_table;
+                if (cpg_quirks & SD_SKIP_FIRST)
+                        table++;
+
                 shift = 0;
                 break;
 
@@ -360,9 +378,15 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
 int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
                               unsigned int pll0_div, u32 mode)
 {
+        const struct soc_device_attribute *attr;
+
         cpg_pll_config = config;
         cpg_pll0_div = pll0_div;
         cpg_mode = mode;
+        attr = soc_device_match(cpg_quirks_match);
+        if (attr)
+                cpg_quirks = (uintptr_t)attr->data;
+        pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
 
         spin_lock_init(&cpg_lock);
 
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 69a7c756658b..f4b013e9352d 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -653,6 +653,12 @@ static const struct of_device_id cpg_mssr_match[] = {
                 .data = &r8a7745_cpg_mssr_info,
         },
 #endif
+#ifdef CONFIG_CLK_R8A77470
+        {
+                .compatible = "renesas,r8a77470-cpg-mssr",
+                .data = &r8a77470_cpg_mssr_info,
+        },
+#endif
 #ifdef CONFIG_CLK_R8A7790
         {
                 .compatible = "renesas,r8a7790-cpg-mssr",
@@ -712,6 +718,12 @@ static const struct of_device_id cpg_mssr_match[] = {
                 .data = &r8a77980_cpg_mssr_info,
         },
 #endif
+#ifdef CONFIG_CLK_R8A77990
+        {
+                .compatible = "renesas,r8a77990-cpg-mssr",
+                .data = &r8a77990_cpg_mssr_info,
+        },
+#endif
 #ifdef CONFIG_CLK_R8A77995
         {
                 .compatible = "renesas,r8a77995-cpg-mssr",
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 97ccb093c10f..642f720b9b05 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -133,6 +133,7 @@ struct cpg_mssr_info {
 
 extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
@@ -142,6 +143,7 @@ extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
 
 
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 59b8d320960a..98e7b9429b83 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -3,7 +3,6 @@
 # Rockchip Clock specific Makefile
 #
 
-obj-y   += clk-rockchip.o
 obj-y   += clk.o
 obj-y   += clk-pll.o
 obj-y   += clk-cpu.o
diff --git a/drivers/clk/rockchip/clk-rockchip.c b/drivers/clk/rockchip/clk-rockchip.c
deleted file mode 100644
index 2c9bb81144c9..000000000000
--- a/drivers/clk/rockchip/clk-rockchip.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (c) 2013 MundoReader S.L.
- * Author: Heiko Stuebner <heiko@sntech.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-static DEFINE_SPINLOCK(clk_lock);
-
-/*
- * Gate clocks
- */
-
-static void __init rk2928_gate_clk_init(struct device_node *node)
-{
-        struct clk_onecell_data *clk_data;
-        const char *clk_parent;
-        const char *clk_name;
-        void __iomem *reg;
-        void __iomem *reg_idx;
-        int flags;
-        int qty;
-        int reg_bit;
-        int clkflags = CLK_SET_RATE_PARENT;
-        int i;
-
-        qty = of_property_count_strings(node, "clock-output-names");
-        if (qty < 0) {
-                pr_err("%s: error in clock-output-names %d\n", __func__, qty);
-                return;
-        }
-
-        if (qty == 0) {
-                pr_info("%s: nothing to do\n", __func__);
-                return;
-        }
-
-        reg = of_iomap(node, 0);
-        if (!reg)
-                return;
-
-        clk_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
-        if (!clk_data) {
-                iounmap(reg);
-                return;
-        }
-
-        clk_data->clks = kzalloc(qty * sizeof(struct clk *), GFP_KERNEL);
-        if (!clk_data->clks) {
-                kfree(clk_data);
-                iounmap(reg);
-                return;
-        }
-
-        flags = CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE;
-
-        for (i = 0; i < qty; i++) {
-                of_property_read_string_index(node, "clock-output-names",
-                                              i, &clk_name);
-
-                /* ignore empty slots */
-                if (!strcmp("reserved", clk_name))
-                        continue;
-
-                clk_parent = of_clk_get_parent_name(node, i);
-
-                /* keep all gates untouched for now */
-                clkflags |= CLK_IGNORE_UNUSED;
-
-                reg_idx = reg + (4 * (i / 16));
-                reg_bit = (i % 16);
-
-                clk_data->clks[i] = clk_register_gate(NULL, clk_name,
-                                                      clk_parent, clkflags,
-                                                      reg_idx, reg_bit,
-                                                      flags,
-                                                      &clk_lock);
-                WARN_ON(IS_ERR(clk_data->clks[i]));
-        }
-
-        clk_data->clk_num = qty;
-
-        of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-}
-CLK_OF_DECLARE(rk2928_gate, "rockchip,rk2928-gate-clk", rk2928_gate_clk_init);
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 3cd8ad59e0b7..326b3fa44f5d 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -274,18 +274,10 @@ static struct clk *rockchip_clk_register_frac_branch(
                 struct clk_mux *frac_mux = &frac->mux;
                 struct clk_init_data init;
                 struct clk *mux_clk;
-                int i, ret;
-
-                frac->mux_frac_idx = -1;
-                for (i = 0; i < child->num_parents; i++) {
-                        if (!strcmp(name, child->parent_names[i])) {
-                                pr_debug("%s: found fractional parent in mux at pos %d\n",
-                                         __func__, i);
-                                frac->mux_frac_idx = i;
-                                break;
-                        }
-                }
+                int ret;
 
+                frac->mux_frac_idx = match_string(child->parent_names,
+                                                  child->num_parents, name);
                 frac->mux_ops = &clk_mux_ops;
                 frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
 
@@ -312,6 +304,8 @@ static struct clk *rockchip_clk_register_frac_branch(
 
                 /* notifier on the fraction divider to catch rate changes */
                 if (frac->mux_frac_idx >= 0) {
+                        pr_debug("%s: found fractional parent in mux at pos %d\n",
+                                 __func__, frac->mux_frac_idx);
                         ret = clk_notifier_register(clk, &frac->clk_nb);
                         if (ret)
                                 pr_err("%s: failed to register clock notifier for %s\n",
diff --git a/drivers/clk/samsung/clk-s3c2410-dclk.c b/drivers/clk/samsung/clk-s3c2410-dclk.c
index 66a904758761..0d92f3e5e3d9 100644
--- a/drivers/clk/samsung/clk-s3c2410-dclk.c
+++ b/drivers/clk/samsung/clk-s3c2410-dclk.c
@@ -219,8 +219,7 @@ static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
 #ifdef CONFIG_PM_SLEEP
 static int s3c24xx_dclk_suspend(struct device *dev)
 {
-        struct platform_device *pdev = to_platform_device(dev);
-        struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
+        struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
 
         s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
         return 0;
@@ -228,8 +227,7 @@ static int s3c24xx_dclk_suspend(struct device *dev)
 
 static int s3c24xx_dclk_resume(struct device *dev)
 {
-        struct platform_device *pdev = to_platform_device(dev);
-        struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
+        struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
 
         writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
         return 0;
diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
index 3a11c382a663..72714633e39c 100644
--- a/drivers/clk/socfpga/clk-s10.c
+++ b/drivers/clk/socfpga/clk-s10.c
@@ -260,46 +260,45 @@ static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
         return 0;
 }
 
-static struct stratix10_clock_data *__socfpga_s10_clk_init(struct device_node *np,
+static struct stratix10_clock_data *__socfpga_s10_clk_init(struct platform_device *pdev,
                                                     int nr_clks)
 {
+        struct device_node *np = pdev->dev.of_node;
+        struct device *dev = &pdev->dev;
         struct stratix10_clock_data *clk_data;
         struct clk **clk_table;
+        struct resource *res;
         void __iomem *base;
 
-        base = of_iomap(np, 0);
-        if (!base) {
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        base = devm_ioremap_resource(dev, res);
+        if (IS_ERR(base)) {
                 pr_err("%s: failed to map clock registers\n", __func__);
-                goto err;
+                return ERR_CAST(base);
         }
 
-        clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+        clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
         if (!clk_data)
-                goto err;
+                return ERR_PTR(-ENOMEM);
 
         clk_data->base = base;
-        clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL);
+        clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
         if (!clk_table)
-                goto err_data;
+                return ERR_PTR(-ENOMEM);
 
         clk_data->clk_data.clks = clk_table;
         clk_data->clk_data.clk_num = nr_clks;
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
         return clk_data;
-
-err_data:
-        kfree(clk_data);
-err:
-        return NULL;
 }
 
-static int s10_clkmgr_init(struct device_node *np)
+static int s10_clkmgr_init(struct platform_device *pdev)
 {
         struct stratix10_clock_data *clk_data;
 
-        clk_data = __socfpga_s10_clk_init(np, STRATIX10_NUM_CLKS);
-        if (!clk_data)
-                return -ENOMEM;
+        clk_data = __socfpga_s10_clk_init(pdev, STRATIX10_NUM_CLKS);
+        if (IS_ERR(clk_data))
+                return PTR_ERR(clk_data);
 
         s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
 
@@ -317,11 +316,7 @@ static int s10_clkmgr_init(struct device_node *np)
 
 static int s10_clkmgr_probe(struct platform_device *pdev)
 {
-        struct device_node *np = pdev->dev.of_node;
-
-        s10_clkmgr_init(np);
-
-        return 0;
+        return  s10_clkmgr_init(pdev);
 }
 
 static const struct of_device_id stratix10_clkmgr_match_table[] = {
@@ -334,6 +329,7 @@ static struct platform_driver stratix10_clkmgr_driver = {
         .probe          = s10_clkmgr_probe,
         .driver         = {
                 .name   = "stratix10-clkmgr",
+                .suppress_bind_attrs = true,
                 .of_match_table = stratix10_clkmgr_match_table,
         },
 };
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
index f911d9f77763..47810be7f15c 100644
--- a/drivers/clk/spear/spear6xx_clock.c
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -147,7 +147,7 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
 
         clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
                         1);
-        clk_register_clkdev(clk, NULL, "wdt");
+        clk_register_clkdev(clk, NULL, "fc880000.wdt");
 
         /* clock derived from pll1 clk */
         clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 79dfd296c3d1..826674d090fd 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -16,6 +16,11 @@ config SUN50I_H6_CCU
         default ARM64 && ARCH_SUNXI
         depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
 
+config SUN50I_H6_R_CCU
+        bool "Support for the Allwinner H6 PRCM CCU"
+        default ARM64 && ARCH_SUNXI
+        depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+
 config SUN4I_A10_CCU
         bool "Support for the Allwinner A10/A20 CCU"
         default MACH_SUN4I
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 128a40ee5c5e..acaa14cfa25c 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -23,6 +23,7 @@ lib-$(CONFIG_SUNXI_CCU)		+= ccu_mp.o
 # SoC support
 obj-$(CONFIG_SUN50I_A64_CCU)    += ccu-sun50i-a64.o
 obj-$(CONFIG_SUN50I_H6_CCU)     += ccu-sun50i-h6.o
+obj-$(CONFIG_SUN50I_H6_R_CCU)   += ccu-sun50i-h6-r.o
 obj-$(CONFIG_SUN4I_A10_CCU)     += ccu-sun4i-a10.o
 obj-$(CONFIG_SUN5I_CCU)         += ccu-sun5i.o
 obj-$(CONFIG_SUN6I_A31_CCU)     += ccu-sun6i-a31.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
new file mode 100644
index 000000000000..27554eaf6929
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_nm.h"
+
+#include "ccu-sun50i-h6-r.h"
+
+/*
+ * Information about AR100 and AHB/APB clocks in R_CCU are gathered from
+ * clock definitions in the BSP source code.
+ */
+
+static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k",
+                                             "pll-periph0", "iosc" };
+static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = {
+        { .index = 2, .shift = 0, .width = 5 },
+};
+
+static struct ccu_div ar100_clk = {
+        .div            = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+        .mux            = {
+                .shift  = 24,
+                .width  = 2,
+
+                .var_predivs    = ar100_r_apb2_predivs,
+                .n_var_predivs  = ARRAY_SIZE(ar100_r_apb2_predivs),
+        },
+
+        .common         = {
+                .reg            = 0x000,
+                .features       = CCU_FEATURE_VARIABLE_PREDIV,
+                .hw.init        = CLK_HW_INIT_PARENTS("ar100",
+                                                      ar100_r_apb2_parents,
+                                                      &ccu_div_ops,
+                                                      0),
+        },
+};
+
+static CLK_FIXED_FACTOR(r_ahb_clk, "r-ahb", "ar100", 1, 1, 0);
+
+static struct ccu_div r_apb1_clk = {
+        .div            = _SUNXI_CCU_DIV(0, 2),
+
+        .common         = {
+                .reg            = 0x00c,
+                .hw.init        = CLK_HW_INIT("r-apb1",
+                                              "r-ahb",
+                                              &ccu_div_ops,
+                                              0),
+        },
+};
+
+static struct ccu_div r_apb2_clk = {
+        .div            = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+        .mux            = {
+                .shift  = 24,
+                .width  = 2,
+
+                .var_predivs    = ar100_r_apb2_predivs,
+                .n_var_predivs  = ARRAY_SIZE(ar100_r_apb2_predivs),
+        },
+
+        .common         = {
+                .reg            = 0x010,
+                .features       = CCU_FEATURE_VARIABLE_PREDIV,
+                .hw.init        = CLK_HW_INIT_PARENTS("r-apb2",
+                                                      ar100_r_apb2_parents,
+                                                      &ccu_div_ops,
+                                                      0),
+        },
+};
+
+/*
+ * Information about the gate/resets are gathered from the clock header file
+ * in the BSP source code, although most of them are unused. The existence
+ * of the hardware block is verified with "3.1 Memory Mapping" chapter in
+ * "Allwinner H6 V200 User Manual V1.1"; and the parent APB buses are verified
+ * with "3.3.2.1 System Bus Tree" chapter inthe same document.
+ */
+static SUNXI_CCU_GATE(r_apb1_timer_clk, "r-apb1-timer", "r-apb1",
+                      0x11c, BIT(0), 0);
+static SUNXI_CCU_GATE(r_apb1_twd_clk,   "r-apb1-twd",   "r-apb1",
+                      0x12c, BIT(0), 0);
+static SUNXI_CCU_GATE(r_apb1_pwm_clk,   "r-apb1-pwm",   "r-apb1",
+                      0x13c, BIT(0), 0);
+static SUNXI_CCU_GATE(r_apb2_uart_clk,  "r-apb2-uart",  "r-apb2",
+                      0x18c, BIT(0), 0);
+static SUNXI_CCU_GATE(r_apb2_i2c_clk,   "r-apb2-i2c",   "r-apb2",
+                      0x19c, BIT(0), 0);
+static SUNXI_CCU_GATE(r_apb1_ir_clk,    "r-apb1-ir",    "r-apb1",
+                      0x1cc, BIT(0), 0);
+static SUNXI_CCU_GATE(r_apb1_w1_clk,    "r-apb1-w1",    "r-apb1",
+                      0x1cc, BIT(0), 0);
+
+/* Information of IR(RX) mod clock is gathered from BSP source code */
+static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
+                                  r_mod0_default_parents, 0x1c0,
+                                  0, 5,         /* M */
+                                  8, 2,         /* P */
+                                  24, 1,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+/*
+ * BSP didn't use the 1-wire function at all now, and the information about
+ * this mod clock is guessed from the IR mod clock above. The existence of
+ * this mod clock is proven by BSP clock header, and the dividers are verified
+ * by contents in the 1-wire related chapter of the User Manual.
+ */
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(w1_clk, "w1",
+                                  r_mod0_default_parents, 0x1e0,
+                                  0, 5,         /* M */
+                                  8, 2,         /* P */
+                                  24, 1,        /* mux */
+                                  BIT(31),      /* gate */
+                                  0);
+
+static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
+        &ar100_clk.common,
+        &r_apb1_clk.common,
+        &r_apb2_clk.common,
+        &r_apb1_timer_clk.common,
+        &r_apb1_twd_clk.common,
+        &r_apb1_pwm_clk.common,
+        &r_apb2_uart_clk.common,
+        &r_apb2_i2c_clk.common,
+        &r_apb1_ir_clk.common,
+        &r_apb1_w1_clk.common,
+        &ir_clk.common,
+        &w1_clk.common,
+};
+
+static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
+        .hws    = {
+                [CLK_AR100]             = &ar100_clk.common.hw,
+                [CLK_R_AHB]             = &r_ahb_clk.hw,
+                [CLK_R_APB1]            = &r_apb1_clk.common.hw,
+                [CLK_R_APB2]            = &r_apb2_clk.common.hw,
+                [CLK_R_APB1_TIMER]      = &r_apb1_timer_clk.common.hw,
+                [CLK_R_APB1_TWD]        = &r_apb1_twd_clk.common.hw,
+                [CLK_R_APB1_PWM]        = &r_apb1_pwm_clk.common.hw,
+                [CLK_R_APB2_UART]       = &r_apb2_uart_clk.common.hw,
+                [CLK_R_APB2_I2C]        = &r_apb2_i2c_clk.common.hw,
+                [CLK_R_APB1_IR]         = &r_apb1_ir_clk.common.hw,
+                [CLK_R_APB1_W1]         = &r_apb1_w1_clk.common.hw,
+                [CLK_IR]                = &ir_clk.common.hw,
+                [CLK_W1]                = &w1_clk.common.hw,
+        },
+        .num    = CLK_NUMBER,
+};
+
+static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
+        [RST_R_APB1_TIMER]      =  { 0x11c, BIT(16) },
+        [RST_R_APB1_TWD]        =  { 0x12c, BIT(16) },
+        [RST_R_APB1_PWM]        =  { 0x13c, BIT(16) },
+        [RST_R_APB2_UART]       =  { 0x18c, BIT(16) },
+        [RST_R_APB2_I2C]        =  { 0x19c, BIT(16) },
+        [RST_R_APB1_IR]         =  { 0x1cc, BIT(16) },
+        [RST_R_APB1_W1]         =  { 0x1ec, BIT(16) },
+};
+
+static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
+        .ccu_clks       = sun50i_h6_r_ccu_clks,
+        .num_ccu_clks   = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
+
+        .hw_clks        = &sun50i_h6_r_hw_clks,
+
+        .resets         = sun50i_h6_r_ccu_resets,
+        .num_resets     = ARRAY_SIZE(sun50i_h6_r_ccu_resets),
+};
+
+static void __init sunxi_r_ccu_init(struct device_node *node,
+                                    const struct sunxi_ccu_desc *desc)
+{
+        void __iomem *reg;
+
+        reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+        if (IS_ERR(reg)) {
+                pr_err("%pOF: Could not map the clock registers\n", node);
+                return;
+        }
+
+        sunxi_ccu_probe(node, reg, desc);
+}
+
+static void __init sun50i_h6_r_ccu_setup(struct device_node *node)
+{
+        sunxi_r_ccu_init(node, &sun50i_h6_r_ccu_desc);
+}
+CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
+               sun50i_h6_r_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
new file mode 100644
index 000000000000..782117dc0b28
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#ifndef _CCU_SUN50I_H6_R_H
+#define _CCU_SUN50I_H6_R_H
+
+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+
+/* AHB/APB bus clocks are not exported except APB1 for R_PIO */
+#define CLK_R_AHB       1
+
+#define CLK_R_APB2      3
+
+#define CLK_NUMBER      (CLK_W1 + 1)
+
+#endif /* _CCU_SUN50I_H6_R_H */
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 933f2e68f42a..65ba6455feb7 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -12,7 +12,8 @@
  */
 
 #include <linux/clk-provider.h>
-#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
 
 #include "ccu_common.h"
 #include "ccu_reset.h"
@@ -1250,17 +1251,45 @@ static struct ccu_mux_nb sun8i_r40_cpu_nb = {
         .bypass_index   = 1, /* index of 24 MHz oscillator */
 };
 
-static void __init sun8i_r40_ccu_setup(struct device_node *node)
+/*
+ * Add a regmap for the GMAC driver (dwmac-sun8i) to access the
+ * GMAC configuration register.
+ * Only this register is allowed to be written, in order to
+ * prevent overriding critical clock configuration.
+ */
+
+#define SUN8I_R40_GMAC_CFG_REG 0x164
+static bool sun8i_r40_ccu_regmap_accessible_reg(struct device *dev,
+                                                unsigned int reg)
+{
+        if (reg == SUN8I_R40_GMAC_CFG_REG)
+                return true;
+        return false;
+}
+
+static struct regmap_config sun8i_r40_ccu_regmap_config = {
+        .reg_bits       = 32,
+        .val_bits       = 32,
+        .reg_stride     = 4,
+        .max_register   = 0x320, /* PLL_LOCK_CTRL_REG */
+
+        /* other devices have no business accessing other registers */
+        .readable_reg   = sun8i_r40_ccu_regmap_accessible_reg,
+        .writeable_reg  = sun8i_r40_ccu_regmap_accessible_reg,
+};
+
+static int sun8i_r40_ccu_probe(struct platform_device *pdev)
 {
+        struct resource *res;
+        struct regmap *regmap;
         void __iomem *reg;
         u32 val;
+        int ret;
 
-        reg = of_io_request_and_map(node, 0, of_node_full_name(node));
-        if (IS_ERR(reg)) {
-                pr_err("%s: Could not map the clock registers\n",
-                       of_node_full_name(node));
-                return;
-        }
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        reg = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(reg))
+                return PTR_ERR(reg);
 
         /* Force the PLL-Audio-1x divider to 4 */
         val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
@@ -1277,7 +1306,14 @@ static void __init sun8i_r40_ccu_setup(struct device_node *node)
         val &= ~GENMASK(25, 20);
         writel(val, reg + SUN8I_R40_USB_CLK_REG);
 
-        sunxi_ccu_probe(node, reg, &sun8i_r40_ccu_desc);
+        regmap = devm_regmap_init_mmio(&pdev->dev, reg,
+                                       &sun8i_r40_ccu_regmap_config);
+        if (IS_ERR(regmap))
+                return PTR_ERR(regmap);
+
+        ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_r40_ccu_desc);
+        if (ret)
+                return ret;
 
         /* Gate then ungate PLL CPU after any rate changes */
         ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb);
@@ -1285,6 +1321,20 @@ static void __init sun8i_r40_ccu_setup(struct device_node *node)
         /* Reparent CPU during PLL CPU rate changes */
         ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
                                   &sun8i_r40_cpu_nb);
+
+        return 0;
 }
-CLK_OF_DECLARE(sun8i_r40_ccu, "allwinner,sun8i-r40-ccu",
-               sun8i_r40_ccu_setup);
+
+static const struct of_device_id sun8i_r40_ccu_ids[] = {
+        { .compatible = "allwinner,sun8i-r40-ccu" },
+        { }
+};
+
+static struct platform_driver sun8i_r40_ccu_driver = {
+        .probe  = sun8i_r40_ccu_probe,
+        .driver = {
+                .name   = "sun8i-r40-ccu",
+                .of_match_table = sun8i_r40_ccu_ids,
+        },
+};
+builtin_platform_driver(sun8i_r40_ccu_driver);
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
index 0a7deee74eea..48ee43734e05 100644
--- a/drivers/clk/tegra/clk-dfll.c
+++ b/drivers/clk/tegra/clk-dfll.c
@@ -1196,42 +1196,24 @@ static const struct file_operations attr_registers_fops = {
         .release        = single_release,
 };
 
-static int dfll_debug_init(struct tegra_dfll *td)
+static void dfll_debug_init(struct tegra_dfll *td)
 {
-        int ret;
+        struct dentry *root;
 
         if (!td || (td->mode == DFLL_UNINITIALIZED))
-                return 0;
-
-        td->debugfs_dir = debugfs_create_dir("tegra_dfll_fcpu", NULL);
-        if (!td->debugfs_dir)
-                return -ENOMEM;
-
-        ret = -ENOMEM;
-
-        if (!debugfs_create_file("enable", S_IRUGO | S_IWUSR,
-                                 td->debugfs_dir, td, &enable_fops))
-                goto err_out;
-
-        if (!debugfs_create_file("lock", S_IRUGO,
-                                 td->debugfs_dir, td, &lock_fops))
-                goto err_out;
+                return;
 
-        if (!debugfs_create_file("rate", S_IRUGO,
-                                 td->debugfs_dir, td, &rate_fops))
-                goto err_out;
+        root = debugfs_create_dir("tegra_dfll_fcpu", NULL);
+        td->debugfs_dir = root;
 
-        if (!debugfs_create_file("registers", S_IRUGO,
-                                 td->debugfs_dir, td, &attr_registers_fops))
-                goto err_out;
-
-        return 0;
-
-err_out:
-        debugfs_remove_recursive(td->debugfs_dir);
-        return ret;
+        debugfs_create_file("enable", S_IRUGO | S_IWUSR, root, td, &enable_fops);
+        debugfs_create_file("lock", S_IRUGO, root, td, &lock_fops);
+        debugfs_create_file("rate", S_IRUGO, root, td, &rate_fops);
+        debugfs_create_file("registers", S_IRUGO, root, td, &attr_registers_fops);
 }
 
+#else
+static void inline dfll_debug_init(struct tegra_dfll *td) { }
 #endif /* CONFIG_DEBUG_FS */
 
 /*
@@ -1715,9 +1697,7 @@ int tegra_dfll_register(struct platform_device *pdev,
                 return ret;
         }
 
-#ifdef CONFIG_DEBUG_FS
         dfll_debug_init(td);
-#endif
 
         return 0;
 }
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 5d5a22d529f5..1824f014202b 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1367,7 +1367,7 @@ static void __init tegra114_clock_init(struct device_node *np)
         tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
                                         &pll_x_params);
 
-        tegra_add_of_provider(np);
+        tegra_add_of_provider(np, of_clk_src_onecell_get);
         tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
 
         tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 50088e976611..0c69c7970950 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1479,7 +1479,7 @@ static void __init tegra124_132_clock_init_post(struct device_node *np)
                                   &pll_x_params);
         tegra_init_special_resets(1, tegra124_reset_assert,
                                   tegra124_reset_deassert);
-        tegra_add_of_provider(np);
+        tegra_add_of_provider(np, of_clk_src_onecell_get);
 
         clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np,
                                                         &emc_lock);
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 0ee56dd04cec..cc857d4d4a86 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -26,6 +26,8 @@
 #include "clk.h"
 #include "clk-id.h"
 
+#define MISC_CLK_ENB 0x48
+
 #define OSC_CTRL 0x50
 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
@@ -831,15 +833,25 @@ static void __init tegra20_periph_clk_init(void)
                                     periph_clk_enb_refcnt);
         clks[TEGRA20_CLK_PEX] = clk;
 
+        /* dev1 OSC divider */
+        clk_register_divider(NULL, "dev1_osc_div", "clk_m",
+                             0, clk_base + MISC_CLK_ENB, 22, 2,
+                             CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY,
+                             NULL);
+
+        /* dev2 OSC divider */
+        clk_register_divider(NULL, "dev2_osc_div", "clk_m",
+                             0, clk_base + MISC_CLK_ENB, 20, 2,
+                             CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY,
+                             NULL);
+
         /* cdev1 */
-        clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000);
-        clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
+        clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0,
                                     clk_base, 0, 94, periph_clk_enb_refcnt);
         clks[TEGRA20_CLK_CDEV1] = clk;
 
         /* cdev2 */
-        clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, 0, 26000000);
-        clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
+        clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0,
                                     clk_base, 0, 93, periph_clk_enb_refcnt);
         clks[TEGRA20_CLK_CDEV2] = clk;
 
@@ -1077,6 +1089,36 @@ static const struct of_device_id pmc_match[] __initconst = {
         { },
 };
 
+static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec,
+                                               void *data)
+{
+        struct clk_hw *parent_hw;
+        struct clk_hw *hw;
+        struct clk *clk;
+
+        clk = of_clk_src_onecell_get(clkspec, data);
+        if (IS_ERR(clk))
+                return clk;
+
+        /*
+         * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent
+         * clock is created by the pinctrl driver. It is possible for clk user
+         * to request these clocks before pinctrl driver got probed and hence
+         * user will get an orphaned clock. That might be undesirable because
+         * user may expect parent clock to be enabled by the child.
+         */
+        if (clkspec->args[0] == TEGRA20_CLK_CDEV1 ||
+            clkspec->args[0] == TEGRA20_CLK_CDEV2) {
+                hw = __clk_get_hw(clk);
+
+                parent_hw = clk_hw_get_parent(hw);
+                if (!parent_hw)
+                        return ERR_PTR(-EPROBE_DEFER);
+        }
+
+        return clk;
+}
+
 static void __init tegra20_clock_init(struct device_node *np)
 {
         struct device_node *node;
@@ -1115,7 +1157,7 @@ static void __init tegra20_clock_init(struct device_node *np)
 
         tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
 
-        tegra_add_of_provider(np);
+        tegra_add_of_provider(np, tegra20_clk_src_onecell_get);
         tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
 
         tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 9fb5d51ccce4..5435d01c636a 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -3567,7 +3567,7 @@ static void __init tegra210_clock_init(struct device_node *np)
         tegra_init_special_resets(2, tegra210_reset_assert,
                                   tegra210_reset_deassert);
 
-        tegra_add_of_provider(np);
+        tegra_add_of_provider(np, of_clk_src_onecell_get);
         tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
 
         tegra210_mbist_clk_init();
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index b316dfb6f6c7..acfe661b2ae7 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1349,7 +1349,7 @@ static void __init tegra30_clock_init(struct device_node *np)
 
         tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
 
-        tegra_add_of_provider(np);
+        tegra_add_of_provider(np, of_clk_src_onecell_get);
         tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
 
         tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index ba923f0d5953..593d76a114f9 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -298,7 +298,8 @@ static struct reset_controller_dev rst_ctlr = {
         .of_reset_n_cells = 1,
 };
 
-void __init tegra_add_of_provider(struct device_node *np)
+void __init tegra_add_of_provider(struct device_node *np,
+                                  void *clk_src_onecell_get)
 {
         int i;
 
@@ -314,7 +315,7 @@ void __init tegra_add_of_provider(struct device_node *np)
 
         clk_data.clks = clks;
         clk_data.clk_num = clk_num;
-        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+        of_clk_add_provider(np, clk_src_onecell_get, &clk_data);
 
         rst_ctlr.of_node = np;
         rst_ctlr.nr_resets = periph_banks * 32 + num_special_reset;
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index ba7e20e6a82b..e1f88463b600 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -763,7 +763,7 @@ struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
 
 struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
 
-void tegra_add_of_provider(struct device_node *np);
+void tegra_add_of_provider(struct device_node *np, void *clk_src_onecell_get);
 void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
 
 void tegra_audio_clk_init(void __iomem *clk_base,
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index ebc78ab2df05..4f5ff9fa11fd 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -51,6 +51,9 @@
 #define UNIPHIER_LD11_SYS_CLK_STDMAC(idx)                               \
         UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
 
+#define UNIPHIER_LD11_SYS_CLK_HSC(idx)                                  \
+        UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9)
+
 #define UNIPHIER_PRO4_SYS_CLK_GIO(idx)                                  \
         UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
 
@@ -182,6 +185,7 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
         /* Index 5 reserved for eMMC PHY */
         UNIPHIER_LD11_SYS_CLK_ETHER(6),
         UNIPHIER_LD11_SYS_CLK_STDMAC(8),                        /* HSC, MIO */
+        UNIPHIER_LD11_SYS_CLK_HSC(9),
         UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
         UNIPHIER_LD11_SYS_CLK_AIO(40),
         UNIPHIER_LD11_SYS_CLK_EVEA(41),
@@ -215,6 +219,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
         UNIPHIER_LD20_SYS_CLK_SD,
         UNIPHIER_LD11_SYS_CLK_ETHER(6),
         UNIPHIER_LD11_SYS_CLK_STDMAC(8),                        /* HSC */
+        UNIPHIER_LD11_SYS_CLK_HSC(9),
         /* GIO is always clock-enabled: no function for 0x210c bit5 */
         /*
          * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
diff --git a/drivers/clocksource/timer-sp804.c b/drivers/clocksource/timer-sp804.c
index 3ac9dec9a038..e01222ea888f 100644
--- a/drivers/clocksource/timer-sp804.c
+++ b/drivers/clocksource/timer-sp804.c
@@ -27,6 +27,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_clk.h>
 #include <linux/of_irq.h>
 #include <linux/sched_clock.h>
 
@@ -245,7 +246,7 @@ static int __init sp804_of_init(struct device_node *np)
                 clk1 = NULL;
 
         /* Get the 2nd clock if the timer has 3 timer clocks */
-        if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
+        if (of_clk_get_parent_count(np) == 3) {
                 clk2 = of_clk_get(np, 1);
                 if (IS_ERR(clk2)) {
                         pr_err("sp804: %s clock not found: %d\n", np->name,
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 020d6d84639c..25e80a5370ca 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -12,12 +12,12 @@
 
 #include <linux/io.h>
 #include <linux/clk.h>
-#include <linux/clk-provider.h>
 #include <linux/gpio/driver.h>
 #include <linux/irqdomain.h>
 #include <linux/irqchip/chained_irq.h>
 #include <linux/export.h>
 #include <linux/of.h>
+#include <linux/of_clk.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>
 #include <linux/of_irq.h>
@@ -1361,7 +1361,7 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
                         goto gpiochip_error;
         }
 
-        ret = of_count_phandle_with_args(node, "clocks", "#clock-cells");
+        ret = of_clk_get_parent_count(node);
         clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
         if (IS_ERR(clk)) {
                 ret = PTR_ERR(clk);
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index 111c44fc1c12..f874baaf934c 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -14,6 +14,7 @@
 #include <linux/pm_clock.h>
 #include <linux/pm_domain.h>
 #include <linux/of_address.h>
+#include <linux/of_clk.h>
 #include <linux/of_platform.h>
 #include <linux/clk.h>
 #include <linux/regmap.h>
@@ -400,8 +401,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
         pd->info = pd_info;
         pd->pmu = pmu;
 
-        pd->num_clks = of_count_phandle_with_args(node, "clocks",
-                                                  "#clock-cells");
+        pd->num_clks = of_clk_get_parent_count(node);
         if (pd->num_clks > 0) {
                 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
                                         sizeof(*pd->clks), GFP_KERNEL);
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 3e3d12ce4587..2d6f3fcf3211 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -31,6 +31,7 @@
 #include <linux/iopoll.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_clk.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/pm_domain.h>
@@ -731,7 +732,7 @@ static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
         unsigned int i, count;
         int err;
 
-        count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+        count = of_clk_get_parent_count(np);
         if (count == 0)
                 return -ENODEV;
 
diff --git a/include/dt-bindings/clock/actions,s900-cmu.h b/include/dt-bindings/clock/actions,s900-cmu.h
new file mode 100644
index 000000000000..7c1251565f43
--- /dev/null
+++ b/include/dt-bindings/clock/actions,s900-cmu.h
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Device Tree binding constants for Actions Semi S900 Clock Management Unit
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Copyright (c) 2018 Linaro Ltd.
+
+#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
+#define __DT_BINDINGS_CLOCK_S900_CMU_H
+
+#define CLK_NONE                        0
+
+/* fixed rate clocks */
+#define CLK_LOSC                        1
+#define CLK_HOSC                        2
+
+/* pll clocks */
+#define CLK_CORE_PLL                    3
+#define CLK_DEV_PLL                     4
+#define CLK_DDR_PLL                     5
+#define CLK_NAND_PLL                    6
+#define CLK_DISPLAY_PLL                 7
+#define CLK_DSI_PLL                     8
+#define CLK_ASSIST_PLL                  9
+#define CLK_AUDIO_PLL                   10
+
+/* system clock */
+#define CLK_CPU                         15
+#define CLK_DEV                         16
+#define CLK_NOC                         17
+#define CLK_NOC_MUX                     18
+#define CLK_NOC_DIV                     19
+#define CLK_AHB                         20
+#define CLK_APB                         21
+#define CLK_DMAC                        22
+
+/* peripheral device clock */
+#define CLK_GPIO                        23
+
+#define CLK_BISP                        24
+#define CLK_CSI0                        25
+#define CLK_CSI1                        26
+
+#define CLK_DE0                         27
+#define CLK_DE1                         28
+#define CLK_DE2                         29
+#define CLK_DE3                         30
+#define CLK_DSI                         32
+
+#define CLK_GPU                         33
+#define CLK_GPU_CORE                    34
+#define CLK_GPU_MEM                     35
+#define CLK_GPU_SYS                     36
+
+#define CLK_HDE                         37
+#define CLK_I2C0                        38
+#define CLK_I2C1                        39
+#define CLK_I2C2                        40
+#define CLK_I2C3                        41
+#define CLK_I2C4                        42
+#define CLK_I2C5                        43
+#define CLK_I2SRX                       44
+#define CLK_I2STX                       45
+#define CLK_IMX                         46
+#define CLK_LCD                         47
+#define CLK_NAND0                       48
+#define CLK_NAND1                       49
+#define CLK_PWM0                        50
+#define CLK_PWM1                        51
+#define CLK_PWM2                        52
+#define CLK_PWM3                        53
+#define CLK_PWM4                        54
+#define CLK_PWM5                        55
+#define CLK_SD0                         56
+#define CLK_SD1                         57
+#define CLK_SD2                         58
+#define CLK_SD3                         59
+#define CLK_SENSOR                      60
+#define CLK_SPEED_SENSOR                61
+#define CLK_SPI0                        62
+#define CLK_SPI1                        63
+#define CLK_SPI2                        64
+#define CLK_SPI3                        65
+#define CLK_THERMAL_SENSOR              66
+#define CLK_UART0                       67
+#define CLK_UART1                       68
+#define CLK_UART2                       69
+#define CLK_UART3                       70
+#define CLK_UART4                       71
+#define CLK_UART5                       72
+#define CLK_UART6                       73
+#define CLK_VCE                         74
+#define CLK_VDE                         75
+
+#define CLK_USB3_480MPLL0               76
+#define CLK_USB3_480MPHY0               77
+#define CLK_USB3_5GPHY                  78
+#define CLK_USB3_CCE                    79
+#define CLK_USB3_MAC                    80
+
+#define CLK_TIMER                       83
+
+#define CLK_HDMI_AUDIO                  84
+
+#define CLK_24M                         85
+
+#define CLK_EDP                         86
+
+#define CLK_24M_EDP                     87
+#define CLK_EDP_PLL                     88
+#define CLK_EDP_LINK                    89
+
+#define CLK_USB2H0_PLLEN                90
+#define CLK_USB2H0_PHY                  91
+#define CLK_USB2H0_CCE                  92
+#define CLK_USB2H1_PLLEN                93
+#define CLK_USB2H1_PHY                  94
+#define CLK_USB2H1_CCE                  95
+
+#define CLK_DDR0                        96
+#define CLK_DDR1                        97
+#define CLK_DMM                         98
+
+#define CLK_ETH_MAC                     99
+#define CLK_RMII_REF                    100
+
+#define CLK_NR_CLKS                     (CLK_RMII_REF + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
index d3558d897a4d..44761849fcbe 100644
--- a/include/dt-bindings/clock/aspeed-clock.h
+++ b/include/dt-bindings/clock/aspeed-clock.h
@@ -38,6 +38,7 @@
 #define ASPEED_CLK_MAC                  32
 #define ASPEED_CLK_BCLK                 33
 #define ASPEED_CLK_MPLL                 34
+#define ASPEED_CLK_24M                  35
 
 #define ASPEED_RESET_XDMA               0
 #define ASPEED_RESET_MCTP               1
@@ -45,8 +46,9 @@
 #define ASPEED_RESET_JTAG_MASTER        3
 #define ASPEED_RESET_MIC                4
 #define ASPEED_RESET_PWM                5
-#define ASPEED_RESET_PCIVGA             6
+#define ASPEED_RESET_PECI               6
 #define ASPEED_RESET_I2C                7
 #define ASPEED_RESET_AHB                8
+#define ASPEED_RESET_CRT1               9
 
 #endif
diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 000000000000..61955016a55b
--- /dev/null
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE         0
+#define CLKID_AO_I2C_MASTER     1
+#define CLKID_AO_I2C_SLAVE      2
+#define CLKID_AO_UART1          3
+#define CLKID_AO_UART2          4
+#define CLKID_AO_IR_BLASTER     5
+#define CLKID_AO_SAR_ADC        6
+#define CLKID_AO_CLK81          7
+#define CLKID_AO_SAR_ADC_SEL    8
+#define CLKID_AO_SAR_ADC_DIV    9
+#define CLKID_AO_SAR_ADC_CLK    10
+#define CLKID_AO_ALT_XTAL       11
+
+#endif
diff --git a/include/dt-bindings/clock/bcm-sr.h b/include/dt-bindings/clock/bcm-sr.h
index cff6c6fe2947..419011ba1a94 100644
--- a/include/dt-bindings/clock/bcm-sr.h
+++ b/include/dt-bindings/clock/bcm-sr.h
@@ -35,7 +35,7 @@
 
 /* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
 #define BCM_SR_GENPLL0                  0
-#define BCM_SR_GENPLL0_SATA_CLK         1
+#define BCM_SR_GENPLL0_125M_CLK         1
 #define BCM_SR_GENPLL0_SCR_CLK          2
 #define BCM_SR_GENPLL0_250M_CLK         3
 #define BCM_SR_GENPLL0_PCIE_AXI_CLK     4
@@ -50,9 +50,11 @@
 /* GENPLL 2 clock channel ID NITRO MHB*/
 #define BCM_SR_GENPLL2                  0
 #define BCM_SR_GENPLL2_NIC_CLK          1
-#define BCM_SR_GENPLL2_250_NITRO_CLK    2
+#define BCM_SR_GENPLL2_TS_500_CLK       2
 #define BCM_SR_GENPLL2_125_NITRO_CLK    3
 #define BCM_SR_GENPLL2_CHIMP_CLK        4
+#define BCM_SR_GENPLL2_NIC_FLASH_CLK    5
+#define BCM_SR_GENPLL2_FS4_CLK          6
 
 /* GENPLL 3 HSLS clock channel ID */
 #define BCM_SR_GENPLL3                  0
@@ -62,11 +64,16 @@
 /* GENPLL 4 SCR clock channel ID */
 #define BCM_SR_GENPLL4                  0
 #define BCM_SR_GENPLL4_CCN_CLK          1
+#define BCM_SR_GENPLL4_TPIU_PLL_CLK     2
+#define BCM_SR_GENPLL4_NOC_CLK          3
+#define BCM_SR_GENPLL4_CHCLK_FS4_CLK    4
+#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5
 
 /* GENPLL 5 FS4 clock channel ID */
 #define BCM_SR_GENPLL5                  0
-#define BCM_SR_GENPLL5_FS_CLK           1
-#define BCM_SR_GENPLL5_SPU_CLK          2
+#define BCM_SR_GENPLL5_FS4_HF_CLK       1
+#define BCM_SR_GENPLL5_CRYPTO_AE_CLK    2
+#define BCM_SR_GENPLL5_RAID_AE_CLK      3
 
 /* GENPLL 6 NITRO clock channel ID */
 #define BCM_SR_GENPLL6                  0
@@ -74,13 +81,16 @@
 
 /* LCPLL0  clock channel ID */
 #define BCM_SR_LCPLL0                   0
-#define BCM_SR_LCPLL0_SATA_REF_CLK      1
-#define BCM_SR_LCPLL0_USB_REF_CLK       2
-#define BCM_SR_LCPLL0_SATA_REFPN_CLK    3
+#define BCM_SR_LCPLL0_SATA_REFP_CLK     1
+#define BCM_SR_LCPLL0_SATA_REFN_CLK     2
+#define BCM_SR_LCPLL0_SATA_350_CLK      3
+#define BCM_SR_LCPLL0_SATA_500_CLK      4
 
 /* LCPLL1  clock channel ID */
 #define BCM_SR_LCPLL1                   0
 #define BCM_SR_LCPLL1_WAN_CLK           1
+#define BCM_SR_LCPLL1_USB_REF_CLK       2
+#define BCM_SR_LCPLL1_CRMU_TS_CLK       3
 
 /* LCPLL PCIE  clock channel ID */
 #define BCM_SR_LCPLL_PCIE               0
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 8ba99a5e3fd3..7a892be90549 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -125,5 +125,7 @@
 #define CLKID_VAPB_1            138
 #define CLKID_VAPB_SEL          139
 #define CLKID_VAPB              140
+#define CLKID_VDEC_1            153
+#define CLKID_VDEC_HEVC         156
 
 #endif /* __GXBB_CLKC_H */
diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
index fab30b3f78b2..136de24733be 100644
--- a/include/dt-bindings/clock/histb-clock.h
+++ b/include/dt-bindings/clock/histb-clock.h
@@ -62,6 +62,14 @@
 #define HISTB_USB2_PHY1_REF_CLK         40
 #define HISTB_USB2_PHY2_REF_CLK         41
 #define HISTB_COMBPHY0_CLK              42
+#define HISTB_USB3_BUS_CLK              43
+#define HISTB_USB3_UTMI_CLK             44
+#define HISTB_USB3_PIPE_CLK             45
+#define HISTB_USB3_SUSPEND_CLK          46
+#define HISTB_USB3_BUS_CLK1             47
+#define HISTB_USB3_UTMI_CLK1            48
+#define HISTB_USB3_PIPE_CLK1            49
+#define HISTB_USB3_SUSPEND_CLK1         50
 
 /* clocks provided by mcu CRG */
 #define HISTB_MCE_CLK                   1
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index da59fd9cdb5e..7ad171b8f3bf 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -271,6 +271,8 @@
 #define IMX6QDL_CLK_PRE_AXI                     258
 #define IMX6QDL_CLK_MLB_SEL                     259
 #define IMX6QDL_CLK_MLB_PODF                    260
-#define IMX6QDL_CLK_END                         261
+#define IMX6QDL_CLK_EPIT1                       261
+#define IMX6QDL_CLK_EPIT2                       262
+#define IMX6QDL_CLK_END                         263
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
index 36f0324902a5..cd2d6c570e86 100644
--- a/include/dt-bindings/clock/imx6sx-clock.h
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -275,6 +275,10 @@
 #define IMX6SX_PLL6_BYPASS              262
 #define IMX6SX_PLL7_BYPASS              263
 #define IMX6SX_CLK_SPDIF_GCLK           264
-#define IMX6SX_CLK_CLK_END              265
+#define IMX6SX_CLK_LVDS2_SEL            265
+#define IMX6SX_CLK_LVDS2_OUT            266
+#define IMX6SX_CLK_LVDS2_IN             267
+#define IMX6SX_CLK_ANACLK2              268
+#define IMX6SX_CLK_CLK_END              269
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
index ee9f1a508d2f..9564597cbfac 100644
--- a/include/dt-bindings/clock/imx6ul-clock.h
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -235,20 +235,27 @@
 #define IMX6UL_CLK_CSI_PODF             222
 #define IMX6UL_CLK_PLL3_120M            223
 #define IMX6UL_CLK_KPP                  224
+#define IMX6UL_CLK_CKO1_SEL             225
+#define IMX6UL_CLK_CKO1_PODF            226
+#define IMX6UL_CLK_CKO1                 227
+#define IMX6UL_CLK_CKO2_SEL             228
+#define IMX6UL_CLK_CKO2_PODF            229
+#define IMX6UL_CLK_CKO2                 230
+#define IMX6UL_CLK_CKO                  231
 
 /* For i.MX6ULL */
-#define IMX6ULL_CLK_ESAI_PRED           225
-#define IMX6ULL_CLK_ESAI_PODF           226
-#define IMX6ULL_CLK_ESAI_EXTAL          227
-#define IMX6ULL_CLK_ESAI_MEM            228
-#define IMX6ULL_CLK_ESAI_IPG            229
-#define IMX6ULL_CLK_DCP_CLK             230
-#define IMX6ULL_CLK_EPDC_PRE_SEL        231
-#define IMX6ULL_CLK_EPDC_SEL            232
-#define IMX6ULL_CLK_EPDC_PODF           233
-#define IMX6ULL_CLK_EPDC_ACLK           234
-#define IMX6ULL_CLK_EPDC_PIX            235
-#define IMX6ULL_CLK_ESAI_SEL            236
-#define IMX6UL_CLK_END                  237
+#define IMX6ULL_CLK_ESAI_PRED           232
+#define IMX6ULL_CLK_ESAI_PODF           233
+#define IMX6ULL_CLK_ESAI_EXTAL          234
+#define IMX6ULL_CLK_ESAI_MEM            235
+#define IMX6ULL_CLK_ESAI_IPG            236
+#define IMX6ULL_CLK_DCP_CLK             237
+#define IMX6ULL_CLK_EPDC_PRE_SEL        238
+#define IMX6ULL_CLK_EPDC_SEL            239
+#define IMX6ULL_CLK_EPDC_PODF           240
+#define IMX6ULL_CLK_EPDC_ACLK           241
+#define IMX6ULL_CLK_EPDC_PIX            242
+#define IMX6ULL_CLK_ESAI_SEL            243
+#define IMX6UL_CLK_END                  244
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index b2325d3e236a..0d67f53bba93 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -168,7 +168,7 @@
 #define IMX7D_SPDIF_ROOT_SRC            155
 #define IMX7D_SPDIF_ROOT_CG             156
 #define IMX7D_SPDIF_ROOT_DIV            157
-#define IMX7D_ENET1_REF_ROOT_CLK        158
+#define IMX7D_ENET1_IPG_ROOT_CLK        158
 #define IMX7D_ENET1_REF_ROOT_SRC        159
 #define IMX7D_ENET1_REF_ROOT_CG         160
 #define IMX7D_ENET1_REF_ROOT_DIV        161
@@ -176,7 +176,7 @@
 #define IMX7D_ENET1_TIME_ROOT_SRC       163
 #define IMX7D_ENET1_TIME_ROOT_CG        164
 #define IMX7D_ENET1_TIME_ROOT_DIV       165
-#define IMX7D_ENET2_REF_ROOT_CLK        166
+#define IMX7D_ENET2_IPG_ROOT_CLK        166
 #define IMX7D_ENET2_REF_ROOT_SRC        167
 #define IMX7D_ENET2_REF_ROOT_CG         168
 #define IMX7D_ENET2_REF_ROOT_DIV        169
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index dea9d46d4fa7..a60f47b49231 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -102,5 +102,6 @@
 #define CLKID_MPLL0             93
 #define CLKID_MPLL1             94
 #define CLKID_MPLL2             95
+#define CLKID_NAND_CLK          112
 
 #endif /* __MESON8B_CLKC_H */
diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
index 24e93dfcee9f..9ac2f2b5710a 100644
--- a/include/dt-bindings/clock/mt2701-clk.h
+++ b/include/dt-bindings/clock/mt2701-clk.h
@@ -171,13 +171,12 @@
 #define CLK_TOP_8BDAC                           151
 #define CLK_TOP_WBG_DIG_416M                    152
 #define CLK_TOP_DPI                             153
-#define CLK_TOP_HDMITX_CLKDIG_CTS               154
-#define CLK_TOP_DSI0_LNTC_DSI                   155
-#define CLK_TOP_AUD_EXT1                        156
-#define CLK_TOP_AUD_EXT2                        157
-#define CLK_TOP_NFI1X_PAD                       158
-#define CLK_TOP_AXISEL_D4                       159
-#define CLK_TOP_NR                              160
+#define CLK_TOP_DSI0_LNTC_DSI                   154
+#define CLK_TOP_AUD_EXT1                        155
+#define CLK_TOP_AUD_EXT2                        156
+#define CLK_TOP_NFI1X_PAD                       157
+#define CLK_TOP_AXISEL_D4                       158
+#define CLK_TOP_NR                              159
 
 /* APMIXEDSYS */
 
@@ -194,7 +193,8 @@
 #define CLK_APMIXED_HADDS2PLL                   11
 #define CLK_APMIXED_AUD2PLL                     12
 #define CLK_APMIXED_TVD2PLL                     13
-#define CLK_APMIXED_NR                          14
+#define CLK_APMIXED_HDMI_REF                    14
+#define CLK_APMIXED_NR                          15
 
 /* DDRPHY */
 
@@ -431,6 +431,10 @@
 #define CLK_ETHSYS_CRYPTO                       8
 #define CLK_ETHSYS_NR                           9
 
+/* G3DSYS */
+#define CLK_G3DSYS_CORE                         1
+#define CLK_G3DSYS_NR                           2
+
 /* BDP */
 
 #define CLK_BDP_BRG_BA                          1
diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
new file mode 100644
index 000000000000..f21522605b94
--- /dev/null
+++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Nuvoton NPCM7xx Clock Generator binding
+ * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk
+ *
+ * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H
+#define __DT_BINDINGS_CLOCK_NPCM7XX_H
+
+
+#define NPCM7XX_CLK_CPU 0
+#define NPCM7XX_CLK_GFX_PIXEL 1
+#define NPCM7XX_CLK_MC 2
+#define NPCM7XX_CLK_ADC 3
+#define NPCM7XX_CLK_AHB 4
+#define NPCM7XX_CLK_TIMER 5
+#define NPCM7XX_CLK_UART 6
+#define NPCM7XX_CLK_MMC  7
+#define NPCM7XX_CLK_SPI3 8
+#define NPCM7XX_CLK_PCI  9
+#define NPCM7XX_CLK_AXI 10
+#define NPCM7XX_CLK_APB4 11
+#define NPCM7XX_CLK_APB3 12
+#define NPCM7XX_CLK_APB2 13
+#define NPCM7XX_CLK_APB1 14
+#define NPCM7XX_CLK_APB5 15
+#define NPCM7XX_CLK_CLKOUT 16
+#define NPCM7XX_CLK_GFX  17
+#define NPCM7XX_CLK_SU   18
+#define NPCM7XX_CLK_SU48 19
+#define NPCM7XX_CLK_SDHC 20
+#define NPCM7XX_CLK_SPI0 21
+#define NPCM7XX_CLK_SPIX 22
+
+#define NPCM7XX_CLK_REFCLK 23
+#define NPCM7XX_CLK_SYSBYPCK 24
+#define NPCM7XX_CLK_MCBYPCK 25
+
+#define NPCM7XX_NUM_CLOCKS       (NPCM7XX_CLK_MCBYPCK+1)
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h
new file mode 100644
index 000000000000..58a242e656b1
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
+#define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
+
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC                             0
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC                             1
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC                             2
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC                             3
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC                             4
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC                             5
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC                             6
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC                             7
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC                             8
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC                             9
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC                             10
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC                             11
+#define BLSP1_UART1_APPS_CLK_SRC                                12
+#define BLSP1_UART2_APPS_CLK_SRC                                13
+#define BLSP1_UART3_APPS_CLK_SRC                                14
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC                             15
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC                             16
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC                             17
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC                             18
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC                             19
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC                             20
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC                             21
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC                             22
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC                             23
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC                             24
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC                             25
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC                             26
+#define BLSP2_UART1_APPS_CLK_SRC                                27
+#define BLSP2_UART2_APPS_CLK_SRC                                28
+#define BLSP2_UART3_APPS_CLK_SRC                                29
+#define GCC_AGGRE1_NOC_XO_CLK                                   30
+#define GCC_AGGRE1_UFS_AXI_CLK                                  31
+#define GCC_AGGRE1_USB3_AXI_CLK                                 32
+#define GCC_APSS_QDSS_TSCTR_DIV2_CLK                            33
+#define GCC_APSS_QDSS_TSCTR_DIV8_CLK                            34
+#define GCC_BIMC_HMSS_AXI_CLK                                   35
+#define GCC_BIMC_MSS_Q6_AXI_CLK                                 36
+#define GCC_BLSP1_AHB_CLK                                       37
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK                             38
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK                             39
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK                             40
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK                             41
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK                             42
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK                             43
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK                             44
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK                             45
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK                             46
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK                             47
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK                             48
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK                             49
+#define GCC_BLSP1_SLEEP_CLK                                     50
+#define GCC_BLSP1_UART1_APPS_CLK                                51
+#define GCC_BLSP1_UART2_APPS_CLK                                52
+#define GCC_BLSP1_UART3_APPS_CLK                                53
+#define GCC_BLSP2_AHB_CLK                                       54
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK                             55
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK                             56
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK                             57
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK                             58
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK                             59
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK                             60
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK                             61
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK                             62
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK                             63
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK                             64
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK                             65
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK                             66
+#define GCC_BLSP2_SLEEP_CLK                                     67
+#define GCC_BLSP2_UART1_APPS_CLK                                68
+#define GCC_BLSP2_UART2_APPS_CLK                                69
+#define GCC_BLSP2_UART3_APPS_CLK                                70
+#define GCC_CFG_NOC_USB3_AXI_CLK                                71
+#define GCC_GP1_CLK                                             72
+#define GCC_GP2_CLK                                             73
+#define GCC_GP3_CLK                                             74
+#define GCC_GPU_BIMC_GFX_CLK                                    75
+#define GCC_GPU_BIMC_GFX_SRC_CLK                                76
+#define GCC_GPU_CFG_AHB_CLK                                     77
+#define GCC_GPU_SNOC_DVM_GFX_CLK                                78
+#define GCC_HMSS_AHB_CLK                                        79
+#define GCC_HMSS_AT_CLK                                         80
+#define GCC_HMSS_DVM_BUS_CLK                                    81
+#define GCC_HMSS_RBCPR_CLK                                      82
+#define GCC_HMSS_TRIG_CLK                                       83
+#define GCC_LPASS_AT_CLK                                        84
+#define GCC_LPASS_TRIG_CLK                                      85
+#define GCC_MMSS_NOC_CFG_AHB_CLK                                86
+#define GCC_MMSS_QM_AHB_CLK                                     87
+#define GCC_MMSS_QM_CORE_CLK                                    88
+#define GCC_MMSS_SYS_NOC_AXI_CLK                                89
+#define GCC_MSS_AT_CLK                                          90
+#define GCC_PCIE_0_AUX_CLK                                      91
+#define GCC_PCIE_0_CFG_AHB_CLK                                  92
+#define GCC_PCIE_0_MSTR_AXI_CLK                                 93
+#define GCC_PCIE_0_PIPE_CLK                                     94
+#define GCC_PCIE_0_SLV_AXI_CLK                                  95
+#define GCC_PCIE_PHY_AUX_CLK                                    96
+#define GCC_PDM2_CLK                                            97
+#define GCC_PDM_AHB_CLK                                         98
+#define GCC_PDM_XO4_CLK                                         99
+#define GCC_PRNG_AHB_CLK                                        100
+#define GCC_SDCC2_AHB_CLK                                       101
+#define GCC_SDCC2_APPS_CLK                                      102
+#define GCC_SDCC4_AHB_CLK                                       103
+#define GCC_SDCC4_APPS_CLK                                      104
+#define GCC_TSIF_AHB_CLK                                        105
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK                          106
+#define GCC_TSIF_REF_CLK                                        107
+#define GCC_UFS_AHB_CLK                                         108
+#define GCC_UFS_AXI_CLK                                         109
+#define GCC_UFS_ICE_CORE_CLK                                    110
+#define GCC_UFS_PHY_AUX_CLK                                     111
+#define GCC_UFS_RX_SYMBOL_0_CLK                                 112
+#define GCC_UFS_RX_SYMBOL_1_CLK                                 113
+#define GCC_UFS_TX_SYMBOL_0_CLK                                 114
+#define GCC_UFS_UNIPRO_CORE_CLK                                 115
+#define GCC_USB30_MASTER_CLK                                    116
+#define GCC_USB30_MOCK_UTMI_CLK                                 117
+#define GCC_USB30_SLEEP_CLK                                     118
+#define GCC_USB3_PHY_AUX_CLK                                    119
+#define GCC_USB3_PHY_PIPE_CLK                                   120
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK                             121
+#define GP1_CLK_SRC                                             122
+#define GP2_CLK_SRC                                             123
+#define GP3_CLK_SRC                                             124
+#define GPLL0                                                   125
+#define GPLL0_OUT_EVEN                                          126
+#define GPLL0_OUT_MAIN                                          127
+#define GPLL0_OUT_ODD                                           128
+#define GPLL0_OUT_TEST                                          129
+#define GPLL1                                                   130
+#define GPLL1_OUT_EVEN                                          131
+#define GPLL1_OUT_MAIN                                          132
+#define GPLL1_OUT_ODD                                           133
+#define GPLL1_OUT_TEST                                          134
+#define GPLL2                                                   135
+#define GPLL2_OUT_EVEN                                          136
+#define GPLL2_OUT_MAIN                                          137
+#define GPLL2_OUT_ODD                                           138
+#define GPLL2_OUT_TEST                                          139
+#define GPLL3                                                   140
+#define GPLL3_OUT_EVEN                                          141
+#define GPLL3_OUT_MAIN                                          142
+#define GPLL3_OUT_ODD                                           143
+#define GPLL3_OUT_TEST                                          144
+#define GPLL4                                                   145
+#define GPLL4_OUT_EVEN                                          146
+#define GPLL4_OUT_MAIN                                          147
+#define GPLL4_OUT_ODD                                           148
+#define GPLL4_OUT_TEST                                          149
+#define GPLL6                                                   150
+#define GPLL6_OUT_EVEN                                          151
+#define GPLL6_OUT_MAIN                                          152
+#define GPLL6_OUT_ODD                                           153
+#define GPLL6_OUT_TEST                                          154
+#define HMSS_AHB_CLK_SRC                                        155
+#define HMSS_RBCPR_CLK_SRC                                      156
+#define PCIE_AUX_CLK_SRC                                        157
+#define PDM2_CLK_SRC                                            158
+#define SDCC2_APPS_CLK_SRC                                      159
+#define SDCC4_APPS_CLK_SRC                                      160
+#define TSIF_REF_CLK_SRC                                        161
+#define UFS_AXI_CLK_SRC                                         162
+#define USB30_MASTER_CLK_SRC                                    163
+#define USB30_MOCK_UTMI_CLK_SRC                                 164
+#define USB3_PHY_AUX_CLK_SRC                                    165
+
+#define PCIE_0_GDSC                                             0
+#define UFS_GDSC                                                1
+#define USB_30_GDSC                                             2
+
+#define GCC_BLSP1_QUP1_BCR                                      0
+#define GCC_BLSP1_QUP2_BCR                                      1
+#define GCC_BLSP1_QUP3_BCR                                      2
+#define GCC_BLSP1_QUP4_BCR                                      3
+#define GCC_BLSP1_QUP5_BCR                                      4
+#define GCC_BLSP1_QUP6_BCR                                      5
+#define GCC_BLSP2_QUP1_BCR                                      6
+#define GCC_BLSP2_QUP2_BCR                                      7
+#define GCC_BLSP2_QUP3_BCR                                      8
+#define GCC_BLSP2_QUP4_BCR                                      9
+#define GCC_BLSP2_QUP5_BCR                                      10
+#define GCC_BLSP2_QUP6_BCR                                      11
+#define GCC_PCIE_0_BCR                                          12
+#define GCC_PDM_BCR                                             13
+#define GCC_SDCC2_BCR                                           14
+#define GCC_SDCC4_BCR                                           15
+#define GCC_TSIF_BCR                                            16
+#define GCC_UFS_BCR                                             17
+#define GCC_USB_30_BCR                                          18
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h
new file mode 100644
index 000000000000..aca61264f12c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sdm845.h
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
+
+/* GCC clock registers */
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK                              0
+#define GCC_AGGRE_UFS_CARD_AXI_CLK                              1
+#define GCC_AGGRE_UFS_PHY_AXI_CLK                               2
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK                             3
+#define GCC_AGGRE_USB3_SEC_AXI_CLK                              4
+#define GCC_BOOT_ROM_AHB_CLK                                    5
+#define GCC_CAMERA_AHB_CLK                                      6
+#define GCC_CAMERA_AXI_CLK                                      7
+#define GCC_CAMERA_XO_CLK                                       8
+#define GCC_CE1_AHB_CLK                                         9
+#define GCC_CE1_AXI_CLK                                         10
+#define GCC_CE1_CLK                                             11
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK                           12
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK                            13
+#define GCC_CPUSS_AHB_CLK                                       14
+#define GCC_CPUSS_AHB_CLK_SRC                                   15
+#define GCC_CPUSS_RBCPR_CLK                                     16
+#define GCC_CPUSS_RBCPR_CLK_SRC                                 17
+#define GCC_DDRSS_GPU_AXI_CLK                                   18
+#define GCC_DISP_AHB_CLK                                        19
+#define GCC_DISP_AXI_CLK                                        20
+#define GCC_DISP_GPLL0_CLK_SRC                                  21
+#define GCC_DISP_GPLL0_DIV_CLK_SRC                              22
+#define GCC_DISP_XO_CLK                                         23
+#define GCC_GP1_CLK                                             24
+#define GCC_GP1_CLK_SRC                                         25
+#define GCC_GP2_CLK                                             26
+#define GCC_GP2_CLK_SRC                                         27
+#define GCC_GP3_CLK                                             28
+#define GCC_GP3_CLK_SRC                                         29
+#define GCC_GPU_CFG_AHB_CLK                                     30
+#define GCC_GPU_GPLL0_CLK_SRC                                   31
+#define GCC_GPU_GPLL0_DIV_CLK_SRC                               32
+#define GCC_GPU_MEMNOC_GFX_CLK                                  33
+#define GCC_GPU_SNOC_DVM_GFX_CLK                                34
+#define GCC_MSS_AXIS2_CLK                                       35
+#define GCC_MSS_CFG_AHB_CLK                                     36
+#define GCC_MSS_GPLL0_DIV_CLK_SRC                               37
+#define GCC_MSS_MFAB_AXIS_CLK                                   38
+#define GCC_MSS_Q6_MEMNOC_AXI_CLK                               39
+#define GCC_MSS_SNOC_AXI_CLK                                    40
+#define GCC_PCIE_0_AUX_CLK                                      41
+#define GCC_PCIE_0_AUX_CLK_SRC                                  42
+#define GCC_PCIE_0_CFG_AHB_CLK                                  43
+#define GCC_PCIE_0_CLKREF_CLK                                   44
+#define GCC_PCIE_0_MSTR_AXI_CLK                                 45
+#define GCC_PCIE_0_PIPE_CLK                                     46
+#define GCC_PCIE_0_SLV_AXI_CLK                                  47
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK                              48
+#define GCC_PCIE_1_AUX_CLK                                      49
+#define GCC_PCIE_1_AUX_CLK_SRC                                  50
+#define GCC_PCIE_1_CFG_AHB_CLK                                  51
+#define GCC_PCIE_1_CLKREF_CLK                                   52
+#define GCC_PCIE_1_MSTR_AXI_CLK                                 53
+#define GCC_PCIE_1_PIPE_CLK                                     54
+#define GCC_PCIE_1_SLV_AXI_CLK                                  55
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK                              56
+#define GCC_PCIE_PHY_AUX_CLK                                    57
+#define GCC_PCIE_PHY_REFGEN_CLK                                 58
+#define GCC_PCIE_PHY_REFGEN_CLK_SRC                             59
+#define GCC_PDM2_CLK                                            60
+#define GCC_PDM2_CLK_SRC                                        61
+#define GCC_PDM_AHB_CLK                                         62
+#define GCC_PDM_XO4_CLK                                         63
+#define GCC_PRNG_AHB_CLK                                        64
+#define GCC_QMIP_CAMERA_AHB_CLK                                 65
+#define GCC_QMIP_DISP_AHB_CLK                                   66
+#define GCC_QMIP_VIDEO_AHB_CLK                                  67
+#define GCC_QUPV3_WRAP0_S0_CLK                                  68
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC                              69
+#define GCC_QUPV3_WRAP0_S1_CLK                                  70
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC                              71
+#define GCC_QUPV3_WRAP0_S2_CLK                                  72
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC                              73
+#define GCC_QUPV3_WRAP0_S3_CLK                                  74
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC                              75
+#define GCC_QUPV3_WRAP0_S4_CLK                                  76
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC                              77
+#define GCC_QUPV3_WRAP0_S5_CLK                                  78
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC                              79
+#define GCC_QUPV3_WRAP0_S6_CLK                                  80
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC                              81
+#define GCC_QUPV3_WRAP0_S7_CLK                                  82
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC                              83
+#define GCC_QUPV3_WRAP1_S0_CLK                                  84
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC                              85
+#define GCC_QUPV3_WRAP1_S1_CLK                                  86
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC                              87
+#define GCC_QUPV3_WRAP1_S2_CLK                                  88
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC                              89
+#define GCC_QUPV3_WRAP1_S3_CLK                                  90
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC                              91
+#define GCC_QUPV3_WRAP1_S4_CLK                                  92
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC                              93
+#define GCC_QUPV3_WRAP1_S5_CLK                                  94
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC                              95
+#define GCC_QUPV3_WRAP1_S6_CLK                                  96
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC                              97
+#define GCC_QUPV3_WRAP1_S7_CLK                                  98
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC                              99
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK                              100
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK                              101
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK                              102
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK                              103
+#define GCC_SDCC2_AHB_CLK                                       104
+#define GCC_SDCC2_APPS_CLK                                      105
+#define GCC_SDCC2_APPS_CLK_SRC                                  106
+#define GCC_SDCC4_AHB_CLK                                       107
+#define GCC_SDCC4_APPS_CLK                                      108
+#define GCC_SDCC4_APPS_CLK_SRC                                  109
+#define GCC_SYS_NOC_CPUSS_AHB_CLK                               110
+#define GCC_TSIF_AHB_CLK                                        111
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK                          112
+#define GCC_TSIF_REF_CLK                                        113
+#define GCC_TSIF_REF_CLK_SRC                                    114
+#define GCC_UFS_CARD_AHB_CLK                                    115
+#define GCC_UFS_CARD_AXI_CLK                                    116
+#define GCC_UFS_CARD_AXI_CLK_SRC                                117
+#define GCC_UFS_CARD_CLKREF_CLK                                 118
+#define GCC_UFS_CARD_ICE_CORE_CLK                               119
+#define GCC_UFS_CARD_ICE_CORE_CLK_SRC                           120
+#define GCC_UFS_CARD_PHY_AUX_CLK                                121
+#define GCC_UFS_CARD_PHY_AUX_CLK_SRC                            122
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK                            123
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK                            124
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK                            125
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK                            126
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC                        127
+#define GCC_UFS_MEM_CLKREF_CLK                                  128
+#define GCC_UFS_PHY_AHB_CLK                                     129
+#define GCC_UFS_PHY_AXI_CLK                                     130
+#define GCC_UFS_PHY_AXI_CLK_SRC                                 131
+#define GCC_UFS_PHY_ICE_CORE_CLK                                132
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC                            133
+#define GCC_UFS_PHY_PHY_AUX_CLK                                 134
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC                             135
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK                             136
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK                             137
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK                             138
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK                             139
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC                         140
+#define GCC_USB30_PRIM_MASTER_CLK                               141
+#define GCC_USB30_PRIM_MASTER_CLK_SRC                           142
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK                            143
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC                        144
+#define GCC_USB30_PRIM_SLEEP_CLK                                145
+#define GCC_USB30_SEC_MASTER_CLK                                146
+#define GCC_USB30_SEC_MASTER_CLK_SRC                            147
+#define GCC_USB30_SEC_MOCK_UTMI_CLK                             148
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC                         149
+#define GCC_USB30_SEC_SLEEP_CLK                                 150
+#define GCC_USB3_PRIM_CLKREF_CLK                                151
+#define GCC_USB3_PRIM_PHY_AUX_CLK                               152
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC                           153
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK                           154
+#define GCC_USB3_PRIM_PHY_PIPE_CLK                              155
+#define GCC_USB3_SEC_CLKREF_CLK                                 156
+#define GCC_USB3_SEC_PHY_AUX_CLK                                157
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC                            158
+#define GCC_USB3_SEC_PHY_PIPE_CLK                               159
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK                            160
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK                             161
+#define GCC_VIDEO_AHB_CLK                                       162
+#define GCC_VIDEO_AXI_CLK                                       163
+#define GCC_VIDEO_XO_CLK                                        164
+#define GPLL0                                                   165
+#define GPLL0_OUT_EVEN                                          166
+#define GPLL0_OUT_MAIN                                          167
+#define GCC_GPU_IREF_CLK                                        168
+#define GCC_SDCC1_AHB_CLK                                       169
+#define GCC_SDCC1_APPS_CLK                                      170
+#define GCC_SDCC1_ICE_CORE_CLK                                  171
+#define GCC_SDCC1_APPS_CLK_SRC                                  172
+#define GCC_SDCC1_ICE_CORE_CLK_SRC                              173
+#define GCC_APC_VS_CLK                                          174
+#define GCC_GPU_VS_CLK                                          175
+#define GCC_MSS_VS_CLK                                          176
+#define GCC_VDDA_VS_CLK                                         177
+#define GCC_VDDCX_VS_CLK                                        178
+#define GCC_VDDMX_VS_CLK                                        179
+#define GCC_VS_CTRL_AHB_CLK                                     180
+#define GCC_VS_CTRL_CLK                                         181
+#define GCC_VS_CTRL_CLK_SRC                                     182
+#define GCC_VSENSOR_CLK_SRC                                     183
+#define GPLL4                                                   184
+
+/* GCC Resets */
+#define GCC_MMSS_BCR                                            0
+#define GCC_PCIE_0_BCR                                          1
+#define GCC_PCIE_1_BCR                                          2
+#define GCC_PCIE_PHY_BCR                                        3
+#define GCC_PDM_BCR                                             4
+#define GCC_PRNG_BCR                                            5
+#define GCC_QUPV3_WRAPPER_0_BCR                                 6
+#define GCC_QUPV3_WRAPPER_1_BCR                                 7
+#define GCC_QUSB2PHY_PRIM_BCR                                   8
+#define GCC_QUSB2PHY_SEC_BCR                                    9
+#define GCC_SDCC2_BCR                                           10
+#define GCC_SDCC4_BCR                                           11
+#define GCC_TSIF_BCR                                            12
+#define GCC_UFS_CARD_BCR                                        13
+#define GCC_UFS_PHY_BCR                                         14
+#define GCC_USB30_PRIM_BCR                                      15
+#define GCC_USB30_SEC_BCR                                       16
+#define GCC_USB3_PHY_PRIM_BCR                                   17
+#define GCC_USB3PHY_PHY_PRIM_BCR                                18
+#define GCC_USB3_DP_PHY_PRIM_BCR                                19
+#define GCC_USB3_PHY_SEC_BCR                                    20
+#define GCC_USB3PHY_PHY_SEC_BCR                                 21
+#define GCC_USB3_DP_PHY_SEC_BCR                                 22
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR                             23
+#define GCC_PCIE_0_PHY_BCR                                      24
+#define GCC_PCIE_1_PHY_BCR                                      25
+
+/* GCC GDSCRs */
+#define PCIE_0_GDSC                                             0
+#define PCIE_1_GDSC                                             1
+#define UFS_CARD_GDSC                                           2
+#define UFS_PHY_GDSC                                            3
+#define USB30_PRIM_GDSC                                         4
+#define USB30_SEC_GDSC                                          5
+#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC                 6
+#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC                  7
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC                      8
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC                      9
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC                       10
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC                       11
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC                        12
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h
new file mode 100644
index 000000000000..f48fbd6f2095
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,rpmh.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
+
+
+#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
+#define _DT_BINDINGS_CLK_MSM_RPMH_H
+
+/* RPMh controlled clocks */
+#define RPMH_CXO_CLK                            0
+#define RPMH_CXO_CLK_A                          1
+#define RPMH_LN_BB_CLK2                         2
+#define RPMH_LN_BB_CLK2_A                       3
+#define RPMH_LN_BB_CLK3                         4
+#define RPMH_LN_BB_CLK3_A                       5
+#define RPMH_RF_CLK1                            6
+#define RPMH_RF_CLK1_A                          7
+#define RPMH_RF_CLK2                            8
+#define RPMH_RF_CLK2_A                          9
+#define RPMH_RF_CLK3                            10
+#define RPMH_RF_CLK3_A                          11
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h
new file mode 100644
index 000000000000..1b868165e8ce
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,videocc-sdm845.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
+
+/* VIDEO_CC clock registers */
+#define VIDEO_CC_APB_CLK                0
+#define VIDEO_CC_AT_CLK                 1
+#define VIDEO_CC_QDSS_TRIG_CLK          2
+#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK    3
+#define VIDEO_CC_VCODEC0_AXI_CLK        4
+#define VIDEO_CC_VCODEC0_CORE_CLK       5
+#define VIDEO_CC_VCODEC1_AXI_CLK        6
+#define VIDEO_CC_VCODEC1_CORE_CLK       7
+#define VIDEO_CC_VENUS_AHB_CLK          8
+#define VIDEO_CC_VENUS_CLK_SRC          9
+#define VIDEO_CC_VENUS_CTL_AXI_CLK      10
+#define VIDEO_CC_VENUS_CTL_CORE_CLK     11
+#define VIDEO_PLL0                      12
+
+/* VIDEO_CC Resets */
+#define VIDEO_CC_VENUS_BCR              0
+#define VIDEO_CC_VCODEC0_BCR            1
+#define VIDEO_CC_VCODEC1_BCR            2
+#define VIDEO_CC_INTERFACE_BCR          3
+
+/* VIDEO_CC GDSCRs */
+#define VENUS_GDSC                      0
+#define VCODEC0_GDSC                    1
+#define VCODEC1_GDSC                    2
+
+#endif
diff --git a/include/dt-bindings/clock/r8a77470-cpg-mssr.h b/include/dt-bindings/clock/r8a77470-cpg-mssr.h
new file mode 100644
index 000000000000..34cba49d0f84
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77470-cpg-mssr.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77470 CPG Core Clocks */
+#define R8A77470_CLK_Z2         0
+#define R8A77470_CLK_ZTR        1
+#define R8A77470_CLK_ZTRD2      2
+#define R8A77470_CLK_ZT         3
+#define R8A77470_CLK_ZX         4
+#define R8A77470_CLK_ZS         5
+#define R8A77470_CLK_HP         6
+#define R8A77470_CLK_B          7
+#define R8A77470_CLK_LB         8
+#define R8A77470_CLK_P          9
+#define R8A77470_CLK_CL         10
+#define R8A77470_CLK_CP         11
+#define R8A77470_CLK_M2         12
+#define R8A77470_CLK_ZB3        13
+#define R8A77470_CLK_SDH        14
+#define R8A77470_CLK_SD0        15
+#define R8A77470_CLK_SD1        16
+#define R8A77470_CLK_SD2        17
+#define R8A77470_CLK_MP         18
+#define R8A77470_CLK_QSPI       19
+#define R8A77470_CLK_CPEX       20
+#define R8A77470_CLK_RCAN       21
+#define R8A77470_CLK_R          22
+#define R8A77470_CLK_OSC        23
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
new file mode 100644
index 000000000000..a596a482f3a9
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77990 CPG Core Clocks */
+#define R8A77990_CLK_Z2                 0
+#define R8A77990_CLK_ZR                 1
+#define R8A77990_CLK_ZG                 2
+#define R8A77990_CLK_ZTR                3
+#define R8A77990_CLK_ZT                 4
+#define R8A77990_CLK_ZX                 5
+#define R8A77990_CLK_S0D1               6
+#define R8A77990_CLK_S0D3               7
+#define R8A77990_CLK_S0D6               8
+#define R8A77990_CLK_S0D12              9
+#define R8A77990_CLK_S0D24              10
+#define R8A77990_CLK_S1D1               11
+#define R8A77990_CLK_S1D2               12
+#define R8A77990_CLK_S1D4               13
+#define R8A77990_CLK_S2D1               14
+#define R8A77990_CLK_S2D2               15
+#define R8A77990_CLK_S2D4               16
+#define R8A77990_CLK_S3D1               17
+#define R8A77990_CLK_S3D2               18
+#define R8A77990_CLK_S3D4               19
+#define R8A77990_CLK_S0D6C              20
+#define R8A77990_CLK_S3D1C              21
+#define R8A77990_CLK_S3D2C              22
+#define R8A77990_CLK_S3D4C              23
+#define R8A77990_CLK_LB                 24
+#define R8A77990_CLK_CL                 25
+#define R8A77990_CLK_ZB3                26
+#define R8A77990_CLK_ZB3D2              27
+#define R8A77990_CLK_CR                 28
+#define R8A77990_CLK_CRD2               29
+#define R8A77990_CLK_SD0H               30
+#define R8A77990_CLK_SD0                31
+#define R8A77990_CLK_SD1H               32
+#define R8A77990_CLK_SD1                33
+#define R8A77990_CLK_SD3H               34
+#define R8A77990_CLK_SD3                35
+#define R8A77990_CLK_RPC                36
+#define R8A77990_CLK_RPCD2              37
+#define R8A77990_CLK_ZA2                38
+#define R8A77990_CLK_ZA8                39
+#define R8A77990_CLK_Z2D                40
+#define R8A77990_CLK_CANFD              41
+#define R8A77990_CLK_MSO                42
+#define R8A77990_CLK_R                  43
+#define R8A77990_CLK_OSC                44
+#define R8A77990_CLK_LV0                45
+#define R8A77990_CLK_LV1                46
+#define R8A77990_CLK_CSI0               47
+#define R8A77990_CLK_CP                 48
+#define R8A77990_CLK_CPEX               49
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h
new file mode 100644
index 000000000000..76136132a13e
--- /dev/null
+++ b/include/dt-bindings/clock/sun50i-h6-r-ccu.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+
+#define CLK_AR100               0
+
+#define CLK_R_APB1              2
+
+#define CLK_R_APB1_TIMER        4
+#define CLK_R_APB1_TWD          5
+#define CLK_R_APB1_PWM          6
+#define CLK_R_APB2_UART         7
+#define CLK_R_APB2_I2C          8
+#define CLK_R_APB1_IR           9
+#define CLK_R_APB1_W1           10
+
+#define CLK_IR                  11
+#define CLK_W1                  12
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h
new file mode 100644
index 000000000000..d342c0b6b2a7
--- /dev/null
+++ b/include/dt-bindings/reset/axg-aoclkc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+
+#define RESET_AO_REMOTE         0
+#define RESET_AO_I2C_MASTER     1
+#define RESET_AO_I2C_SLAVE      2
+#define RESET_AO_UART1          3
+#define RESET_AO_UART2          4
+#define RESET_AO_IR_BLASTER     5
+
+#endif
diff --git a/include/dt-bindings/reset/mt2701-resets.h b/include/dt-bindings/reset/mt2701-resets.h
index 21deb547cfa4..50b7f066da9a 100644
--- a/include/dt-bindings/reset/mt2701-resets.h
+++ b/include/dt-bindings/reset/mt2701-resets.h
@@ -87,4 +87,7 @@
 #define MT2701_ETHSYS_GMAC_RST                  23
 #define MT2701_ETHSYS_PPE_RST                   31
 
+/* G3DSYS resets */
+#define MT2701_G3DSYS_CORE_RST                  0
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h
new file mode 100644
index 000000000000..01c84dba49a4
--- /dev/null
+++ b/include/dt-bindings/reset/sun50i-h6-r-ccu.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
+
+#define RST_R_APB1_TIMER        0
+#define RST_R_APB1_TWD          1
+#define RST_R_APB1_PWM          2
+#define RST_R_APB2_UART         3
+#define RST_R_APB2_I2C          4
+#define RST_R_APB1_IR           5
+#define RST_R_APB1_W1           6
+
+#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 1d25e149c1c5..b7cfa037e593 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -13,6 +13,7 @@
 
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/of_clk.h>
 
 #ifdef CONFIG_COMMON_CLK
 
@@ -218,7 +219,7 @@ struct clk_ops {
         int             (*get_phase)(struct clk_hw *hw);
         int             (*set_phase)(struct clk_hw *hw, int degrees);
         void            (*init)(struct clk_hw *hw);
-        int             (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
+        void            (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
 };
 
 /**
@@ -805,8 +806,6 @@ unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
 
 struct of_device_id;
 
-typedef void (*of_clk_init_cb_t)(struct device_node *);
-
 struct clk_onecell_data {
         struct clk **clks;
         unsigned int clk_num;
@@ -893,13 +892,10 @@ struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
                                      void *data);
-unsigned int of_clk_get_parent_count(struct device_node *np);
 int of_clk_parent_fill(struct device_node *np, const char **parents,
                        unsigned int size);
-const char *of_clk_get_parent_name(struct device_node *np, int index);
 int of_clk_detect_critical(struct device_node *np, int index,
                             unsigned long *flags);
-void of_clk_init(const struct of_device_id *matches);
 
 #else /* !CONFIG_OF */
 
@@ -946,26 +942,16 @@ of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
 {
         return ERR_PTR(-ENOENT);
 }
-static inline unsigned int of_clk_get_parent_count(struct device_node *np)
-{
-        return 0;
-}
 static inline int of_clk_parent_fill(struct device_node *np,
                                      const char **parents, unsigned int size)
 {
         return 0;
 }
-static inline const char *of_clk_get_parent_name(struct device_node *np,
-                                                 int index)
-{
-        return NULL;
-}
 static inline int of_clk_detect_critical(struct device_node *np, int index,
                                           unsigned long *flags)
 {
         return 0;
 }
-static inline void of_clk_init(const struct of_device_id *matches) {}
 #endif /* CONFIG_OF */
 
 /*
@@ -999,10 +985,5 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
 
 #endif  /* platform dependent I/O accessors */
 
-#ifdef CONFIG_DEBUG_FS
-struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
-                                void *data, const struct file_operations *fops);
-#endif
-
 #endif /* CONFIG_COMMON_CLK */
 #endif /* CLK_PROVIDER_H */
diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h
new file mode 100644
index 000000000000..8a7b5cd7eac0
--- /dev/null
+++ b/include/linux/clk/davinci.h
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Clock drivers for TI DaVinci PLL and PSC controllers
+ *
+ * Copyright (C) 2018 David Lechner <david@lechnology.com>
+ */
+
+#ifndef __LINUX_CLK_DAVINCI_PLL_H___
+#define __LINUX_CLK_DAVINCI_PLL_H___
+
+#include <linux/device.h>
+#include <linux/regmap.h>
+
+/* function for registering clocks in early boot */
+
+#ifdef CONFIG_ARCH_DAVINCI_DA830
+int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DA850
+int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM355
+int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
+int dm355_psc_init(struct device *dev, void __iomem *base);
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM365
+int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
+int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
+int dm365_psc_init(struct device *dev, void __iomem *base);
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM644x
+int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
+int dm644x_psc_init(struct device *dev, void __iomem *base);
+#endif
+#ifdef CONFIG_ARCH_DAVINCI_DM646x
+int dm646x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
+int dm646x_psc_init(struct device *dev, void __iomem *base);
+#endif
+
+#endif /* __LINUX_CLK_DAVINCI_PLL_H___ */
diff --git a/include/linux/of_clk.h b/include/linux/of_clk.h
new file mode 100644
index 000000000000..b27da9f164cb
--- /dev/null
+++ b/include/linux/of_clk.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * OF clock helpers
+ */
+
+#ifndef __LINUX_OF_CLK_H
+#define __LINUX_OF_CLK_H
+
+#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_OF)
+
+unsigned int of_clk_get_parent_count(struct device_node *np);
+const char *of_clk_get_parent_name(struct device_node *np, int index);
+void of_clk_init(const struct of_device_id *matches);
+
+#else /* !CONFIG_COMMON_CLK || !CONFIG_OF */
+
+static inline unsigned int of_clk_get_parent_count(struct device_node *np)
+{
+        return 0;
+}
+static inline const char *of_clk_get_parent_name(struct device_node *np,
+                                                 int index)
+{
+        return NULL;
+}
+static inline void of_clk_init(const struct of_device_id *matches) {}
+
+#endif /* !CONFIG_COMMON_CLK || !CONFIG_OF */
+
+#endif /* __LINUX_OF_CLK_H */