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authorLinus Torvalds <torvalds@linux-foundation.org>2014-06-07 22:44:40 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-06-07 22:44:40 -0400
commit639b4ac691c6f6e48921dc576379c176f82f3250 (patch)
tree6cf521ae7d46ca8dfa139ca67dd32545de8d2a75
parent9d2cd01b15d0782adb81e40094b67904d77b03df (diff)
parent5208ed2ca16526cdbec25abe594a3cc3aea210f4 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6 into next
Pull crypto updates from Herbert Xu: "Here is the crypto update for 3.16: - Added test vectors for SHA/AES-CCM/DES-CBC/3DES-CBC. - Fixed a number of error-path memory leaks in tcrypt. - Fixed error-path memory leak in caam. - Removed unnecessary global mutex from mxs-dcp. - Added ahash walk interface that can actually be asynchronous. - Cleaned up caam error reporting. - Allow crypto_user get operation to be used by non-root users. - Add support for SSS module on Exynos. - Misc fixes" * git://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6: (60 commits) crypto: testmgr - add aead cbc des, des3_ede tests crypto: testmgr - Fix DMA-API warning crypto: cesa - tfm->__crt_alg->cra_type directly crypto: sahara - tfm->__crt_alg->cra_name directly crypto: padlock - tfm->__crt_alg->cra_name directly crypto: n2 - tfm->__crt_alg->cra_name directly crypto: dcp - tfm->__crt_alg->cra_name directly crypto: cesa - tfm->__crt_alg->cra_name directly crypto: ccp - tfm->__crt_alg->cra_name directly crypto: geode - Don't use tfm->__crt_alg->cra_name directly crypto: geode - Weed out printk() from probe() crypto: geode - Consistently use AES_KEYSIZE_128 crypto: geode - Kill AES_IV_LENGTH crypto: geode - Kill AES_MIN_BLOCK_SIZE crypto: mxs-dcp - Remove global mutex crypto: hash - Add real ahash walk interface hwrng: n2-drv - Introduce the use of the managed version of kzalloc crypto: caam - reinitialize keys_fit_inline for decrypt and givencrypt crypto: s5p-sss - fix multiplatform build hwrng: timeriomem - remove unnecessary OOM messages ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/crypto/samsung-sss.txt34
-rw-r--r--arch/x86/crypto/ghash-clmulni-intel_asm.S4
-rw-r--r--arch/x86/crypto/ghash-clmulni-intel_glue.c12
-rw-r--r--crypto/ahash.c41
-rw-r--r--crypto/crypto_user.c12
-rw-r--r--crypto/tcrypt.c52
-rw-r--r--crypto/testmgr.c181
-rw-r--r--crypto/testmgr.h1441
-rw-r--r--drivers/char/hw_random/Kconfig101
-rw-r--r--drivers/char/hw_random/Makefile1
-rw-r--r--drivers/char/hw_random/n2-drv.c24
-rw-r--r--drivers/char/hw_random/omap-rng.c4
-rw-r--r--drivers/char/hw_random/picoxcell-rng.c181
-rw-r--r--drivers/char/hw_random/timeriomem-rng.c4
-rw-r--r--drivers/crypto/Kconfig6
-rw-r--r--drivers/crypto/atmel-aes.c8
-rw-r--r--drivers/crypto/bfin_crc.c103
-rw-r--r--drivers/crypto/bfin_crc.h125
-rw-r--r--drivers/crypto/caam/caamalg.c31
-rw-r--r--drivers/crypto/caam/caamhash.c32
-rw-r--r--drivers/crypto/caam/caamrng.c7
-rw-r--r--drivers/crypto/caam/error.c393
-rw-r--r--drivers/crypto/caam/error.h2
-rw-r--r--drivers/crypto/caam/key_gen.c7
-rw-r--r--drivers/crypto/ccp/ccp-crypto-aes-xts.c4
-rw-r--r--drivers/crypto/ccp/ccp-pci.c7
-rw-r--r--drivers/crypto/geode-aes.c28
-rw-r--r--drivers/crypto/geode-aes.h6
-rw-r--r--drivers/crypto/mv_cesa.c6
-rw-r--r--drivers/crypto/mxs-dcp.c52
-rw-r--r--drivers/crypto/n2_core.c4
-rw-r--r--drivers/crypto/nx/nx-842.c4
-rw-r--r--drivers/crypto/omap-des.c33
-rw-r--r--drivers/crypto/padlock-sha.c2
-rw-r--r--drivers/crypto/s5p-sss.c148
-rw-r--r--drivers/crypto/sahara.c2
-rw-r--r--include/crypto/internal/hash.h13
37 files changed, 2369 insertions, 746 deletions
diff --git a/Documentation/devicetree/bindings/crypto/samsung-sss.txt b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
new file mode 100644
index 000000000000..a6dafa83c6df
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/samsung-sss.txt
@@ -0,0 +1,34 @@
1Samsung SoC SSS (Security SubSystem) module
2
3The SSS module in S5PV210 SoC supports the following:
4-- Feeder (FeedCtrl)
5-- Advanced Encryption Standard (AES)
6-- Data Encryption Standard (DES)/3DES
7-- Public Key Accelerator (PKA)
8-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
9-- PRNG: Pseudo Random Number Generator
10
11The SSS module in Exynos4 (Exynos4210) and
12Exynos5 (Exynos5420 and Exynos5250) SoCs
13supports the following also:
14-- ARCFOUR (ARC4)
15-- True Random Number Generator (TRNG)
16-- Secure Key Manager
17
18Required properties:
19
20- compatible : Should contain entries for this and backward compatible
21 SSS versions:
22 - "samsung,s5pv210-secss" for S5PV210 SoC.
23 - "samsung,exynos4210-secss" for Exynos4210, Exynos4212, Exynos4412, Exynos5250,
24 Exynos5260 and Exynos5420 SoCs.
25- reg : Offset and length of the register set for the module
26- interrupts : interrupt specifiers of SSS module interrupts, should contain
27 following entries:
28 - first : feed control interrupt (required for all variants),
29 - second : hash interrupt (required only for samsung,s5pv210-secss).
30
31- clocks : list of clock phandle and specifier pairs for all clocks listed in
32 clock-names property.
33- clock-names : list of device clock input names; should contain one entry
34 "secss".
diff --git a/arch/x86/crypto/ghash-clmulni-intel_asm.S b/arch/x86/crypto/ghash-clmulni-intel_asm.S
index 185fad49d86f..5d1e0075ac24 100644
--- a/arch/x86/crypto/ghash-clmulni-intel_asm.S
+++ b/arch/x86/crypto/ghash-clmulni-intel_asm.S
@@ -92,7 +92,7 @@ __clmul_gf128mul_ble:
92 ret 92 ret
93ENDPROC(__clmul_gf128mul_ble) 93ENDPROC(__clmul_gf128mul_ble)
94 94
95/* void clmul_ghash_mul(char *dst, const be128 *shash) */ 95/* void clmul_ghash_mul(char *dst, const u128 *shash) */
96ENTRY(clmul_ghash_mul) 96ENTRY(clmul_ghash_mul)
97 movups (%rdi), DATA 97 movups (%rdi), DATA
98 movups (%rsi), SHASH 98 movups (%rsi), SHASH
@@ -106,7 +106,7 @@ ENDPROC(clmul_ghash_mul)
106 106
107/* 107/*
108 * void clmul_ghash_update(char *dst, const char *src, unsigned int srclen, 108 * void clmul_ghash_update(char *dst, const char *src, unsigned int srclen,
109 * const be128 *shash); 109 * const u128 *shash);
110 */ 110 */
111ENTRY(clmul_ghash_update) 111ENTRY(clmul_ghash_update)
112 cmp $16, %rdx 112 cmp $16, %rdx
diff --git a/arch/x86/crypto/ghash-clmulni-intel_glue.c b/arch/x86/crypto/ghash-clmulni-intel_glue.c
index d785cf2c529c..88bb7ba8b175 100644
--- a/arch/x86/crypto/ghash-clmulni-intel_glue.c
+++ b/arch/x86/crypto/ghash-clmulni-intel_glue.c
@@ -25,17 +25,17 @@
25#define GHASH_BLOCK_SIZE 16 25#define GHASH_BLOCK_SIZE 16
26#define GHASH_DIGEST_SIZE 16 26#define GHASH_DIGEST_SIZE 16
27 27
28void clmul_ghash_mul(char *dst, const be128 *shash); 28void clmul_ghash_mul(char *dst, const u128 *shash);
29 29
30void clmul_ghash_update(char *dst, const char *src, unsigned int srclen, 30void clmul_ghash_update(char *dst, const char *src, unsigned int srclen,
31 const be128 *shash); 31 const u128 *shash);
32 32
33struct ghash_async_ctx { 33struct ghash_async_ctx {
34 struct cryptd_ahash *cryptd_tfm; 34 struct cryptd_ahash *cryptd_tfm;
35}; 35};
36 36
37struct ghash_ctx { 37struct ghash_ctx {
38 be128 shash; 38 u128 shash;
39}; 39};
40 40
41struct ghash_desc_ctx { 41struct ghash_desc_ctx {
@@ -68,11 +68,11 @@ static int ghash_setkey(struct crypto_shash *tfm,
68 a = be64_to_cpu(x->a); 68 a = be64_to_cpu(x->a);
69 b = be64_to_cpu(x->b); 69 b = be64_to_cpu(x->b);
70 70
71 ctx->shash.a = (__be64)((b << 1) | (a >> 63)); 71 ctx->shash.a = (b << 1) | (a >> 63);
72 ctx->shash.b = (__be64)((a << 1) | (b >> 63)); 72 ctx->shash.b = (a << 1) | (b >> 63);
73 73
74 if (a >> 63) 74 if (a >> 63)
75 ctx->shash.b ^= cpu_to_be64(0xc2); 75 ctx->shash.b ^= ((u64)0xc2) << 56;
76 76
77 return 0; 77 return 0;
78} 78}
diff --git a/crypto/ahash.c b/crypto/ahash.c
index 6e7223392e80..f2a5d8f656ff 100644
--- a/crypto/ahash.c
+++ b/crypto/ahash.c
@@ -15,6 +15,7 @@
15 15
16#include <crypto/internal/hash.h> 16#include <crypto/internal/hash.h>
17#include <crypto/scatterwalk.h> 17#include <crypto/scatterwalk.h>
18#include <linux/bug.h>
18#include <linux/err.h> 19#include <linux/err.h>
19#include <linux/kernel.h> 20#include <linux/kernel.h>
20#include <linux/module.h> 21#include <linux/module.h>
@@ -46,7 +47,10 @@ static int hash_walk_next(struct crypto_hash_walk *walk)
46 unsigned int nbytes = min(walk->entrylen, 47 unsigned int nbytes = min(walk->entrylen,
47 ((unsigned int)(PAGE_SIZE)) - offset); 48 ((unsigned int)(PAGE_SIZE)) - offset);
48 49
49 walk->data = kmap_atomic(walk->pg); 50 if (walk->flags & CRYPTO_ALG_ASYNC)
51 walk->data = kmap(walk->pg);
52 else
53 walk->data = kmap_atomic(walk->pg);
50 walk->data += offset; 54 walk->data += offset;
51 55
52 if (offset & alignmask) { 56 if (offset & alignmask) {
@@ -93,8 +97,16 @@ int crypto_hash_walk_done(struct crypto_hash_walk *walk, int err)
93 return nbytes; 97 return nbytes;
94 } 98 }
95 99
96 kunmap_atomic(walk->data); 100 if (walk->flags & CRYPTO_ALG_ASYNC)
97 crypto_yield(walk->flags); 101 kunmap(walk->pg);
102 else {
103 kunmap_atomic(walk->data);
104 /*
105 * The may sleep test only makes sense for sync users.
106 * Async users don't need to sleep here anyway.
107 */
108 crypto_yield(walk->flags);
109 }
98 110
99 if (err) 111 if (err)
100 return err; 112 return err;
@@ -124,12 +136,31 @@ int crypto_hash_walk_first(struct ahash_request *req,
124 136
125 walk->alignmask = crypto_ahash_alignmask(crypto_ahash_reqtfm(req)); 137 walk->alignmask = crypto_ahash_alignmask(crypto_ahash_reqtfm(req));
126 walk->sg = req->src; 138 walk->sg = req->src;
127 walk->flags = req->base.flags; 139 walk->flags = req->base.flags & CRYPTO_TFM_REQ_MASK;
128 140
129 return hash_walk_new_entry(walk); 141 return hash_walk_new_entry(walk);
130} 142}
131EXPORT_SYMBOL_GPL(crypto_hash_walk_first); 143EXPORT_SYMBOL_GPL(crypto_hash_walk_first);
132 144
145int crypto_ahash_walk_first(struct ahash_request *req,
146 struct crypto_hash_walk *walk)
147{
148 walk->total = req->nbytes;
149
150 if (!walk->total)
151 return 0;
152
153 walk->alignmask = crypto_ahash_alignmask(crypto_ahash_reqtfm(req));
154 walk->sg = req->src;
155 walk->flags = req->base.flags & CRYPTO_TFM_REQ_MASK;
156 walk->flags |= CRYPTO_ALG_ASYNC;
157
158 BUILD_BUG_ON(CRYPTO_TFM_REQ_MASK & CRYPTO_ALG_ASYNC);
159
160 return hash_walk_new_entry(walk);
161}
162EXPORT_SYMBOL_GPL(crypto_ahash_walk_first);
163
133int crypto_hash_walk_first_compat(struct hash_desc *hdesc, 164int crypto_hash_walk_first_compat(struct hash_desc *hdesc,
134 struct crypto_hash_walk *walk, 165 struct crypto_hash_walk *walk,
135 struct scatterlist *sg, unsigned int len) 166 struct scatterlist *sg, unsigned int len)
@@ -141,7 +172,7 @@ int crypto_hash_walk_first_compat(struct hash_desc *hdesc,
141 172
142 walk->alignmask = crypto_hash_alignmask(hdesc->tfm); 173 walk->alignmask = crypto_hash_alignmask(hdesc->tfm);
143 walk->sg = sg; 174 walk->sg = sg;
144 walk->flags = hdesc->flags; 175 walk->flags = hdesc->flags & CRYPTO_TFM_REQ_MASK;
145 176
146 return hash_walk_new_entry(walk); 177 return hash_walk_new_entry(walk);
147} 178}
diff --git a/crypto/crypto_user.c b/crypto/crypto_user.c
index 43665d0d0905..e2a34feec7a4 100644
--- a/crypto/crypto_user.c
+++ b/crypto/crypto_user.c
@@ -265,6 +265,9 @@ static int crypto_update_alg(struct sk_buff *skb, struct nlmsghdr *nlh,
265 struct nlattr *priority = attrs[CRYPTOCFGA_PRIORITY_VAL]; 265 struct nlattr *priority = attrs[CRYPTOCFGA_PRIORITY_VAL];
266 LIST_HEAD(list); 266 LIST_HEAD(list);
267 267
268 if (!netlink_capable(skb, CAP_NET_ADMIN))
269 return -EPERM;
270
268 if (!null_terminated(p->cru_name) || !null_terminated(p->cru_driver_name)) 271 if (!null_terminated(p->cru_name) || !null_terminated(p->cru_driver_name))
269 return -EINVAL; 272 return -EINVAL;
270 273
@@ -295,6 +298,9 @@ static int crypto_del_alg(struct sk_buff *skb, struct nlmsghdr *nlh,
295 struct crypto_alg *alg; 298 struct crypto_alg *alg;
296 struct crypto_user_alg *p = nlmsg_data(nlh); 299 struct crypto_user_alg *p = nlmsg_data(nlh);
297 300
301 if (!netlink_capable(skb, CAP_NET_ADMIN))
302 return -EPERM;
303
298 if (!null_terminated(p->cru_name) || !null_terminated(p->cru_driver_name)) 304 if (!null_terminated(p->cru_name) || !null_terminated(p->cru_driver_name))
299 return -EINVAL; 305 return -EINVAL;
300 306
@@ -379,6 +385,9 @@ static int crypto_add_alg(struct sk_buff *skb, struct nlmsghdr *nlh,
379 struct crypto_user_alg *p = nlmsg_data(nlh); 385 struct crypto_user_alg *p = nlmsg_data(nlh);
380 struct nlattr *priority = attrs[CRYPTOCFGA_PRIORITY_VAL]; 386 struct nlattr *priority = attrs[CRYPTOCFGA_PRIORITY_VAL];
381 387
388 if (!netlink_capable(skb, CAP_NET_ADMIN))
389 return -EPERM;
390
382 if (!null_terminated(p->cru_name) || !null_terminated(p->cru_driver_name)) 391 if (!null_terminated(p->cru_name) || !null_terminated(p->cru_driver_name))
383 return -EINVAL; 392 return -EINVAL;
384 393
@@ -466,9 +475,6 @@ static int crypto_user_rcv_msg(struct sk_buff *skb, struct nlmsghdr *nlh)
466 type -= CRYPTO_MSG_BASE; 475 type -= CRYPTO_MSG_BASE;
467 link = &crypto_dispatch[type]; 476 link = &crypto_dispatch[type];
468 477
469 if (!netlink_capable(skb, CAP_NET_ADMIN))
470 return -EPERM;
471
472 if ((type == (CRYPTO_MSG_GETALG - CRYPTO_MSG_BASE) && 478 if ((type == (CRYPTO_MSG_GETALG - CRYPTO_MSG_BASE) &&
473 (nlh->nlmsg_flags & NLM_F_DUMP))) { 479 (nlh->nlmsg_flags & NLM_F_DUMP))) {
474 struct crypto_alg *alg; 480 struct crypto_alg *alg;
diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c
index 870be7b4dc05..ba247cf30858 100644
--- a/crypto/tcrypt.c
+++ b/crypto/tcrypt.c
@@ -282,6 +282,11 @@ static void test_aead_speed(const char *algo, int enc, unsigned int sec,
282 unsigned int *b_size; 282 unsigned int *b_size;
283 unsigned int iv_len; 283 unsigned int iv_len;
284 284
285 if (aad_size >= PAGE_SIZE) {
286 pr_err("associate data length (%u) too big\n", aad_size);
287 return;
288 }
289
285 if (enc == ENCRYPT) 290 if (enc == ENCRYPT)
286 e = "encryption"; 291 e = "encryption";
287 else 292 else
@@ -308,14 +313,14 @@ static void test_aead_speed(const char *algo, int enc, unsigned int sec,
308 if (IS_ERR(tfm)) { 313 if (IS_ERR(tfm)) {
309 pr_err("alg: aead: Failed to load transform for %s: %ld\n", algo, 314 pr_err("alg: aead: Failed to load transform for %s: %ld\n", algo,
310 PTR_ERR(tfm)); 315 PTR_ERR(tfm));
311 return; 316 goto out_notfm;
312 } 317 }
313 318
314 req = aead_request_alloc(tfm, GFP_KERNEL); 319 req = aead_request_alloc(tfm, GFP_KERNEL);
315 if (!req) { 320 if (!req) {
316 pr_err("alg: aead: Failed to allocate request for %s\n", 321 pr_err("alg: aead: Failed to allocate request for %s\n",
317 algo); 322 algo);
318 goto out; 323 goto out_noreq;
319 } 324 }
320 325
321 i = 0; 326 i = 0;
@@ -323,14 +328,7 @@ static void test_aead_speed(const char *algo, int enc, unsigned int sec,
323 b_size = aead_sizes; 328 b_size = aead_sizes;
324 do { 329 do {
325 assoc = axbuf[0]; 330 assoc = axbuf[0];
326 331 memset(assoc, 0xff, aad_size);
327 if (aad_size < PAGE_SIZE)
328 memset(assoc, 0xff, aad_size);
329 else {
330 pr_err("associate data length (%u) too big\n",
331 aad_size);
332 goto out_nosg;
333 }
334 sg_init_one(&asg[0], assoc, aad_size); 332 sg_init_one(&asg[0], assoc, aad_size);
335 333
336 if ((*keysize + *b_size) > TVMEMSIZE * PAGE_SIZE) { 334 if ((*keysize + *b_size) > TVMEMSIZE * PAGE_SIZE) {
@@ -392,7 +390,10 @@ static void test_aead_speed(const char *algo, int enc, unsigned int sec,
392 } while (*keysize); 390 } while (*keysize);
393 391
394out: 392out:
393 aead_request_free(req);
394out_noreq:
395 crypto_free_aead(tfm); 395 crypto_free_aead(tfm);
396out_notfm:
396 kfree(sg); 397 kfree(sg);
397out_nosg: 398out_nosg:
398 testmgr_free_buf(xoutbuf); 399 testmgr_free_buf(xoutbuf);
@@ -1518,7 +1519,36 @@ static int do_test(int m)
1518 case 157: 1519 case 157:
1519 ret += tcrypt_test("authenc(hmac(sha1),ecb(cipher_null))"); 1520 ret += tcrypt_test("authenc(hmac(sha1),ecb(cipher_null))");
1520 break; 1521 break;
1521 1522 case 181:
1523 ret += tcrypt_test("authenc(hmac(sha1),cbc(des))");
1524 break;
1525 case 182:
1526 ret += tcrypt_test("authenc(hmac(sha1),cbc(des3_ede))");
1527 break;
1528 case 183:
1529 ret += tcrypt_test("authenc(hmac(sha224),cbc(des))");
1530 break;
1531 case 184:
1532 ret += tcrypt_test("authenc(hmac(sha224),cbc(des3_ede))");
1533 break;
1534 case 185:
1535 ret += tcrypt_test("authenc(hmac(sha256),cbc(des))");
1536 break;
1537 case 186:
1538 ret += tcrypt_test("authenc(hmac(sha256),cbc(des3_ede))");
1539 break;
1540 case 187:
1541 ret += tcrypt_test("authenc(hmac(sha384),cbc(des))");
1542 break;
1543 case 188:
1544 ret += tcrypt_test("authenc(hmac(sha384),cbc(des3_ede))");
1545 break;
1546 case 189:
1547 ret += tcrypt_test("authenc(hmac(sha512),cbc(des))");
1548 break;
1549 case 190:
1550 ret += tcrypt_test("authenc(hmac(sha512),cbc(des3_ede))");
1551 break;
1522 case 200: 1552 case 200:
1523 test_cipher_speed("ecb(aes)", ENCRYPT, sec, NULL, 0, 1553 test_cipher_speed("ecb(aes)", ENCRYPT, sec, NULL, 0,
1524 speed_template_16_24_32); 1554 speed_template_16_24_32);
diff --git a/crypto/testmgr.c b/crypto/testmgr.c
index dc3cf3535ef0..498649ac1953 100644
--- a/crypto/testmgr.c
+++ b/crypto/testmgr.c
@@ -414,16 +414,18 @@ static int __test_aead(struct crypto_aead *tfm, int enc,
414 void *input; 414 void *input;
415 void *output; 415 void *output;
416 void *assoc; 416 void *assoc;
417 char iv[MAX_IVLEN]; 417 char *iv;
418 char *xbuf[XBUFSIZE]; 418 char *xbuf[XBUFSIZE];
419 char *xoutbuf[XBUFSIZE]; 419 char *xoutbuf[XBUFSIZE];
420 char *axbuf[XBUFSIZE]; 420 char *axbuf[XBUFSIZE];
421 421
422 iv = kzalloc(MAX_IVLEN, GFP_KERNEL);
423 if (!iv)
424 return ret;
422 if (testmgr_alloc_buf(xbuf)) 425 if (testmgr_alloc_buf(xbuf))
423 goto out_noxbuf; 426 goto out_noxbuf;
424 if (testmgr_alloc_buf(axbuf)) 427 if (testmgr_alloc_buf(axbuf))
425 goto out_noaxbuf; 428 goto out_noaxbuf;
426
427 if (diff_dst && testmgr_alloc_buf(xoutbuf)) 429 if (diff_dst && testmgr_alloc_buf(xoutbuf))
428 goto out_nooutbuf; 430 goto out_nooutbuf;
429 431
@@ -767,6 +769,7 @@ out_nooutbuf:
767out_noaxbuf: 769out_noaxbuf:
768 testmgr_free_buf(xbuf); 770 testmgr_free_buf(xbuf);
769out_noxbuf: 771out_noxbuf:
772 kfree(iv);
770 return ret; 773 return ret;
771} 774}
772 775
@@ -1831,8 +1834,38 @@ static const struct alg_test_desc alg_test_descs[] = {
1831 .suite = { 1834 .suite = {
1832 .aead = { 1835 .aead = {
1833 .enc = { 1836 .enc = {
1834 .vecs = hmac_sha1_aes_cbc_enc_tv_template, 1837 .vecs =
1835 .count = HMAC_SHA1_AES_CBC_ENC_TEST_VECTORS 1838 hmac_sha1_aes_cbc_enc_tv_temp,
1839 .count =
1840 HMAC_SHA1_AES_CBC_ENC_TEST_VEC
1841 }
1842 }
1843 }
1844 }, {
1845 .alg = "authenc(hmac(sha1),cbc(des))",
1846 .test = alg_test_aead,
1847 .fips_allowed = 1,
1848 .suite = {
1849 .aead = {
1850 .enc = {
1851 .vecs =
1852 hmac_sha1_des_cbc_enc_tv_temp,
1853 .count =
1854 HMAC_SHA1_DES_CBC_ENC_TEST_VEC
1855 }
1856 }
1857 }
1858 }, {
1859 .alg = "authenc(hmac(sha1),cbc(des3_ede))",
1860 .test = alg_test_aead,
1861 .fips_allowed = 1,
1862 .suite = {
1863 .aead = {
1864 .enc = {
1865 .vecs =
1866 hmac_sha1_des3_ede_cbc_enc_tv_temp,
1867 .count =
1868 HMAC_SHA1_DES3_EDE_CBC_ENC_TEST_VEC
1836 } 1869 }
1837 } 1870 }
1838 } 1871 }
@@ -1843,12 +1876,44 @@ static const struct alg_test_desc alg_test_descs[] = {
1843 .suite = { 1876 .suite = {
1844 .aead = { 1877 .aead = {
1845 .enc = { 1878 .enc = {
1846 .vecs = hmac_sha1_ecb_cipher_null_enc_tv_template, 1879 .vecs =
1847 .count = HMAC_SHA1_ECB_CIPHER_NULL_ENC_TEST_VECTORS 1880 hmac_sha1_ecb_cipher_null_enc_tv_temp,
1881 .count =
1882 HMAC_SHA1_ECB_CIPHER_NULL_ENC_TEST_VEC
1848 }, 1883 },
1849 .dec = { 1884 .dec = {
1850 .vecs = hmac_sha1_ecb_cipher_null_dec_tv_template, 1885 .vecs =
1851 .count = HMAC_SHA1_ECB_CIPHER_NULL_DEC_TEST_VECTORS 1886 hmac_sha1_ecb_cipher_null_dec_tv_temp,
1887 .count =
1888 HMAC_SHA1_ECB_CIPHER_NULL_DEC_TEST_VEC
1889 }
1890 }
1891 }
1892 }, {
1893 .alg = "authenc(hmac(sha224),cbc(des))",
1894 .test = alg_test_aead,
1895 .fips_allowed = 1,
1896 .suite = {
1897 .aead = {
1898 .enc = {
1899 .vecs =
1900 hmac_sha224_des_cbc_enc_tv_temp,
1901 .count =
1902 HMAC_SHA224_DES_CBC_ENC_TEST_VEC
1903 }
1904 }
1905 }
1906 }, {
1907 .alg = "authenc(hmac(sha224),cbc(des3_ede))",
1908 .test = alg_test_aead,
1909 .fips_allowed = 1,
1910 .suite = {
1911 .aead = {
1912 .enc = {
1913 .vecs =
1914 hmac_sha224_des3_ede_cbc_enc_tv_temp,
1915 .count =
1916 HMAC_SHA224_DES3_EDE_CBC_ENC_TEST_VEC
1852 } 1917 }
1853 } 1918 }
1854 } 1919 }
@@ -1859,8 +1924,66 @@ static const struct alg_test_desc alg_test_descs[] = {
1859 .suite = { 1924 .suite = {
1860 .aead = { 1925 .aead = {
1861 .enc = { 1926 .enc = {
1862 .vecs = hmac_sha256_aes_cbc_enc_tv_template, 1927 .vecs =
1863 .count = HMAC_SHA256_AES_CBC_ENC_TEST_VECTORS 1928 hmac_sha256_aes_cbc_enc_tv_temp,
1929 .count =
1930 HMAC_SHA256_AES_CBC_ENC_TEST_VEC
1931 }
1932 }
1933 }
1934 }, {
1935 .alg = "authenc(hmac(sha256),cbc(des))",
1936 .test = alg_test_aead,
1937 .fips_allowed = 1,
1938 .suite = {
1939 .aead = {
1940 .enc = {
1941 .vecs =
1942 hmac_sha256_des_cbc_enc_tv_temp,
1943 .count =
1944 HMAC_SHA256_DES_CBC_ENC_TEST_VEC
1945 }
1946 }
1947 }
1948 }, {
1949 .alg = "authenc(hmac(sha256),cbc(des3_ede))",
1950 .test = alg_test_aead,
1951 .fips_allowed = 1,
1952 .suite = {
1953 .aead = {
1954 .enc = {
1955 .vecs =
1956 hmac_sha256_des3_ede_cbc_enc_tv_temp,
1957 .count =
1958 HMAC_SHA256_DES3_EDE_CBC_ENC_TEST_VEC
1959 }
1960 }
1961 }
1962 }, {
1963 .alg = "authenc(hmac(sha384),cbc(des))",
1964 .test = alg_test_aead,
1965 .fips_allowed = 1,
1966 .suite = {
1967 .aead = {
1968 .enc = {
1969 .vecs =
1970 hmac_sha384_des_cbc_enc_tv_temp,
1971 .count =
1972 HMAC_SHA384_DES_CBC_ENC_TEST_VEC
1973 }
1974 }
1975 }
1976 }, {
1977 .alg = "authenc(hmac(sha384),cbc(des3_ede))",
1978 .test = alg_test_aead,
1979 .fips_allowed = 1,
1980 .suite = {
1981 .aead = {
1982 .enc = {
1983 .vecs =
1984 hmac_sha384_des3_ede_cbc_enc_tv_temp,
1985 .count =
1986 HMAC_SHA384_DES3_EDE_CBC_ENC_TEST_VEC
1864 } 1987 }
1865 } 1988 }
1866 } 1989 }
@@ -1871,8 +1994,38 @@ static const struct alg_test_desc alg_test_descs[] = {
1871 .suite = { 1994 .suite = {
1872 .aead = { 1995 .aead = {
1873 .enc = { 1996 .enc = {
1874 .vecs = hmac_sha512_aes_cbc_enc_tv_template, 1997 .vecs =
1875 .count = HMAC_SHA512_AES_CBC_ENC_TEST_VECTORS 1998 hmac_sha512_aes_cbc_enc_tv_temp,
1999 .count =
2000 HMAC_SHA512_AES_CBC_ENC_TEST_VEC
2001 }
2002 }
2003 }
2004 }, {
2005 .alg = "authenc(hmac(sha512),cbc(des))",
2006 .test = alg_test_aead,
2007 .fips_allowed = 1,
2008 .suite = {
2009 .aead = {
2010 .enc = {
2011 .vecs =
2012 hmac_sha512_des_cbc_enc_tv_temp,
2013 .count =
2014 HMAC_SHA512_DES_CBC_ENC_TEST_VEC
2015 }
2016 }
2017 }
2018 }, {
2019 .alg = "authenc(hmac(sha512),cbc(des3_ede))",
2020 .test = alg_test_aead,
2021 .fips_allowed = 1,
2022 .suite = {
2023 .aead = {
2024 .enc = {
2025 .vecs =
2026 hmac_sha512_des3_ede_cbc_enc_tv_temp,
2027 .count =
2028 HMAC_SHA512_DES3_EDE_CBC_ENC_TEST_VEC
1876 } 2029 }
1877 } 2030 }
1878 } 2031 }
@@ -3273,8 +3426,8 @@ test_done:
3273 panic("%s: %s alg self test failed in fips mode!\n", driver, alg); 3426 panic("%s: %s alg self test failed in fips mode!\n", driver, alg);
3274 3427
3275 if (fips_enabled && !rc) 3428 if (fips_enabled && !rc)
3276 printk(KERN_INFO "alg: self-tests for %s (%s) passed\n", 3429 pr_info(KERN_INFO "alg: self-tests for %s (%s) passed\n",
3277 driver, alg); 3430 driver, alg);
3278 3431
3279 return rc; 3432 return rc;
3280 3433
diff --git a/crypto/testmgr.h b/crypto/testmgr.h
index 3db83dbba1d9..69d0dd8ef27e 100644
--- a/crypto/testmgr.h
+++ b/crypto/testmgr.h
@@ -487,10 +487,15 @@ static struct hash_testvec crct10dif_tv_template[] = {
487 * SHA1 test vectors from from FIPS PUB 180-1 487 * SHA1 test vectors from from FIPS PUB 180-1
488 * Long vector from CAVS 5.0 488 * Long vector from CAVS 5.0
489 */ 489 */
490#define SHA1_TEST_VECTORS 3 490#define SHA1_TEST_VECTORS 6
491 491
492static struct hash_testvec sha1_tv_template[] = { 492static struct hash_testvec sha1_tv_template[] = {
493 { 493 {
494 .plaintext = "",
495 .psize = 0,
496 .digest = "\xda\x39\xa3\xee\x5e\x6b\x4b\x0d\x32\x55"
497 "\xbf\xef\x95\x60\x18\x90\xaf\xd8\x07\x09",
498 }, {
494 .plaintext = "abc", 499 .plaintext = "abc",
495 .psize = 3, 500 .psize = 3,
496 .digest = "\xa9\x99\x3e\x36\x47\x06\x81\x6a\xba\x3e" 501 .digest = "\xa9\x99\x3e\x36\x47\x06\x81\x6a\xba\x3e"
@@ -529,6 +534,144 @@ static struct hash_testvec sha1_tv_template[] = {
529 "\x45\x9c\x02\xb6\x9b\x4a\xa8\xf5\x82\x17", 534 "\x45\x9c\x02\xb6\x9b\x4a\xa8\xf5\x82\x17",
530 .np = 4, 535 .np = 4,
531 .tap = { 63, 64, 31, 5 } 536 .tap = { 63, 64, 31, 5 }
537 }, {
538 .plaintext = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+-",
539 .psize = 64,
540 .digest = "\xc8\x71\xf6\x9a\x63\xcc\xa9\x84\x84\x82"
541 "\x64\xe7\x79\x95\x5d\xd7\x19\x41\x7c\x91",
542 }, {
543 .plaintext = "\x08\x9f\x13\xaa\x41\xd8\x4c\xe3"
544 "\x7a\x11\x85\x1c\xb3\x27\xbe\x55"
545 "\xec\x60\xf7\x8e\x02\x99\x30\xc7"
546 "\x3b\xd2\x69\x00\x74\x0b\xa2\x16"
547 "\xad\x44\xdb\x4f\xe6\x7d\x14\x88"
548 "\x1f\xb6\x2a\xc1\x58\xef\x63\xfa"
549 "\x91\x05\x9c\x33\xca\x3e\xd5\x6c"
550 "\x03\x77\x0e\xa5\x19\xb0\x47\xde"
551 "\x52\xe9\x80\x17\x8b\x22\xb9\x2d"
552 "\xc4\x5b\xf2\x66\xfd\x94\x08\x9f"
553 "\x36\xcd\x41\xd8\x6f\x06\x7a\x11"
554 "\xa8\x1c\xb3\x4a\xe1\x55\xec\x83"
555 "\x1a\x8e\x25\xbc\x30\xc7\x5e\xf5"
556 "\x69\x00\x97\x0b\xa2\x39\xd0\x44"
557 "\xdb\x72\x09\x7d\x14\xab\x1f\xb6"
558 "\x4d\xe4\x58\xef\x86\x1d\x91\x28"
559 "\xbf\x33\xca\x61\xf8\x6c\x03\x9a"
560 "\x0e\xa5\x3c\xd3\x47\xde\x75\x0c"
561 "\x80\x17\xae\x22\xb9\x50\xe7\x5b"
562 "\xf2\x89\x20\x94\x2b\xc2\x36\xcd"
563 "\x64\xfb\x6f\x06\x9d\x11\xa8\x3f"
564 "\xd6\x4a\xe1\x78\x0f\x83\x1a\xb1"
565 "\x25\xbc\x53\xea\x5e\xf5\x8c\x00"
566 "\x97\x2e\xc5\x39\xd0\x67\xfe\x72"
567 "\x09\xa0\x14\xab\x42\xd9\x4d\xe4"
568 "\x7b\x12\x86\x1d\xb4\x28\xbf\x56"
569 "\xed\x61\xf8\x8f\x03\x9a\x31\xc8"
570 "\x3c\xd3\x6a\x01\x75\x0c\xa3\x17"
571 "\xae\x45\xdc\x50\xe7\x7e\x15\x89"
572 "\x20\xb7\x2b\xc2\x59\xf0\x64\xfb"
573 "\x92\x06\x9d\x34\xcb\x3f\xd6\x6d"
574 "\x04\x78\x0f\xa6\x1a\xb1\x48\xdf"
575 "\x53\xea\x81\x18\x8c\x23\xba\x2e"
576 "\xc5\x5c\xf3\x67\xfe\x95\x09\xa0"
577 "\x37\xce\x42\xd9\x70\x07\x7b\x12"
578 "\xa9\x1d\xb4\x4b\xe2\x56\xed\x84"
579 "\x1b\x8f\x26\xbd\x31\xc8\x5f\xf6"
580 "\x6a\x01\x98\x0c\xa3\x3a\xd1\x45"
581 "\xdc\x73\x0a\x7e\x15\xac\x20\xb7"
582 "\x4e\xe5\x59\xf0\x87\x1e\x92\x29"
583 "\xc0\x34\xcb\x62\xf9\x6d\x04\x9b"
584 "\x0f\xa6\x3d\xd4\x48\xdf\x76\x0d"
585 "\x81\x18\xaf\x23\xba\x51\xe8\x5c"
586 "\xf3\x8a\x21\x95\x2c\xc3\x37\xce"
587 "\x65\xfc\x70\x07\x9e\x12\xa9\x40"
588 "\xd7\x4b\xe2\x79\x10\x84\x1b\xb2"
589 "\x26\xbd\x54\xeb\x5f\xf6\x8d\x01"
590 "\x98\x2f\xc6\x3a\xd1\x68\xff\x73"
591 "\x0a\xa1\x15\xac\x43\xda\x4e\xe5"
592 "\x7c\x13\x87\x1e\xb5\x29\xc0\x57"
593 "\xee\x62\xf9\x90\x04\x9b\x32\xc9"
594 "\x3d\xd4\x6b\x02\x76\x0d\xa4\x18"
595 "\xaf\x46\xdd\x51\xe8\x7f\x16\x8a"
596 "\x21\xb8\x2c\xc3\x5a\xf1\x65\xfc"
597 "\x93\x07\x9e\x35\xcc\x40\xd7\x6e"
598 "\x05\x79\x10\xa7\x1b\xb2\x49\xe0"
599 "\x54\xeb\x82\x19\x8d\x24\xbb\x2f"
600 "\xc6\x5d\xf4\x68\xff\x96\x0a\xa1"
601 "\x38\xcf\x43\xda\x71\x08\x7c\x13"
602 "\xaa\x1e\xb5\x4c\xe3\x57\xee\x85"
603 "\x1c\x90\x27\xbe\x32\xc9\x60\xf7"
604 "\x6b\x02\x99\x0d\xa4\x3b\xd2\x46"
605 "\xdd\x74\x0b\x7f\x16\xad\x21\xb8"
606 "\x4f\xe6\x5a\xf1\x88\x1f\x93\x2a"
607 "\xc1\x35\xcc\x63\xfa\x6e\x05\x9c"
608 "\x10\xa7\x3e\xd5\x49\xe0\x77\x0e"
609 "\x82\x19\xb0\x24\xbb\x52\xe9\x5d"
610 "\xf4\x8b\x22\x96\x2d\xc4\x38\xcf"
611 "\x66\xfd\x71\x08\x9f\x13\xaa\x41"
612 "\xd8\x4c\xe3\x7a\x11\x85\x1c\xb3"
613 "\x27\xbe\x55\xec\x60\xf7\x8e\x02"
614 "\x99\x30\xc7\x3b\xd2\x69\x00\x74"
615 "\x0b\xa2\x16\xad\x44\xdb\x4f\xe6"
616 "\x7d\x14\x88\x1f\xb6\x2a\xc1\x58"
617 "\xef\x63\xfa\x91\x05\x9c\x33\xca"
618 "\x3e\xd5\x6c\x03\x77\x0e\xa5\x19"
619 "\xb0\x47\xde\x52\xe9\x80\x17\x8b"
620 "\x22\xb9\x2d\xc4\x5b\xf2\x66\xfd"
621 "\x94\x08\x9f\x36\xcd\x41\xd8\x6f"
622 "\x06\x7a\x11\xa8\x1c\xb3\x4a\xe1"
623 "\x55\xec\x83\x1a\x8e\x25\xbc\x30"
624 "\xc7\x5e\xf5\x69\x00\x97\x0b\xa2"
625 "\x39\xd0\x44\xdb\x72\x09\x7d\x14"
626 "\xab\x1f\xb6\x4d\xe4\x58\xef\x86"
627 "\x1d\x91\x28\xbf\x33\xca\x61\xf8"
628 "\x6c\x03\x9a\x0e\xa5\x3c\xd3\x47"
629 "\xde\x75\x0c\x80\x17\xae\x22\xb9"
630 "\x50\xe7\x5b\xf2\x89\x20\x94\x2b"
631 "\xc2\x36\xcd\x64\xfb\x6f\x06\x9d"
632 "\x11\xa8\x3f\xd6\x4a\xe1\x78\x0f"
633 "\x83\x1a\xb1\x25\xbc\x53\xea\x5e"
634 "\xf5\x8c\x00\x97\x2e\xc5\x39\xd0"
635 "\x67\xfe\x72\x09\xa0\x14\xab\x42"
636 "\xd9\x4d\xe4\x7b\x12\x86\x1d\xb4"
637 "\x28\xbf\x56\xed\x61\xf8\x8f\x03"
638 "\x9a\x31\xc8\x3c\xd3\x6a\x01\x75"
639 "\x0c\xa3\x17\xae\x45\xdc\x50\xe7"
640 "\x7e\x15\x89\x20\xb7\x2b\xc2\x59"
641 "\xf0\x64\xfb\x92\x06\x9d\x34\xcb"
642 "\x3f\xd6\x6d\x04\x78\x0f\xa6\x1a"
643 "\xb1\x48\xdf\x53\xea\x81\x18\x8c"
644 "\x23\xba\x2e\xc5\x5c\xf3\x67\xfe"
645 "\x95\x09\xa0\x37\xce\x42\xd9\x70"
646 "\x07\x7b\x12\xa9\x1d\xb4\x4b\xe2"
647 "\x56\xed\x84\x1b\x8f\x26\xbd\x31"
648 "\xc8\x5f\xf6\x6a\x01\x98\x0c\xa3"
649 "\x3a\xd1\x45\xdc\x73\x0a\x7e\x15"
650 "\xac\x20\xb7\x4e\xe5\x59\xf0\x87"
651 "\x1e\x92\x29\xc0\x34\xcb\x62\xf9"
652 "\x6d\x04\x9b\x0f\xa6\x3d\xd4\x48"
653 "\xdf\x76\x0d\x81\x18\xaf\x23\xba"
654 "\x51\xe8\x5c\xf3\x8a\x21\x95\x2c"
655 "\xc3\x37\xce\x65\xfc\x70\x07\x9e"
656 "\x12\xa9\x40\xd7\x4b\xe2\x79\x10"
657 "\x84\x1b\xb2\x26\xbd\x54\xeb\x5f"
658 "\xf6\x8d\x01\x98\x2f\xc6\x3a\xd1"
659 "\x68\xff\x73\x0a\xa1\x15\xac\x43"
660 "\xda\x4e\xe5\x7c\x13\x87\x1e\xb5"
661 "\x29\xc0\x57\xee\x62\xf9\x90\x04"
662 "\x9b\x32\xc9\x3d\xd4\x6b\x02\x76"
663 "\x0d\xa4\x18\xaf\x46\xdd\x51\xe8"
664 "\x7f\x16\x8a\x21\xb8\x2c\xc3\x5a"
665 "\xf1\x65\xfc\x93\x07\x9e\x35\xcc"
666 "\x40\xd7\x6e\x05\x79\x10\xa7\x1b"
667 "\xb2\x49\xe0\x54\xeb\x82\x19\x8d"
668 "\x24\xbb\x2f\xc6\x5d\xf4\x68\xff"
669 "\x96\x0a\xa1\x38\xcf\x43\xda\x71"
670 "\x08\x7c\x13\xaa\x1e\xb5\x4c",
671 .psize = 1023,
672 .digest = "\xb8\xe3\x54\xed\xc5\xfc\xef\xa4"
673 "\x55\x73\x4a\x81\x99\xe4\x47\x2a"
674 "\x30\xd6\xc9\x85",
532 } 675 }
533}; 676};
534 677
@@ -536,10 +679,17 @@ static struct hash_testvec sha1_tv_template[] = {
536/* 679/*
537 * SHA224 test vectors from from FIPS PUB 180-2 680 * SHA224 test vectors from from FIPS PUB 180-2
538 */ 681 */
539#define SHA224_TEST_VECTORS 2 682#define SHA224_TEST_VECTORS 5
540 683
541static struct hash_testvec sha224_tv_template[] = { 684static struct hash_testvec sha224_tv_template[] = {
542 { 685 {
686 .plaintext = "",
687 .psize = 0,
688 .digest = "\xd1\x4a\x02\x8c\x2a\x3a\x2b\xc9"
689 "\x47\x61\x02\xbb\x28\x82\x34\xc4"
690 "\x15\xa2\xb0\x1f\x82\x8e\xa6\x2a"
691 "\xc5\xb3\xe4\x2f",
692 }, {
543 .plaintext = "abc", 693 .plaintext = "abc",
544 .psize = 3, 694 .psize = 3,
545 .digest = "\x23\x09\x7D\x22\x34\x05\xD8\x22" 695 .digest = "\x23\x09\x7D\x22\x34\x05\xD8\x22"
@@ -556,16 +706,164 @@ static struct hash_testvec sha224_tv_template[] = {
556 "\x52\x52\x25\x25", 706 "\x52\x52\x25\x25",
557 .np = 2, 707 .np = 2,
558 .tap = { 28, 28 } 708 .tap = { 28, 28 }
709 }, {
710 .plaintext = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+-",
711 .psize = 64,
712 .digest = "\xc4\xdb\x2b\x3a\x58\xc3\x99\x01"
713 "\x42\xfd\x10\x92\xaa\x4e\x04\x08"
714 "\x58\xbb\xbb\xe8\xf8\x14\xa7\x0c"
715 "\xef\x3b\xcb\x0e",
716 }, {
717 .plaintext = "\x08\x9f\x13\xaa\x41\xd8\x4c\xe3"
718 "\x7a\x11\x85\x1c\xb3\x27\xbe\x55"
719 "\xec\x60\xf7\x8e\x02\x99\x30\xc7"
720 "\x3b\xd2\x69\x00\x74\x0b\xa2\x16"
721 "\xad\x44\xdb\x4f\xe6\x7d\x14\x88"
722 "\x1f\xb6\x2a\xc1\x58\xef\x63\xfa"
723 "\x91\x05\x9c\x33\xca\x3e\xd5\x6c"
724 "\x03\x77\x0e\xa5\x19\xb0\x47\xde"
725 "\x52\xe9\x80\x17\x8b\x22\xb9\x2d"
726 "\xc4\x5b\xf2\x66\xfd\x94\x08\x9f"
727 "\x36\xcd\x41\xd8\x6f\x06\x7a\x11"
728 "\xa8\x1c\xb3\x4a\xe1\x55\xec\x83"
729 "\x1a\x8e\x25\xbc\x30\xc7\x5e\xf5"
730 "\x69\x00\x97\x0b\xa2\x39\xd0\x44"
731 "\xdb\x72\x09\x7d\x14\xab\x1f\xb6"
732 "\x4d\xe4\x58\xef\x86\x1d\x91\x28"
733 "\xbf\x33\xca\x61\xf8\x6c\x03\x9a"
734 "\x0e\xa5\x3c\xd3\x47\xde\x75\x0c"
735 "\x80\x17\xae\x22\xb9\x50\xe7\x5b"
736 "\xf2\x89\x20\x94\x2b\xc2\x36\xcd"
737 "\x64\xfb\x6f\x06\x9d\x11\xa8\x3f"
738 "\xd6\x4a\xe1\x78\x0f\x83\x1a\xb1"
739 "\x25\xbc\x53\xea\x5e\xf5\x8c\x00"
740 "\x97\x2e\xc5\x39\xd0\x67\xfe\x72"
741 "\x09\xa0\x14\xab\x42\xd9\x4d\xe4"
742 "\x7b\x12\x86\x1d\xb4\x28\xbf\x56"
743 "\xed\x61\xf8\x8f\x03\x9a\x31\xc8"
744 "\x3c\xd3\x6a\x01\x75\x0c\xa3\x17"
745 "\xae\x45\xdc\x50\xe7\x7e\x15\x89"
746 "\x20\xb7\x2b\xc2\x59\xf0\x64\xfb"
747 "\x92\x06\x9d\x34\xcb\x3f\xd6\x6d"
748 "\x04\x78\x0f\xa6\x1a\xb1\x48\xdf"
749 "\x53\xea\x81\x18\x8c\x23\xba\x2e"
750 "\xc5\x5c\xf3\x67\xfe\x95\x09\xa0"
751 "\x37\xce\x42\xd9\x70\x07\x7b\x12"
752 "\xa9\x1d\xb4\x4b\xe2\x56\xed\x84"
753 "\x1b\x8f\x26\xbd\x31\xc8\x5f\xf6"
754 "\x6a\x01\x98\x0c\xa3\x3a\xd1\x45"
755 "\xdc\x73\x0a\x7e\x15\xac\x20\xb7"
756 "\x4e\xe5\x59\xf0\x87\x1e\x92\x29"
757 "\xc0\x34\xcb\x62\xf9\x6d\x04\x9b"
758 "\x0f\xa6\x3d\xd4\x48\xdf\x76\x0d"
759 "\x81\x18\xaf\x23\xba\x51\xe8\x5c"
760 "\xf3\x8a\x21\x95\x2c\xc3\x37\xce"
761 "\x65\xfc\x70\x07\x9e\x12\xa9\x40"
762 "\xd7\x4b\xe2\x79\x10\x84\x1b\xb2"
763 "\x26\xbd\x54\xeb\x5f\xf6\x8d\x01"
764 "\x98\x2f\xc6\x3a\xd1\x68\xff\x73"
765 "\x0a\xa1\x15\xac\x43\xda\x4e\xe5"
766 "\x7c\x13\x87\x1e\xb5\x29\xc0\x57"
767 "\xee\x62\xf9\x90\x04\x9b\x32\xc9"
768 "\x3d\xd4\x6b\x02\x76\x0d\xa4\x18"
769 "\xaf\x46\xdd\x51\xe8\x7f\x16\x8a"
770 "\x21\xb8\x2c\xc3\x5a\xf1\x65\xfc"
771 "\x93\x07\x9e\x35\xcc\x40\xd7\x6e"
772 "\x05\x79\x10\xa7\x1b\xb2\x49\xe0"
773 "\x54\xeb\x82\x19\x8d\x24\xbb\x2f"
774 "\xc6\x5d\xf4\x68\xff\x96\x0a\xa1"
775 "\x38\xcf\x43\xda\x71\x08\x7c\x13"
776 "\xaa\x1e\xb5\x4c\xe3\x57\xee\x85"
777 "\x1c\x90\x27\xbe\x32\xc9\x60\xf7"
778 "\x6b\x02\x99\x0d\xa4\x3b\xd2\x46"
779 "\xdd\x74\x0b\x7f\x16\xad\x21\xb8"
780 "\x4f\xe6\x5a\xf1\x88\x1f\x93\x2a"
781 "\xc1\x35\xcc\x63\xfa\x6e\x05\x9c"
782 "\x10\xa7\x3e\xd5\x49\xe0\x77\x0e"
783 "\x82\x19\xb0\x24\xbb\x52\xe9\x5d"
784 "\xf4\x8b\x22\x96\x2d\xc4\x38\xcf"
785 "\x66\xfd\x71\x08\x9f\x13\xaa\x41"
786 "\xd8\x4c\xe3\x7a\x11\x85\x1c\xb3"
787 "\x27\xbe\x55\xec\x60\xf7\x8e\x02"
788 "\x99\x30\xc7\x3b\xd2\x69\x00\x74"
789 "\x0b\xa2\x16\xad\x44\xdb\x4f\xe6"
790 "\x7d\x14\x88\x1f\xb6\x2a\xc1\x58"
791 "\xef\x63\xfa\x91\x05\x9c\x33\xca"
792 "\x3e\xd5\x6c\x03\x77\x0e\xa5\x19"
793 "\xb0\x47\xde\x52\xe9\x80\x17\x8b"
794 "\x22\xb9\x2d\xc4\x5b\xf2\x66\xfd"
795 "\x94\x08\x9f\x36\xcd\x41\xd8\x6f"
796 "\x06\x7a\x11\xa8\x1c\xb3\x4a\xe1"
797 "\x55\xec\x83\x1a\x8e\x25\xbc\x30"
798 "\xc7\x5e\xf5\x69\x00\x97\x0b\xa2"
799 "\x39\xd0\x44\xdb\x72\x09\x7d\x14"
800 "\xab\x1f\xb6\x4d\xe4\x58\xef\x86"
801 "\x1d\x91\x28\xbf\x33\xca\x61\xf8"
802 "\x6c\x03\x9a\x0e\xa5\x3c\xd3\x47"
803 "\xde\x75\x0c\x80\x17\xae\x22\xb9"
804 "\x50\xe7\x5b\xf2\x89\x20\x94\x2b"
805 "\xc2\x36\xcd\x64\xfb\x6f\x06\x9d"
806 "\x11\xa8\x3f\xd6\x4a\xe1\x78\x0f"
807 "\x83\x1a\xb1\x25\xbc\x53\xea\x5e"
808 "\xf5\x8c\x00\x97\x2e\xc5\x39\xd0"
809 "\x67\xfe\x72\x09\xa0\x14\xab\x42"
810 "\xd9\x4d\xe4\x7b\x12\x86\x1d\xb4"
811 "\x28\xbf\x56\xed\x61\xf8\x8f\x03"
812 "\x9a\x31\xc8\x3c\xd3\x6a\x01\x75"
813 "\x0c\xa3\x17\xae\x45\xdc\x50\xe7"
814 "\x7e\x15\x89\x20\xb7\x2b\xc2\x59"
815 "\xf0\x64\xfb\x92\x06\x9d\x34\xcb"
816 "\x3f\xd6\x6d\x04\x78\x0f\xa6\x1a"
817 "\xb1\x48\xdf\x53\xea\x81\x18\x8c"
818 "\x23\xba\x2e\xc5\x5c\xf3\x67\xfe"
819 "\x95\x09\xa0\x37\xce\x42\xd9\x70"
820 "\x07\x7b\x12\xa9\x1d\xb4\x4b\xe2"
821 "\x56\xed\x84\x1b\x8f\x26\xbd\x31"
822 "\xc8\x5f\xf6\x6a\x01\x98\x0c\xa3"
823 "\x3a\xd1\x45\xdc\x73\x0a\x7e\x15"
824 "\xac\x20\xb7\x4e\xe5\x59\xf0\x87"
825 "\x1e\x92\x29\xc0\x34\xcb\x62\xf9"
826 "\x6d\x04\x9b\x0f\xa6\x3d\xd4\x48"
827 "\xdf\x76\x0d\x81\x18\xaf\x23\xba"
828 "\x51\xe8\x5c\xf3\x8a\x21\x95\x2c"
829 "\xc3\x37\xce\x65\xfc\x70\x07\x9e"
830 "\x12\xa9\x40\xd7\x4b\xe2\x79\x10"
831 "\x84\x1b\xb2\x26\xbd\x54\xeb\x5f"
832 "\xf6\x8d\x01\x98\x2f\xc6\x3a\xd1"
833 "\x68\xff\x73\x0a\xa1\x15\xac\x43"
834 "\xda\x4e\xe5\x7c\x13\x87\x1e\xb5"
835 "\x29\xc0\x57\xee\x62\xf9\x90\x04"
836 "\x9b\x32\xc9\x3d\xd4\x6b\x02\x76"
837 "\x0d\xa4\x18\xaf\x46\xdd\x51\xe8"
838 "\x7f\x16\x8a\x21\xb8\x2c\xc3\x5a"
839 "\xf1\x65\xfc\x93\x07\x9e\x35\xcc"
840 "\x40\xd7\x6e\x05\x79\x10\xa7\x1b"
841 "\xb2\x49\xe0\x54\xeb\x82\x19\x8d"
842 "\x24\xbb\x2f\xc6\x5d\xf4\x68\xff"
843 "\x96\x0a\xa1\x38\xcf\x43\xda\x71"
844 "\x08\x7c\x13\xaa\x1e\xb5\x4c",
845 .psize = 1023,
846 .digest = "\x98\x43\x07\x63\x75\xe0\xa7\x1c"
847 "\x78\xb1\x8b\xfd\x04\xf5\x2d\x91"
848 "\x20\x48\xa4\x28\xff\x55\xb1\xd3"
849 "\xe6\xf9\x4f\xcc",
559 } 850 }
560}; 851};
561 852
562/* 853/*
563 * SHA256 test vectors from from NIST 854 * SHA256 test vectors from from NIST
564 */ 855 */
565#define SHA256_TEST_VECTORS 2 856#define SHA256_TEST_VECTORS 5
566 857
567static struct hash_testvec sha256_tv_template[] = { 858static struct hash_testvec sha256_tv_template[] = {
568 { 859 {
860 .plaintext = "",
861 .psize = 0,
862 .digest = "\xe3\xb0\xc4\x42\x98\xfc\x1c\x14"
863 "\x9a\xfb\xf4\xc8\x99\x6f\xb9\x24"
864 "\x27\xae\x41\xe4\x64\x9b\x93\x4c"
865 "\xa4\x95\x99\x1b\x78\x52\xb8\x55",
866 }, {
569 .plaintext = "abc", 867 .plaintext = "abc",
570 .psize = 3, 868 .psize = 3,
571 .digest = "\xba\x78\x16\xbf\x8f\x01\xcf\xea" 869 .digest = "\xba\x78\x16\xbf\x8f\x01\xcf\xea"
@@ -581,16 +879,166 @@ static struct hash_testvec sha256_tv_template[] = {
581 "\xf6\xec\xed\xd4\x19\xdb\x06\xc1", 879 "\xf6\xec\xed\xd4\x19\xdb\x06\xc1",
582 .np = 2, 880 .np = 2,
583 .tap = { 28, 28 } 881 .tap = { 28, 28 }
584 }, 882 }, {
883 .plaintext = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+-",
884 .psize = 64,
885 .digest = "\xb5\xfe\xad\x56\x7d\xff\xcb\xa4"
886 "\x2c\x32\x29\x32\x19\xbb\xfb\xfa"
887 "\xd6\xff\x94\xa3\x72\x91\x85\x66"
888 "\x3b\xa7\x87\x77\x58\xa3\x40\x3a",
889 }, {
890 .plaintext = "\x08\x9f\x13\xaa\x41\xd8\x4c\xe3"
891 "\x7a\x11\x85\x1c\xb3\x27\xbe\x55"
892 "\xec\x60\xf7\x8e\x02\x99\x30\xc7"
893 "\x3b\xd2\x69\x00\x74\x0b\xa2\x16"
894 "\xad\x44\xdb\x4f\xe6\x7d\x14\x88"
895 "\x1f\xb6\x2a\xc1\x58\xef\x63\xfa"
896 "\x91\x05\x9c\x33\xca\x3e\xd5\x6c"
897 "\x03\x77\x0e\xa5\x19\xb0\x47\xde"
898 "\x52\xe9\x80\x17\x8b\x22\xb9\x2d"
899 "\xc4\x5b\xf2\x66\xfd\x94\x08\x9f"
900 "\x36\xcd\x41\xd8\x6f\x06\x7a\x11"
901 "\xa8\x1c\xb3\x4a\xe1\x55\xec\x83"
902 "\x1a\x8e\x25\xbc\x30\xc7\x5e\xf5"
903 "\x69\x00\x97\x0b\xa2\x39\xd0\x44"
904 "\xdb\x72\x09\x7d\x14\xab\x1f\xb6"
905 "\x4d\xe4\x58\xef\x86\x1d\x91\x28"
906 "\xbf\x33\xca\x61\xf8\x6c\x03\x9a"
907 "\x0e\xa5\x3c\xd3\x47\xde\x75\x0c"
908 "\x80\x17\xae\x22\xb9\x50\xe7\x5b"
909 "\xf2\x89\x20\x94\x2b\xc2\x36\xcd"
910 "\x64\xfb\x6f\x06\x9d\x11\xa8\x3f"
911 "\xd6\x4a\xe1\x78\x0f\x83\x1a\xb1"
912 "\x25\xbc\x53\xea\x5e\xf5\x8c\x00"
913 "\x97\x2e\xc5\x39\xd0\x67\xfe\x72"
914 "\x09\xa0\x14\xab\x42\xd9\x4d\xe4"
915 "\x7b\x12\x86\x1d\xb4\x28\xbf\x56"
916 "\xed\x61\xf8\x8f\x03\x9a\x31\xc8"
917 "\x3c\xd3\x6a\x01\x75\x0c\xa3\x17"
918 "\xae\x45\xdc\x50\xe7\x7e\x15\x89"
919 "\x20\xb7\x2b\xc2\x59\xf0\x64\xfb"
920 "\x92\x06\x9d\x34\xcb\x3f\xd6\x6d"
921 "\x04\x78\x0f\xa6\x1a\xb1\x48\xdf"
922 "\x53\xea\x81\x18\x8c\x23\xba\x2e"
923 "\xc5\x5c\xf3\x67\xfe\x95\x09\xa0"
924 "\x37\xce\x42\xd9\x70\x07\x7b\x12"
925 "\xa9\x1d\xb4\x4b\xe2\x56\xed\x84"
926 "\x1b\x8f\x26\xbd\x31\xc8\x5f\xf6"
927 "\x6a\x01\x98\x0c\xa3\x3a\xd1\x45"
928 "\xdc\x73\x0a\x7e\x15\xac\x20\xb7"
929 "\x4e\xe5\x59\xf0\x87\x1e\x92\x29"
930 "\xc0\x34\xcb\x62\xf9\x6d\x04\x9b"
931 "\x0f\xa6\x3d\xd4\x48\xdf\x76\x0d"
932 "\x81\x18\xaf\x23\xba\x51\xe8\x5c"
933 "\xf3\x8a\x21\x95\x2c\xc3\x37\xce"
934 "\x65\xfc\x70\x07\x9e\x12\xa9\x40"
935 "\xd7\x4b\xe2\x79\x10\x84\x1b\xb2"
936 "\x26\xbd\x54\xeb\x5f\xf6\x8d\x01"
937 "\x98\x2f\xc6\x3a\xd1\x68\xff\x73"
938 "\x0a\xa1\x15\xac\x43\xda\x4e\xe5"
939 "\x7c\x13\x87\x1e\xb5\x29\xc0\x57"
940 "\xee\x62\xf9\x90\x04\x9b\x32\xc9"
941 "\x3d\xd4\x6b\x02\x76\x0d\xa4\x18"
942 "\xaf\x46\xdd\x51\xe8\x7f\x16\x8a"
943 "\x21\xb8\x2c\xc3\x5a\xf1\x65\xfc"
944 "\x93\x07\x9e\x35\xcc\x40\xd7\x6e"
945 "\x05\x79\x10\xa7\x1b\xb2\x49\xe0"
946 "\x54\xeb\x82\x19\x8d\x24\xbb\x2f"
947 "\xc6\x5d\xf4\x68\xff\x96\x0a\xa1"
948 "\x38\xcf\x43\xda\x71\x08\x7c\x13"
949 "\xaa\x1e\xb5\x4c\xe3\x57\xee\x85"
950 "\x1c\x90\x27\xbe\x32\xc9\x60\xf7"
951 "\x6b\x02\x99\x0d\xa4\x3b\xd2\x46"
952 "\xdd\x74\x0b\x7f\x16\xad\x21\xb8"
953 "\x4f\xe6\x5a\xf1\x88\x1f\x93\x2a"
954 "\xc1\x35\xcc\x63\xfa\x6e\x05\x9c"
955 "\x10\xa7\x3e\xd5\x49\xe0\x77\x0e"
956 "\x82\x19\xb0\x24\xbb\x52\xe9\x5d"
957 "\xf4\x8b\x22\x96\x2d\xc4\x38\xcf"
958 "\x66\xfd\x71\x08\x9f\x13\xaa\x41"
959 "\xd8\x4c\xe3\x7a\x11\x85\x1c\xb3"
960 "\x27\xbe\x55\xec\x60\xf7\x8e\x02"
961 "\x99\x30\xc7\x3b\xd2\x69\x00\x74"
962 "\x0b\xa2\x16\xad\x44\xdb\x4f\xe6"
963 "\x7d\x14\x88\x1f\xb6\x2a\xc1\x58"
964 "\xef\x63\xfa\x91\x05\x9c\x33\xca"
965 "\x3e\xd5\x6c\x03\x77\x0e\xa5\x19"
966 "\xb0\x47\xde\x52\xe9\x80\x17\x8b"
967 "\x22\xb9\x2d\xc4\x5b\xf2\x66\xfd"
968 "\x94\x08\x9f\x36\xcd\x41\xd8\x6f"
969 "\x06\x7a\x11\xa8\x1c\xb3\x4a\xe1"
970 "\x55\xec\x83\x1a\x8e\x25\xbc\x30"
971 "\xc7\x5e\xf5\x69\x00\x97\x0b\xa2"
972 "\x39\xd0\x44\xdb\x72\x09\x7d\x14"
973 "\xab\x1f\xb6\x4d\xe4\x58\xef\x86"
974 "\x1d\x91\x28\xbf\x33\xca\x61\xf8"
975 "\x6c\x03\x9a\x0e\xa5\x3c\xd3\x47"
976 "\xde\x75\x0c\x80\x17\xae\x22\xb9"
977 "\x50\xe7\x5b\xf2\x89\x20\x94\x2b"
978 "\xc2\x36\xcd\x64\xfb\x6f\x06\x9d"
979 "\x11\xa8\x3f\xd6\x4a\xe1\x78\x0f"
980 "\x83\x1a\xb1\x25\xbc\x53\xea\x5e"
981 "\xf5\x8c\x00\x97\x2e\xc5\x39\xd0"
982 "\x67\xfe\x72\x09\xa0\x14\xab\x42"
983 "\xd9\x4d\xe4\x7b\x12\x86\x1d\xb4"
984 "\x28\xbf\x56\xed\x61\xf8\x8f\x03"
985 "\x9a\x31\xc8\x3c\xd3\x6a\x01\x75"
986 "\x0c\xa3\x17\xae\x45\xdc\x50\xe7"
987 "\x7e\x15\x89\x20\xb7\x2b\xc2\x59"
988 "\xf0\x64\xfb\x92\x06\x9d\x34\xcb"
989 "\x3f\xd6\x6d\x04\x78\x0f\xa6\x1a"
990 "\xb1\x48\xdf\x53\xea\x81\x18\x8c"
991 "\x23\xba\x2e\xc5\x5c\xf3\x67\xfe"
992 "\x95\x09\xa0\x37\xce\x42\xd9\x70"
993 "\x07\x7b\x12\xa9\x1d\xb4\x4b\xe2"
994 "\x56\xed\x84\x1b\x8f\x26\xbd\x31"
995 "\xc8\x5f\xf6\x6a\x01\x98\x0c\xa3"
996 "\x3a\xd1\x45\xdc\x73\x0a\x7e\x15"
997 "\xac\x20\xb7\x4e\xe5\x59\xf0\x87"
998 "\x1e\x92\x29\xc0\x34\xcb\x62\xf9"
999 "\x6d\x04\x9b\x0f\xa6\x3d\xd4\x48"
1000 "\xdf\x76\x0d\x81\x18\xaf\x23\xba"
1001 "\x51\xe8\x5c\xf3\x8a\x21\x95\x2c"
1002 "\xc3\x37\xce\x65\xfc\x70\x07\x9e"
1003 "\x12\xa9\x40\xd7\x4b\xe2\x79\x10"
1004 "\x84\x1b\xb2\x26\xbd\x54\xeb\x5f"
1005 "\xf6\x8d\x01\x98\x2f\xc6\x3a\xd1"
1006 "\x68\xff\x73\x0a\xa1\x15\xac\x43"
1007 "\xda\x4e\xe5\x7c\x13\x87\x1e\xb5"
1008 "\x29\xc0\x57\xee\x62\xf9\x90\x04"
1009 "\x9b\x32\xc9\x3d\xd4\x6b\x02\x76"
1010 "\x0d\xa4\x18\xaf\x46\xdd\x51\xe8"
1011 "\x7f\x16\x8a\x21\xb8\x2c\xc3\x5a"
1012 "\xf1\x65\xfc\x93\x07\x9e\x35\xcc"
1013 "\x40\xd7\x6e\x05\x79\x10\xa7\x1b"
1014 "\xb2\x49\xe0\x54\xeb\x82\x19\x8d"
1015 "\x24\xbb\x2f\xc6\x5d\xf4\x68\xff"
1016 "\x96\x0a\xa1\x38\xcf\x43\xda\x71"
1017 "\x08\x7c\x13\xaa\x1e\xb5\x4c",
1018 .psize = 1023,
1019 .digest = "\xc5\xce\x0c\xca\x01\x4f\x53\x3a"
1020 "\x32\x32\x17\xcc\xd4\x6a\x71\xa9"
1021 "\xf3\xed\x50\x10\x64\x8e\x06\xbe"
1022 "\x9b\x4a\xa6\xbb\x05\x89\x59\x51",
1023 }
585}; 1024};
586 1025
587/* 1026/*
588 * SHA384 test vectors from from NIST and kerneli 1027 * SHA384 test vectors from from NIST and kerneli
589 */ 1028 */
590#define SHA384_TEST_VECTORS 4 1029#define SHA384_TEST_VECTORS 6
591 1030
592static struct hash_testvec sha384_tv_template[] = { 1031static struct hash_testvec sha384_tv_template[] = {
593 { 1032 {
1033 .plaintext = "",
1034 .psize = 0,
1035 .digest = "\x38\xb0\x60\xa7\x51\xac\x96\x38"
1036 "\x4c\xd9\x32\x7e\xb1\xb1\xe3\x6a"
1037 "\x21\xfd\xb7\x11\x14\xbe\x07\x43"
1038 "\x4c\x0c\xc7\xbf\x63\xf6\xe1\xda"
1039 "\x27\x4e\xde\xbf\xe7\x6f\x65\xfb"
1040 "\xd5\x1a\xd2\xf1\x48\x98\xb9\x5b",
1041 }, {
594 .plaintext= "abc", 1042 .plaintext= "abc",
595 .psize = 3, 1043 .psize = 3,
596 .digest = "\xcb\x00\x75\x3f\x45\xa3\x5e\x8b" 1044 .digest = "\xcb\x00\x75\x3f\x45\xa3\x5e\x8b"
@@ -630,16 +1078,163 @@ static struct hash_testvec sha384_tv_template[] = {
630 "\xc9\x38\xe2\xd1\x99\xe8\xbe\xa4", 1078 "\xc9\x38\xe2\xd1\x99\xe8\xbe\xa4",
631 .np = 4, 1079 .np = 4,
632 .tap = { 26, 26, 26, 26 } 1080 .tap = { 26, 26, 26, 26 }
633 }, 1081 }, {
1082 .plaintext = "\x08\x9f\x13\xaa\x41\xd8\x4c\xe3"
1083 "\x7a\x11\x85\x1c\xb3\x27\xbe\x55"
1084 "\xec\x60\xf7\x8e\x02\x99\x30\xc7"
1085 "\x3b\xd2\x69\x00\x74\x0b\xa2\x16"
1086 "\xad\x44\xdb\x4f\xe6\x7d\x14\x88"
1087 "\x1f\xb6\x2a\xc1\x58\xef\x63\xfa"
1088 "\x91\x05\x9c\x33\xca\x3e\xd5\x6c"
1089 "\x03\x77\x0e\xa5\x19\xb0\x47\xde"
1090 "\x52\xe9\x80\x17\x8b\x22\xb9\x2d"
1091 "\xc4\x5b\xf2\x66\xfd\x94\x08\x9f"
1092 "\x36\xcd\x41\xd8\x6f\x06\x7a\x11"
1093 "\xa8\x1c\xb3\x4a\xe1\x55\xec\x83"
1094 "\x1a\x8e\x25\xbc\x30\xc7\x5e\xf5"
1095 "\x69\x00\x97\x0b\xa2\x39\xd0\x44"
1096 "\xdb\x72\x09\x7d\x14\xab\x1f\xb6"
1097 "\x4d\xe4\x58\xef\x86\x1d\x91\x28"
1098 "\xbf\x33\xca\x61\xf8\x6c\x03\x9a"
1099 "\x0e\xa5\x3c\xd3\x47\xde\x75\x0c"
1100 "\x80\x17\xae\x22\xb9\x50\xe7\x5b"
1101 "\xf2\x89\x20\x94\x2b\xc2\x36\xcd"
1102 "\x64\xfb\x6f\x06\x9d\x11\xa8\x3f"
1103 "\xd6\x4a\xe1\x78\x0f\x83\x1a\xb1"
1104 "\x25\xbc\x53\xea\x5e\xf5\x8c\x00"
1105 "\x97\x2e\xc5\x39\xd0\x67\xfe\x72"
1106 "\x09\xa0\x14\xab\x42\xd9\x4d\xe4"
1107 "\x7b\x12\x86\x1d\xb4\x28\xbf\x56"
1108 "\xed\x61\xf8\x8f\x03\x9a\x31\xc8"
1109 "\x3c\xd3\x6a\x01\x75\x0c\xa3\x17"
1110 "\xae\x45\xdc\x50\xe7\x7e\x15\x89"
1111 "\x20\xb7\x2b\xc2\x59\xf0\x64\xfb"
1112 "\x92\x06\x9d\x34\xcb\x3f\xd6\x6d"
1113 "\x04\x78\x0f\xa6\x1a\xb1\x48\xdf"
1114 "\x53\xea\x81\x18\x8c\x23\xba\x2e"
1115 "\xc5\x5c\xf3\x67\xfe\x95\x09\xa0"
1116 "\x37\xce\x42\xd9\x70\x07\x7b\x12"
1117 "\xa9\x1d\xb4\x4b\xe2\x56\xed\x84"
1118 "\x1b\x8f\x26\xbd\x31\xc8\x5f\xf6"
1119 "\x6a\x01\x98\x0c\xa3\x3a\xd1\x45"
1120 "\xdc\x73\x0a\x7e\x15\xac\x20\xb7"
1121 "\x4e\xe5\x59\xf0\x87\x1e\x92\x29"
1122 "\xc0\x34\xcb\x62\xf9\x6d\x04\x9b"
1123 "\x0f\xa6\x3d\xd4\x48\xdf\x76\x0d"
1124 "\x81\x18\xaf\x23\xba\x51\xe8\x5c"
1125 "\xf3\x8a\x21\x95\x2c\xc3\x37\xce"
1126 "\x65\xfc\x70\x07\x9e\x12\xa9\x40"
1127 "\xd7\x4b\xe2\x79\x10\x84\x1b\xb2"
1128 "\x26\xbd\x54\xeb\x5f\xf6\x8d\x01"
1129 "\x98\x2f\xc6\x3a\xd1\x68\xff\x73"
1130 "\x0a\xa1\x15\xac\x43\xda\x4e\xe5"
1131 "\x7c\x13\x87\x1e\xb5\x29\xc0\x57"
1132 "\xee\x62\xf9\x90\x04\x9b\x32\xc9"
1133 "\x3d\xd4\x6b\x02\x76\x0d\xa4\x18"
1134 "\xaf\x46\xdd\x51\xe8\x7f\x16\x8a"
1135 "\x21\xb8\x2c\xc3\x5a\xf1\x65\xfc"
1136 "\x93\x07\x9e\x35\xcc\x40\xd7\x6e"
1137 "\x05\x79\x10\xa7\x1b\xb2\x49\xe0"
1138 "\x54\xeb\x82\x19\x8d\x24\xbb\x2f"
1139 "\xc6\x5d\xf4\x68\xff\x96\x0a\xa1"
1140 "\x38\xcf\x43\xda\x71\x08\x7c\x13"
1141 "\xaa\x1e\xb5\x4c\xe3\x57\xee\x85"
1142 "\x1c\x90\x27\xbe\x32\xc9\x60\xf7"
1143 "\x6b\x02\x99\x0d\xa4\x3b\xd2\x46"
1144 "\xdd\x74\x0b\x7f\x16\xad\x21\xb8"
1145 "\x4f\xe6\x5a\xf1\x88\x1f\x93\x2a"
1146 "\xc1\x35\xcc\x63\xfa\x6e\x05\x9c"
1147 "\x10\xa7\x3e\xd5\x49\xe0\x77\x0e"
1148 "\x82\x19\xb0\x24\xbb\x52\xe9\x5d"
1149 "\xf4\x8b\x22\x96\x2d\xc4\x38\xcf"
1150 "\x66\xfd\x71\x08\x9f\x13\xaa\x41"
1151 "\xd8\x4c\xe3\x7a\x11\x85\x1c\xb3"
1152 "\x27\xbe\x55\xec\x60\xf7\x8e\x02"
1153 "\x99\x30\xc7\x3b\xd2\x69\x00\x74"
1154 "\x0b\xa2\x16\xad\x44\xdb\x4f\xe6"
1155 "\x7d\x14\x88\x1f\xb6\x2a\xc1\x58"
1156 "\xef\x63\xfa\x91\x05\x9c\x33\xca"
1157 "\x3e\xd5\x6c\x03\x77\x0e\xa5\x19"
1158 "\xb0\x47\xde\x52\xe9\x80\x17\x8b"
1159 "\x22\xb9\x2d\xc4\x5b\xf2\x66\xfd"
1160 "\x94\x08\x9f\x36\xcd\x41\xd8\x6f"
1161 "\x06\x7a\x11\xa8\x1c\xb3\x4a\xe1"
1162 "\x55\xec\x83\x1a\x8e\x25\xbc\x30"
1163 "\xc7\x5e\xf5\x69\x00\x97\x0b\xa2"
1164 "\x39\xd0\x44\xdb\x72\x09\x7d\x14"
1165 "\xab\x1f\xb6\x4d\xe4\x58\xef\x86"
1166 "\x1d\x91\x28\xbf\x33\xca\x61\xf8"
1167 "\x6c\x03\x9a\x0e\xa5\x3c\xd3\x47"
1168 "\xde\x75\x0c\x80\x17\xae\x22\xb9"
1169 "\x50\xe7\x5b\xf2\x89\x20\x94\x2b"
1170 "\xc2\x36\xcd\x64\xfb\x6f\x06\x9d"
1171 "\x11\xa8\x3f\xd6\x4a\xe1\x78\x0f"
1172 "\x83\x1a\xb1\x25\xbc\x53\xea\x5e"
1173 "\xf5\x8c\x00\x97\x2e\xc5\x39\xd0"
1174 "\x67\xfe\x72\x09\xa0\x14\xab\x42"
1175 "\xd9\x4d\xe4\x7b\x12\x86\x1d\xb4"
1176 "\x28\xbf\x56\xed\x61\xf8\x8f\x03"
1177 "\x9a\x31\xc8\x3c\xd3\x6a\x01\x75"
1178 "\x0c\xa3\x17\xae\x45\xdc\x50\xe7"
1179 "\x7e\x15\x89\x20\xb7\x2b\xc2\x59"
1180 "\xf0\x64\xfb\x92\x06\x9d\x34\xcb"
1181 "\x3f\xd6\x6d\x04\x78\x0f\xa6\x1a"
1182 "\xb1\x48\xdf\x53\xea\x81\x18\x8c"
1183 "\x23\xba\x2e\xc5\x5c\xf3\x67\xfe"
1184 "\x95\x09\xa0\x37\xce\x42\xd9\x70"
1185 "\x07\x7b\x12\xa9\x1d\xb4\x4b\xe2"
1186 "\x56\xed\x84\x1b\x8f\x26\xbd\x31"
1187 "\xc8\x5f\xf6\x6a\x01\x98\x0c\xa3"
1188 "\x3a\xd1\x45\xdc\x73\x0a\x7e\x15"
1189 "\xac\x20\xb7\x4e\xe5\x59\xf0\x87"
1190 "\x1e\x92\x29\xc0\x34\xcb\x62\xf9"
1191 "\x6d\x04\x9b\x0f\xa6\x3d\xd4\x48"
1192 "\xdf\x76\x0d\x81\x18\xaf\x23\xba"
1193 "\x51\xe8\x5c\xf3\x8a\x21\x95\x2c"
1194 "\xc3\x37\xce\x65\xfc\x70\x07\x9e"
1195 "\x12\xa9\x40\xd7\x4b\xe2\x79\x10"
1196 "\x84\x1b\xb2\x26\xbd\x54\xeb\x5f"
1197 "\xf6\x8d\x01\x98\x2f\xc6\x3a\xd1"
1198 "\x68\xff\x73\x0a\xa1\x15\xac\x43"
1199 "\xda\x4e\xe5\x7c\x13\x87\x1e\xb5"
1200 "\x29\xc0\x57\xee\x62\xf9\x90\x04"
1201 "\x9b\x32\xc9\x3d\xd4\x6b\x02\x76"
1202 "\x0d\xa4\x18\xaf\x46\xdd\x51\xe8"
1203 "\x7f\x16\x8a\x21\xb8\x2c\xc3\x5a"
1204 "\xf1\x65\xfc\x93\x07\x9e\x35\xcc"
1205 "\x40\xd7\x6e\x05\x79\x10\xa7\x1b"
1206 "\xb2\x49\xe0\x54\xeb\x82\x19\x8d"
1207 "\x24\xbb\x2f\xc6\x5d\xf4\x68\xff"
1208 "\x96\x0a\xa1\x38\xcf\x43\xda\x71"
1209 "\x08\x7c\x13\xaa\x1e\xb5\x4c",
1210 .psize = 1023,
1211 .digest = "\x4d\x97\x23\xc8\xea\x7a\x7c\x15"
1212 "\xb8\xff\x97\x9c\xf5\x13\x4f\x31"
1213 "\xde\x67\xf7\x24\x73\xcd\x70\x1c"
1214 "\x03\x4a\xba\x8a\x87\x49\xfe\xdc"
1215 "\x75\x29\x62\x83\xae\x3f\x17\xab"
1216 "\xfd\x10\x4d\x8e\x17\x1c\x1f\xca",
1217 }
634}; 1218};
635 1219
636/* 1220/*
637 * SHA512 test vectors from from NIST and kerneli 1221 * SHA512 test vectors from from NIST and kerneli
638 */ 1222 */
639#define SHA512_TEST_VECTORS 4 1223#define SHA512_TEST_VECTORS 6
640 1224
641static struct hash_testvec sha512_tv_template[] = { 1225static struct hash_testvec sha512_tv_template[] = {
642 { 1226 {
1227 .plaintext = "",
1228 .psize = 0,
1229 .digest = "\xcf\x83\xe1\x35\x7e\xef\xb8\xbd"
1230 "\xf1\x54\x28\x50\xd6\x6d\x80\x07"
1231 "\xd6\x20\xe4\x05\x0b\x57\x15\xdc"
1232 "\x83\xf4\xa9\x21\xd3\x6c\xe9\xce"
1233 "\x47\xd0\xd1\x3c\x5d\x85\xf2\xb0"
1234 "\xff\x83\x18\xd2\x87\x7e\xec\x2f"
1235 "\x63\xb9\x31\xbd\x47\x41\x7a\x81"
1236 "\xa5\x38\x32\x7a\xf9\x27\xda\x3e",
1237 }, {
643 .plaintext = "abc", 1238 .plaintext = "abc",
644 .psize = 3, 1239 .psize = 3,
645 .digest = "\xdd\xaf\x35\xa1\x93\x61\x7a\xba" 1240 .digest = "\xdd\xaf\x35\xa1\x93\x61\x7a\xba"
@@ -687,7 +1282,145 @@ static struct hash_testvec sha512_tv_template[] = {
687 "\xed\xb4\x19\x87\x23\x28\x50\xc9", 1282 "\xed\xb4\x19\x87\x23\x28\x50\xc9",
688 .np = 4, 1283 .np = 4,
689 .tap = { 26, 26, 26, 26 } 1284 .tap = { 26, 26, 26, 26 }
690 }, 1285 }, {
1286 .plaintext = "\x08\x9f\x13\xaa\x41\xd8\x4c\xe3"
1287 "\x7a\x11\x85\x1c\xb3\x27\xbe\x55"
1288 "\xec\x60\xf7\x8e\x02\x99\x30\xc7"
1289 "\x3b\xd2\x69\x00\x74\x0b\xa2\x16"
1290 "\xad\x44\xdb\x4f\xe6\x7d\x14\x88"
1291 "\x1f\xb6\x2a\xc1\x58\xef\x63\xfa"
1292 "\x91\x05\x9c\x33\xca\x3e\xd5\x6c"
1293 "\x03\x77\x0e\xa5\x19\xb0\x47\xde"
1294 "\x52\xe9\x80\x17\x8b\x22\xb9\x2d"
1295 "\xc4\x5b\xf2\x66\xfd\x94\x08\x9f"
1296 "\x36\xcd\x41\xd8\x6f\x06\x7a\x11"
1297 "\xa8\x1c\xb3\x4a\xe1\x55\xec\x83"
1298 "\x1a\x8e\x25\xbc\x30\xc7\x5e\xf5"
1299 "\x69\x00\x97\x0b\xa2\x39\xd0\x44"
1300 "\xdb\x72\x09\x7d\x14\xab\x1f\xb6"
1301 "\x4d\xe4\x58\xef\x86\x1d\x91\x28"
1302 "\xbf\x33\xca\x61\xf8\x6c\x03\x9a"
1303 "\x0e\xa5\x3c\xd3\x47\xde\x75\x0c"
1304 "\x80\x17\xae\x22\xb9\x50\xe7\x5b"
1305 "\xf2\x89\x20\x94\x2b\xc2\x36\xcd"
1306 "\x64\xfb\x6f\x06\x9d\x11\xa8\x3f"
1307 "\xd6\x4a\xe1\x78\x0f\x83\x1a\xb1"
1308 "\x25\xbc\x53\xea\x5e\xf5\x8c\x00"
1309 "\x97\x2e\xc5\x39\xd0\x67\xfe\x72"
1310 "\x09\xa0\x14\xab\x42\xd9\x4d\xe4"
1311 "\x7b\x12\x86\x1d\xb4\x28\xbf\x56"
1312 "\xed\x61\xf8\x8f\x03\x9a\x31\xc8"
1313 "\x3c\xd3\x6a\x01\x75\x0c\xa3\x17"
1314 "\xae\x45\xdc\x50\xe7\x7e\x15\x89"
1315 "\x20\xb7\x2b\xc2\x59\xf0\x64\xfb"
1316 "\x92\x06\x9d\x34\xcb\x3f\xd6\x6d"
1317 "\x04\x78\x0f\xa6\x1a\xb1\x48\xdf"
1318 "\x53\xea\x81\x18\x8c\x23\xba\x2e"
1319 "\xc5\x5c\xf3\x67\xfe\x95\x09\xa0"
1320 "\x37\xce\x42\xd9\x70\x07\x7b\x12"
1321 "\xa9\x1d\xb4\x4b\xe2\x56\xed\x84"
1322 "\x1b\x8f\x26\xbd\x31\xc8\x5f\xf6"
1323 "\x6a\x01\x98\x0c\xa3\x3a\xd1\x45"
1324 "\xdc\x73\x0a\x7e\x15\xac\x20\xb7"
1325 "\x4e\xe5\x59\xf0\x87\x1e\x92\x29"
1326 "\xc0\x34\xcb\x62\xf9\x6d\x04\x9b"
1327 "\x0f\xa6\x3d\xd4\x48\xdf\x76\x0d"
1328 "\x81\x18\xaf\x23\xba\x51\xe8\x5c"
1329 "\xf3\x8a\x21\x95\x2c\xc3\x37\xce"
1330 "\x65\xfc\x70\x07\x9e\x12\xa9\x40"
1331 "\xd7\x4b\xe2\x79\x10\x84\x1b\xb2"
1332 "\x26\xbd\x54\xeb\x5f\xf6\x8d\x01"
1333 "\x98\x2f\xc6\x3a\xd1\x68\xff\x73"
1334 "\x0a\xa1\x15\xac\x43\xda\x4e\xe5"
1335 "\x7c\x13\x87\x1e\xb5\x29\xc0\x57"
1336 "\xee\x62\xf9\x90\x04\x9b\x32\xc9"
1337 "\x3d\xd4\x6b\x02\x76\x0d\xa4\x18"
1338 "\xaf\x46\xdd\x51\xe8\x7f\x16\x8a"
1339 "\x21\xb8\x2c\xc3\x5a\xf1\x65\xfc"
1340 "\x93\x07\x9e\x35\xcc\x40\xd7\x6e"
1341 "\x05\x79\x10\xa7\x1b\xb2\x49\xe0"
1342 "\x54\xeb\x82\x19\x8d\x24\xbb\x2f"
1343 "\xc6\x5d\xf4\x68\xff\x96\x0a\xa1"
1344 "\x38\xcf\x43\xda\x71\x08\x7c\x13"
1345 "\xaa\x1e\xb5\x4c\xe3\x57\xee\x85"
1346 "\x1c\x90\x27\xbe\x32\xc9\x60\xf7"
1347 "\x6b\x02\x99\x0d\xa4\x3b\xd2\x46"
1348 "\xdd\x74\x0b\x7f\x16\xad\x21\xb8"
1349 "\x4f\xe6\x5a\xf1\x88\x1f\x93\x2a"
1350 "\xc1\x35\xcc\x63\xfa\x6e\x05\x9c"
1351 "\x10\xa7\x3e\xd5\x49\xe0\x77\x0e"
1352 "\x82\x19\xb0\x24\xbb\x52\xe9\x5d"
1353 "\xf4\x8b\x22\x96\x2d\xc4\x38\xcf"
1354 "\x66\xfd\x71\x08\x9f\x13\xaa\x41"
1355 "\xd8\x4c\xe3\x7a\x11\x85\x1c\xb3"
1356 "\x27\xbe\x55\xec\x60\xf7\x8e\x02"
1357 "\x99\x30\xc7\x3b\xd2\x69\x00\x74"
1358 "\x0b\xa2\x16\xad\x44\xdb\x4f\xe6"
1359 "\x7d\x14\x88\x1f\xb6\x2a\xc1\x58"
1360 "\xef\x63\xfa\x91\x05\x9c\x33\xca"
1361 "\x3e\xd5\x6c\x03\x77\x0e\xa5\x19"
1362 "\xb0\x47\xde\x52\xe9\x80\x17\x8b"
1363 "\x22\xb9\x2d\xc4\x5b\xf2\x66\xfd"
1364 "\x94\x08\x9f\x36\xcd\x41\xd8\x6f"
1365 "\x06\x7a\x11\xa8\x1c\xb3\x4a\xe1"
1366 "\x55\xec\x83\x1a\x8e\x25\xbc\x30"
1367 "\xc7\x5e\xf5\x69\x00\x97\x0b\xa2"
1368 "\x39\xd0\x44\xdb\x72\x09\x7d\x14"
1369 "\xab\x1f\xb6\x4d\xe4\x58\xef\x86"
1370 "\x1d\x91\x28\xbf\x33\xca\x61\xf8"
1371 "\x6c\x03\x9a\x0e\xa5\x3c\xd3\x47"
1372 "\xde\x75\x0c\x80\x17\xae\x22\xb9"
1373 "\x50\xe7\x5b\xf2\x89\x20\x94\x2b"
1374 "\xc2\x36\xcd\x64\xfb\x6f\x06\x9d"
1375 "\x11\xa8\x3f\xd6\x4a\xe1\x78\x0f"
1376 "\x83\x1a\xb1\x25\xbc\x53\xea\x5e"
1377 "\xf5\x8c\x00\x97\x2e\xc5\x39\xd0"
1378 "\x67\xfe\x72\x09\xa0\x14\xab\x42"
1379 "\xd9\x4d\xe4\x7b\x12\x86\x1d\xb4"
1380 "\x28\xbf\x56\xed\x61\xf8\x8f\x03"
1381 "\x9a\x31\xc8\x3c\xd3\x6a\x01\x75"
1382 "\x0c\xa3\x17\xae\x45\xdc\x50\xe7"
1383 "\x7e\x15\x89\x20\xb7\x2b\xc2\x59"
1384 "\xf0\x64\xfb\x92\x06\x9d\x34\xcb"
1385 "\x3f\xd6\x6d\x04\x78\x0f\xa6\x1a"
1386 "\xb1\x48\xdf\x53\xea\x81\x18\x8c"
1387 "\x23\xba\x2e\xc5\x5c\xf3\x67\xfe"
1388 "\x95\x09\xa0\x37\xce\x42\xd9\x70"
1389 "\x07\x7b\x12\xa9\x1d\xb4\x4b\xe2"
1390 "\x56\xed\x84\x1b\x8f\x26\xbd\x31"
1391 "\xc8\x5f\xf6\x6a\x01\x98\x0c\xa3"
1392 "\x3a\xd1\x45\xdc\x73\x0a\x7e\x15"
1393 "\xac\x20\xb7\x4e\xe5\x59\xf0\x87"
1394 "\x1e\x92\x29\xc0\x34\xcb\x62\xf9"
1395 "\x6d\x04\x9b\x0f\xa6\x3d\xd4\x48"
1396 "\xdf\x76\x0d\x81\x18\xaf\x23\xba"
1397 "\x51\xe8\x5c\xf3\x8a\x21\x95\x2c"
1398 "\xc3\x37\xce\x65\xfc\x70\x07\x9e"
1399 "\x12\xa9\x40\xd7\x4b\xe2\x79\x10"
1400 "\x84\x1b\xb2\x26\xbd\x54\xeb\x5f"
1401 "\xf6\x8d\x01\x98\x2f\xc6\x3a\xd1"
1402 "\x68\xff\x73\x0a\xa1\x15\xac\x43"
1403 "\xda\x4e\xe5\x7c\x13\x87\x1e\xb5"
1404 "\x29\xc0\x57\xee\x62\xf9\x90\x04"
1405 "\x9b\x32\xc9\x3d\xd4\x6b\x02\x76"
1406 "\x0d\xa4\x18\xaf\x46\xdd\x51\xe8"
1407 "\x7f\x16\x8a\x21\xb8\x2c\xc3\x5a"
1408 "\xf1\x65\xfc\x93\x07\x9e\x35\xcc"
1409 "\x40\xd7\x6e\x05\x79\x10\xa7\x1b"
1410 "\xb2\x49\xe0\x54\xeb\x82\x19\x8d"
1411 "\x24\xbb\x2f\xc6\x5d\xf4\x68\xff"
1412 "\x96\x0a\xa1\x38\xcf\x43\xda\x71"
1413 "\x08\x7c\x13\xaa\x1e\xb5\x4c",
1414 .psize = 1023,
1415 .digest = "\x76\xc9\xd4\x91\x7a\x5f\x0f\xaa"
1416 "\x13\x39\xf3\x01\x7a\xfa\xe5\x41"
1417 "\x5f\x0b\xf8\xeb\x32\xfc\xbf\xb0"
1418 "\xfa\x8c\xcd\x17\x83\xe2\xfa\xeb"
1419 "\x1c\x19\xde\xe2\x75\xdc\x34\x64"
1420 "\x5f\x35\x9c\x61\x2f\x10\xf9\xec"
1421 "\x59\xca\x9d\xcc\x25\x0c\x43\xba"
1422 "\x85\xa8\xf8\xfe\xb5\x24\xb2\xee",
1423 }
691}; 1424};
692 1425
693 1426
@@ -12823,11 +13556,11 @@ static struct cipher_testvec cast6_xts_dec_tv_template[] = {
12823#define AES_CBC_DEC_TEST_VECTORS 5 13556#define AES_CBC_DEC_TEST_VECTORS 5
12824#define HMAC_MD5_ECB_CIPHER_NULL_ENC_TEST_VECTORS 2 13557#define HMAC_MD5_ECB_CIPHER_NULL_ENC_TEST_VECTORS 2
12825#define HMAC_MD5_ECB_CIPHER_NULL_DEC_TEST_VECTORS 2 13558#define HMAC_MD5_ECB_CIPHER_NULL_DEC_TEST_VECTORS 2
12826#define HMAC_SHA1_ECB_CIPHER_NULL_ENC_TEST_VECTORS 2 13559#define HMAC_SHA1_ECB_CIPHER_NULL_ENC_TEST_VEC 2
12827#define HMAC_SHA1_ECB_CIPHER_NULL_DEC_TEST_VECTORS 2 13560#define HMAC_SHA1_ECB_CIPHER_NULL_DEC_TEST_VEC 2
12828#define HMAC_SHA1_AES_CBC_ENC_TEST_VECTORS 7 13561#define HMAC_SHA1_AES_CBC_ENC_TEST_VEC 7
12829#define HMAC_SHA256_AES_CBC_ENC_TEST_VECTORS 7 13562#define HMAC_SHA256_AES_CBC_ENC_TEST_VEC 7
12830#define HMAC_SHA512_AES_CBC_ENC_TEST_VECTORS 7 13563#define HMAC_SHA512_AES_CBC_ENC_TEST_VEC 7
12831#define AES_LRW_ENC_TEST_VECTORS 8 13564#define AES_LRW_ENC_TEST_VECTORS 8
12832#define AES_LRW_DEC_TEST_VECTORS 8 13565#define AES_LRW_DEC_TEST_VECTORS 8
12833#define AES_XTS_ENC_TEST_VECTORS 5 13566#define AES_XTS_ENC_TEST_VECTORS 5
@@ -12844,7 +13577,7 @@ static struct cipher_testvec cast6_xts_dec_tv_template[] = {
12844#define AES_GCM_4106_DEC_TEST_VECTORS 7 13577#define AES_GCM_4106_DEC_TEST_VECTORS 7
12845#define AES_GCM_4543_ENC_TEST_VECTORS 1 13578#define AES_GCM_4543_ENC_TEST_VECTORS 1
12846#define AES_GCM_4543_DEC_TEST_VECTORS 2 13579#define AES_GCM_4543_DEC_TEST_VECTORS 2
12847#define AES_CCM_ENC_TEST_VECTORS 7 13580#define AES_CCM_ENC_TEST_VECTORS 8
12848#define AES_CCM_DEC_TEST_VECTORS 7 13581#define AES_CCM_DEC_TEST_VECTORS 7
12849#define AES_CCM_4309_ENC_TEST_VECTORS 7 13582#define AES_CCM_4309_ENC_TEST_VECTORS 7
12850#define AES_CCM_4309_DEC_TEST_VECTORS 10 13583#define AES_CCM_4309_DEC_TEST_VECTORS 10
@@ -13715,7 +14448,7 @@ static struct aead_testvec hmac_md5_ecb_cipher_null_dec_tv_template[] = {
13715 }, 14448 },
13716}; 14449};
13717 14450
13718static struct aead_testvec hmac_sha1_aes_cbc_enc_tv_template[] = { 14451static struct aead_testvec hmac_sha1_aes_cbc_enc_tv_temp[] = {
13719 { /* RFC 3602 Case 1 */ 14452 { /* RFC 3602 Case 1 */
13720#ifdef __LITTLE_ENDIAN 14453#ifdef __LITTLE_ENDIAN
13721 .key = "\x08\x00" /* rta length */ 14454 .key = "\x08\x00" /* rta length */
@@ -13964,7 +14697,7 @@ static struct aead_testvec hmac_sha1_aes_cbc_enc_tv_template[] = {
13964 }, 14697 },
13965}; 14698};
13966 14699
13967static struct aead_testvec hmac_sha1_ecb_cipher_null_enc_tv_template[] = { 14700static struct aead_testvec hmac_sha1_ecb_cipher_null_enc_tv_temp[] = {
13968 { /* Input data from RFC 2410 Case 1 */ 14701 { /* Input data from RFC 2410 Case 1 */
13969#ifdef __LITTLE_ENDIAN 14702#ifdef __LITTLE_ENDIAN
13970 .key = "\x08\x00" /* rta length */ 14703 .key = "\x08\x00" /* rta length */
@@ -14010,7 +14743,7 @@ static struct aead_testvec hmac_sha1_ecb_cipher_null_enc_tv_template[] = {
14010 }, 14743 },
14011}; 14744};
14012 14745
14013static struct aead_testvec hmac_sha1_ecb_cipher_null_dec_tv_template[] = { 14746static struct aead_testvec hmac_sha1_ecb_cipher_null_dec_tv_temp[] = {
14014 { 14747 {
14015#ifdef __LITTLE_ENDIAN 14748#ifdef __LITTLE_ENDIAN
14016 .key = "\x08\x00" /* rta length */ 14749 .key = "\x08\x00" /* rta length */
@@ -14056,7 +14789,7 @@ static struct aead_testvec hmac_sha1_ecb_cipher_null_dec_tv_template[] = {
14056 }, 14789 },
14057}; 14790};
14058 14791
14059static struct aead_testvec hmac_sha256_aes_cbc_enc_tv_template[] = { 14792static struct aead_testvec hmac_sha256_aes_cbc_enc_tv_temp[] = {
14060 { /* RFC 3602 Case 1 */ 14793 { /* RFC 3602 Case 1 */
14061#ifdef __LITTLE_ENDIAN 14794#ifdef __LITTLE_ENDIAN
14062 .key = "\x08\x00" /* rta length */ 14795 .key = "\x08\x00" /* rta length */
@@ -14319,7 +15052,7 @@ static struct aead_testvec hmac_sha256_aes_cbc_enc_tv_template[] = {
14319 }, 15052 },
14320}; 15053};
14321 15054
14322static struct aead_testvec hmac_sha512_aes_cbc_enc_tv_template[] = { 15055static struct aead_testvec hmac_sha512_aes_cbc_enc_tv_temp[] = {
14323 { /* RFC 3602 Case 1 */ 15056 { /* RFC 3602 Case 1 */
14324#ifdef __LITTLE_ENDIAN 15057#ifdef __LITTLE_ENDIAN
14325 .key = "\x08\x00" /* rta length */ 15058 .key = "\x08\x00" /* rta length */
@@ -14638,6 +15371,652 @@ static struct aead_testvec hmac_sha512_aes_cbc_enc_tv_template[] = {
14638 }, 15371 },
14639}; 15372};
14640 15373
15374#define HMAC_SHA1_DES_CBC_ENC_TEST_VEC 1
15375
15376static struct aead_testvec hmac_sha1_des_cbc_enc_tv_temp[] = {
15377 { /*Generated with cryptopp*/
15378#ifdef __LITTLE_ENDIAN
15379 .key = "\x08\x00" /* rta length */
15380 "\x01\x00" /* rta type */
15381#else
15382 .key = "\x00\x08" /* rta length */
15383 "\x00\x01" /* rta type */
15384#endif
15385 "\x00\x00\x00\x08" /* enc key length */
15386 "\x11\x22\x33\x44\x55\x66\x77\x88"
15387 "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
15388 "\x22\x33\x44\x55"
15389 "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24",
15390 .klen = 8 + 20 + 8,
15391 .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
15392 .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
15393 .alen = 8,
15394 .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
15395 "\x53\x20\x63\x65\x65\x72\x73\x74"
15396 "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
15397 "\x20\x79\x65\x53\x72\x63\x74\x65"
15398 "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
15399 "\x79\x6e\x53\x20\x63\x65\x65\x72"
15400 "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
15401 "\x6e\x61\x20\x79\x65\x53\x72\x63"
15402 "\x74\x65\x20\x73\x6f\x54\x20\x6f"
15403 "\x61\x4d\x79\x6e\x53\x20\x63\x65"
15404 "\x65\x72\x73\x74\x54\x20\x6f\x6f"
15405 "\x4d\x20\x6e\x61\x20\x79\x65\x53"
15406 "\x72\x63\x74\x65\x20\x73\x6f\x54"
15407 "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
15408 "\x63\x65\x65\x72\x73\x74\x54\x20"
15409 "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
15410 .ilen = 128,
15411 .result = "\x70\xd6\xde\x64\x87\x17\xf1\xe8"
15412 "\x54\x31\x85\x37\xed\x6b\x01\x8d"
15413 "\xe3\xcc\xe0\x1d\x5e\xf3\xfe\xf1"
15414 "\x41\xaa\x33\x91\xa7\x7d\x99\x88"
15415 "\x4d\x85\x6e\x2f\xa3\x69\xf5\x82"
15416 "\x3a\x6f\x25\xcb\x7d\x58\x1f\x9b"
15417 "\xaa\x9c\x11\xd5\x76\x67\xce\xde"
15418 "\x56\xd7\x5a\x80\x69\xea\x3a\x02"
15419 "\xf0\xc7\x7c\xe3\xcb\x40\xe5\x52"
15420 "\xd1\x10\x92\x78\x0b\x8e\x5b\xf1"
15421 "\xe3\x26\x1f\xe1\x15\x41\xc7\xba"
15422 "\x99\xdb\x08\x51\x1c\xd3\x01\xf4"
15423 "\x87\x47\x39\xb8\xd2\xdd\xbd\xfb"
15424 "\x66\x13\xdf\x1c\x01\x44\xf0\x7a"
15425 "\x1a\x6b\x13\xf5\xd5\x0b\xb8\xba"
15426 "\x53\xba\xe1\x76\xe3\x82\x07\x86"
15427 "\x95\x16\x20\x09\xf5\x95\x19\xfd"
15428 "\x3c\xc7\xe0\x42\xc0\x14\x69\xfa"
15429 "\x5c\x44\xa9\x37",
15430 .rlen = 128 + 20,
15431 },
15432};
15433
15434#define HMAC_SHA224_DES_CBC_ENC_TEST_VEC 1
15435
15436static struct aead_testvec hmac_sha224_des_cbc_enc_tv_temp[] = {
15437 { /*Generated with cryptopp*/
15438#ifdef __LITTLE_ENDIAN
15439 .key = "\x08\x00" /* rta length */
15440 "\x01\x00" /* rta type */
15441#else
15442 .key = "\x00\x08" /* rta length */
15443 "\x00\x01" /* rta type */
15444#endif
15445 "\x00\x00\x00\x08" /* enc key length */
15446 "\x11\x22\x33\x44\x55\x66\x77\x88"
15447 "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
15448 "\x22\x33\x44\x55\x66\x77\x88\x99"
15449 "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24",
15450 .klen = 8 + 24 + 8,
15451 .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
15452 .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
15453 .alen = 8,
15454 .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
15455 "\x53\x20\x63\x65\x65\x72\x73\x74"
15456 "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
15457 "\x20\x79\x65\x53\x72\x63\x74\x65"
15458 "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
15459 "\x79\x6e\x53\x20\x63\x65\x65\x72"
15460 "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
15461 "\x6e\x61\x20\x79\x65\x53\x72\x63"
15462 "\x74\x65\x20\x73\x6f\x54\x20\x6f"
15463 "\x61\x4d\x79\x6e\x53\x20\x63\x65"
15464 "\x65\x72\x73\x74\x54\x20\x6f\x6f"
15465 "\x4d\x20\x6e\x61\x20\x79\x65\x53"
15466 "\x72\x63\x74\x65\x20\x73\x6f\x54"
15467 "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
15468 "\x63\x65\x65\x72\x73\x74\x54\x20"
15469 "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
15470 .ilen = 128,
15471 .result = "\x70\xd6\xde\x64\x87\x17\xf1\xe8"
15472 "\x54\x31\x85\x37\xed\x6b\x01\x8d"
15473 "\xe3\xcc\xe0\x1d\x5e\xf3\xfe\xf1"
15474 "\x41\xaa\x33\x91\xa7\x7d\x99\x88"
15475 "\x4d\x85\x6e\x2f\xa3\x69\xf5\x82"
15476 "\x3a\x6f\x25\xcb\x7d\x58\x1f\x9b"
15477 "\xaa\x9c\x11\xd5\x76\x67\xce\xde"
15478 "\x56\xd7\x5a\x80\x69\xea\x3a\x02"
15479 "\xf0\xc7\x7c\xe3\xcb\x40\xe5\x52"
15480 "\xd1\x10\x92\x78\x0b\x8e\x5b\xf1"
15481 "\xe3\x26\x1f\xe1\x15\x41\xc7\xba"
15482 "\x99\xdb\x08\x51\x1c\xd3\x01\xf4"
15483 "\x87\x47\x39\xb8\xd2\xdd\xbd\xfb"
15484 "\x66\x13\xdf\x1c\x01\x44\xf0\x7a"
15485 "\x1a\x6b\x13\xf5\xd5\x0b\xb8\xba"
15486 "\x53\xba\xe1\x76\xe3\x82\x07\x86"
15487 "\x9c\x2d\x7e\xee\x20\x34\x55\x0a"
15488 "\xce\xb5\x4e\x64\x53\xe7\xbf\x91"
15489 "\xab\xd4\xd9\xda\xc9\x12\xae\xf7",
15490 .rlen = 128 + 24,
15491 },
15492};
15493
15494#define HMAC_SHA256_DES_CBC_ENC_TEST_VEC 1
15495
15496static struct aead_testvec hmac_sha256_des_cbc_enc_tv_temp[] = {
15497 { /*Generated with cryptopp*/
15498#ifdef __LITTLE_ENDIAN
15499 .key = "\x08\x00" /* rta length */
15500 "\x01\x00" /* rta type */
15501#else
15502 .key = "\x00\x08" /* rta length */
15503 "\x00\x01" /* rta type */
15504#endif
15505 "\x00\x00\x00\x08" /* enc key length */
15506 "\x11\x22\x33\x44\x55\x66\x77\x88"
15507 "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
15508 "\x22\x33\x44\x55\x66\x77\x88\x99"
15509 "\xaa\xbb\xcc\xdd\xee\xff\x11\x22"
15510 "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24",
15511 .klen = 8 + 32 + 8,
15512 .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
15513 .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
15514 .alen = 8,
15515 .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
15516 "\x53\x20\x63\x65\x65\x72\x73\x74"
15517 "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
15518 "\x20\x79\x65\x53\x72\x63\x74\x65"
15519 "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
15520 "\x79\x6e\x53\x20\x63\x65\x65\x72"
15521 "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
15522 "\x6e\x61\x20\x79\x65\x53\x72\x63"
15523 "\x74\x65\x20\x73\x6f\x54\x20\x6f"
15524 "\x61\x4d\x79\x6e\x53\x20\x63\x65"
15525 "\x65\x72\x73\x74\x54\x20\x6f\x6f"
15526 "\x4d\x20\x6e\x61\x20\x79\x65\x53"
15527 "\x72\x63\x74\x65\x20\x73\x6f\x54"
15528 "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
15529 "\x63\x65\x65\x72\x73\x74\x54\x20"
15530 "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
15531 .ilen = 128,
15532 .result = "\x70\xd6\xde\x64\x87\x17\xf1\xe8"
15533 "\x54\x31\x85\x37\xed\x6b\x01\x8d"
15534 "\xe3\xcc\xe0\x1d\x5e\xf3\xfe\xf1"
15535 "\x41\xaa\x33\x91\xa7\x7d\x99\x88"
15536 "\x4d\x85\x6e\x2f\xa3\x69\xf5\x82"
15537 "\x3a\x6f\x25\xcb\x7d\x58\x1f\x9b"
15538 "\xaa\x9c\x11\xd5\x76\x67\xce\xde"
15539 "\x56\xd7\x5a\x80\x69\xea\x3a\x02"
15540 "\xf0\xc7\x7c\xe3\xcb\x40\xe5\x52"
15541 "\xd1\x10\x92\x78\x0b\x8e\x5b\xf1"
15542 "\xe3\x26\x1f\xe1\x15\x41\xc7\xba"
15543 "\x99\xdb\x08\x51\x1c\xd3\x01\xf4"
15544 "\x87\x47\x39\xb8\xd2\xdd\xbd\xfb"
15545 "\x66\x13\xdf\x1c\x01\x44\xf0\x7a"
15546 "\x1a\x6b\x13\xf5\xd5\x0b\xb8\xba"
15547 "\x53\xba\xe1\x76\xe3\x82\x07\x86"
15548 "\xc6\x58\xa1\x60\x70\x91\x39\x36"
15549 "\x50\xf6\x5d\xab\x4b\x51\x4e\x5e"
15550 "\xde\x63\xde\x76\x52\xde\x9f\xba"
15551 "\x90\xcf\x15\xf2\xbb\x6e\x84\x00",
15552 .rlen = 128 + 32,
15553 },
15554};
15555
15556#define HMAC_SHA384_DES_CBC_ENC_TEST_VEC 1
15557
15558static struct aead_testvec hmac_sha384_des_cbc_enc_tv_temp[] = {
15559 { /*Generated with cryptopp*/
15560#ifdef __LITTLE_ENDIAN
15561 .key = "\x08\x00" /* rta length */
15562 "\x01\x00" /* rta type */
15563#else
15564 .key = "\x00\x08" /* rta length */
15565 "\x00\x01" /* rta type */
15566#endif
15567 "\x00\x00\x00\x08" /* enc key length */
15568 "\x11\x22\x33\x44\x55\x66\x77\x88"
15569 "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
15570 "\x22\x33\x44\x55\x66\x77\x88\x99"
15571 "\xaa\xbb\xcc\xdd\xee\xff\x11\x22"
15572 "\x33\x44\x55\x66\x77\x88\x99\xaa"
15573 "\xbb\xcc\xdd\xee\xff\x11\x22\x33"
15574 "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24",
15575 .klen = 8 + 48 + 8,
15576 .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
15577 .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
15578 .alen = 8,
15579 .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
15580 "\x53\x20\x63\x65\x65\x72\x73\x74"
15581 "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
15582 "\x20\x79\x65\x53\x72\x63\x74\x65"
15583 "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
15584 "\x79\x6e\x53\x20\x63\x65\x65\x72"
15585 "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
15586 "\x6e\x61\x20\x79\x65\x53\x72\x63"
15587 "\x74\x65\x20\x73\x6f\x54\x20\x6f"
15588 "\x61\x4d\x79\x6e\x53\x20\x63\x65"
15589 "\x65\x72\x73\x74\x54\x20\x6f\x6f"
15590 "\x4d\x20\x6e\x61\x20\x79\x65\x53"
15591 "\x72\x63\x74\x65\x20\x73\x6f\x54"
15592 "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
15593 "\x63\x65\x65\x72\x73\x74\x54\x20"
15594 "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
15595 .ilen = 128,
15596 .result = "\x70\xd6\xde\x64\x87\x17\xf1\xe8"
15597 "\x54\x31\x85\x37\xed\x6b\x01\x8d"
15598 "\xe3\xcc\xe0\x1d\x5e\xf3\xfe\xf1"
15599 "\x41\xaa\x33\x91\xa7\x7d\x99\x88"
15600 "\x4d\x85\x6e\x2f\xa3\x69\xf5\x82"
15601 "\x3a\x6f\x25\xcb\x7d\x58\x1f\x9b"
15602 "\xaa\x9c\x11\xd5\x76\x67\xce\xde"
15603 "\x56\xd7\x5a\x80\x69\xea\x3a\x02"
15604 "\xf0\xc7\x7c\xe3\xcb\x40\xe5\x52"
15605 "\xd1\x10\x92\x78\x0b\x8e\x5b\xf1"
15606 "\xe3\x26\x1f\xe1\x15\x41\xc7\xba"
15607 "\x99\xdb\x08\x51\x1c\xd3\x01\xf4"
15608 "\x87\x47\x39\xb8\xd2\xdd\xbd\xfb"
15609 "\x66\x13\xdf\x1c\x01\x44\xf0\x7a"
15610 "\x1a\x6b\x13\xf5\xd5\x0b\xb8\xba"
15611 "\x53\xba\xe1\x76\xe3\x82\x07\x86"
15612 "\xa8\x8e\x9c\x74\x8c\x2b\x99\xa0"
15613 "\xc8\x8c\xef\x25\x07\x83\x11\x3a"
15614 "\x31\x8d\xbe\x3b\x6a\xd7\x96\xfe"
15615 "\x5e\x67\xb5\x74\xe7\xe7\x85\x61"
15616 "\x6a\x95\x26\x75\xcc\x53\x89\xf3"
15617 "\x74\xc9\x2a\x76\x20\xa2\x64\x62",
15618 .rlen = 128 + 48,
15619 },
15620};
15621
15622#define HMAC_SHA512_DES_CBC_ENC_TEST_VEC 1
15623
15624static struct aead_testvec hmac_sha512_des_cbc_enc_tv_temp[] = {
15625 { /*Generated with cryptopp*/
15626#ifdef __LITTLE_ENDIAN
15627 .key = "\x08\x00" /* rta length */
15628 "\x01\x00" /* rta type */
15629#else
15630 .key = "\x00\x08" /* rta length */
15631 "\x00\x01" /* rta type */
15632#endif
15633 "\x00\x00\x00\x08" /* enc key length */
15634 "\x11\x22\x33\x44\x55\x66\x77\x88"
15635 "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
15636 "\x22\x33\x44\x55\x66\x77\x88\x99"
15637 "\xaa\xbb\xcc\xdd\xee\xff\x11\x22"
15638 "\x33\x44\x55\x66\x77\x88\x99\xaa"
15639 "\xbb\xcc\xdd\xee\xff\x11\x22\x33"
15640 "\x44\x55\x66\x77\x88\x99\xaa\xbb"
15641 "\xcc\xdd\xee\xff\x11\x22\x33\x44"
15642 "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24",
15643 .klen = 8 + 64 + 8,
15644 .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
15645 .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
15646 .alen = 8,
15647 .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
15648 "\x53\x20\x63\x65\x65\x72\x73\x74"
15649 "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
15650 "\x20\x79\x65\x53\x72\x63\x74\x65"
15651 "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
15652 "\x79\x6e\x53\x20\x63\x65\x65\x72"
15653 "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
15654 "\x6e\x61\x20\x79\x65\x53\x72\x63"
15655 "\x74\x65\x20\x73\x6f\x54\x20\x6f"
15656 "\x61\x4d\x79\x6e\x53\x20\x63\x65"
15657 "\x65\x72\x73\x74\x54\x20\x6f\x6f"
15658 "\x4d\x20\x6e\x61\x20\x79\x65\x53"
15659 "\x72\x63\x74\x65\x20\x73\x6f\x54"
15660 "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
15661 "\x63\x65\x65\x72\x73\x74\x54\x20"
15662 "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
15663 .ilen = 128,
15664 .result = "\x70\xd6\xde\x64\x87\x17\xf1\xe8"
15665 "\x54\x31\x85\x37\xed\x6b\x01\x8d"
15666 "\xe3\xcc\xe0\x1d\x5e\xf3\xfe\xf1"
15667 "\x41\xaa\x33\x91\xa7\x7d\x99\x88"
15668 "\x4d\x85\x6e\x2f\xa3\x69\xf5\x82"
15669 "\x3a\x6f\x25\xcb\x7d\x58\x1f\x9b"
15670 "\xaa\x9c\x11\xd5\x76\x67\xce\xde"
15671 "\x56\xd7\x5a\x80\x69\xea\x3a\x02"
15672 "\xf0\xc7\x7c\xe3\xcb\x40\xe5\x52"
15673 "\xd1\x10\x92\x78\x0b\x8e\x5b\xf1"
15674 "\xe3\x26\x1f\xe1\x15\x41\xc7\xba"
15675 "\x99\xdb\x08\x51\x1c\xd3\x01\xf4"
15676 "\x87\x47\x39\xb8\xd2\xdd\xbd\xfb"
15677 "\x66\x13\xdf\x1c\x01\x44\xf0\x7a"
15678 "\x1a\x6b\x13\xf5\xd5\x0b\xb8\xba"
15679 "\x53\xba\xe1\x76\xe3\x82\x07\x86"
15680 "\xc6\x2c\x73\x88\xb0\x9d\x5f\x3e"
15681 "\x5b\x78\xca\x0e\xab\x8a\xa3\xbb"
15682 "\xd9\x1d\xc3\xe3\x05\xac\x76\xfb"
15683 "\x58\x83\xda\x67\xfb\x21\x24\xa2"
15684 "\xb1\xa7\xd7\x66\xa6\x8d\xa6\x93"
15685 "\x97\xe2\xe3\xb8\xaa\x48\x85\xee"
15686 "\x8c\xf6\x07\x95\x1f\xa6\x6c\x96"
15687 "\x99\xc7\x5c\x8d\xd8\xb5\x68\x7b",
15688 .rlen = 128 + 64,
15689 },
15690};
15691
15692#define HMAC_SHA1_DES3_EDE_CBC_ENC_TEST_VEC 1
15693
15694static struct aead_testvec hmac_sha1_des3_ede_cbc_enc_tv_temp[] = {
15695 { /*Generated with cryptopp*/
15696#ifdef __LITTLE_ENDIAN
15697 .key = "\x08\x00" /* rta length */
15698 "\x01\x00" /* rta type */
15699#else
15700 .key = "\x00\x08" /* rta length */
15701 "\x00\x01" /* rta type */
15702#endif
15703 "\x00\x00\x00\x18" /* enc key length */
15704 "\x11\x22\x33\x44\x55\x66\x77\x88"
15705 "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
15706 "\x22\x33\x44\x55"
15707 "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24"
15708 "\x44\x4D\x99\x5A\x12\xD6\x40\xC0"
15709 "\xEA\xC2\x84\xE8\x14\x95\xDB\xE8",
15710 .klen = 8 + 20 + 24,
15711 .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
15712 .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
15713 .alen = 8,
15714 .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
15715 "\x53\x20\x63\x65\x65\x72\x73\x74"
15716 "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
15717 "\x20\x79\x65\x53\x72\x63\x74\x65"
15718 "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
15719 "\x79\x6e\x53\x20\x63\x65\x65\x72"
15720 "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
15721 "\x6e\x61\x20\x79\x65\x53\x72\x63"
15722 "\x74\x65\x20\x73\x6f\x54\x20\x6f"
15723 "\x61\x4d\x79\x6e\x53\x20\x63\x65"
15724 "\x65\x72\x73\x74\x54\x20\x6f\x6f"
15725 "\x4d\x20\x6e\x61\x20\x79\x65\x53"
15726 "\x72\x63\x74\x65\x20\x73\x6f\x54"
15727 "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
15728 "\x63\x65\x65\x72\x73\x74\x54\x20"
15729 "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
15730 .ilen = 128,
15731 .result = "\x0e\x2d\xb6\x97\x3c\x56\x33\xf4"
15732 "\x67\x17\x21\xc7\x6e\x8a\xd5\x49"
15733 "\x74\xb3\x49\x05\xc5\x1c\xd0\xed"
15734 "\x12\x56\x5c\x53\x96\xb6\x00\x7d"
15735 "\x90\x48\xfc\xf5\x8d\x29\x39\xcc"
15736 "\x8a\xd5\x35\x18\x36\x23\x4e\xd7"
15737 "\x76\xd1\xda\x0c\x94\x67\xbb\x04"
15738 "\x8b\xf2\x03\x6c\xa8\xcf\xb6\xea"
15739 "\x22\x64\x47\xaa\x8f\x75\x13\xbf"
15740 "\x9f\xc2\xc3\xf0\xc9\x56\xc5\x7a"
15741 "\x71\x63\x2e\x89\x7b\x1e\x12\xca"
15742 "\xe2\x5f\xaf\xd8\xa4\xf8\xc9\x7a"
15743 "\xd6\xf9\x21\x31\x62\x44\x45\xa6"
15744 "\xd6\xbc\x5a\xd3\x2d\x54\x43\xcc"
15745 "\x9d\xde\xa5\x70\xe9\x42\x45\x8a"
15746 "\x6b\xfa\xb1\x91\x13\xb0\xd9\x19"
15747 "\x67\x6d\xb1\xf5\xb8\x10\xdc\xc6"
15748 "\x75\x86\x96\x6b\xb1\xc5\xe4\xcf"
15749 "\xd1\x60\x91\xb3",
15750 .rlen = 128 + 20,
15751 },
15752};
15753
15754#define HMAC_SHA224_DES3_EDE_CBC_ENC_TEST_VEC 1
15755
15756static struct aead_testvec hmac_sha224_des3_ede_cbc_enc_tv_temp[] = {
15757 { /*Generated with cryptopp*/
15758#ifdef __LITTLE_ENDIAN
15759 .key = "\x08\x00" /* rta length */
15760 "\x01\x00" /* rta type */
15761#else
15762 .key = "\x00\x08" /* rta length */
15763 "\x00\x01" /* rta type */
15764#endif
15765 "\x00\x00\x00\x18" /* enc key length */
15766 "\x11\x22\x33\x44\x55\x66\x77\x88"
15767 "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
15768 "\x22\x33\x44\x55\x66\x77\x88\x99"
15769 "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24"
15770 "\x44\x4D\x99\x5A\x12\xD6\x40\xC0"
15771 "\xEA\xC2\x84\xE8\x14\x95\xDB\xE8",
15772 .klen = 8 + 24 + 24,
15773 .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
15774 .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
15775 .alen = 8,
15776 .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
15777 "\x53\x20\x63\x65\x65\x72\x73\x74"
15778 "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
15779 "\x20\x79\x65\x53\x72\x63\x74\x65"
15780 "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
15781 "\x79\x6e\x53\x20\x63\x65\x65\x72"
15782 "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
15783 "\x6e\x61\x20\x79\x65\x53\x72\x63"
15784 "\x74\x65\x20\x73\x6f\x54\x20\x6f"
15785 "\x61\x4d\x79\x6e\x53\x20\x63\x65"
15786 "\x65\x72\x73\x74\x54\x20\x6f\x6f"
15787 "\x4d\x20\x6e\x61\x20\x79\x65\x53"
15788 "\x72\x63\x74\x65\x20\x73\x6f\x54"
15789 "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
15790 "\x63\x65\x65\x72\x73\x74\x54\x20"
15791 "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
15792 .ilen = 128,
15793 .result = "\x0e\x2d\xb6\x97\x3c\x56\x33\xf4"
15794 "\x67\x17\x21\xc7\x6e\x8a\xd5\x49"
15795 "\x74\xb3\x49\x05\xc5\x1c\xd0\xed"
15796 "\x12\x56\x5c\x53\x96\xb6\x00\x7d"
15797 "\x90\x48\xfc\xf5\x8d\x29\x39\xcc"
15798 "\x8a\xd5\x35\x18\x36\x23\x4e\xd7"
15799 "\x76\xd1\xda\x0c\x94\x67\xbb\x04"
15800 "\x8b\xf2\x03\x6c\xa8\xcf\xb6\xea"
15801 "\x22\x64\x47\xaa\x8f\x75\x13\xbf"
15802 "\x9f\xc2\xc3\xf0\xc9\x56\xc5\x7a"
15803 "\x71\x63\x2e\x89\x7b\x1e\x12\xca"
15804 "\xe2\x5f\xaf\xd8\xa4\xf8\xc9\x7a"
15805 "\xd6\xf9\x21\x31\x62\x44\x45\xa6"
15806 "\xd6\xbc\x5a\xd3\x2d\x54\x43\xcc"
15807 "\x9d\xde\xa5\x70\xe9\x42\x45\x8a"
15808 "\x6b\xfa\xb1\x91\x13\xb0\xd9\x19"
15809 "\x15\x24\x7f\x5a\x45\x4a\x66\xce"
15810 "\x2b\x0b\x93\x99\x2f\x9d\x0c\x6c"
15811 "\x56\x1f\xe1\xa6\x41\xb2\x4c\xd0",
15812 .rlen = 128 + 24,
15813 },
15814};
15815
15816#define HMAC_SHA256_DES3_EDE_CBC_ENC_TEST_VEC 1
15817
15818static struct aead_testvec hmac_sha256_des3_ede_cbc_enc_tv_temp[] = {
15819 { /*Generated with cryptopp*/
15820#ifdef __LITTLE_ENDIAN
15821 .key = "\x08\x00" /* rta length */
15822 "\x01\x00" /* rta type */
15823#else
15824 .key = "\x00\x08" /* rta length */
15825 "\x00\x01" /* rta type */
15826#endif
15827 "\x00\x00\x00\x18" /* enc key length */
15828 "\x11\x22\x33\x44\x55\x66\x77\x88"
15829 "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
15830 "\x22\x33\x44\x55\x66\x77\x88\x99"
15831 "\xaa\xbb\xcc\xdd\xee\xff\x11\x22"
15832 "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24"
15833 "\x44\x4D\x99\x5A\x12\xD6\x40\xC0"
15834 "\xEA\xC2\x84\xE8\x14\x95\xDB\xE8",
15835 .klen = 8 + 32 + 24,
15836 .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
15837 .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
15838 .alen = 8,
15839 .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
15840 "\x53\x20\x63\x65\x65\x72\x73\x74"
15841 "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
15842 "\x20\x79\x65\x53\x72\x63\x74\x65"
15843 "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
15844 "\x79\x6e\x53\x20\x63\x65\x65\x72"
15845 "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
15846 "\x6e\x61\x20\x79\x65\x53\x72\x63"
15847 "\x74\x65\x20\x73\x6f\x54\x20\x6f"
15848 "\x61\x4d\x79\x6e\x53\x20\x63\x65"
15849 "\x65\x72\x73\x74\x54\x20\x6f\x6f"
15850 "\x4d\x20\x6e\x61\x20\x79\x65\x53"
15851 "\x72\x63\x74\x65\x20\x73\x6f\x54"
15852 "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
15853 "\x63\x65\x65\x72\x73\x74\x54\x20"
15854 "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
15855 .ilen = 128,
15856 .result = "\x0e\x2d\xb6\x97\x3c\x56\x33\xf4"
15857 "\x67\x17\x21\xc7\x6e\x8a\xd5\x49"
15858 "\x74\xb3\x49\x05\xc5\x1c\xd0\xed"
15859 "\x12\x56\x5c\x53\x96\xb6\x00\x7d"
15860 "\x90\x48\xfc\xf5\x8d\x29\x39\xcc"
15861 "\x8a\xd5\x35\x18\x36\x23\x4e\xd7"
15862 "\x76\xd1\xda\x0c\x94\x67\xbb\x04"
15863 "\x8b\xf2\x03\x6c\xa8\xcf\xb6\xea"
15864 "\x22\x64\x47\xaa\x8f\x75\x13\xbf"
15865 "\x9f\xc2\xc3\xf0\xc9\x56\xc5\x7a"
15866 "\x71\x63\x2e\x89\x7b\x1e\x12\xca"
15867 "\xe2\x5f\xaf\xd8\xa4\xf8\xc9\x7a"
15868 "\xd6\xf9\x21\x31\x62\x44\x45\xa6"
15869 "\xd6\xbc\x5a\xd3\x2d\x54\x43\xcc"
15870 "\x9d\xde\xa5\x70\xe9\x42\x45\x8a"
15871 "\x6b\xfa\xb1\x91\x13\xb0\xd9\x19"
15872 "\x73\xb0\xea\x9f\xe8\x18\x80\xd6"
15873 "\x56\x38\x44\xc0\xdb\xe3\x4f\x71"
15874 "\xf7\xce\xd1\xd3\xf8\xbd\x3e\x4f"
15875 "\xca\x43\x95\xdf\x80\x61\x81\xa9",
15876 .rlen = 128 + 32,
15877 },
15878};
15879
15880#define HMAC_SHA384_DES3_EDE_CBC_ENC_TEST_VEC 1
15881
15882static struct aead_testvec hmac_sha384_des3_ede_cbc_enc_tv_temp[] = {
15883 { /*Generated with cryptopp*/
15884#ifdef __LITTLE_ENDIAN
15885 .key = "\x08\x00" /* rta length */
15886 "\x01\x00" /* rta type */
15887#else
15888 .key = "\x00\x08" /* rta length */
15889 "\x00\x01" /* rta type */
15890#endif
15891 "\x00\x00\x00\x18" /* enc key length */
15892 "\x11\x22\x33\x44\x55\x66\x77\x88"
15893 "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
15894 "\x22\x33\x44\x55\x66\x77\x88\x99"
15895 "\xaa\xbb\xcc\xdd\xee\xff\x11\x22"
15896 "\x33\x44\x55\x66\x77\x88\x99\xaa"
15897 "\xbb\xcc\xdd\xee\xff\x11\x22\x33"
15898 "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24"
15899 "\x44\x4D\x99\x5A\x12\xD6\x40\xC0"
15900 "\xEA\xC2\x84\xE8\x14\x95\xDB\xE8",
15901 .klen = 8 + 48 + 24,
15902 .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
15903 .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
15904 .alen = 8,
15905 .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
15906 "\x53\x20\x63\x65\x65\x72\x73\x74"
15907 "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
15908 "\x20\x79\x65\x53\x72\x63\x74\x65"
15909 "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
15910 "\x79\x6e\x53\x20\x63\x65\x65\x72"
15911 "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
15912 "\x6e\x61\x20\x79\x65\x53\x72\x63"
15913 "\x74\x65\x20\x73\x6f\x54\x20\x6f"
15914 "\x61\x4d\x79\x6e\x53\x20\x63\x65"
15915 "\x65\x72\x73\x74\x54\x20\x6f\x6f"
15916 "\x4d\x20\x6e\x61\x20\x79\x65\x53"
15917 "\x72\x63\x74\x65\x20\x73\x6f\x54"
15918 "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
15919 "\x63\x65\x65\x72\x73\x74\x54\x20"
15920 "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
15921 .ilen = 128,
15922 .result = "\x0e\x2d\xb6\x97\x3c\x56\x33\xf4"
15923 "\x67\x17\x21\xc7\x6e\x8a\xd5\x49"
15924 "\x74\xb3\x49\x05\xc5\x1c\xd0\xed"
15925 "\x12\x56\x5c\x53\x96\xb6\x00\x7d"
15926 "\x90\x48\xfc\xf5\x8d\x29\x39\xcc"
15927 "\x8a\xd5\x35\x18\x36\x23\x4e\xd7"
15928 "\x76\xd1\xda\x0c\x94\x67\xbb\x04"
15929 "\x8b\xf2\x03\x6c\xa8\xcf\xb6\xea"
15930 "\x22\x64\x47\xaa\x8f\x75\x13\xbf"
15931 "\x9f\xc2\xc3\xf0\xc9\x56\xc5\x7a"
15932 "\x71\x63\x2e\x89\x7b\x1e\x12\xca"
15933 "\xe2\x5f\xaf\xd8\xa4\xf8\xc9\x7a"
15934 "\xd6\xf9\x21\x31\x62\x44\x45\xa6"
15935 "\xd6\xbc\x5a\xd3\x2d\x54\x43\xcc"
15936 "\x9d\xde\xa5\x70\xe9\x42\x45\x8a"
15937 "\x6b\xfa\xb1\x91\x13\xb0\xd9\x19"
15938 "\x6d\x77\xfc\x80\x9d\x8a\x9c\xb7"
15939 "\x70\xe7\x93\xbf\x73\xe6\x9f\x83"
15940 "\x99\x62\x23\xe6\x5b\xd0\xda\x18"
15941 "\xa4\x32\x8a\x0b\x46\xd7\xf0\x39"
15942 "\x36\x5d\x13\x2f\x86\x10\x78\xd6"
15943 "\xd6\xbe\x5c\xb9\x15\x89\xf9\x1b",
15944 .rlen = 128 + 48,
15945 },
15946};
15947
15948#define HMAC_SHA512_DES3_EDE_CBC_ENC_TEST_VEC 1
15949
15950static struct aead_testvec hmac_sha512_des3_ede_cbc_enc_tv_temp[] = {
15951 { /*Generated with cryptopp*/
15952#ifdef __LITTLE_ENDIAN
15953 .key = "\x08\x00" /* rta length */
15954 "\x01\x00" /* rta type */
15955#else
15956 .key = "\x00\x08" /* rta length */
15957 "\x00\x01" /* rta type */
15958#endif
15959 "\x00\x00\x00\x18" /* enc key length */
15960 "\x11\x22\x33\x44\x55\x66\x77\x88"
15961 "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
15962 "\x22\x33\x44\x55\x66\x77\x88\x99"
15963 "\xaa\xbb\xcc\xdd\xee\xff\x11\x22"
15964 "\x33\x44\x55\x66\x77\x88\x99\xaa"
15965 "\xbb\xcc\xdd\xee\xff\x11\x22\x33"
15966 "\x44\x55\x66\x77\x88\x99\xaa\xbb"
15967 "\xcc\xdd\xee\xff\x11\x22\x33\x44"
15968 "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24"
15969 "\x44\x4D\x99\x5A\x12\xD6\x40\xC0"
15970 "\xEA\xC2\x84\xE8\x14\x95\xDB\xE8",
15971 .klen = 8 + 64 + 24,
15972 .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
15973 .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
15974 .alen = 8,
15975 .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
15976 "\x53\x20\x63\x65\x65\x72\x73\x74"
15977 "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
15978 "\x20\x79\x65\x53\x72\x63\x74\x65"
15979 "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
15980 "\x79\x6e\x53\x20\x63\x65\x65\x72"
15981 "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
15982 "\x6e\x61\x20\x79\x65\x53\x72\x63"
15983 "\x74\x65\x20\x73\x6f\x54\x20\x6f"
15984 "\x61\x4d\x79\x6e\x53\x20\x63\x65"
15985 "\x65\x72\x73\x74\x54\x20\x6f\x6f"
15986 "\x4d\x20\x6e\x61\x20\x79\x65\x53"
15987 "\x72\x63\x74\x65\x20\x73\x6f\x54"
15988 "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
15989 "\x63\x65\x65\x72\x73\x74\x54\x20"
15990 "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
15991 .ilen = 128,
15992 .result = "\x0e\x2d\xb6\x97\x3c\x56\x33\xf4"
15993 "\x67\x17\x21\xc7\x6e\x8a\xd5\x49"
15994 "\x74\xb3\x49\x05\xc5\x1c\xd0\xed"
15995 "\x12\x56\x5c\x53\x96\xb6\x00\x7d"
15996 "\x90\x48\xfc\xf5\x8d\x29\x39\xcc"
15997 "\x8a\xd5\x35\x18\x36\x23\x4e\xd7"
15998 "\x76\xd1\xda\x0c\x94\x67\xbb\x04"
15999 "\x8b\xf2\x03\x6c\xa8\xcf\xb6\xea"
16000 "\x22\x64\x47\xaa\x8f\x75\x13\xbf"
16001 "\x9f\xc2\xc3\xf0\xc9\x56\xc5\x7a"
16002 "\x71\x63\x2e\x89\x7b\x1e\x12\xca"
16003 "\xe2\x5f\xaf\xd8\xa4\xf8\xc9\x7a"
16004 "\xd6\xf9\x21\x31\x62\x44\x45\xa6"
16005 "\xd6\xbc\x5a\xd3\x2d\x54\x43\xcc"
16006 "\x9d\xde\xa5\x70\xe9\x42\x45\x8a"
16007 "\x6b\xfa\xb1\x91\x13\xb0\xd9\x19"
16008 "\x41\xb5\x1f\xbb\xbd\x4e\xb8\x32"
16009 "\x22\x86\x4e\x57\x1b\x2a\xd8\x6e"
16010 "\xa9\xfb\xc8\xf3\xbf\x2d\xae\x2b"
16011 "\x3b\xbc\x41\xe8\x38\xbb\xf1\x60"
16012 "\x4c\x68\xa9\x4e\x8c\x73\xa7\xc0"
16013 "\x2a\x74\xd4\x65\x12\xcb\x55\xf2"
16014 "\xd5\x02\x6d\xe6\xaf\xc9\x2f\xf2"
16015 "\x57\xaa\x85\xf7\xf3\x6a\xcb\xdb",
16016 .rlen = 128 + 64,
16017 },
16018};
16019
14641static struct cipher_testvec aes_lrw_enc_tv_template[] = { 16020static struct cipher_testvec aes_lrw_enc_tv_template[] = {
14642 /* from http://grouper.ieee.org/groups/1619/email/pdf00017.pdf */ 16021 /* from http://grouper.ieee.org/groups/1619/email/pdf00017.pdf */
14643 { /* LRW-32-AES 1 */ 16022 { /* LRW-32-AES 1 */
@@ -18746,7 +20125,29 @@ static struct aead_testvec aes_ccm_enc_tv_template[] = {
18746 "\x7c\xf9\xbe\xc2\x40\x88\x97\xc6" 20125 "\x7c\xf9\xbe\xc2\x40\x88\x97\xc6"
18747 "\xba", 20126 "\xba",
18748 .rlen = 33, 20127 .rlen = 33,
18749 }, 20128 }, {
20129 /*
20130 * This is the same vector as aes_ccm_rfc4309_enc_tv_template[0]
20131 * below but rewritten to use the ccm algorithm directly.
20132 */
20133 .key = "\x83\xac\x54\x66\xc2\xeb\xe5\x05"
20134 "\x2e\x01\xd1\xfc\x5d\x82\x66\x2e",
20135 .klen = 16,
20136 .iv = "\x03\x96\xac\x59\x30\x07\xa1\xe2\xa2\xc7\x55\x24\0\0\0\0",
20137 .alen = 0,
20138 .input = "\x19\xc8\x81\xf6\xe9\x86\xff\x93"
20139 "\x0b\x78\x67\xe5\xbb\xb7\xfc\x6e"
20140 "\x83\x77\xb3\xa6\x0c\x8c\x9f\x9c"
20141 "\x35\x2e\xad\xe0\x62\xf9\x91\xa1",
20142 .ilen = 32,
20143 .result = "\xab\x6f\xe1\x69\x1d\x19\x99\xa8"
20144 "\x92\xa0\xc4\x6f\x7e\xe2\x8b\xb1"
20145 "\x70\xbb\x8c\xa6\x4c\x6e\x97\x8a"
20146 "\x57\x2b\xbe\x5d\x98\xa6\xb1\x32"
20147 "\xda\x24\xea\xd9\xa1\x39\x98\xfd"
20148 "\xa4\xbe\xd9\xf2\x1a\x6d\x22\xa8",
20149 .rlen = 48,
20150 }
18750}; 20151};
18751 20152
18752static struct aead_testvec aes_ccm_dec_tv_template[] = { 20153static struct aead_testvec aes_ccm_dec_tv_template[] = {
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index 244759bbd7b7..836b061ced35 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -2,7 +2,7 @@
2# Hardware Random Number Generator (RNG) configuration 2# Hardware Random Number Generator (RNG) configuration
3# 3#
4 4
5config HW_RANDOM 5menuconfig HW_RANDOM
6 tristate "Hardware Random Number Generator Core support" 6 tristate "Hardware Random Number Generator Core support"
7 default m 7 default m
8 ---help--- 8 ---help---
@@ -20,9 +20,11 @@ config HW_RANDOM
20 20
21 If unsure, say Y. 21 If unsure, say Y.
22 22
23if HW_RANDOM
24
23config HW_RANDOM_TIMERIOMEM 25config HW_RANDOM_TIMERIOMEM
24 tristate "Timer IOMEM HW Random Number Generator support" 26 tristate "Timer IOMEM HW Random Number Generator support"
25 depends on HW_RANDOM && HAS_IOMEM 27 depends on HAS_IOMEM
26 ---help--- 28 ---help---
27 This driver provides kernel-side support for a generic Random 29 This driver provides kernel-side support for a generic Random
28 Number Generator used by reading a 'dumb' iomem address that 30 Number Generator used by reading a 'dumb' iomem address that
@@ -36,7 +38,7 @@ config HW_RANDOM_TIMERIOMEM
36 38
37config HW_RANDOM_INTEL 39config HW_RANDOM_INTEL
38 tristate "Intel HW Random Number Generator support" 40 tristate "Intel HW Random Number Generator support"
39 depends on HW_RANDOM && (X86 || IA64) && PCI 41 depends on (X86 || IA64) && PCI
40 default HW_RANDOM 42 default HW_RANDOM
41 ---help--- 43 ---help---
42 This driver provides kernel-side support for the Random Number 44 This driver provides kernel-side support for the Random Number
@@ -49,7 +51,7 @@ config HW_RANDOM_INTEL
49 51
50config HW_RANDOM_AMD 52config HW_RANDOM_AMD
51 tristate "AMD HW Random Number Generator support" 53 tristate "AMD HW Random Number Generator support"
52 depends on HW_RANDOM && (X86 || PPC_MAPLE) && PCI 54 depends on (X86 || PPC_MAPLE) && PCI
53 default HW_RANDOM 55 default HW_RANDOM
54 ---help--- 56 ---help---
55 This driver provides kernel-side support for the Random Number 57 This driver provides kernel-side support for the Random Number
@@ -62,8 +64,8 @@ config HW_RANDOM_AMD
62 64
63config HW_RANDOM_ATMEL 65config HW_RANDOM_ATMEL
64 tristate "Atmel Random Number Generator support" 66 tristate "Atmel Random Number Generator support"
65 depends on HW_RANDOM && HAVE_CLK 67 depends on ARCH_AT91 && HAVE_CLK
66 default (HW_RANDOM && ARCH_AT91) 68 default HW_RANDOM
67 ---help--- 69 ---help---
68 This driver provides kernel-side support for the Random Number 70 This driver provides kernel-side support for the Random Number
69 Generator hardware found on Atmel AT91 devices. 71 Generator hardware found on Atmel AT91 devices.
@@ -75,7 +77,7 @@ config HW_RANDOM_ATMEL
75 77
76config HW_RANDOM_BCM63XX 78config HW_RANDOM_BCM63XX
77 tristate "Broadcom BCM63xx Random Number Generator support" 79 tristate "Broadcom BCM63xx Random Number Generator support"
78 depends on HW_RANDOM && BCM63XX 80 depends on BCM63XX
79 default HW_RANDOM 81 default HW_RANDOM
80 ---help--- 82 ---help---
81 This driver provides kernel-side support for the Random Number 83 This driver provides kernel-side support for the Random Number
@@ -88,7 +90,7 @@ config HW_RANDOM_BCM63XX
88 90
89config HW_RANDOM_BCM2835 91config HW_RANDOM_BCM2835
90 tristate "Broadcom BCM2835 Random Number Generator support" 92 tristate "Broadcom BCM2835 Random Number Generator support"
91 depends on HW_RANDOM && ARCH_BCM2835 93 depends on ARCH_BCM2835
92 default HW_RANDOM 94 default HW_RANDOM
93 ---help--- 95 ---help---
94 This driver provides kernel-side support for the Random Number 96 This driver provides kernel-side support for the Random Number
@@ -101,7 +103,7 @@ config HW_RANDOM_BCM2835
101 103
102config HW_RANDOM_GEODE 104config HW_RANDOM_GEODE
103 tristate "AMD Geode HW Random Number Generator support" 105 tristate "AMD Geode HW Random Number Generator support"
104 depends on HW_RANDOM && X86_32 && PCI 106 depends on X86_32 && PCI
105 default HW_RANDOM 107 default HW_RANDOM
106 ---help--- 108 ---help---
107 This driver provides kernel-side support for the Random Number 109 This driver provides kernel-side support for the Random Number
@@ -114,7 +116,7 @@ config HW_RANDOM_GEODE
114 116
115config HW_RANDOM_N2RNG 117config HW_RANDOM_N2RNG
116 tristate "Niagara2 Random Number Generator support" 118 tristate "Niagara2 Random Number Generator support"
117 depends on HW_RANDOM && SPARC64 119 depends on SPARC64
118 default HW_RANDOM 120 default HW_RANDOM
119 ---help--- 121 ---help---
120 This driver provides kernel-side support for the Random Number 122 This driver provides kernel-side support for the Random Number
@@ -127,7 +129,7 @@ config HW_RANDOM_N2RNG
127 129
128config HW_RANDOM_VIA 130config HW_RANDOM_VIA
129 tristate "VIA HW Random Number Generator support" 131 tristate "VIA HW Random Number Generator support"
130 depends on HW_RANDOM && X86 132 depends on X86
131 default HW_RANDOM 133 default HW_RANDOM
132 ---help--- 134 ---help---
133 This driver provides kernel-side support for the Random Number 135 This driver provides kernel-side support for the Random Number
@@ -140,7 +142,7 @@ config HW_RANDOM_VIA
140 142
141config HW_RANDOM_IXP4XX 143config HW_RANDOM_IXP4XX
142 tristate "Intel IXP4xx NPU HW Pseudo-Random Number Generator support" 144 tristate "Intel IXP4xx NPU HW Pseudo-Random Number Generator support"
143 depends on HW_RANDOM && ARCH_IXP4XX 145 depends on ARCH_IXP4XX
144 default HW_RANDOM 146 default HW_RANDOM
145 ---help--- 147 ---help---
146 This driver provides kernel-side support for the Pseudo-Random 148 This driver provides kernel-side support for the Pseudo-Random
@@ -153,7 +155,7 @@ config HW_RANDOM_IXP4XX
153 155
154config HW_RANDOM_OMAP 156config HW_RANDOM_OMAP
155 tristate "OMAP Random Number Generator support" 157 tristate "OMAP Random Number Generator support"
156 depends on HW_RANDOM && (ARCH_OMAP16XX || ARCH_OMAP2PLUS) 158 depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS
157 default HW_RANDOM 159 default HW_RANDOM
158 ---help--- 160 ---help---
159 This driver provides kernel-side support for the Random Number 161 This driver provides kernel-side support for the Random Number
@@ -167,7 +169,7 @@ config HW_RANDOM_OMAP
167 169
168config HW_RANDOM_OMAP3_ROM 170config HW_RANDOM_OMAP3_ROM
169 tristate "OMAP3 ROM Random Number Generator support" 171 tristate "OMAP3 ROM Random Number Generator support"
170 depends on HW_RANDOM && ARCH_OMAP3 172 depends on ARCH_OMAP3
171 default HW_RANDOM 173 default HW_RANDOM
172 ---help--- 174 ---help---
173 This driver provides kernel-side support for the Random Number 175 This driver provides kernel-side support for the Random Number
@@ -180,7 +182,7 @@ config HW_RANDOM_OMAP3_ROM
180 182
181config HW_RANDOM_OCTEON 183config HW_RANDOM_OCTEON
182 tristate "Octeon Random Number Generator support" 184 tristate "Octeon Random Number Generator support"
183 depends on HW_RANDOM && CAVIUM_OCTEON_SOC 185 depends on CAVIUM_OCTEON_SOC
184 default HW_RANDOM 186 default HW_RANDOM
185 ---help--- 187 ---help---
186 This driver provides kernel-side support for the Random Number 188 This driver provides kernel-side support for the Random Number
@@ -193,7 +195,7 @@ config HW_RANDOM_OCTEON
193 195
194config HW_RANDOM_PASEMI 196config HW_RANDOM_PASEMI
195 tristate "PA Semi HW Random Number Generator support" 197 tristate "PA Semi HW Random Number Generator support"
196 depends on HW_RANDOM && PPC_PASEMI 198 depends on PPC_PASEMI
197 default HW_RANDOM 199 default HW_RANDOM
198 ---help--- 200 ---help---
199 This driver provides kernel-side support for the Random Number 201 This driver provides kernel-side support for the Random Number
@@ -206,7 +208,7 @@ config HW_RANDOM_PASEMI
206 208
207config HW_RANDOM_VIRTIO 209config HW_RANDOM_VIRTIO
208 tristate "VirtIO Random Number Generator support" 210 tristate "VirtIO Random Number Generator support"
209 depends on HW_RANDOM && VIRTIO 211 depends on VIRTIO
210 ---help--- 212 ---help---
211 This driver provides kernel-side support for the virtual Random Number 213 This driver provides kernel-side support for the virtual Random Number
212 Generator hardware. 214 Generator hardware.
@@ -216,7 +218,7 @@ config HW_RANDOM_VIRTIO
216 218
217config HW_RANDOM_TX4939 219config HW_RANDOM_TX4939
218 tristate "TX4939 Random Number Generator support" 220 tristate "TX4939 Random Number Generator support"
219 depends on HW_RANDOM && SOC_TX4939 221 depends on SOC_TX4939
220 default HW_RANDOM 222 default HW_RANDOM
221 ---help--- 223 ---help---
222 This driver provides kernel-side support for the Random Number 224 This driver provides kernel-side support for the Random Number
@@ -229,7 +231,8 @@ config HW_RANDOM_TX4939
229 231
230config HW_RANDOM_MXC_RNGA 232config HW_RANDOM_MXC_RNGA
231 tristate "Freescale i.MX RNGA Random Number Generator" 233 tristate "Freescale i.MX RNGA Random Number Generator"
232 depends on HW_RANDOM && ARCH_HAS_RNGA 234 depends on ARCH_HAS_RNGA
235 default HW_RANDOM
233 ---help--- 236 ---help---
234 This driver provides kernel-side support for the Random Number 237 This driver provides kernel-side support for the Random Number
235 Generator hardware found on Freescale i.MX processors. 238 Generator hardware found on Freescale i.MX processors.
@@ -241,7 +244,8 @@ config HW_RANDOM_MXC_RNGA
241 244
242config HW_RANDOM_NOMADIK 245config HW_RANDOM_NOMADIK
243 tristate "ST-Ericsson Nomadik Random Number Generator support" 246 tristate "ST-Ericsson Nomadik Random Number Generator support"
244 depends on HW_RANDOM && ARCH_NOMADIK 247 depends on ARCH_NOMADIK
248 default HW_RANDOM
245 ---help--- 249 ---help---
246 This driver provides kernel-side support for the Random Number 250 This driver provides kernel-side support for the Random Number
247 Generator hardware found on ST-Ericsson SoCs (8815 and 8500). 251 Generator hardware found on ST-Ericsson SoCs (8815 and 8500).
@@ -251,21 +255,10 @@ config HW_RANDOM_NOMADIK
251 255
252 If unsure, say Y. 256 If unsure, say Y.
253 257
254config HW_RANDOM_PICOXCELL
255 tristate "Picochip picoXcell true random number generator support"
256 depends on HW_RANDOM && ARCH_PICOXCELL && PICOXCELL_PC3X3
257 ---help---
258 This driver provides kernel-side support for the Random Number
259 Generator hardware found on Picochip PC3x3 and later devices.
260
261 To compile this driver as a module, choose M here: the
262 module will be called picoxcell-rng.
263
264 If unsure, say Y.
265
266config HW_RANDOM_PPC4XX 258config HW_RANDOM_PPC4XX
267 tristate "PowerPC 4xx generic true random number generator support" 259 tristate "PowerPC 4xx generic true random number generator support"
268 depends on HW_RANDOM && PPC && 4xx 260 depends on PPC && 4xx
261 default HW_RANDOM
269 ---help--- 262 ---help---
270 This driver provides the kernel-side support for the TRNG hardware 263 This driver provides the kernel-side support for the TRNG hardware
271 found in the security function of some PowerPC 4xx SoCs. 264 found in the security function of some PowerPC 4xx SoCs.
@@ -275,24 +268,9 @@ config HW_RANDOM_PPC4XX
275 268
276 If unsure, say N. 269 If unsure, say N.
277 270
278config UML_RANDOM
279 depends on UML
280 tristate "Hardware random number generator"
281 help
282 This option enables UML's "hardware" random number generator. It
283 attaches itself to the host's /dev/random, supplying as much entropy
284 as the host has, rather than the small amount the UML gets from its
285 own drivers. It registers itself as a standard hardware random number
286 generator, major 10, minor 183, and the canonical device name is
287 /dev/hwrng.
288 The way to make use of this is to install the rng-tools package
289 (check your distro, or download from
290 http://sourceforge.net/projects/gkernel/). rngd periodically reads
291 /dev/hwrng and injects the entropy into /dev/random.
292
293config HW_RANDOM_PSERIES 271config HW_RANDOM_PSERIES
294 tristate "pSeries HW Random Number Generator support" 272 tristate "pSeries HW Random Number Generator support"
295 depends on HW_RANDOM && PPC64 && IBMVIO 273 depends on PPC64 && IBMVIO
296 default HW_RANDOM 274 default HW_RANDOM
297 ---help--- 275 ---help---
298 This driver provides kernel-side support for the Random Number 276 This driver provides kernel-side support for the Random Number
@@ -305,7 +283,7 @@ config HW_RANDOM_PSERIES
305 283
306config HW_RANDOM_POWERNV 284config HW_RANDOM_POWERNV
307 tristate "PowerNV Random Number Generator support" 285 tristate "PowerNV Random Number Generator support"
308 depends on HW_RANDOM && PPC_POWERNV 286 depends on PPC_POWERNV
309 default HW_RANDOM 287 default HW_RANDOM
310 ---help--- 288 ---help---
311 This is the driver for Random Number Generator hardware found 289 This is the driver for Random Number Generator hardware found
@@ -318,7 +296,8 @@ config HW_RANDOM_POWERNV
318 296
319config HW_RANDOM_EXYNOS 297config HW_RANDOM_EXYNOS
320 tristate "EXYNOS HW random number generator support" 298 tristate "EXYNOS HW random number generator support"
321 depends on HW_RANDOM && HAS_IOMEM && HAVE_CLK 299 depends on ARCH_EXYNOS
300 default HW_RANDOM
322 ---help--- 301 ---help---
323 This driver provides kernel-side support for the Random Number 302 This driver provides kernel-side support for the Random Number
324 Generator hardware found on EXYNOS SOCs. 303 Generator hardware found on EXYNOS SOCs.
@@ -330,7 +309,7 @@ config HW_RANDOM_EXYNOS
330 309
331config HW_RANDOM_TPM 310config HW_RANDOM_TPM
332 tristate "TPM HW Random Number Generator support" 311 tristate "TPM HW Random Number Generator support"
333 depends on HW_RANDOM && TCG_TPM 312 depends on TCG_TPM
334 default HW_RANDOM 313 default HW_RANDOM
335 ---help--- 314 ---help---
336 This driver provides kernel-side support for the Random Number 315 This driver provides kernel-side support for the Random Number
@@ -344,6 +323,7 @@ config HW_RANDOM_TPM
344config HW_RANDOM_MSM 323config HW_RANDOM_MSM
345 tristate "Qualcomm SoCs Random Number Generator support" 324 tristate "Qualcomm SoCs Random Number Generator support"
346 depends on HW_RANDOM && ARCH_QCOM 325 depends on HW_RANDOM && ARCH_QCOM
326 default HW_RANDOM
347 ---help--- 327 ---help---
348 This driver provides kernel-side support for the Random Number 328 This driver provides kernel-side support for the Random Number
349 Generator hardware found on Qualcomm SoCs. 329 Generator hardware found on Qualcomm SoCs.
@@ -352,3 +332,20 @@ config HW_RANDOM_MSM
352 module will be called msm-rng. 332 module will be called msm-rng.
353 333
354 If unsure, say Y. 334 If unsure, say Y.
335
336endif # HW_RANDOM
337
338config UML_RANDOM
339 depends on UML
340 tristate "Hardware random number generator"
341 help
342 This option enables UML's "hardware" random number generator. It
343 attaches itself to the host's /dev/random, supplying as much entropy
344 as the host has, rather than the small amount the UML gets from its
345 own drivers. It registers itself as a standard hardware random number
346 generator, major 10, minor 183, and the canonical device name is
347 /dev/hwrng.
348 The way to make use of this is to install the rng-tools package
349 (check your distro, or download from
350 http://sourceforge.net/projects/gkernel/). rngd periodically reads
351 /dev/hwrng and injects the entropy into /dev/random.
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index 3ae7755a52e7..199ed283e149 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -22,7 +22,6 @@ obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o
22obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o 22obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o
23obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o 23obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o
24obj-$(CONFIG_HW_RANDOM_NOMADIK) += nomadik-rng.o 24obj-$(CONFIG_HW_RANDOM_NOMADIK) += nomadik-rng.o
25obj-$(CONFIG_HW_RANDOM_PICOXCELL) += picoxcell-rng.o
26obj-$(CONFIG_HW_RANDOM_PPC4XX) += ppc4xx-rng.o 25obj-$(CONFIG_HW_RANDOM_PPC4XX) += ppc4xx-rng.o
27obj-$(CONFIG_HW_RANDOM_PSERIES) += pseries-rng.o 26obj-$(CONFIG_HW_RANDOM_PSERIES) += pseries-rng.o
28obj-$(CONFIG_HW_RANDOM_POWERNV) += powernv-rng.o 27obj-$(CONFIG_HW_RANDOM_POWERNV) += powernv-rng.o
diff --git a/drivers/char/hw_random/n2-drv.c b/drivers/char/hw_random/n2-drv.c
index 432232eefe05..292a5889f675 100644
--- a/drivers/char/hw_random/n2-drv.c
+++ b/drivers/char/hw_random/n2-drv.c
@@ -632,7 +632,7 @@ static int n2rng_probe(struct platform_device *op)
632 multi_capable = (match->data != NULL); 632 multi_capable = (match->data != NULL);
633 633
634 n2rng_driver_version(); 634 n2rng_driver_version();
635 np = kzalloc(sizeof(*np), GFP_KERNEL); 635 np = devm_kzalloc(&op->dev, sizeof(*np), GFP_KERNEL);
636 if (!np) 636 if (!np)
637 goto out; 637 goto out;
638 np->op = op; 638 np->op = op;
@@ -653,7 +653,7 @@ static int n2rng_probe(struct platform_device *op)
653 &np->hvapi_minor)) { 653 &np->hvapi_minor)) {
654 dev_err(&op->dev, "Cannot register suitable " 654 dev_err(&op->dev, "Cannot register suitable "
655 "HVAPI version.\n"); 655 "HVAPI version.\n");
656 goto out_free; 656 goto out;
657 } 657 }
658 } 658 }
659 659
@@ -676,15 +676,16 @@ static int n2rng_probe(struct platform_device *op)
676 dev_info(&op->dev, "Registered RNG HVAPI major %lu minor %lu\n", 676 dev_info(&op->dev, "Registered RNG HVAPI major %lu minor %lu\n",
677 np->hvapi_major, np->hvapi_minor); 677 np->hvapi_major, np->hvapi_minor);
678 678
679 np->units = kzalloc(sizeof(struct n2rng_unit) * np->num_units, 679 np->units = devm_kzalloc(&op->dev,
680 GFP_KERNEL); 680 sizeof(struct n2rng_unit) * np->num_units,
681 GFP_KERNEL);
681 err = -ENOMEM; 682 err = -ENOMEM;
682 if (!np->units) 683 if (!np->units)
683 goto out_hvapi_unregister; 684 goto out_hvapi_unregister;
684 685
685 err = n2rng_init_control(np); 686 err = n2rng_init_control(np);
686 if (err) 687 if (err)
687 goto out_free_units; 688 goto out_hvapi_unregister;
688 689
689 dev_info(&op->dev, "Found %s RNG, units: %d\n", 690 dev_info(&op->dev, "Found %s RNG, units: %d\n",
690 ((np->flags & N2RNG_FLAG_MULTI) ? 691 ((np->flags & N2RNG_FLAG_MULTI) ?
@@ -697,7 +698,7 @@ static int n2rng_probe(struct platform_device *op)
697 698
698 err = hwrng_register(&np->hwrng); 699 err = hwrng_register(&np->hwrng);
699 if (err) 700 if (err)
700 goto out_free_units; 701 goto out_hvapi_unregister;
701 702
702 platform_set_drvdata(op, np); 703 platform_set_drvdata(op, np);
703 704
@@ -705,15 +706,9 @@ static int n2rng_probe(struct platform_device *op)
705 706
706 return 0; 707 return 0;
707 708
708out_free_units:
709 kfree(np->units);
710 np->units = NULL;
711
712out_hvapi_unregister: 709out_hvapi_unregister:
713 sun4v_hvapi_unregister(HV_GRP_RNG); 710 sun4v_hvapi_unregister(HV_GRP_RNG);
714 711
715out_free:
716 kfree(np);
717out: 712out:
718 return err; 713 return err;
719} 714}
@@ -730,11 +725,6 @@ static int n2rng_remove(struct platform_device *op)
730 725
731 sun4v_hvapi_unregister(HV_GRP_RNG); 726 sun4v_hvapi_unregister(HV_GRP_RNG);
732 727
733 kfree(np->units);
734 np->units = NULL;
735
736 kfree(np);
737
738 return 0; 728 return 0;
739} 729}
740 730
diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c
index 9b89ff4881de..f66ea258382f 100644
--- a/drivers/char/hw_random/omap-rng.c
+++ b/drivers/char/hw_random/omap-rng.c
@@ -369,10 +369,8 @@ static int omap_rng_probe(struct platform_device *pdev)
369 int ret; 369 int ret;
370 370
371 priv = devm_kzalloc(dev, sizeof(struct omap_rng_dev), GFP_KERNEL); 371 priv = devm_kzalloc(dev, sizeof(struct omap_rng_dev), GFP_KERNEL);
372 if (!priv) { 372 if (!priv)
373 dev_err(&pdev->dev, "could not allocate memory\n");
374 return -ENOMEM; 373 return -ENOMEM;
375 };
376 374
377 omap_rng_ops.priv = (unsigned long)priv; 375 omap_rng_ops.priv = (unsigned long)priv;
378 platform_set_drvdata(pdev, priv); 376 platform_set_drvdata(pdev, priv);
diff --git a/drivers/char/hw_random/picoxcell-rng.c b/drivers/char/hw_random/picoxcell-rng.c
deleted file mode 100644
index eab5448ad56f..000000000000
--- a/drivers/char/hw_random/picoxcell-rng.c
+++ /dev/null
@@ -1,181 +0,0 @@
1/*
2 * Copyright (c) 2010-2011 Picochip Ltd., Jamie Iles
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * All enquiries to support@picochip.com
9 */
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/hw_random.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18
19#define DATA_REG_OFFSET 0x0200
20#define CSR_REG_OFFSET 0x0278
21#define CSR_OUT_EMPTY_MASK (1 << 24)
22#define CSR_FAULT_MASK (1 << 1)
23#define TRNG_BLOCK_RESET_MASK (1 << 0)
24#define TAI_REG_OFFSET 0x0380
25
26/*
27 * The maximum amount of time in microseconds to spend waiting for data if the
28 * core wants us to wait. The TRNG should generate 32 bits every 320ns so a
29 * timeout of 20us seems reasonable. The TRNG does builtin tests of the data
30 * for randomness so we can't always assume there is data present.
31 */
32#define PICO_TRNG_TIMEOUT 20
33
34static void __iomem *rng_base;
35static struct clk *rng_clk;
36static struct device *rng_dev;
37
38static inline u32 picoxcell_trng_read_csr(void)
39{
40 return __raw_readl(rng_base + CSR_REG_OFFSET);
41}
42
43static inline bool picoxcell_trng_is_empty(void)
44{
45 return picoxcell_trng_read_csr() & CSR_OUT_EMPTY_MASK;
46}
47
48/*
49 * Take the random number generator out of reset and make sure the interrupts
50 * are masked. We shouldn't need to get large amounts of random bytes so just
51 * poll the status register. The hardware generates 32 bits every 320ns so we
52 * shouldn't have to wait long enough to warrant waiting for an IRQ.
53 */
54static void picoxcell_trng_start(void)
55{
56 __raw_writel(0, rng_base + TAI_REG_OFFSET);
57 __raw_writel(0, rng_base + CSR_REG_OFFSET);
58}
59
60static void picoxcell_trng_reset(void)
61{
62 __raw_writel(TRNG_BLOCK_RESET_MASK, rng_base + CSR_REG_OFFSET);
63 __raw_writel(TRNG_BLOCK_RESET_MASK, rng_base + TAI_REG_OFFSET);
64 picoxcell_trng_start();
65}
66
67/*
68 * Get some random data from the random number generator. The hw_random core
69 * layer provides us with locking.
70 */
71static int picoxcell_trng_read(struct hwrng *rng, void *buf, size_t max,
72 bool wait)
73{
74 int i;
75
76 /* Wait for some data to become available. */
77 for (i = 0; i < PICO_TRNG_TIMEOUT && picoxcell_trng_is_empty(); ++i) {
78 if (!wait)
79 return 0;
80
81 udelay(1);
82 }
83
84 if (picoxcell_trng_read_csr() & CSR_FAULT_MASK) {
85 dev_err(rng_dev, "fault detected, resetting TRNG\n");
86 picoxcell_trng_reset();
87 return -EIO;
88 }
89
90 if (i == PICO_TRNG_TIMEOUT)
91 return 0;
92
93 *(u32 *)buf = __raw_readl(rng_base + DATA_REG_OFFSET);
94 return sizeof(u32);
95}
96
97static struct hwrng picoxcell_trng = {
98 .name = "picoxcell",
99 .read = picoxcell_trng_read,
100};
101
102static int picoxcell_trng_probe(struct platform_device *pdev)
103{
104 int ret;
105 struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
106
107 rng_base = devm_ioremap_resource(&pdev->dev, mem);
108 if (IS_ERR(rng_base))
109 return PTR_ERR(rng_base);
110
111 rng_clk = devm_clk_get(&pdev->dev, NULL);
112 if (IS_ERR(rng_clk)) {
113 dev_warn(&pdev->dev, "no clk\n");
114 return PTR_ERR(rng_clk);
115 }
116
117 ret = clk_enable(rng_clk);
118 if (ret) {
119 dev_warn(&pdev->dev, "unable to enable clk\n");
120 return ret;
121 }
122
123 picoxcell_trng_start();
124 ret = hwrng_register(&picoxcell_trng);
125 if (ret)
126 goto err_register;
127
128 rng_dev = &pdev->dev;
129 dev_info(&pdev->dev, "pixoxcell random number generator active\n");
130
131 return 0;
132
133err_register:
134 clk_disable(rng_clk);
135 return ret;
136}
137
138static int picoxcell_trng_remove(struct platform_device *pdev)
139{
140 hwrng_unregister(&picoxcell_trng);
141 clk_disable(rng_clk);
142
143 return 0;
144}
145
146#ifdef CONFIG_PM
147static int picoxcell_trng_suspend(struct device *dev)
148{
149 clk_disable(rng_clk);
150
151 return 0;
152}
153
154static int picoxcell_trng_resume(struct device *dev)
155{
156 return clk_enable(rng_clk);
157}
158
159static const struct dev_pm_ops picoxcell_trng_pm_ops = {
160 .suspend = picoxcell_trng_suspend,
161 .resume = picoxcell_trng_resume,
162};
163#endif /* CONFIG_PM */
164
165static struct platform_driver picoxcell_trng_driver = {
166 .probe = picoxcell_trng_probe,
167 .remove = picoxcell_trng_remove,
168 .driver = {
169 .name = "picoxcell-trng",
170 .owner = THIS_MODULE,
171#ifdef CONFIG_PM
172 .pm = &picoxcell_trng_pm_ops,
173#endif /* CONFIG_PM */
174 },
175};
176
177module_platform_driver(picoxcell_trng_driver);
178
179MODULE_LICENSE("GPL");
180MODULE_AUTHOR("Jamie Iles");
181MODULE_DESCRIPTION("Picochip picoXcell TRNG driver");
diff --git a/drivers/char/hw_random/timeriomem-rng.c b/drivers/char/hw_random/timeriomem-rng.c
index 439ff8b28c43..b6ab9ac3f34d 100644
--- a/drivers/char/hw_random/timeriomem-rng.c
+++ b/drivers/char/hw_random/timeriomem-rng.c
@@ -120,10 +120,8 @@ static int timeriomem_rng_probe(struct platform_device *pdev)
120 /* Allocate memory for the device structure (and zero it) */ 120 /* Allocate memory for the device structure (and zero it) */
121 priv = devm_kzalloc(&pdev->dev, 121 priv = devm_kzalloc(&pdev->dev,
122 sizeof(struct timeriomem_rng_private_data), GFP_KERNEL); 122 sizeof(struct timeriomem_rng_private_data), GFP_KERNEL);
123 if (!priv) { 123 if (!priv)
124 dev_err(&pdev->dev, "failed to allocate device structure.\n");
125 return -ENOMEM; 124 return -ENOMEM;
126 }
127 125
128 platform_set_drvdata(pdev, priv); 126 platform_set_drvdata(pdev, priv);
129 127
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 03ccdb0ccf9e..f066fa23cc05 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -301,14 +301,14 @@ config CRYPTO_DEV_SAHARA
301 found in some Freescale i.MX chips. 301 found in some Freescale i.MX chips.
302 302
303config CRYPTO_DEV_S5P 303config CRYPTO_DEV_S5P
304 tristate "Support for Samsung S5PV210 crypto accelerator" 304 tristate "Support for Samsung S5PV210/Exynos crypto accelerator"
305 depends on ARCH_S5PV210 305 depends on ARCH_S5PV210 || ARCH_EXYNOS
306 select CRYPTO_AES 306 select CRYPTO_AES
307 select CRYPTO_ALGAPI 307 select CRYPTO_ALGAPI
308 select CRYPTO_BLKCIPHER 308 select CRYPTO_BLKCIPHER
309 help 309 help
310 This option allows you to have support for S5P crypto acceleration. 310 This option allows you to have support for S5P crypto acceleration.
311 Select this to offload Samsung S5PV210 or S5PC110 from AES 311 Select this to offload Samsung S5PV210 or S5PC110, Exynos from AES
312 algorithms execution. 312 algorithms execution.
313 313
314config CRYPTO_DEV_NX 314config CRYPTO_DEV_NX
diff --git a/drivers/crypto/atmel-aes.c b/drivers/crypto/atmel-aes.c
index d7c9e317423c..a083474991ab 100644
--- a/drivers/crypto/atmel-aes.c
+++ b/drivers/crypto/atmel-aes.c
@@ -716,6 +716,12 @@ static int atmel_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
716 return -EINVAL; 716 return -EINVAL;
717 } 717 }
718 ctx->block_size = CFB32_BLOCK_SIZE; 718 ctx->block_size = CFB32_BLOCK_SIZE;
719 } else if (mode & AES_FLAGS_CFB64) {
720 if (!IS_ALIGNED(req->nbytes, CFB64_BLOCK_SIZE)) {
721 pr_err("request size is not exact amount of CFB64 blocks\n");
722 return -EINVAL;
723 }
724 ctx->block_size = CFB64_BLOCK_SIZE;
719 } else { 725 } else {
720 if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) { 726 if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
721 pr_err("request size is not exact amount of AES blocks\n"); 727 pr_err("request size is not exact amount of AES blocks\n");
@@ -1069,7 +1075,7 @@ static struct crypto_alg aes_algs[] = {
1069 .cra_driver_name = "atmel-cfb8-aes", 1075 .cra_driver_name = "atmel-cfb8-aes",
1070 .cra_priority = 100, 1076 .cra_priority = 100,
1071 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 1077 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1072 .cra_blocksize = CFB64_BLOCK_SIZE, 1078 .cra_blocksize = CFB8_BLOCK_SIZE,
1073 .cra_ctxsize = sizeof(struct atmel_aes_ctx), 1079 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1074 .cra_alignmask = 0x0, 1080 .cra_alignmask = 0x0,
1075 .cra_type = &crypto_ablkcipher_type, 1081 .cra_type = &crypto_ablkcipher_type,
diff --git a/drivers/crypto/bfin_crc.c b/drivers/crypto/bfin_crc.c
index c9ff298e6d26..b099e33cb073 100644
--- a/drivers/crypto/bfin_crc.c
+++ b/drivers/crypto/bfin_crc.c
@@ -29,10 +29,11 @@
29#include <crypto/hash.h> 29#include <crypto/hash.h>
30#include <crypto/internal/hash.h> 30#include <crypto/internal/hash.h>
31 31
32#include <asm/blackfin.h>
33#include <asm/bfin_crc.h>
34#include <asm/dma.h> 32#include <asm/dma.h>
35#include <asm/portmux.h> 33#include <asm/portmux.h>
34#include <asm/io.h>
35
36#include "bfin_crc.h"
36 37
37#define CRC_CCRYPTO_QUEUE_LENGTH 5 38#define CRC_CCRYPTO_QUEUE_LENGTH 5
38 39
@@ -54,12 +55,13 @@ struct bfin_crypto_crc {
54 int irq; 55 int irq;
55 int dma_ch; 56 int dma_ch;
56 u32 poly; 57 u32 poly;
57 volatile struct crc_register *regs; 58 struct crc_register *regs;
58 59
59 struct ahash_request *req; /* current request in operation */ 60 struct ahash_request *req; /* current request in operation */
60 struct dma_desc_array *sg_cpu; /* virt addr of sg dma descriptors */ 61 struct dma_desc_array *sg_cpu; /* virt addr of sg dma descriptors */
61 dma_addr_t sg_dma; /* phy addr of sg dma descriptors */ 62 dma_addr_t sg_dma; /* phy addr of sg dma descriptors */
62 u8 *sg_mid_buf; 63 u8 *sg_mid_buf;
64 dma_addr_t sg_mid_dma; /* phy addr of sg mid buffer */
63 65
64 struct tasklet_struct done_task; 66 struct tasklet_struct done_task;
65 struct crypto_queue queue; /* waiting requests */ 67 struct crypto_queue queue; /* waiting requests */
@@ -132,13 +134,13 @@ static struct scatterlist *sg_get(struct scatterlist *sg_list, unsigned int nent
132 134
133static int bfin_crypto_crc_init_hw(struct bfin_crypto_crc *crc, u32 key) 135static int bfin_crypto_crc_init_hw(struct bfin_crypto_crc *crc, u32 key)
134{ 136{
135 crc->regs->datacntrld = 0; 137 writel(0, &crc->regs->datacntrld);
136 crc->regs->control = MODE_CALC_CRC << OPMODE_OFFSET; 138 writel(MODE_CALC_CRC << OPMODE_OFFSET, &crc->regs->control);
137 crc->regs->curresult = key; 139 writel(key, &crc->regs->curresult);
138 140
139 /* setup CRC interrupts */ 141 /* setup CRC interrupts */
140 crc->regs->status = CMPERRI | DCNTEXPI; 142 writel(CMPERRI | DCNTEXPI, &crc->regs->status);
141 crc->regs->intrenset = CMPERRI | DCNTEXPI; 143 writel(CMPERRI | DCNTEXPI, &crc->regs->intrenset);
142 144
143 return 0; 145 return 0;
144} 146}
@@ -194,7 +196,6 @@ static void bfin_crypto_crc_config_dma(struct bfin_crypto_crc *crc)
194 dma_map_sg(crc->dev, ctx->sg, ctx->sg_nents, DMA_TO_DEVICE); 196 dma_map_sg(crc->dev, ctx->sg, ctx->sg_nents, DMA_TO_DEVICE);
195 197
196 for_each_sg(ctx->sg, sg, ctx->sg_nents, j) { 198 for_each_sg(ctx->sg, sg, ctx->sg_nents, j) {
197 dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 | DMAEN | PSIZE_32;
198 dma_addr = sg_dma_address(sg); 199 dma_addr = sg_dma_address(sg);
199 /* deduce extra bytes in last sg */ 200 /* deduce extra bytes in last sg */
200 if (sg_is_last(sg)) 201 if (sg_is_last(sg))
@@ -207,12 +208,29 @@ static void bfin_crypto_crc_config_dma(struct bfin_crypto_crc *crc)
207 bytes in current sg buffer. Move addr of current 208 bytes in current sg buffer. Move addr of current
208 sg and deduce the length of current sg. 209 sg and deduce the length of current sg.
209 */ 210 */
210 memcpy(crc->sg_mid_buf +((i-1) << 2) + mid_dma_count, 211 memcpy(crc->sg_mid_buf +(i << 2) + mid_dma_count,
211 (void *)dma_addr, 212 sg_virt(sg),
212 CHKSUM_DIGEST_SIZE - mid_dma_count); 213 CHKSUM_DIGEST_SIZE - mid_dma_count);
213 dma_addr += CHKSUM_DIGEST_SIZE - mid_dma_count; 214 dma_addr += CHKSUM_DIGEST_SIZE - mid_dma_count;
214 dma_count -= CHKSUM_DIGEST_SIZE - mid_dma_count; 215 dma_count -= CHKSUM_DIGEST_SIZE - mid_dma_count;
216
217 dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 |
218 DMAEN | PSIZE_32 | WDSIZE_32;
219
220 /* setup new dma descriptor for next middle dma */
221 crc->sg_cpu[i].start_addr = crc->sg_mid_dma + (i << 2);
222 crc->sg_cpu[i].cfg = dma_config;
223 crc->sg_cpu[i].x_count = 1;
224 crc->sg_cpu[i].x_modify = CHKSUM_DIGEST_SIZE;
225 dev_dbg(crc->dev, "%d: crc_dma: start_addr:0x%lx, "
226 "cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
227 i, crc->sg_cpu[i].start_addr,
228 crc->sg_cpu[i].cfg, crc->sg_cpu[i].x_count,
229 crc->sg_cpu[i].x_modify);
230 i++;
215 } 231 }
232
233 dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 | DMAEN | PSIZE_32;
216 /* chop current sg dma len to multiple of 32 bits */ 234 /* chop current sg dma len to multiple of 32 bits */
217 mid_dma_count = dma_count % 4; 235 mid_dma_count = dma_count % 4;
218 dma_count &= ~0x3; 236 dma_count &= ~0x3;
@@ -243,24 +261,9 @@ static void bfin_crypto_crc_config_dma(struct bfin_crypto_crc *crc)
243 261
244 if (mid_dma_count) { 262 if (mid_dma_count) {
245 /* copy extra bytes to next middle dma buffer */ 263 /* copy extra bytes to next middle dma buffer */
246 dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 |
247 DMAEN | PSIZE_32 | WDSIZE_32;
248 memcpy(crc->sg_mid_buf + (i << 2), 264 memcpy(crc->sg_mid_buf + (i << 2),
249 (void *)(dma_addr + (dma_count << 2)), 265 (u8*)sg_virt(sg) + (dma_count << 2),
250 mid_dma_count); 266 mid_dma_count);
251 /* setup new dma descriptor for next middle dma */
252 crc->sg_cpu[i].start_addr = dma_map_single(crc->dev,
253 crc->sg_mid_buf + (i << 2),
254 CHKSUM_DIGEST_SIZE, DMA_TO_DEVICE);
255 crc->sg_cpu[i].cfg = dma_config;
256 crc->sg_cpu[i].x_count = 1;
257 crc->sg_cpu[i].x_modify = CHKSUM_DIGEST_SIZE;
258 dev_dbg(crc->dev, "%d: crc_dma: start_addr:0x%lx, "
259 "cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
260 i, crc->sg_cpu[i].start_addr,
261 crc->sg_cpu[i].cfg, crc->sg_cpu[i].x_count,
262 crc->sg_cpu[i].x_modify);
263 i++;
264 } 267 }
265 } 268 }
266 269
@@ -303,6 +306,7 @@ static int bfin_crypto_crc_handle_queue(struct bfin_crypto_crc *crc,
303 int nsg, i, j; 306 int nsg, i, j;
304 unsigned int nextlen; 307 unsigned int nextlen;
305 unsigned long flags; 308 unsigned long flags;
309 u32 reg;
306 310
307 spin_lock_irqsave(&crc->lock, flags); 311 spin_lock_irqsave(&crc->lock, flags);
308 if (req) 312 if (req)
@@ -402,13 +406,14 @@ finish_update:
402 ctx->sg_buflen += CHKSUM_DIGEST_SIZE; 406 ctx->sg_buflen += CHKSUM_DIGEST_SIZE;
403 407
404 /* set CRC data count before start DMA */ 408 /* set CRC data count before start DMA */
405 crc->regs->datacnt = ctx->sg_buflen >> 2; 409 writel(ctx->sg_buflen >> 2, &crc->regs->datacnt);
406 410
407 /* setup and enable CRC DMA */ 411 /* setup and enable CRC DMA */
408 bfin_crypto_crc_config_dma(crc); 412 bfin_crypto_crc_config_dma(crc);
409 413
410 /* finally kick off CRC operation */ 414 /* finally kick off CRC operation */
411 crc->regs->control |= BLKEN; 415 reg = readl(&crc->regs->control);
416 writel(reg | BLKEN, &crc->regs->control);
412 417
413 return -EINPROGRESS; 418 return -EINPROGRESS;
414} 419}
@@ -529,14 +534,17 @@ static void bfin_crypto_crc_done_task(unsigned long data)
529static irqreturn_t bfin_crypto_crc_handler(int irq, void *dev_id) 534static irqreturn_t bfin_crypto_crc_handler(int irq, void *dev_id)
530{ 535{
531 struct bfin_crypto_crc *crc = dev_id; 536 struct bfin_crypto_crc *crc = dev_id;
537 u32 reg;
532 538
533 if (crc->regs->status & DCNTEXP) { 539 if (readl(&crc->regs->status) & DCNTEXP) {
534 crc->regs->status = DCNTEXP; 540 writel(DCNTEXP, &crc->regs->status);
535 541
536 /* prepare results */ 542 /* prepare results */
537 put_unaligned_le32(crc->regs->result, crc->req->result); 543 put_unaligned_le32(readl(&crc->regs->result),
544 crc->req->result);
538 545
539 crc->regs->control &= ~BLKEN; 546 reg = readl(&crc->regs->control);
547 writel(reg & ~BLKEN, &crc->regs->control);
540 crc->busy = 0; 548 crc->busy = 0;
541 549
542 if (crc->req->base.complete) 550 if (crc->req->base.complete)
@@ -560,7 +568,7 @@ static int bfin_crypto_crc_suspend(struct platform_device *pdev, pm_message_t st
560 struct bfin_crypto_crc *crc = platform_get_drvdata(pdev); 568 struct bfin_crypto_crc *crc = platform_get_drvdata(pdev);
561 int i = 100000; 569 int i = 100000;
562 570
563 while ((crc->regs->control & BLKEN) && --i) 571 while ((readl(&crc->regs->control) & BLKEN) && --i)
564 cpu_relax(); 572 cpu_relax();
565 573
566 if (i == 0) 574 if (i == 0)
@@ -647,29 +655,32 @@ static int bfin_crypto_crc_probe(struct platform_device *pdev)
647 * 1 last + 1 next dma descriptors 655 * 1 last + 1 next dma descriptors
648 */ 656 */
649 crc->sg_mid_buf = (u8 *)(crc->sg_cpu + ((CRC_MAX_DMA_DESC + 1) << 1)); 657 crc->sg_mid_buf = (u8 *)(crc->sg_cpu + ((CRC_MAX_DMA_DESC + 1) << 1));
658 crc->sg_mid_dma = crc->sg_dma + sizeof(struct dma_desc_array)
659 * ((CRC_MAX_DMA_DESC + 1) << 1);
650 660
651 crc->regs->control = 0; 661 writel(0, &crc->regs->control);
652 crc->regs->poly = crc->poly = (u32)pdev->dev.platform_data; 662 crc->poly = (u32)pdev->dev.platform_data;
663 writel(crc->poly, &crc->regs->poly);
653 664
654 while (!(crc->regs->status & LUTDONE) && (--timeout) > 0) 665 while (!(readl(&crc->regs->status) & LUTDONE) && (--timeout) > 0)
655 cpu_relax(); 666 cpu_relax();
656 667
657 if (timeout == 0) 668 if (timeout == 0)
658 dev_info(&pdev->dev, "init crc poly timeout\n"); 669 dev_info(&pdev->dev, "init crc poly timeout\n");
659 670
671 platform_set_drvdata(pdev, crc);
672
660 spin_lock(&crc_list.lock); 673 spin_lock(&crc_list.lock);
661 list_add(&crc->list, &crc_list.dev_list); 674 list_add(&crc->list, &crc_list.dev_list);
662 spin_unlock(&crc_list.lock); 675 spin_unlock(&crc_list.lock);
663 676
664 platform_set_drvdata(pdev, crc); 677 if (list_is_singular(&crc_list.dev_list)) {
665 678 ret = crypto_register_ahash(&algs);
666 ret = crypto_register_ahash(&algs); 679 if (ret) {
667 if (ret) { 680 dev_err(&pdev->dev,
668 spin_lock(&crc_list.lock); 681 "Can't register crypto ahash device\n");
669 list_del(&crc->list); 682 goto out_error_dma;
670 spin_unlock(&crc_list.lock); 683 }
671 dev_err(&pdev->dev, "Cann't register crypto ahash device\n");
672 goto out_error_dma;
673 } 684 }
674 685
675 dev_info(&pdev->dev, "initialized\n"); 686 dev_info(&pdev->dev, "initialized\n");
diff --git a/drivers/crypto/bfin_crc.h b/drivers/crypto/bfin_crc.h
new file mode 100644
index 000000000000..75cef4dc85a1
--- /dev/null
+++ b/drivers/crypto/bfin_crc.h
@@ -0,0 +1,125 @@
1/*
2 * bfin_crc.h - interface to Blackfin CRC controllers
3 *
4 * Copyright 2012 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_CRC_H__
10#define __BFIN_CRC_H__
11
12/* Function driver which use hardware crc must initialize the structure */
13struct crc_info {
14 /* Input data address */
15 unsigned char *in_addr;
16 /* Output data address */
17 unsigned char *out_addr;
18 /* Input or output bytes */
19 unsigned long datasize;
20 union {
21 /* CRC to compare with that of input buffer */
22 unsigned long crc_compare;
23 /* Value to compare with input data */
24 unsigned long val_verify;
25 /* Value to fill */
26 unsigned long val_fill;
27 };
28 /* Value to program the 32b CRC Polynomial */
29 unsigned long crc_poly;
30 union {
31 /* CRC calculated from the input data */
32 unsigned long crc_result;
33 /* First failed position to verify input data */
34 unsigned long pos_verify;
35 };
36 /* CRC mirror flags */
37 unsigned int bitmirr:1;
38 unsigned int bytmirr:1;
39 unsigned int w16swp:1;
40 unsigned int fdsel:1;
41 unsigned int rsltmirr:1;
42 unsigned int polymirr:1;
43 unsigned int cmpmirr:1;
44};
45
46/* Userspace interface */
47#define CRC_IOC_MAGIC 'C'
48#define CRC_IOC_CALC_CRC _IOWR('C', 0x01, unsigned int)
49#define CRC_IOC_MEMCPY_CRC _IOWR('C', 0x02, unsigned int)
50#define CRC_IOC_VERIFY_VAL _IOWR('C', 0x03, unsigned int)
51#define CRC_IOC_FILL_VAL _IOWR('C', 0x04, unsigned int)
52
53
54#ifdef __KERNEL__
55
56#include <linux/types.h>
57#include <linux/spinlock.h>
58#include <linux/miscdevice.h>
59
60struct crc_register {
61 u32 control;
62 u32 datacnt;
63 u32 datacntrld;
64 u32 __pad_1[2];
65 u32 compare;
66 u32 fillval;
67 u32 datafifo;
68 u32 intren;
69 u32 intrenset;
70 u32 intrenclr;
71 u32 poly;
72 u32 __pad_2[4];
73 u32 status;
74 u32 datacntcap;
75 u32 __pad_3;
76 u32 result;
77 u32 curresult;
78 u32 __pad_4[3];
79 u32 revid;
80};
81
82/* CRC_STATUS Masks */
83#define CMPERR 0x00000002 /* Compare error */
84#define DCNTEXP 0x00000010 /* datacnt register expired */
85#define IBR 0x00010000 /* Input buffer ready */
86#define OBR 0x00020000 /* Output buffer ready */
87#define IRR 0x00040000 /* Immediate result readt */
88#define LUTDONE 0x00080000 /* Look-up table generation done */
89#define FSTAT 0x00700000 /* FIFO status */
90#define MAX_FIFO 4 /* Max fifo size */
91
92/* CRC_CONTROL Masks */
93#define BLKEN 0x00000001 /* Block enable */
94#define OPMODE 0x000000F0 /* Operation mode */
95#define OPMODE_OFFSET 4 /* Operation mode mask offset*/
96#define MODE_DMACPY_CRC 1 /* MTM CRC compute and compare */
97#define MODE_DATA_FILL 2 /* MTM data fill */
98#define MODE_CALC_CRC 3 /* MSM CRC compute and compare */
99#define MODE_DATA_VERIFY 4 /* MSM data verify */
100#define AUTOCLRZ 0x00000100 /* Auto clear to zero */
101#define AUTOCLRF 0x00000200 /* Auto clear to one */
102#define OBRSTALL 0x00001000 /* Stall on output buffer ready */
103#define IRRSTALL 0x00002000 /* Stall on immediate result ready */
104#define BITMIRR 0x00010000 /* Mirror bits within each byte of 32-bit input data */
105#define BITMIRR_OFFSET 16 /* Mirror bits offset */
106#define BYTMIRR 0x00020000 /* Mirror bytes of 32-bit input data */
107#define BYTMIRR_OFFSET 17 /* Mirror bytes offset */
108#define W16SWP 0x00040000 /* Mirror uppper and lower 16-bit word of 32-bit input data */
109#define W16SWP_OFFSET 18 /* Mirror 16-bit word offset */
110#define FDSEL 0x00080000 /* FIFO is written after input data is mirrored */
111#define FDSEL_OFFSET 19 /* Mirror FIFO offset */
112#define RSLTMIRR 0x00100000 /* CRC result registers are mirrored. */
113#define RSLTMIRR_OFFSET 20 /* Mirror CRC result offset. */
114#define POLYMIRR 0x00200000 /* CRC poly register is mirrored. */
115#define POLYMIRR_OFFSET 21 /* Mirror CRC poly offset. */
116#define CMPMIRR 0x00400000 /* CRC compare register is mirrored. */
117#define CMPMIRR_OFFSET 22 /* Mirror CRC compare offset. */
118
119/* CRC_INTREN Masks */
120#define CMPERRI 0x02 /* CRC_ERROR_INTR */
121#define DCNTEXPI 0x10 /* CRC_STATUS_INTR */
122
123#endif
124
125#endif
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 5f891254db73..c09ce1f040d3 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -303,6 +303,7 @@ static int aead_null_set_sh_desc(struct crypto_aead *aead)
303 * Job Descriptor and Shared Descriptors 303 * Job Descriptor and Shared Descriptors
304 * must all fit into the 64-word Descriptor h/w Buffer 304 * must all fit into the 64-word Descriptor h/w Buffer
305 */ 305 */
306 keys_fit_inline = false;
306 if (DESC_AEAD_NULL_DEC_LEN + DESC_JOB_IO_LEN + 307 if (DESC_AEAD_NULL_DEC_LEN + DESC_JOB_IO_LEN +
307 ctx->split_key_pad_len <= CAAM_DESC_BYTES_MAX) 308 ctx->split_key_pad_len <= CAAM_DESC_BYTES_MAX)
308 keys_fit_inline = true; 309 keys_fit_inline = true;
@@ -472,6 +473,7 @@ static int aead_set_sh_desc(struct crypto_aead *aead)
472 * Job Descriptor and Shared Descriptors 473 * Job Descriptor and Shared Descriptors
473 * must all fit into the 64-word Descriptor h/w Buffer 474 * must all fit into the 64-word Descriptor h/w Buffer
474 */ 475 */
476 keys_fit_inline = false;
475 if (DESC_AEAD_DEC_LEN + DESC_JOB_IO_LEN + 477 if (DESC_AEAD_DEC_LEN + DESC_JOB_IO_LEN +
476 ctx->split_key_pad_len + ctx->enckeylen <= 478 ctx->split_key_pad_len + ctx->enckeylen <=
477 CAAM_DESC_BYTES_MAX) 479 CAAM_DESC_BYTES_MAX)
@@ -527,6 +529,7 @@ static int aead_set_sh_desc(struct crypto_aead *aead)
527 * Job Descriptor and Shared Descriptors 529 * Job Descriptor and Shared Descriptors
528 * must all fit into the 64-word Descriptor h/w Buffer 530 * must all fit into the 64-word Descriptor h/w Buffer
529 */ 531 */
532 keys_fit_inline = false;
530 if (DESC_AEAD_GIVENC_LEN + DESC_JOB_IO_LEN + 533 if (DESC_AEAD_GIVENC_LEN + DESC_JOB_IO_LEN +
531 ctx->split_key_pad_len + ctx->enckeylen <= 534 ctx->split_key_pad_len + ctx->enckeylen <=
532 CAAM_DESC_BYTES_MAX) 535 CAAM_DESC_BYTES_MAX)
@@ -918,11 +921,8 @@ static void aead_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
918 edesc = (struct aead_edesc *)((char *)desc - 921 edesc = (struct aead_edesc *)((char *)desc -
919 offsetof(struct aead_edesc, hw_desc)); 922 offsetof(struct aead_edesc, hw_desc));
920 923
921 if (err) { 924 if (err)
922 char tmp[CAAM_ERROR_STR_MAX]; 925 caam_jr_strstatus(jrdev, err);
923
924 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
925 }
926 926
927 aead_unmap(jrdev, edesc, req); 927 aead_unmap(jrdev, edesc, req);
928 928
@@ -969,11 +969,8 @@ static void aead_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
969 req->cryptlen - ctx->authsize, 1); 969 req->cryptlen - ctx->authsize, 1);
970#endif 970#endif
971 971
972 if (err) { 972 if (err)
973 char tmp[CAAM_ERROR_STR_MAX]; 973 caam_jr_strstatus(jrdev, err);
974
975 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
976 }
977 974
978 aead_unmap(jrdev, edesc, req); 975 aead_unmap(jrdev, edesc, req);
979 976
@@ -1018,11 +1015,8 @@ static void ablkcipher_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
1018 edesc = (struct ablkcipher_edesc *)((char *)desc - 1015 edesc = (struct ablkcipher_edesc *)((char *)desc -
1019 offsetof(struct ablkcipher_edesc, hw_desc)); 1016 offsetof(struct ablkcipher_edesc, hw_desc));
1020 1017
1021 if (err) { 1018 if (err)
1022 char tmp[CAAM_ERROR_STR_MAX]; 1019 caam_jr_strstatus(jrdev, err);
1023
1024 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
1025 }
1026 1020
1027#ifdef DEBUG 1021#ifdef DEBUG
1028 print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ", 1022 print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
@@ -1053,11 +1047,8 @@ static void ablkcipher_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
1053 1047
1054 edesc = (struct ablkcipher_edesc *)((char *)desc - 1048 edesc = (struct ablkcipher_edesc *)((char *)desc -
1055 offsetof(struct ablkcipher_edesc, hw_desc)); 1049 offsetof(struct ablkcipher_edesc, hw_desc));
1056 if (err) { 1050 if (err)
1057 char tmp[CAAM_ERROR_STR_MAX]; 1051 caam_jr_strstatus(jrdev, err);
1058
1059 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
1060 }
1061 1052
1062#ifdef DEBUG 1053#ifdef DEBUG
1063 print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ", 1054 print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
index 0378328f47a7..0d9284ef96a8 100644
--- a/drivers/crypto/caam/caamhash.c
+++ b/drivers/crypto/caam/caamhash.c
@@ -545,7 +545,8 @@ static int ahash_setkey(struct crypto_ahash *ahash,
545 DMA_TO_DEVICE); 545 DMA_TO_DEVICE);
546 if (dma_mapping_error(jrdev, ctx->key_dma)) { 546 if (dma_mapping_error(jrdev, ctx->key_dma)) {
547 dev_err(jrdev, "unable to map key i/o memory\n"); 547 dev_err(jrdev, "unable to map key i/o memory\n");
548 return -ENOMEM; 548 ret = -ENOMEM;
549 goto map_err;
549 } 550 }
550#ifdef DEBUG 551#ifdef DEBUG
551 print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ", 552 print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
@@ -559,6 +560,7 @@ static int ahash_setkey(struct crypto_ahash *ahash,
559 DMA_TO_DEVICE); 560 DMA_TO_DEVICE);
560 } 561 }
561 562
563map_err:
562 kfree(hashed_key); 564 kfree(hashed_key);
563 return ret; 565 return ret;
564badkey: 566badkey:
@@ -631,11 +633,8 @@ static void ahash_done(struct device *jrdev, u32 *desc, u32 err,
631 633
632 edesc = (struct ahash_edesc *)((char *)desc - 634 edesc = (struct ahash_edesc *)((char *)desc -
633 offsetof(struct ahash_edesc, hw_desc)); 635 offsetof(struct ahash_edesc, hw_desc));
634 if (err) { 636 if (err)
635 char tmp[CAAM_ERROR_STR_MAX]; 637 caam_jr_strstatus(jrdev, err);
636
637 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
638 }
639 638
640 ahash_unmap(jrdev, edesc, req, digestsize); 639 ahash_unmap(jrdev, edesc, req, digestsize);
641 kfree(edesc); 640 kfree(edesc);
@@ -669,11 +668,8 @@ static void ahash_done_bi(struct device *jrdev, u32 *desc, u32 err,
669 668
670 edesc = (struct ahash_edesc *)((char *)desc - 669 edesc = (struct ahash_edesc *)((char *)desc -
671 offsetof(struct ahash_edesc, hw_desc)); 670 offsetof(struct ahash_edesc, hw_desc));
672 if (err) { 671 if (err)
673 char tmp[CAAM_ERROR_STR_MAX]; 672 caam_jr_strstatus(jrdev, err);
674
675 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
676 }
677 673
678 ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL); 674 ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL);
679 kfree(edesc); 675 kfree(edesc);
@@ -707,11 +703,8 @@ static void ahash_done_ctx_src(struct device *jrdev, u32 *desc, u32 err,
707 703
708 edesc = (struct ahash_edesc *)((char *)desc - 704 edesc = (struct ahash_edesc *)((char *)desc -
709 offsetof(struct ahash_edesc, hw_desc)); 705 offsetof(struct ahash_edesc, hw_desc));
710 if (err) { 706 if (err)
711 char tmp[CAAM_ERROR_STR_MAX]; 707 caam_jr_strstatus(jrdev, err);
712
713 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
714 }
715 708
716 ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE); 709 ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE);
717 kfree(edesc); 710 kfree(edesc);
@@ -745,11 +738,8 @@ static void ahash_done_ctx_dst(struct device *jrdev, u32 *desc, u32 err,
745 738
746 edesc = (struct ahash_edesc *)((char *)desc - 739 edesc = (struct ahash_edesc *)((char *)desc -
747 offsetof(struct ahash_edesc, hw_desc)); 740 offsetof(struct ahash_edesc, hw_desc));
748 if (err) { 741 if (err)
749 char tmp[CAAM_ERROR_STR_MAX]; 742 caam_jr_strstatus(jrdev, err);
750
751 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
752 }
753 743
754 ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_TO_DEVICE); 744 ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_TO_DEVICE);
755 kfree(edesc); 745 kfree(edesc);
diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
index 3529b54048c9..8c07d3153f12 100644
--- a/drivers/crypto/caam/caamrng.c
+++ b/drivers/crypto/caam/caamrng.c
@@ -103,11 +103,8 @@ static void rng_done(struct device *jrdev, u32 *desc, u32 err, void *context)
103 bd = (struct buf_data *)((char *)desc - 103 bd = (struct buf_data *)((char *)desc -
104 offsetof(struct buf_data, hw_desc)); 104 offsetof(struct buf_data, hw_desc));
105 105
106 if (err) { 106 if (err)
107 char tmp[CAAM_ERROR_STR_MAX]; 107 caam_jr_strstatus(jrdev, err);
108
109 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
110 }
111 108
112 atomic_set(&bd->empty, BUF_NOT_EMPTY); 109 atomic_set(&bd->empty, BUF_NOT_EMPTY);
113 complete(&bd->filled); 110 complete(&bd->filled);
diff --git a/drivers/crypto/caam/error.c b/drivers/crypto/caam/error.c
index 0eabd81e1a90..6531054a44c8 100644
--- a/drivers/crypto/caam/error.c
+++ b/drivers/crypto/caam/error.c
@@ -11,247 +11,208 @@
11#include "jr.h" 11#include "jr.h"
12#include "error.h" 12#include "error.h"
13 13
14#define SPRINTFCAT(str, format, param, max_alloc) \ 14static const struct {
15{ \ 15 u8 value;
16 char *tmp; \ 16 const char *error_text;
17 \ 17} desc_error_list[] = {
18 tmp = kmalloc(sizeof(format) + max_alloc, GFP_ATOMIC); \ 18 { 0x00, "No error." },
19 if (likely(tmp)) { \ 19 { 0x01, "SGT Length Error. The descriptor is trying to read more data than is contained in the SGT table." },
20 sprintf(tmp, format, param); \ 20 { 0x02, "SGT Null Entry Error." },
21 strcat(str, tmp); \ 21 { 0x03, "Job Ring Control Error. There is a bad value in the Job Ring Control register." },
22 kfree(tmp); \ 22 { 0x04, "Invalid Descriptor Command. The Descriptor Command field is invalid." },
23 } else { \ 23 { 0x05, "Reserved." },
24 strcat(str, "kmalloc failure in SPRINTFCAT"); \ 24 { 0x06, "Invalid KEY Command" },
25 } \ 25 { 0x07, "Invalid LOAD Command" },
26} 26 { 0x08, "Invalid STORE Command" },
27 27 { 0x09, "Invalid OPERATION Command" },
28static void report_jump_idx(u32 status, char *outstr) 28 { 0x0A, "Invalid FIFO LOAD Command" },
29 { 0x0B, "Invalid FIFO STORE Command" },
30 { 0x0C, "Invalid MOVE/MOVE_LEN Command" },
31 { 0x0D, "Invalid JUMP Command. A nonlocal JUMP Command is invalid because the target is not a Job Header Command, or the jump is from a Trusted Descriptor to a Job Descriptor, or because the target Descriptor contains a Shared Descriptor." },
32 { 0x0E, "Invalid MATH Command" },
33 { 0x0F, "Invalid SIGNATURE Command" },
34 { 0x10, "Invalid Sequence Command. A SEQ IN PTR OR SEQ OUT PTR Command is invalid or a SEQ KEY, SEQ LOAD, SEQ FIFO LOAD, or SEQ FIFO STORE decremented the input or output sequence length below 0. This error may result if a built-in PROTOCOL Command has encountered a malformed PDU." },
35 { 0x11, "Skip data type invalid. The type must be 0xE or 0xF."},
36 { 0x12, "Shared Descriptor Header Error" },
37 { 0x13, "Header Error. Invalid length or parity, or certain other problems." },
38 { 0x14, "Burster Error. Burster has gotten to an illegal state" },
39 { 0x15, "Context Register Length Error. The descriptor is trying to read or write past the end of the Context Register. A SEQ LOAD or SEQ STORE with the VLF bit set was executed with too large a length in the variable length register (VSOL for SEQ STORE or VSIL for SEQ LOAD)." },
40 { 0x16, "DMA Error" },
41 { 0x17, "Reserved." },
42 { 0x1A, "Job failed due to JR reset" },
43 { 0x1B, "Job failed due to Fail Mode" },
44 { 0x1C, "DECO Watchdog timer timeout error" },
45 { 0x1D, "DECO tried to copy a key from another DECO but the other DECO's Key Registers were locked" },
46 { 0x1E, "DECO attempted to copy data from a DECO that had an unmasked Descriptor error" },
47 { 0x1F, "LIODN error. DECO was trying to share from itself or from another DECO but the two Non-SEQ LIODN values didn't match or the 'shared from' DECO's Descriptor required that the SEQ LIODNs be the same and they aren't." },
48 { 0x20, "DECO has completed a reset initiated via the DRR register" },
49 { 0x21, "Nonce error. When using EKT (CCM) key encryption option in the FIFO STORE Command, the Nonce counter reached its maximum value and this encryption mode can no longer be used." },
50 { 0x22, "Meta data is too large (> 511 bytes) for TLS decap (input frame; block ciphers) and IPsec decap (output frame, when doing the next header byte update) and DCRC (output frame)." },
51 { 0x23, "Read Input Frame error" },
52 { 0x24, "JDKEK, TDKEK or TDSK not loaded error" },
53 { 0x80, "DNR (do not run) error" },
54 { 0x81, "undefined protocol command" },
55 { 0x82, "invalid setting in PDB" },
56 { 0x83, "Anti-replay LATE error" },
57 { 0x84, "Anti-replay REPLAY error" },
58 { 0x85, "Sequence number overflow" },
59 { 0x86, "Sigver invalid signature" },
60 { 0x87, "DSA Sign Illegal test descriptor" },
61 { 0x88, "Protocol Format Error - A protocol has seen an error in the format of data received. When running RSA, this means that formatting with random padding was used, and did not follow the form: 0x00, 0x02, 8-to-N bytes of non-zero pad, 0x00, F data." },
62 { 0x89, "Protocol Size Error - A protocol has seen an error in size. When running RSA, pdb size N < (size of F) when no formatting is used; or pdb size N < (F + 11) when formatting is used." },
63 { 0xC1, "Blob Command error: Undefined mode" },
64 { 0xC2, "Blob Command error: Secure Memory Blob mode error" },
65 { 0xC4, "Blob Command error: Black Blob key or input size error" },
66 { 0xC5, "Blob Command error: Invalid key destination" },
67 { 0xC8, "Blob Command error: Trusted/Secure mode error" },
68 { 0xF0, "IPsec TTL or hop limit field either came in as 0, or was decremented to 0" },
69 { 0xF1, "3GPP HFN matches or exceeds the Threshold" },
70};
71
72static const char * const cha_id_list[] = {
73 "",
74 "AES",
75 "DES",
76 "ARC4",
77 "MDHA",
78 "RNG",
79 "SNOW f8",
80 "Kasumi f8/9",
81 "PKHA",
82 "CRCA",
83 "SNOW f9",
84 "ZUCE",
85 "ZUCA",
86};
87
88static const char * const err_id_list[] = {
89 "No error.",
90 "Mode error.",
91 "Data size error.",
92 "Key size error.",
93 "PKHA A memory size error.",
94 "PKHA B memory size error.",
95 "Data arrived out of sequence error.",
96 "PKHA divide-by-zero error.",
97 "PKHA modulus even error.",
98 "DES key parity error.",
99 "ICV check failed.",
100 "Hardware error.",
101 "Unsupported CCM AAD size.",
102 "Class 1 CHA is not reset",
103 "Invalid CHA combination was selected",
104 "Invalid CHA selected.",
105};
106
107static const char * const rng_err_id_list[] = {
108 "",
109 "",
110 "",
111 "Instantiate",
112 "Not instantiated",
113 "Test instantiate",
114 "Prediction resistance",
115 "Prediction resistance and test request",
116 "Uninstantiate",
117 "Secure key generation",
118};
119
120static void report_ccb_status(struct device *jrdev, const u32 status,
121 const char *error)
29{ 122{
123 u8 cha_id = (status & JRSTA_CCBERR_CHAID_MASK) >>
124 JRSTA_CCBERR_CHAID_SHIFT;
125 u8 err_id = status & JRSTA_CCBERR_ERRID_MASK;
30 u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >> 126 u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >>
31 JRSTA_DECOERR_INDEX_SHIFT; 127 JRSTA_DECOERR_INDEX_SHIFT;
128 char *idx_str;
129 const char *cha_str = "unidentified cha_id value 0x";
130 char cha_err_code[3] = { 0 };
131 const char *err_str = "unidentified err_id value 0x";
132 char err_err_code[3] = { 0 };
32 133
33 if (status & JRSTA_DECOERR_JUMP) 134 if (status & JRSTA_DECOERR_JUMP)
34 strcat(outstr, "jump tgt desc idx "); 135 idx_str = "jump tgt desc idx";
35 else 136 else
36 strcat(outstr, "desc idx "); 137 idx_str = "desc idx";
37
38 SPRINTFCAT(outstr, "%d: ", idx, sizeof("255"));
39}
40
41static void report_ccb_status(u32 status, char *outstr)
42{
43 static const char * const cha_id_list[] = {
44 "",
45 "AES",
46 "DES",
47 "ARC4",
48 "MDHA",
49 "RNG",
50 "SNOW f8",
51 "Kasumi f8/9",
52 "PKHA",
53 "CRCA",
54 "SNOW f9",
55 "ZUCE",
56 "ZUCA",
57 };
58 static const char * const err_id_list[] = {
59 "No error.",
60 "Mode error.",
61 "Data size error.",
62 "Key size error.",
63 "PKHA A memory size error.",
64 "PKHA B memory size error.",
65 "Data arrived out of sequence error.",
66 "PKHA divide-by-zero error.",
67 "PKHA modulus even error.",
68 "DES key parity error.",
69 "ICV check failed.",
70 "Hardware error.",
71 "Unsupported CCM AAD size.",
72 "Class 1 CHA is not reset",
73 "Invalid CHA combination was selected",
74 "Invalid CHA selected.",
75 };
76 static const char * const rng_err_id_list[] = {
77 "",
78 "",
79 "",
80 "Instantiate",
81 "Not instantiated",
82 "Test instantiate",
83 "Prediction resistance",
84 "Prediction resistance and test request",
85 "Uninstantiate",
86 "Secure key generation",
87 };
88 u8 cha_id = (status & JRSTA_CCBERR_CHAID_MASK) >>
89 JRSTA_CCBERR_CHAID_SHIFT;
90 u8 err_id = status & JRSTA_CCBERR_ERRID_MASK;
91 138
92 report_jump_idx(status, outstr); 139 if (cha_id < ARRAY_SIZE(cha_id_list))
93 140 cha_str = cha_id_list[cha_id];
94 if (cha_id < ARRAY_SIZE(cha_id_list)) { 141 else
95 SPRINTFCAT(outstr, "%s: ", cha_id_list[cha_id], 142 snprintf(cha_err_code, sizeof(cha_err_code), "%02x", cha_id);
96 strlen(cha_id_list[cha_id]));
97 } else {
98 SPRINTFCAT(outstr, "unidentified cha_id value 0x%02x: ",
99 cha_id, sizeof("ff"));
100 }
101 143
102 if ((cha_id << JRSTA_CCBERR_CHAID_SHIFT) == JRSTA_CCBERR_CHAID_RNG && 144 if ((cha_id << JRSTA_CCBERR_CHAID_SHIFT) == JRSTA_CCBERR_CHAID_RNG &&
103 err_id < ARRAY_SIZE(rng_err_id_list) && 145 err_id < ARRAY_SIZE(rng_err_id_list) &&
104 strlen(rng_err_id_list[err_id])) { 146 strlen(rng_err_id_list[err_id])) {
105 /* RNG-only error */ 147 /* RNG-only error */
106 SPRINTFCAT(outstr, "%s", rng_err_id_list[err_id], 148 err_str = rng_err_id_list[err_id];
107 strlen(rng_err_id_list[err_id])); 149 } else if (err_id < ARRAY_SIZE(err_id_list))
108 } else if (err_id < ARRAY_SIZE(err_id_list)) { 150 err_str = err_id_list[err_id];
109 SPRINTFCAT(outstr, "%s", err_id_list[err_id], 151 else
110 strlen(err_id_list[err_id])); 152 snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id);
111 } else { 153
112 SPRINTFCAT(outstr, "unidentified err_id value 0x%02x", 154 dev_err(jrdev, "%08x: %s: %s %d: %s%s: %s%s\n",
113 err_id, sizeof("ff")); 155 status, error, idx_str, idx,
114 } 156 cha_str, cha_err_code,
157 err_str, err_err_code);
115} 158}
116 159
117static void report_jump_status(u32 status, char *outstr) 160static void report_jump_status(struct device *jrdev, const u32 status,
161 const char *error)
118{ 162{
119 SPRINTFCAT(outstr, "%s() not implemented", __func__, sizeof(__func__)); 163 dev_err(jrdev, "%08x: %s: %s() not implemented\n",
164 status, error, __func__);
120} 165}
121 166
122static void report_deco_status(u32 status, char *outstr) 167static void report_deco_status(struct device *jrdev, const u32 status,
168 const char *error)
123{ 169{
124 static const struct { 170 u8 err_id = status & JRSTA_DECOERR_ERROR_MASK;
125 u8 value; 171 u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >>
126 char *error_text; 172 JRSTA_DECOERR_INDEX_SHIFT;
127 } desc_error_list[] = { 173 char *idx_str;
128 { 0x00, "No error." }, 174 const char *err_str = "unidentified error value 0x";
129 { 0x01, "SGT Length Error. The descriptor is trying to read " 175 char err_err_code[3] = { 0 };
130 "more data than is contained in the SGT table." },
131 { 0x02, "SGT Null Entry Error." },
132 { 0x03, "Job Ring Control Error. There is a bad value in the "
133 "Job Ring Control register." },
134 { 0x04, "Invalid Descriptor Command. The Descriptor Command "
135 "field is invalid." },
136 { 0x05, "Reserved." },
137 { 0x06, "Invalid KEY Command" },
138 { 0x07, "Invalid LOAD Command" },
139 { 0x08, "Invalid STORE Command" },
140 { 0x09, "Invalid OPERATION Command" },
141 { 0x0A, "Invalid FIFO LOAD Command" },
142 { 0x0B, "Invalid FIFO STORE Command" },
143 { 0x0C, "Invalid MOVE/MOVE_LEN Command" },
144 { 0x0D, "Invalid JUMP Command. A nonlocal JUMP Command is "
145 "invalid because the target is not a Job Header "
146 "Command, or the jump is from a Trusted Descriptor to "
147 "a Job Descriptor, or because the target Descriptor "
148 "contains a Shared Descriptor." },
149 { 0x0E, "Invalid MATH Command" },
150 { 0x0F, "Invalid SIGNATURE Command" },
151 { 0x10, "Invalid Sequence Command. A SEQ IN PTR OR SEQ OUT PTR "
152 "Command is invalid or a SEQ KEY, SEQ LOAD, SEQ FIFO "
153 "LOAD, or SEQ FIFO STORE decremented the input or "
154 "output sequence length below 0. This error may result "
155 "if a built-in PROTOCOL Command has encountered a "
156 "malformed PDU." },
157 { 0x11, "Skip data type invalid. The type must be 0xE or 0xF."},
158 { 0x12, "Shared Descriptor Header Error" },
159 { 0x13, "Header Error. Invalid length or parity, or certain "
160 "other problems." },
161 { 0x14, "Burster Error. Burster has gotten to an illegal "
162 "state" },
163 { 0x15, "Context Register Length Error. The descriptor is "
164 "trying to read or write past the end of the Context "
165 "Register. A SEQ LOAD or SEQ STORE with the VLF bit "
166 "set was executed with too large a length in the "
167 "variable length register (VSOL for SEQ STORE or VSIL "
168 "for SEQ LOAD)." },
169 { 0x16, "DMA Error" },
170 { 0x17, "Reserved." },
171 { 0x1A, "Job failed due to JR reset" },
172 { 0x1B, "Job failed due to Fail Mode" },
173 { 0x1C, "DECO Watchdog timer timeout error" },
174 { 0x1D, "DECO tried to copy a key from another DECO but the "
175 "other DECO's Key Registers were locked" },
176 { 0x1E, "DECO attempted to copy data from a DECO that had an "
177 "unmasked Descriptor error" },
178 { 0x1F, "LIODN error. DECO was trying to share from itself or "
179 "from another DECO but the two Non-SEQ LIODN values "
180 "didn't match or the 'shared from' DECO's Descriptor "
181 "required that the SEQ LIODNs be the same and they "
182 "aren't." },
183 { 0x20, "DECO has completed a reset initiated via the DRR "
184 "register" },
185 { 0x21, "Nonce error. When using EKT (CCM) key encryption "
186 "option in the FIFO STORE Command, the Nonce counter "
187 "reached its maximum value and this encryption mode "
188 "can no longer be used." },
189 { 0x22, "Meta data is too large (> 511 bytes) for TLS decap "
190 "(input frame; block ciphers) and IPsec decap (output "
191 "frame, when doing the next header byte update) and "
192 "DCRC (output frame)." },
193 { 0x23, "Read Input Frame error" },
194 { 0x24, "JDKEK, TDKEK or TDSK not loaded error" },
195 { 0x80, "DNR (do not run) error" },
196 { 0x81, "undefined protocol command" },
197 { 0x82, "invalid setting in PDB" },
198 { 0x83, "Anti-replay LATE error" },
199 { 0x84, "Anti-replay REPLAY error" },
200 { 0x85, "Sequence number overflow" },
201 { 0x86, "Sigver invalid signature" },
202 { 0x87, "DSA Sign Illegal test descriptor" },
203 { 0x88, "Protocol Format Error - A protocol has seen an error "
204 "in the format of data received. When running RSA, "
205 "this means that formatting with random padding was "
206 "used, and did not follow the form: 0x00, 0x02, 8-to-N "
207 "bytes of non-zero pad, 0x00, F data." },
208 { 0x89, "Protocol Size Error - A protocol has seen an error in "
209 "size. When running RSA, pdb size N < (size of F) when "
210 "no formatting is used; or pdb size N < (F + 11) when "
211 "formatting is used." },
212 { 0xC1, "Blob Command error: Undefined mode" },
213 { 0xC2, "Blob Command error: Secure Memory Blob mode error" },
214 { 0xC4, "Blob Command error: Black Blob key or input size "
215 "error" },
216 { 0xC5, "Blob Command error: Invalid key destination" },
217 { 0xC8, "Blob Command error: Trusted/Secure mode error" },
218 { 0xF0, "IPsec TTL or hop limit field either came in as 0, "
219 "or was decremented to 0" },
220 { 0xF1, "3GPP HFN matches or exceeds the Threshold" },
221 };
222 u8 desc_error = status & JRSTA_DECOERR_ERROR_MASK;
223 int i; 176 int i;
224 177
225 report_jump_idx(status, outstr); 178 if (status & JRSTA_DECOERR_JUMP)
179 idx_str = "jump tgt desc idx";
180 else
181 idx_str = "desc idx";
226 182
227 for (i = 0; i < ARRAY_SIZE(desc_error_list); i++) 183 for (i = 0; i < ARRAY_SIZE(desc_error_list); i++)
228 if (desc_error_list[i].value == desc_error) 184 if (desc_error_list[i].value == err_id)
229 break; 185 break;
230 186
231 if (i != ARRAY_SIZE(desc_error_list) && desc_error_list[i].error_text) { 187 if (i != ARRAY_SIZE(desc_error_list) && desc_error_list[i].error_text)
232 SPRINTFCAT(outstr, "%s", desc_error_list[i].error_text, 188 err_str = desc_error_list[i].error_text;
233 strlen(desc_error_list[i].error_text)); 189 else
234 } else { 190 snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id);
235 SPRINTFCAT(outstr, "unidentified error value 0x%02x", 191
236 desc_error, sizeof("ff")); 192 dev_err(jrdev, "%08x: %s: %s %d: %s%s\n",
237 } 193 status, error, idx_str, idx, err_str, err_err_code);
238} 194}
239 195
240static void report_jr_status(u32 status, char *outstr) 196static void report_jr_status(struct device *jrdev, const u32 status,
197 const char *error)
241{ 198{
242 SPRINTFCAT(outstr, "%s() not implemented", __func__, sizeof(__func__)); 199 dev_err(jrdev, "%08x: %s: %s() not implemented\n",
200 status, error, __func__);
243} 201}
244 202
245static void report_cond_code_status(u32 status, char *outstr) 203static void report_cond_code_status(struct device *jrdev, const u32 status,
204 const char *error)
246{ 205{
247 SPRINTFCAT(outstr, "%s() not implemented", __func__, sizeof(__func__)); 206 dev_err(jrdev, "%08x: %s: %s() not implemented\n",
207 status, error, __func__);
248} 208}
249 209
250char *caam_jr_strstatus(char *outstr, u32 status) 210void caam_jr_strstatus(struct device *jrdev, u32 status)
251{ 211{
252 static const struct stat_src { 212 static const struct stat_src {
253 void (*report_ssed)(u32 status, char *outstr); 213 void (*report_ssed)(struct device *jrdev, const u32 status,
254 char *error; 214 const char *error);
215 const char *error;
255 } status_src[] = { 216 } status_src[] = {
256 { NULL, "No error" }, 217 { NULL, "No error" },
257 { NULL, NULL }, 218 { NULL, NULL },
@@ -263,12 +224,16 @@ char *caam_jr_strstatus(char *outstr, u32 status)
263 { report_cond_code_status, "Condition Code" }, 224 { report_cond_code_status, "Condition Code" },
264 }; 225 };
265 u32 ssrc = status >> JRSTA_SSRC_SHIFT; 226 u32 ssrc = status >> JRSTA_SSRC_SHIFT;
266 227 const char *error = status_src[ssrc].error;
267 sprintf(outstr, "%s: ", status_src[ssrc].error); 228
268 229 /*
269 if (status_src[ssrc].report_ssed) 230 * If there is no further error handling function, just
270 status_src[ssrc].report_ssed(status, outstr); 231 * print the error code, error string and exit. Otherwise
271 232 * call the handler function.
272 return outstr; 233 */
234 if (!status_src[ssrc].report_ssed)
235 dev_err(jrdev, "%08x: %s: \n", status, status_src[ssrc].error);
236 else
237 status_src[ssrc].report_ssed(jrdev, status, error);
273} 238}
274EXPORT_SYMBOL(caam_jr_strstatus); 239EXPORT_SYMBOL(caam_jr_strstatus);
diff --git a/drivers/crypto/caam/error.h b/drivers/crypto/caam/error.h
index 02c7baa1748e..b6350b0d9153 100644
--- a/drivers/crypto/caam/error.h
+++ b/drivers/crypto/caam/error.h
@@ -7,5 +7,5 @@
7#ifndef CAAM_ERROR_H 7#ifndef CAAM_ERROR_H
8#define CAAM_ERROR_H 8#define CAAM_ERROR_H
9#define CAAM_ERROR_STR_MAX 302 9#define CAAM_ERROR_STR_MAX 302
10extern char *caam_jr_strstatus(char *outstr, u32 status); 10void caam_jr_strstatus(struct device *jrdev, u32 status);
11#endif /* CAAM_ERROR_H */ 11#endif /* CAAM_ERROR_H */
diff --git a/drivers/crypto/caam/key_gen.c b/drivers/crypto/caam/key_gen.c
index ea2e406610eb..871703c49d2c 100644
--- a/drivers/crypto/caam/key_gen.c
+++ b/drivers/crypto/caam/key_gen.c
@@ -19,11 +19,8 @@ void split_key_done(struct device *dev, u32 *desc, u32 err,
19 dev_err(dev, "%s %d: err 0x%x\n", __func__, __LINE__, err); 19 dev_err(dev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
20#endif 20#endif
21 21
22 if (err) { 22 if (err)
23 char tmp[CAAM_ERROR_STR_MAX]; 23 caam_jr_strstatus(dev, err);
24
25 dev_err(dev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
26 }
27 24
28 res->err = err; 25 res->err = err;
29 26
diff --git a/drivers/crypto/ccp/ccp-crypto-aes-xts.c b/drivers/crypto/ccp/ccp-crypto-aes-xts.c
index 0237ab58f242..0cc5594b7de3 100644
--- a/drivers/crypto/ccp/ccp-crypto-aes-xts.c
+++ b/drivers/crypto/ccp/ccp-crypto-aes-xts.c
@@ -191,12 +191,12 @@ static int ccp_aes_xts_cra_init(struct crypto_tfm *tfm)
191 ctx->complete = ccp_aes_xts_complete; 191 ctx->complete = ccp_aes_xts_complete;
192 ctx->u.aes.key_len = 0; 192 ctx->u.aes.key_len = 0;
193 193
194 fallback_tfm = crypto_alloc_ablkcipher(tfm->__crt_alg->cra_name, 0, 194 fallback_tfm = crypto_alloc_ablkcipher(crypto_tfm_alg_name(tfm), 0,
195 CRYPTO_ALG_ASYNC | 195 CRYPTO_ALG_ASYNC |
196 CRYPTO_ALG_NEED_FALLBACK); 196 CRYPTO_ALG_NEED_FALLBACK);
197 if (IS_ERR(fallback_tfm)) { 197 if (IS_ERR(fallback_tfm)) {
198 pr_warn("could not load fallback driver %s\n", 198 pr_warn("could not load fallback driver %s\n",
199 tfm->__crt_alg->cra_name); 199 crypto_tfm_alg_name(tfm));
200 return PTR_ERR(fallback_tfm); 200 return PTR_ERR(fallback_tfm);
201 } 201 }
202 ctx->u.aes.tfm_ablkcipher = fallback_tfm; 202 ctx->u.aes.tfm_ablkcipher = fallback_tfm;
diff --git a/drivers/crypto/ccp/ccp-pci.c b/drivers/crypto/ccp/ccp-pci.c
index 93319f9db753..0d746236df5e 100644
--- a/drivers/crypto/ccp/ccp-pci.c
+++ b/drivers/crypto/ccp/ccp-pci.c
@@ -48,12 +48,11 @@ static int ccp_get_msix_irqs(struct ccp_device *ccp)
48 for (v = 0; v < ARRAY_SIZE(msix_entry); v++) 48 for (v = 0; v < ARRAY_SIZE(msix_entry); v++)
49 msix_entry[v].entry = v; 49 msix_entry[v].entry = v;
50 50
51 while ((ret = pci_enable_msix(pdev, msix_entry, v)) > 0) 51 ret = pci_enable_msix_range(pdev, msix_entry, 1, v);
52 v = ret; 52 if (ret < 0)
53 if (ret)
54 return ret; 53 return ret;
55 54
56 ccp_pci->msix_count = v; 55 ccp_pci->msix_count = ret;
57 for (v = 0; v < ccp_pci->msix_count; v++) { 56 for (v = 0; v < ccp_pci->msix_count; v++) {
58 /* Set the interrupt names and request the irqs */ 57 /* Set the interrupt names and request the irqs */
59 snprintf(ccp_pci->msix[v].name, name_len, "ccp-%u", v); 58 snprintf(ccp_pci->msix[v].name, name_len, "ccp-%u", v);
diff --git a/drivers/crypto/geode-aes.c b/drivers/crypto/geode-aes.c
index 0c9ff4971724..fe538e5287a5 100644
--- a/drivers/crypto/geode-aes.c
+++ b/drivers/crypto/geode-aes.c
@@ -226,7 +226,7 @@ geode_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
226 op->dst = (void *) out; 226 op->dst = (void *) out;
227 op->mode = AES_MODE_ECB; 227 op->mode = AES_MODE_ECB;
228 op->flags = 0; 228 op->flags = 0;
229 op->len = AES_MIN_BLOCK_SIZE; 229 op->len = AES_BLOCK_SIZE;
230 op->dir = AES_DIR_ENCRYPT; 230 op->dir = AES_DIR_ENCRYPT;
231 231
232 geode_aes_crypt(op); 232 geode_aes_crypt(op);
@@ -247,7 +247,7 @@ geode_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
247 op->dst = (void *) out; 247 op->dst = (void *) out;
248 op->mode = AES_MODE_ECB; 248 op->mode = AES_MODE_ECB;
249 op->flags = 0; 249 op->flags = 0;
250 op->len = AES_MIN_BLOCK_SIZE; 250 op->len = AES_BLOCK_SIZE;
251 op->dir = AES_DIR_DECRYPT; 251 op->dir = AES_DIR_DECRYPT;
252 252
253 geode_aes_crypt(op); 253 geode_aes_crypt(op);
@@ -255,7 +255,7 @@ geode_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
255 255
256static int fallback_init_cip(struct crypto_tfm *tfm) 256static int fallback_init_cip(struct crypto_tfm *tfm)
257{ 257{
258 const char *name = tfm->__crt_alg->cra_name; 258 const char *name = crypto_tfm_alg_name(tfm);
259 struct geode_aes_op *op = crypto_tfm_ctx(tfm); 259 struct geode_aes_op *op = crypto_tfm_ctx(tfm);
260 260
261 op->fallback.cip = crypto_alloc_cipher(name, 0, 261 op->fallback.cip = crypto_alloc_cipher(name, 0,
@@ -286,7 +286,7 @@ static struct crypto_alg geode_alg = {
286 CRYPTO_ALG_NEED_FALLBACK, 286 CRYPTO_ALG_NEED_FALLBACK,
287 .cra_init = fallback_init_cip, 287 .cra_init = fallback_init_cip,
288 .cra_exit = fallback_exit_cip, 288 .cra_exit = fallback_exit_cip,
289 .cra_blocksize = AES_MIN_BLOCK_SIZE, 289 .cra_blocksize = AES_BLOCK_SIZE,
290 .cra_ctxsize = sizeof(struct geode_aes_op), 290 .cra_ctxsize = sizeof(struct geode_aes_op),
291 .cra_module = THIS_MODULE, 291 .cra_module = THIS_MODULE,
292 .cra_u = { 292 .cra_u = {
@@ -320,7 +320,7 @@ geode_cbc_decrypt(struct blkcipher_desc *desc,
320 op->src = walk.src.virt.addr, 320 op->src = walk.src.virt.addr,
321 op->dst = walk.dst.virt.addr; 321 op->dst = walk.dst.virt.addr;
322 op->mode = AES_MODE_CBC; 322 op->mode = AES_MODE_CBC;
323 op->len = nbytes - (nbytes % AES_MIN_BLOCK_SIZE); 323 op->len = nbytes - (nbytes % AES_BLOCK_SIZE);
324 op->dir = AES_DIR_DECRYPT; 324 op->dir = AES_DIR_DECRYPT;
325 325
326 ret = geode_aes_crypt(op); 326 ret = geode_aes_crypt(op);
@@ -352,7 +352,7 @@ geode_cbc_encrypt(struct blkcipher_desc *desc,
352 op->src = walk.src.virt.addr, 352 op->src = walk.src.virt.addr,
353 op->dst = walk.dst.virt.addr; 353 op->dst = walk.dst.virt.addr;
354 op->mode = AES_MODE_CBC; 354 op->mode = AES_MODE_CBC;
355 op->len = nbytes - (nbytes % AES_MIN_BLOCK_SIZE); 355 op->len = nbytes - (nbytes % AES_BLOCK_SIZE);
356 op->dir = AES_DIR_ENCRYPT; 356 op->dir = AES_DIR_ENCRYPT;
357 357
358 ret = geode_aes_crypt(op); 358 ret = geode_aes_crypt(op);
@@ -365,7 +365,7 @@ geode_cbc_encrypt(struct blkcipher_desc *desc,
365 365
366static int fallback_init_blk(struct crypto_tfm *tfm) 366static int fallback_init_blk(struct crypto_tfm *tfm)
367{ 367{
368 const char *name = tfm->__crt_alg->cra_name; 368 const char *name = crypto_tfm_alg_name(tfm);
369 struct geode_aes_op *op = crypto_tfm_ctx(tfm); 369 struct geode_aes_op *op = crypto_tfm_ctx(tfm);
370 370
371 op->fallback.blk = crypto_alloc_blkcipher(name, 0, 371 op->fallback.blk = crypto_alloc_blkcipher(name, 0,
@@ -396,7 +396,7 @@ static struct crypto_alg geode_cbc_alg = {
396 CRYPTO_ALG_NEED_FALLBACK, 396 CRYPTO_ALG_NEED_FALLBACK,
397 .cra_init = fallback_init_blk, 397 .cra_init = fallback_init_blk,
398 .cra_exit = fallback_exit_blk, 398 .cra_exit = fallback_exit_blk,
399 .cra_blocksize = AES_MIN_BLOCK_SIZE, 399 .cra_blocksize = AES_BLOCK_SIZE,
400 .cra_ctxsize = sizeof(struct geode_aes_op), 400 .cra_ctxsize = sizeof(struct geode_aes_op),
401 .cra_alignmask = 15, 401 .cra_alignmask = 15,
402 .cra_type = &crypto_blkcipher_type, 402 .cra_type = &crypto_blkcipher_type,
@@ -408,7 +408,7 @@ static struct crypto_alg geode_cbc_alg = {
408 .setkey = geode_setkey_blk, 408 .setkey = geode_setkey_blk,
409 .encrypt = geode_cbc_encrypt, 409 .encrypt = geode_cbc_encrypt,
410 .decrypt = geode_cbc_decrypt, 410 .decrypt = geode_cbc_decrypt,
411 .ivsize = AES_IV_LENGTH, 411 .ivsize = AES_BLOCK_SIZE,
412 } 412 }
413 } 413 }
414}; 414};
@@ -432,7 +432,7 @@ geode_ecb_decrypt(struct blkcipher_desc *desc,
432 op->src = walk.src.virt.addr, 432 op->src = walk.src.virt.addr,
433 op->dst = walk.dst.virt.addr; 433 op->dst = walk.dst.virt.addr;
434 op->mode = AES_MODE_ECB; 434 op->mode = AES_MODE_ECB;
435 op->len = nbytes - (nbytes % AES_MIN_BLOCK_SIZE); 435 op->len = nbytes - (nbytes % AES_BLOCK_SIZE);
436 op->dir = AES_DIR_DECRYPT; 436 op->dir = AES_DIR_DECRYPT;
437 437
438 ret = geode_aes_crypt(op); 438 ret = geode_aes_crypt(op);
@@ -462,7 +462,7 @@ geode_ecb_encrypt(struct blkcipher_desc *desc,
462 op->src = walk.src.virt.addr, 462 op->src = walk.src.virt.addr,
463 op->dst = walk.dst.virt.addr; 463 op->dst = walk.dst.virt.addr;
464 op->mode = AES_MODE_ECB; 464 op->mode = AES_MODE_ECB;
465 op->len = nbytes - (nbytes % AES_MIN_BLOCK_SIZE); 465 op->len = nbytes - (nbytes % AES_BLOCK_SIZE);
466 op->dir = AES_DIR_ENCRYPT; 466 op->dir = AES_DIR_ENCRYPT;
467 467
468 ret = geode_aes_crypt(op); 468 ret = geode_aes_crypt(op);
@@ -482,7 +482,7 @@ static struct crypto_alg geode_ecb_alg = {
482 CRYPTO_ALG_NEED_FALLBACK, 482 CRYPTO_ALG_NEED_FALLBACK,
483 .cra_init = fallback_init_blk, 483 .cra_init = fallback_init_blk,
484 .cra_exit = fallback_exit_blk, 484 .cra_exit = fallback_exit_blk,
485 .cra_blocksize = AES_MIN_BLOCK_SIZE, 485 .cra_blocksize = AES_BLOCK_SIZE,
486 .cra_ctxsize = sizeof(struct geode_aes_op), 486 .cra_ctxsize = sizeof(struct geode_aes_op),
487 .cra_alignmask = 15, 487 .cra_alignmask = 15,
488 .cra_type = &crypto_blkcipher_type, 488 .cra_type = &crypto_blkcipher_type,
@@ -547,7 +547,7 @@ static int geode_aes_probe(struct pci_dev *dev, const struct pci_device_id *id)
547 if (ret) 547 if (ret)
548 goto eecb; 548 goto eecb;
549 549
550 printk(KERN_NOTICE "geode-aes: GEODE AES engine enabled.\n"); 550 dev_notice(&dev->dev, "GEODE AES engine enabled.\n");
551 return 0; 551 return 0;
552 552
553 eecb: 553 eecb:
@@ -565,7 +565,7 @@ static int geode_aes_probe(struct pci_dev *dev, const struct pci_device_id *id)
565 eenable: 565 eenable:
566 pci_disable_device(dev); 566 pci_disable_device(dev);
567 567
568 printk(KERN_ERR "geode-aes: GEODE AES initialization failed.\n"); 568 dev_err(&dev->dev, "GEODE AES initialization failed.\n");
569 return ret; 569 return ret;
570} 570}
571 571
diff --git a/drivers/crypto/geode-aes.h b/drivers/crypto/geode-aes.h
index f1855b50da48..f442ca972e3c 100644
--- a/drivers/crypto/geode-aes.h
+++ b/drivers/crypto/geode-aes.h
@@ -10,10 +10,6 @@
10#define _GEODE_AES_H_ 10#define _GEODE_AES_H_
11 11
12/* driver logic flags */ 12/* driver logic flags */
13#define AES_IV_LENGTH 16
14#define AES_KEY_LENGTH 16
15#define AES_MIN_BLOCK_SIZE 16
16
17#define AES_MODE_ECB 0 13#define AES_MODE_ECB 0
18#define AES_MODE_CBC 1 14#define AES_MODE_CBC 1
19 15
@@ -64,7 +60,7 @@ struct geode_aes_op {
64 u32 flags; 60 u32 flags;
65 int len; 61 int len;
66 62
67 u8 key[AES_KEY_LENGTH]; 63 u8 key[AES_KEYSIZE_128];
68 u8 *iv; 64 u8 *iv;
69 65
70 union { 66 union {
diff --git a/drivers/crypto/mv_cesa.c b/drivers/crypto/mv_cesa.c
index 8d1e6f8e9e9c..29d0ee504907 100644
--- a/drivers/crypto/mv_cesa.c
+++ b/drivers/crypto/mv_cesa.c
@@ -622,8 +622,8 @@ static int queue_manag(void *data)
622 } 622 }
623 623
624 if (async_req) { 624 if (async_req) {
625 if (async_req->tfm->__crt_alg->cra_type != 625 if (crypto_tfm_alg_type(async_req->tfm) !=
626 &crypto_ahash_type) { 626 CRYPTO_ALG_TYPE_AHASH) {
627 struct ablkcipher_request *req = 627 struct ablkcipher_request *req =
628 ablkcipher_request_cast(async_req); 628 ablkcipher_request_cast(async_req);
629 mv_start_new_crypt_req(req); 629 mv_start_new_crypt_req(req);
@@ -843,7 +843,7 @@ static int mv_hash_setkey(struct crypto_ahash *tfm, const u8 * key,
843static int mv_cra_hash_init(struct crypto_tfm *tfm, const char *base_hash_name, 843static int mv_cra_hash_init(struct crypto_tfm *tfm, const char *base_hash_name,
844 enum hash_op op, int count_add) 844 enum hash_op op, int count_add)
845{ 845{
846 const char *fallback_driver_name = tfm->__crt_alg->cra_name; 846 const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
847 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm); 847 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
848 struct crypto_shash *fallback_tfm = NULL; 848 struct crypto_shash *fallback_tfm = NULL;
849 struct crypto_shash *base_hash = NULL; 849 struct crypto_shash *base_hash = NULL;
diff --git a/drivers/crypto/mxs-dcp.c b/drivers/crypto/mxs-dcp.c
index 7bbe0ab21eca..b5f7e6db24d4 100644
--- a/drivers/crypto/mxs-dcp.c
+++ b/drivers/crypto/mxs-dcp.c
@@ -104,7 +104,6 @@ struct dcp_sha_req_ctx {
104 * design of Linux Crypto API. 104 * design of Linux Crypto API.
105 */ 105 */
106static struct dcp *global_sdcp; 106static struct dcp *global_sdcp;
107static DEFINE_MUTEX(global_mutex);
108 107
109/* DCP register layout. */ 108/* DCP register layout. */
110#define MXS_DCP_CTRL 0x00 109#define MXS_DCP_CTRL 0x00
@@ -482,7 +481,7 @@ static int mxs_dcp_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
482 481
483static int mxs_dcp_aes_fallback_init(struct crypto_tfm *tfm) 482static int mxs_dcp_aes_fallback_init(struct crypto_tfm *tfm)
484{ 483{
485 const char *name = tfm->__crt_alg->cra_name; 484 const char *name = crypto_tfm_alg_name(tfm);
486 const uint32_t flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK; 485 const uint32_t flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK;
487 struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm); 486 struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm);
488 struct crypto_ablkcipher *blk; 487 struct crypto_ablkcipher *blk;
@@ -907,60 +906,49 @@ static int mxs_dcp_probe(struct platform_device *pdev)
907 struct resource *iores; 906 struct resource *iores;
908 int dcp_vmi_irq, dcp_irq; 907 int dcp_vmi_irq, dcp_irq;
909 908
910 mutex_lock(&global_mutex);
911 if (global_sdcp) { 909 if (global_sdcp) {
912 dev_err(dev, "Only one DCP instance allowed!\n"); 910 dev_err(dev, "Only one DCP instance allowed!\n");
913 ret = -ENODEV; 911 return -ENODEV;
914 goto err_mutex;
915 } 912 }
916 913
917 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 914 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
918 dcp_vmi_irq = platform_get_irq(pdev, 0); 915 dcp_vmi_irq = platform_get_irq(pdev, 0);
919 if (dcp_vmi_irq < 0) { 916 if (dcp_vmi_irq < 0)
920 ret = dcp_vmi_irq; 917 return dcp_vmi_irq;
921 goto err_mutex;
922 }
923 918
924 dcp_irq = platform_get_irq(pdev, 1); 919 dcp_irq = platform_get_irq(pdev, 1);
925 if (dcp_irq < 0) { 920 if (dcp_irq < 0)
926 ret = dcp_irq; 921 return dcp_irq;
927 goto err_mutex;
928 }
929 922
930 sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL); 923 sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL);
931 if (!sdcp) { 924 if (!sdcp)
932 ret = -ENOMEM; 925 return -ENOMEM;
933 goto err_mutex;
934 }
935 926
936 sdcp->dev = dev; 927 sdcp->dev = dev;
937 sdcp->base = devm_ioremap_resource(dev, iores); 928 sdcp->base = devm_ioremap_resource(dev, iores);
938 if (IS_ERR(sdcp->base)) { 929 if (IS_ERR(sdcp->base))
939 ret = PTR_ERR(sdcp->base); 930 return PTR_ERR(sdcp->base);
940 goto err_mutex; 931
941 }
942 932
943 ret = devm_request_irq(dev, dcp_vmi_irq, mxs_dcp_irq, 0, 933 ret = devm_request_irq(dev, dcp_vmi_irq, mxs_dcp_irq, 0,
944 "dcp-vmi-irq", sdcp); 934 "dcp-vmi-irq", sdcp);
945 if (ret) { 935 if (ret) {
946 dev_err(dev, "Failed to claim DCP VMI IRQ!\n"); 936 dev_err(dev, "Failed to claim DCP VMI IRQ!\n");
947 goto err_mutex; 937 return ret;
948 } 938 }
949 939
950 ret = devm_request_irq(dev, dcp_irq, mxs_dcp_irq, 0, 940 ret = devm_request_irq(dev, dcp_irq, mxs_dcp_irq, 0,
951 "dcp-irq", sdcp); 941 "dcp-irq", sdcp);
952 if (ret) { 942 if (ret) {
953 dev_err(dev, "Failed to claim DCP IRQ!\n"); 943 dev_err(dev, "Failed to claim DCP IRQ!\n");
954 goto err_mutex; 944 return ret;
955 } 945 }
956 946
957 /* Allocate coherent helper block. */ 947 /* Allocate coherent helper block. */
958 sdcp->coh = devm_kzalloc(dev, sizeof(*sdcp->coh) + DCP_ALIGNMENT, 948 sdcp->coh = devm_kzalloc(dev, sizeof(*sdcp->coh) + DCP_ALIGNMENT,
959 GFP_KERNEL); 949 GFP_KERNEL);
960 if (!sdcp->coh) { 950 if (!sdcp->coh)
961 ret = -ENOMEM; 951 return -ENOMEM;
962 goto err_mutex;
963 }
964 952
965 /* Re-align the structure so it fits the DCP constraints. */ 953 /* Re-align the structure so it fits the DCP constraints. */
966 sdcp->coh = PTR_ALIGN(sdcp->coh, DCP_ALIGNMENT); 954 sdcp->coh = PTR_ALIGN(sdcp->coh, DCP_ALIGNMENT);
@@ -968,7 +956,7 @@ static int mxs_dcp_probe(struct platform_device *pdev)
968 /* Restart the DCP block. */ 956 /* Restart the DCP block. */
969 ret = stmp_reset_block(sdcp->base); 957 ret = stmp_reset_block(sdcp->base);
970 if (ret) 958 if (ret)
971 goto err_mutex; 959 return ret;
972 960
973 /* Initialize control register. */ 961 /* Initialize control register. */
974 writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES | 962 writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES |
@@ -1006,8 +994,7 @@ static int mxs_dcp_probe(struct platform_device *pdev)
1006 NULL, "mxs_dcp_chan/sha"); 994 NULL, "mxs_dcp_chan/sha");
1007 if (IS_ERR(sdcp->thread[DCP_CHAN_HASH_SHA])) { 995 if (IS_ERR(sdcp->thread[DCP_CHAN_HASH_SHA])) {
1008 dev_err(dev, "Error starting SHA thread!\n"); 996 dev_err(dev, "Error starting SHA thread!\n");
1009 ret = PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]); 997 return PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]);
1010 goto err_mutex;
1011 } 998 }
1012 999
1013 sdcp->thread[DCP_CHAN_CRYPTO] = kthread_run(dcp_chan_thread_aes, 1000 sdcp->thread[DCP_CHAN_CRYPTO] = kthread_run(dcp_chan_thread_aes,
@@ -1064,9 +1051,6 @@ err_destroy_aes_thread:
1064 1051
1065err_destroy_sha_thread: 1052err_destroy_sha_thread:
1066 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]); 1053 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1067
1068err_mutex:
1069 mutex_unlock(&global_mutex);
1070 return ret; 1054 return ret;
1071} 1055}
1072 1056
@@ -1088,9 +1072,7 @@ static int mxs_dcp_remove(struct platform_device *pdev)
1088 1072
1089 platform_set_drvdata(pdev, NULL); 1073 platform_set_drvdata(pdev, NULL);
1090 1074
1091 mutex_lock(&global_mutex);
1092 global_sdcp = NULL; 1075 global_sdcp = NULL;
1093 mutex_unlock(&global_mutex);
1094 1076
1095 return 0; 1077 return 0;
1096} 1078}
diff --git a/drivers/crypto/n2_core.c b/drivers/crypto/n2_core.c
index e1f0ab413c3b..7263c10a56ee 100644
--- a/drivers/crypto/n2_core.c
+++ b/drivers/crypto/n2_core.c
@@ -356,7 +356,7 @@ static int n2_hash_async_finup(struct ahash_request *req)
356 356
357static int n2_hash_cra_init(struct crypto_tfm *tfm) 357static int n2_hash_cra_init(struct crypto_tfm *tfm)
358{ 358{
359 const char *fallback_driver_name = tfm->__crt_alg->cra_name; 359 const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
360 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm); 360 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
361 struct n2_hash_ctx *ctx = crypto_ahash_ctx(ahash); 361 struct n2_hash_ctx *ctx = crypto_ahash_ctx(ahash);
362 struct crypto_ahash *fallback_tfm; 362 struct crypto_ahash *fallback_tfm;
@@ -391,7 +391,7 @@ static void n2_hash_cra_exit(struct crypto_tfm *tfm)
391 391
392static int n2_hmac_cra_init(struct crypto_tfm *tfm) 392static int n2_hmac_cra_init(struct crypto_tfm *tfm)
393{ 393{
394 const char *fallback_driver_name = tfm->__crt_alg->cra_name; 394 const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
395 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm); 395 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
396 struct n2_hmac_ctx *ctx = crypto_ahash_ctx(ahash); 396 struct n2_hmac_ctx *ctx = crypto_ahash_ctx(ahash);
397 struct n2_hmac_alg *n2alg = n2_hmac_alg(tfm); 397 struct n2_hmac_alg *n2alg = n2_hmac_alg(tfm);
diff --git a/drivers/crypto/nx/nx-842.c b/drivers/crypto/nx/nx-842.c
index 5ce8b5765121..502edf0a2933 100644
--- a/drivers/crypto/nx/nx-842.c
+++ b/drivers/crypto/nx/nx-842.c
@@ -1229,7 +1229,7 @@ static int __exit nx842_remove(struct vio_dev *viodev)
1229 old_devdata = rcu_dereference_check(devdata, 1229 old_devdata = rcu_dereference_check(devdata,
1230 lockdep_is_held(&devdata_mutex)); 1230 lockdep_is_held(&devdata_mutex));
1231 of_reconfig_notifier_unregister(&nx842_of_nb); 1231 of_reconfig_notifier_unregister(&nx842_of_nb);
1232 rcu_assign_pointer(devdata, NULL); 1232 RCU_INIT_POINTER(devdata, NULL);
1233 spin_unlock_irqrestore(&devdata_mutex, flags); 1233 spin_unlock_irqrestore(&devdata_mutex, flags);
1234 synchronize_rcu(); 1234 synchronize_rcu();
1235 dev_set_drvdata(&viodev->dev, NULL); 1235 dev_set_drvdata(&viodev->dev, NULL);
@@ -1280,7 +1280,7 @@ static void __exit nx842_exit(void)
1280 spin_lock_irqsave(&devdata_mutex, flags); 1280 spin_lock_irqsave(&devdata_mutex, flags);
1281 old_devdata = rcu_dereference_check(devdata, 1281 old_devdata = rcu_dereference_check(devdata,
1282 lockdep_is_held(&devdata_mutex)); 1282 lockdep_is_held(&devdata_mutex));
1283 rcu_assign_pointer(devdata, NULL); 1283 RCU_INIT_POINTER(devdata, NULL);
1284 spin_unlock_irqrestore(&devdata_mutex, flags); 1284 spin_unlock_irqrestore(&devdata_mutex, flags);
1285 synchronize_rcu(); 1285 synchronize_rcu();
1286 if (old_devdata) 1286 if (old_devdata)
diff --git a/drivers/crypto/omap-des.c b/drivers/crypto/omap-des.c
index ec5f13162b73..b8bc84be8741 100644
--- a/drivers/crypto/omap-des.c
+++ b/drivers/crypto/omap-des.c
@@ -223,12 +223,19 @@ static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
223 223
224static int omap_des_hw_init(struct omap_des_dev *dd) 224static int omap_des_hw_init(struct omap_des_dev *dd)
225{ 225{
226 int err;
227
226 /* 228 /*
227 * clocks are enabled when request starts and disabled when finished. 229 * clocks are enabled when request starts and disabled when finished.
228 * It may be long delays between requests. 230 * It may be long delays between requests.
229 * Device might go to off mode to save power. 231 * Device might go to off mode to save power.
230 */ 232 */
231 pm_runtime_get_sync(dd->dev); 233 err = pm_runtime_get_sync(dd->dev);
234 if (err < 0) {
235 pm_runtime_put_noidle(dd->dev);
236 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
237 return err;
238 }
232 239
233 if (!(dd->flags & FLAGS_INIT)) { 240 if (!(dd->flags & FLAGS_INIT)) {
234 dd->flags |= FLAGS_INIT; 241 dd->flags |= FLAGS_INIT;
@@ -1074,16 +1081,20 @@ static int omap_des_probe(struct platform_device *pdev)
1074 if (err) 1081 if (err)
1075 goto err_res; 1082 goto err_res;
1076 1083
1077 dd->io_base = devm_request_and_ioremap(dev, res); 1084 dd->io_base = devm_ioremap_resource(dev, res);
1078 if (!dd->io_base) { 1085 if (IS_ERR(dd->io_base)) {
1079 dev_err(dev, "can't ioremap\n"); 1086 err = PTR_ERR(dd->io_base);
1080 err = -ENOMEM;
1081 goto err_res; 1087 goto err_res;
1082 } 1088 }
1083 dd->phys_base = res->start; 1089 dd->phys_base = res->start;
1084 1090
1085 pm_runtime_enable(dev); 1091 pm_runtime_enable(dev);
1086 pm_runtime_get_sync(dev); 1092 err = pm_runtime_get_sync(dev);
1093 if (err < 0) {
1094 pm_runtime_put_noidle(dev);
1095 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
1096 goto err_get;
1097 }
1087 1098
1088 omap_des_dma_stop(dd); 1099 omap_des_dma_stop(dd);
1089 1100
@@ -1148,6 +1159,7 @@ err_algs:
1148err_irq: 1159err_irq:
1149 tasklet_kill(&dd->done_task); 1160 tasklet_kill(&dd->done_task);
1150 tasklet_kill(&dd->queue_task); 1161 tasklet_kill(&dd->queue_task);
1162err_get:
1151 pm_runtime_disable(dev); 1163 pm_runtime_disable(dev);
1152err_res: 1164err_res:
1153 dd = NULL; 1165 dd = NULL;
@@ -1191,7 +1203,14 @@ static int omap_des_suspend(struct device *dev)
1191 1203
1192static int omap_des_resume(struct device *dev) 1204static int omap_des_resume(struct device *dev)
1193{ 1205{
1194 pm_runtime_get_sync(dev); 1206 int err;
1207
1208 err = pm_runtime_get_sync(dev);
1209 if (err < 0) {
1210 pm_runtime_put_noidle(dev);
1211 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err);
1212 return err;
1213 }
1195 return 0; 1214 return 0;
1196} 1215}
1197#endif 1216#endif
diff --git a/drivers/crypto/padlock-sha.c b/drivers/crypto/padlock-sha.c
index 9266c0e25492..bace885634f2 100644
--- a/drivers/crypto/padlock-sha.c
+++ b/drivers/crypto/padlock-sha.c
@@ -211,7 +211,7 @@ static int padlock_sha256_final(struct shash_desc *desc, u8 *out)
211static int padlock_cra_init(struct crypto_tfm *tfm) 211static int padlock_cra_init(struct crypto_tfm *tfm)
212{ 212{
213 struct crypto_shash *hash = __crypto_shash_cast(tfm); 213 struct crypto_shash *hash = __crypto_shash_cast(tfm);
214 const char *fallback_driver_name = tfm->__crt_alg->cra_name; 214 const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
215 struct padlock_sha_ctx *ctx = crypto_tfm_ctx(tfm); 215 struct padlock_sha_ctx *ctx = crypto_tfm_ctx(tfm);
216 struct crypto_shash *fallback_tfm; 216 struct crypto_shash *fallback_tfm;
217 int err = -ENOMEM; 217 int err = -ENOMEM;
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index be45762f390a..4197ad9a711b 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -22,6 +22,7 @@
22#include <linux/scatterlist.h> 22#include <linux/scatterlist.h>
23#include <linux/dma-mapping.h> 23#include <linux/dma-mapping.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/of.h>
25#include <linux/crypto.h> 26#include <linux/crypto.h>
26#include <linux/interrupt.h> 27#include <linux/interrupt.h>
27 28
@@ -29,9 +30,6 @@
29#include <crypto/aes.h> 30#include <crypto/aes.h>
30#include <crypto/ctr.h> 31#include <crypto/ctr.h>
31 32
32#include <plat/cpu.h>
33#include <mach/dma.h>
34
35#define _SBF(s, v) ((v) << (s)) 33#define _SBF(s, v) ((v) << (s))
36#define _BIT(b) _SBF(b, 1) 34#define _BIT(b) _SBF(b, 1)
37 35
@@ -105,7 +103,7 @@
105#define SSS_REG_FCPKDMAO 0x005C 103#define SSS_REG_FCPKDMAO 0x005C
106 104
107/* AES registers */ 105/* AES registers */
108#define SSS_REG_AES_CONTROL 0x4000 106#define SSS_REG_AES_CONTROL 0x00
109#define SSS_AES_BYTESWAP_DI _BIT(11) 107#define SSS_AES_BYTESWAP_DI _BIT(11)
110#define SSS_AES_BYTESWAP_DO _BIT(10) 108#define SSS_AES_BYTESWAP_DO _BIT(10)
111#define SSS_AES_BYTESWAP_IV _BIT(9) 109#define SSS_AES_BYTESWAP_IV _BIT(9)
@@ -121,21 +119,25 @@
121#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02) 119#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
122#define SSS_AES_MODE_DECRYPT _BIT(0) 120#define SSS_AES_MODE_DECRYPT _BIT(0)
123 121
124#define SSS_REG_AES_STATUS 0x4004 122#define SSS_REG_AES_STATUS 0x04
125#define SSS_AES_BUSY _BIT(2) 123#define SSS_AES_BUSY _BIT(2)
126#define SSS_AES_INPUT_READY _BIT(1) 124#define SSS_AES_INPUT_READY _BIT(1)
127#define SSS_AES_OUTPUT_READY _BIT(0) 125#define SSS_AES_OUTPUT_READY _BIT(0)
128 126
129#define SSS_REG_AES_IN_DATA(s) (0x4010 + (s << 2)) 127#define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2))
130#define SSS_REG_AES_OUT_DATA(s) (0x4020 + (s << 2)) 128#define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2))
131#define SSS_REG_AES_IV_DATA(s) (0x4030 + (s << 2)) 129#define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2))
132#define SSS_REG_AES_CNT_DATA(s) (0x4040 + (s << 2)) 130#define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2))
133#define SSS_REG_AES_KEY_DATA(s) (0x4080 + (s << 2)) 131#define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2))
134 132
135#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg)) 133#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
136#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg)) 134#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
137#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg)) 135#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))
138 136
137#define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg)
138#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
139 SSS_AES_REG(dev, reg))
140
139/* HW engine modes */ 141/* HW engine modes */
140#define FLAGS_AES_DECRYPT _BIT(0) 142#define FLAGS_AES_DECRYPT _BIT(0)
141#define FLAGS_AES_MODE_MASK _SBF(1, 0x03) 143#define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
@@ -145,6 +147,20 @@
145#define AES_KEY_LEN 16 147#define AES_KEY_LEN 16
146#define CRYPTO_QUEUE_LEN 1 148#define CRYPTO_QUEUE_LEN 1
147 149
150/**
151 * struct samsung_aes_variant - platform specific SSS driver data
152 * @has_hash_irq: true if SSS module uses hash interrupt, false otherwise
153 * @aes_offset: AES register offset from SSS module's base.
154 *
155 * Specifies platform specific configuration of SSS module.
156 * Note: A structure for driver specific platform data is used for future
157 * expansion of its usage.
158 */
159struct samsung_aes_variant {
160 bool has_hash_irq;
161 unsigned int aes_offset;
162};
163
148struct s5p_aes_reqctx { 164struct s5p_aes_reqctx {
149 unsigned long mode; 165 unsigned long mode;
150}; 166};
@@ -161,6 +177,7 @@ struct s5p_aes_dev {
161 struct device *dev; 177 struct device *dev;
162 struct clk *clk; 178 struct clk *clk;
163 void __iomem *ioaddr; 179 void __iomem *ioaddr;
180 void __iomem *aes_ioaddr;
164 int irq_hash; 181 int irq_hash;
165 int irq_fc; 182 int irq_fc;
166 183
@@ -173,10 +190,48 @@ struct s5p_aes_dev {
173 struct crypto_queue queue; 190 struct crypto_queue queue;
174 bool busy; 191 bool busy;
175 spinlock_t lock; 192 spinlock_t lock;
193
194 struct samsung_aes_variant *variant;
176}; 195};
177 196
178static struct s5p_aes_dev *s5p_dev; 197static struct s5p_aes_dev *s5p_dev;
179 198
199static const struct samsung_aes_variant s5p_aes_data = {
200 .has_hash_irq = true,
201 .aes_offset = 0x4000,
202};
203
204static const struct samsung_aes_variant exynos_aes_data = {
205 .has_hash_irq = false,
206 .aes_offset = 0x200,
207};
208
209static const struct of_device_id s5p_sss_dt_match[] = {
210 {
211 .compatible = "samsung,s5pv210-secss",
212 .data = &s5p_aes_data,
213 },
214 {
215 .compatible = "samsung,exynos4210-secss",
216 .data = &exynos_aes_data,
217 },
218 { },
219};
220MODULE_DEVICE_TABLE(of, s5p_sss_dt_match);
221
222static inline struct samsung_aes_variant *find_s5p_sss_version
223 (struct platform_device *pdev)
224{
225 if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) {
226 const struct of_device_id *match;
227 match = of_match_node(s5p_sss_dt_match,
228 pdev->dev.of_node);
229 return (struct samsung_aes_variant *)match->data;
230 }
231 return (struct samsung_aes_variant *)
232 platform_get_device_id(pdev)->driver_data;
233}
234
180static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg) 235static void s5p_set_dma_indata(struct s5p_aes_dev *dev, struct scatterlist *sg)
181{ 236{
182 SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg)); 237 SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg));
@@ -272,8 +327,12 @@ static void s5p_aes_tx(struct s5p_aes_dev *dev)
272 } 327 }
273 328
274 s5p_set_dma_outdata(dev, dev->sg_dst); 329 s5p_set_dma_outdata(dev, dev->sg_dst);
275 } else 330 } else {
276 s5p_aes_complete(dev, err); 331 s5p_aes_complete(dev, err);
332
333 dev->busy = true;
334 tasklet_schedule(&dev->tasklet);
335 }
277} 336}
278 337
279static void s5p_aes_rx(struct s5p_aes_dev *dev) 338static void s5p_aes_rx(struct s5p_aes_dev *dev)
@@ -322,14 +381,15 @@ static void s5p_set_aes(struct s5p_aes_dev *dev,
322{ 381{
323 void __iomem *keystart; 382 void __iomem *keystart;
324 383
325 memcpy(dev->ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10); 384 if (iv)
385 memcpy(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 0x10);
326 386
327 if (keylen == AES_KEYSIZE_256) 387 if (keylen == AES_KEYSIZE_256)
328 keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(0); 388 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0);
329 else if (keylen == AES_KEYSIZE_192) 389 else if (keylen == AES_KEYSIZE_192)
330 keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(2); 390 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2);
331 else 391 else
332 keystart = dev->ioaddr + SSS_REG_AES_KEY_DATA(4); 392 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4);
333 393
334 memcpy(keystart, key, keylen); 394 memcpy(keystart, key, keylen);
335} 395}
@@ -379,7 +439,7 @@ static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
379 if (err) 439 if (err)
380 goto outdata_error; 440 goto outdata_error;
381 441
382 SSS_WRITE(dev, AES_CONTROL, aes_control); 442 SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
383 s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen); 443 s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen);
384 444
385 s5p_set_dma_indata(dev, req->src); 445 s5p_set_dma_indata(dev, req->src);
@@ -410,10 +470,13 @@ static void s5p_tasklet_cb(unsigned long data)
410 spin_lock_irqsave(&dev->lock, flags); 470 spin_lock_irqsave(&dev->lock, flags);
411 backlog = crypto_get_backlog(&dev->queue); 471 backlog = crypto_get_backlog(&dev->queue);
412 async_req = crypto_dequeue_request(&dev->queue); 472 async_req = crypto_dequeue_request(&dev->queue);
413 spin_unlock_irqrestore(&dev->lock, flags);
414 473
415 if (!async_req) 474 if (!async_req) {
475 dev->busy = false;
476 spin_unlock_irqrestore(&dev->lock, flags);
416 return; 477 return;
478 }
479 spin_unlock_irqrestore(&dev->lock, flags);
417 480
418 if (backlog) 481 if (backlog)
419 backlog->complete(backlog, -EINPROGRESS); 482 backlog->complete(backlog, -EINPROGRESS);
@@ -432,14 +495,13 @@ static int s5p_aes_handle_req(struct s5p_aes_dev *dev,
432 int err; 495 int err;
433 496
434 spin_lock_irqsave(&dev->lock, flags); 497 spin_lock_irqsave(&dev->lock, flags);
498 err = ablkcipher_enqueue_request(&dev->queue, req);
435 if (dev->busy) { 499 if (dev->busy) {
436 err = -EAGAIN;
437 spin_unlock_irqrestore(&dev->lock, flags); 500 spin_unlock_irqrestore(&dev->lock, flags);
438 goto exit; 501 goto exit;
439 } 502 }
440 dev->busy = true; 503 dev->busy = true;
441 504
442 err = ablkcipher_enqueue_request(&dev->queue, req);
443 spin_unlock_irqrestore(&dev->lock, flags); 505 spin_unlock_irqrestore(&dev->lock, flags);
444 506
445 tasklet_schedule(&dev->tasklet); 507 tasklet_schedule(&dev->tasklet);
@@ -564,6 +626,7 @@ static int s5p_aes_probe(struct platform_device *pdev)
564 struct s5p_aes_dev *pdata; 626 struct s5p_aes_dev *pdata;
565 struct device *dev = &pdev->dev; 627 struct device *dev = &pdev->dev;
566 struct resource *res; 628 struct resource *res;
629 struct samsung_aes_variant *variant;
567 630
568 if (s5p_dev) 631 if (s5p_dev)
569 return -EEXIST; 632 return -EEXIST;
@@ -577,30 +640,25 @@ static int s5p_aes_probe(struct platform_device *pdev)
577 if (IS_ERR(pdata->ioaddr)) 640 if (IS_ERR(pdata->ioaddr))
578 return PTR_ERR(pdata->ioaddr); 641 return PTR_ERR(pdata->ioaddr);
579 642
643 variant = find_s5p_sss_version(pdev);
644
580 pdata->clk = devm_clk_get(dev, "secss"); 645 pdata->clk = devm_clk_get(dev, "secss");
581 if (IS_ERR(pdata->clk)) { 646 if (IS_ERR(pdata->clk)) {
582 dev_err(dev, "failed to find secss clock source\n"); 647 dev_err(dev, "failed to find secss clock source\n");
583 return -ENOENT; 648 return -ENOENT;
584 } 649 }
585 650
586 clk_enable(pdata->clk); 651 err = clk_prepare_enable(pdata->clk);
652 if (err < 0) {
653 dev_err(dev, "Enabling SSS clk failed, err %d\n", err);
654 return err;
655 }
587 656
588 spin_lock_init(&pdata->lock); 657 spin_lock_init(&pdata->lock);
589 658
590 pdata->irq_hash = platform_get_irq_byname(pdev, "hash"); 659 pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset;
591 if (pdata->irq_hash < 0) {
592 err = pdata->irq_hash;
593 dev_warn(dev, "hash interrupt is not available.\n");
594 goto err_irq;
595 }
596 err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
597 IRQF_SHARED, pdev->name, pdev);
598 if (err < 0) {
599 dev_warn(dev, "hash interrupt is not available.\n");
600 goto err_irq;
601 }
602 660
603 pdata->irq_fc = platform_get_irq_byname(pdev, "feed control"); 661 pdata->irq_fc = platform_get_irq(pdev, 0);
604 if (pdata->irq_fc < 0) { 662 if (pdata->irq_fc < 0) {
605 err = pdata->irq_fc; 663 err = pdata->irq_fc;
606 dev_warn(dev, "feed control interrupt is not available.\n"); 664 dev_warn(dev, "feed control interrupt is not available.\n");
@@ -613,6 +671,23 @@ static int s5p_aes_probe(struct platform_device *pdev)
613 goto err_irq; 671 goto err_irq;
614 } 672 }
615 673
674 if (variant->has_hash_irq) {
675 pdata->irq_hash = platform_get_irq(pdev, 1);
676 if (pdata->irq_hash < 0) {
677 err = pdata->irq_hash;
678 dev_warn(dev, "hash interrupt is not available.\n");
679 goto err_irq;
680 }
681 err = devm_request_irq(dev, pdata->irq_hash, s5p_aes_interrupt,
682 IRQF_SHARED, pdev->name, pdev);
683 if (err < 0) {
684 dev_warn(dev, "hash interrupt is not available.\n");
685 goto err_irq;
686 }
687 }
688
689 pdata->busy = false;
690 pdata->variant = variant;
616 pdata->dev = dev; 691 pdata->dev = dev;
617 platform_set_drvdata(pdev, pdata); 692 platform_set_drvdata(pdev, pdata);
618 s5p_dev = pdata; 693 s5p_dev = pdata;
@@ -639,7 +714,7 @@ static int s5p_aes_probe(struct platform_device *pdev)
639 tasklet_kill(&pdata->tasklet); 714 tasklet_kill(&pdata->tasklet);
640 715
641 err_irq: 716 err_irq:
642 clk_disable(pdata->clk); 717 clk_disable_unprepare(pdata->clk);
643 718
644 s5p_dev = NULL; 719 s5p_dev = NULL;
645 720
@@ -659,7 +734,7 @@ static int s5p_aes_remove(struct platform_device *pdev)
659 734
660 tasklet_kill(&pdata->tasklet); 735 tasklet_kill(&pdata->tasklet);
661 736
662 clk_disable(pdata->clk); 737 clk_disable_unprepare(pdata->clk);
663 738
664 s5p_dev = NULL; 739 s5p_dev = NULL;
665 740
@@ -672,6 +747,7 @@ static struct platform_driver s5p_aes_crypto = {
672 .driver = { 747 .driver = {
673 .owner = THIS_MODULE, 748 .owner = THIS_MODULE,
674 .name = "s5p-secss", 749 .name = "s5p-secss",
750 .of_match_table = s5p_sss_dt_match,
675 }, 751 },
676}; 752};
677 753
diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c
index 07a5987ce67d..164e1ec624e3 100644
--- a/drivers/crypto/sahara.c
+++ b/drivers/crypto/sahara.c
@@ -728,7 +728,7 @@ static int sahara_aes_cbc_decrypt(struct ablkcipher_request *req)
728 728
729static int sahara_aes_cra_init(struct crypto_tfm *tfm) 729static int sahara_aes_cra_init(struct crypto_tfm *tfm)
730{ 730{
731 const char *name = tfm->__crt_alg->cra_name; 731 const char *name = crypto_tfm_alg_name(tfm);
732 struct sahara_ctx *ctx = crypto_tfm_ctx(tfm); 732 struct sahara_ctx *ctx = crypto_tfm_ctx(tfm);
733 733
734 ctx->fallback = crypto_alloc_ablkcipher(name, 0, 734 ctx->fallback = crypto_alloc_ablkcipher(name, 0,
diff --git a/include/crypto/internal/hash.h b/include/crypto/internal/hash.h
index 821eae8cbd8c..9b6f32a6cad1 100644
--- a/include/crypto/internal/hash.h
+++ b/include/crypto/internal/hash.h
@@ -55,15 +55,28 @@ extern const struct crypto_type crypto_ahash_type;
55int crypto_hash_walk_done(struct crypto_hash_walk *walk, int err); 55int crypto_hash_walk_done(struct crypto_hash_walk *walk, int err);
56int crypto_hash_walk_first(struct ahash_request *req, 56int crypto_hash_walk_first(struct ahash_request *req,
57 struct crypto_hash_walk *walk); 57 struct crypto_hash_walk *walk);
58int crypto_ahash_walk_first(struct ahash_request *req,
59 struct crypto_hash_walk *walk);
58int crypto_hash_walk_first_compat(struct hash_desc *hdesc, 60int crypto_hash_walk_first_compat(struct hash_desc *hdesc,
59 struct crypto_hash_walk *walk, 61 struct crypto_hash_walk *walk,
60 struct scatterlist *sg, unsigned int len); 62 struct scatterlist *sg, unsigned int len);
61 63
64static inline int crypto_ahash_walk_done(struct crypto_hash_walk *walk,
65 int err)
66{
67 return crypto_hash_walk_done(walk, err);
68}
69
62static inline int crypto_hash_walk_last(struct crypto_hash_walk *walk) 70static inline int crypto_hash_walk_last(struct crypto_hash_walk *walk)
63{ 71{
64 return !(walk->entrylen | walk->total); 72 return !(walk->entrylen | walk->total);
65} 73}
66 74
75static inline int crypto_ahash_walk_last(struct crypto_hash_walk *walk)
76{
77 return crypto_hash_walk_last(walk);
78}
79
67int crypto_register_ahash(struct ahash_alg *alg); 80int crypto_register_ahash(struct ahash_alg *alg);
68int crypto_unregister_ahash(struct ahash_alg *alg); 81int crypto_unregister_ahash(struct ahash_alg *alg);
69int ahash_register_instance(struct crypto_template *tmpl, 82int ahash_register_instance(struct crypto_template *tmpl,
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 03:02:17 -0400