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authorLABBE Corentin <clabbe.montjoie@gmail.com>2015-07-17 10:39:41 -0400
committerHerbert Xu <herbert@gondor.apana.org.au>2015-07-20 03:54:08 -0400
commit6298e948215f2a3eb8a9af5c490d025deb66f179 (patch)
tree96f35246a1201aa14c1a23b902e073dee7bfc96a
parente757d5c4c367e747ae15186b753788f9c2752753 (diff)
crypto: sunxi-ss - Add Allwinner Security System crypto accelerator
Add support for the Security System included in Allwinner SoC A20. The Security System is a hardware cryptographic accelerator that support: - MD5 and SHA1 hash algorithms - AES block cipher in CBC/ECB mode with 128/196/256bits keys. - DES and 3DES block cipher in CBC/ECB mode Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat
-rw-r--r--drivers/crypto/Kconfig17
-rw-r--r--drivers/crypto/Makefile1
-rw-r--r--drivers/crypto/sunxi-ss/Makefile2
-rw-r--r--drivers/crypto/sunxi-ss/sun4i-ss-cipher.c542
-rw-r--r--drivers/crypto/sunxi-ss/sun4i-ss-core.c403
-rw-r--r--drivers/crypto/sunxi-ss/sun4i-ss-hash.c492
-rw-r--r--drivers/crypto/sunxi-ss/sun4i-ss.h199
7 files changed, 1656 insertions, 0 deletions
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 4044125fb5d5..07bc7aa6b224 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -480,4 +480,21 @@ config CRYPTO_DEV_IMGTEC_HASH
480 hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256 480 hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256
481 hashing algorithms. 481 hashing algorithms.
482 482
483config CRYPTO_DEV_SUN4I_SS
484 tristate "Support for Allwinner Security System cryptographic accelerator"
485 depends on ARCH_SUNXI
486 select CRYPTO_MD5
487 select CRYPTO_SHA1
488 select CRYPTO_AES
489 select CRYPTO_DES
490 select CRYPTO_BLKCIPHER
491 help
492 Some Allwinner SoC have a crypto accelerator named
493 Security System. Select this if you want to use it.
494 The Security System handle AES/DES/3DES ciphers in CBC mode
495 and SHA1 and MD5 hash algorithms.
496
497 To compile this driver as a module, choose M here: the module
498 will be called sun4i-ss.
499
483endif # CRYPTO_HW 500endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index e35c07a8da85..c3ced6fbd1b8 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
28obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/ 28obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/
29obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/ 29obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
30obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/ 30obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
31obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
diff --git a/drivers/crypto/sunxi-ss/Makefile b/drivers/crypto/sunxi-ss/Makefile
new file mode 100644
index 000000000000..8f4c7a273141
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sun4i-ss.o
2sun4i-ss-y += sun4i-ss-core.o sun4i-ss-hash.o sun4i-ss-cipher.o
diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c b/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c
new file mode 100644
index 000000000000..e070c316e8b7
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c
@@ -0,0 +1,542 @@
1/*
2 * sun4i-ss-cipher.c - hardware cryptographic accelerator for Allwinner A20 SoC
3 *
4 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
5 *
6 * This file add support for AES cipher with 128,192,256 bits
7 * keysize in CBC and ECB mode.
8 * Add support also for DES and 3DES in CBC and ECB mode.
9 *
10 * You could find the datasheet in Documentation/arm/sunxi/README
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17#include "sun4i-ss.h"
18
19static int sun4i_ss_opti_poll(struct ablkcipher_request *areq)
20{
21 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
22 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
23 struct sun4i_ss_ctx *ss = op->ss;
24 unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
25 struct sun4i_cipher_req_ctx *ctx = ablkcipher_request_ctx(areq);
26 u32 mode = ctx->mode;
27 /* when activating SS, the default FIFO space is SS_RX_DEFAULT(32) */
28 u32 rx_cnt = SS_RX_DEFAULT;
29 u32 tx_cnt = 0;
30 u32 spaces;
31 u32 v;
32 int i, err = 0;
33 unsigned int ileft = areq->nbytes;
34 unsigned int oleft = areq->nbytes;
35 unsigned int todo;
36 struct sg_mapping_iter mi, mo;
37 unsigned int oi, oo; /* offset for in and out */
38
39 if (areq->nbytes == 0)
40 return 0;
41
42 if (!areq->info) {
43 dev_err_ratelimited(ss->dev, "ERROR: Empty IV\n");
44 return -EINVAL;
45 }
46
47 if (!areq->src || !areq->dst) {
48 dev_err_ratelimited(ss->dev, "ERROR: Some SGs are NULL\n");
49 return -EINVAL;
50 }
51
52 spin_lock_bh(&ss->slock);
53
54 for (i = 0; i < op->keylen; i += 4)
55 writel(*(op->key + i / 4), ss->base + SS_KEY0 + i);
56
57 if (areq->info) {
58 for (i = 0; i < 4 && i < ivsize / 4; i++) {
59 v = *(u32 *)(areq->info + i * 4);
60 writel(v, ss->base + SS_IV0 + i * 4);
61 }
62 }
63 writel(mode, ss->base + SS_CTL);
64
65 sg_miter_start(&mi, areq->src, sg_nents(areq->src),
66 SG_MITER_FROM_SG | SG_MITER_ATOMIC);
67 sg_miter_start(&mo, areq->dst, sg_nents(areq->dst),
68 SG_MITER_TO_SG | SG_MITER_ATOMIC);
69 sg_miter_next(&mi);
70 sg_miter_next(&mo);
71 if (!mi.addr || !mo.addr) {
72 dev_err_ratelimited(ss->dev, "ERROR: sg_miter return null\n");
73 err = -EINVAL;
74 goto release_ss;
75 }
76
77 ileft = areq->nbytes / 4;
78 oleft = areq->nbytes / 4;
79 oi = 0;
80 oo = 0;
81 do {
82 todo = min3(rx_cnt, ileft, (mi.length - oi) / 4);
83 if (todo > 0) {
84 ileft -= todo;
85 writesl(ss->base + SS_RXFIFO, mi.addr + oi, todo);
86 oi += todo * 4;
87 }
88 if (oi == mi.length) {
89 sg_miter_next(&mi);
90 oi = 0;
91 }
92
93 spaces = readl(ss->base + SS_FCSR);
94 rx_cnt = SS_RXFIFO_SPACES(spaces);
95 tx_cnt = SS_TXFIFO_SPACES(spaces);
96
97 todo = min3(tx_cnt, oleft, (mo.length - oo) / 4);
98 if (todo > 0) {
99 oleft -= todo;
100 readsl(ss->base + SS_TXFIFO, mo.addr + oo, todo);
101 oo += todo * 4;
102 }
103 if (oo == mo.length) {
104 sg_miter_next(&mo);
105 oo = 0;
106 }
107 } while (mo.length > 0);
108
109 if (areq->info) {
110 for (i = 0; i < 4 && i < ivsize / 4; i++) {
111 v = readl(ss->base + SS_IV0 + i * 4);
112 *(u32 *)(areq->info + i * 4) = v;
113 }
114 }
115
116release_ss:
117 sg_miter_stop(&mi);
118 sg_miter_stop(&mo);
119 writel(0, ss->base + SS_CTL);
120 spin_unlock_bh(&ss->slock);
121 return err;
122}
123
124/* Generic function that support SG with size not multiple of 4 */
125static int sun4i_ss_cipher_poll(struct ablkcipher_request *areq)
126{
127 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
128 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
129 struct sun4i_ss_ctx *ss = op->ss;
130 int no_chunk = 1;
131 struct scatterlist *in_sg = areq->src;
132 struct scatterlist *out_sg = areq->dst;
133 unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
134 struct sun4i_cipher_req_ctx *ctx = ablkcipher_request_ctx(areq);
135 u32 mode = ctx->mode;
136 /* when activating SS, the default FIFO space is SS_RX_DEFAULT(32) */
137 u32 rx_cnt = SS_RX_DEFAULT;
138 u32 tx_cnt = 0;
139 u32 v;
140 u32 spaces;
141 int i, err = 0;
142 unsigned int ileft = areq->nbytes;
143 unsigned int oleft = areq->nbytes;
144 unsigned int todo;
145 struct sg_mapping_iter mi, mo;
146 unsigned int oi, oo; /* offset for in and out */
147 char buf[4 * SS_RX_MAX];/* buffer for linearize SG src */
148 char bufo[4 * SS_TX_MAX]; /* buffer for linearize SG dst */
149 unsigned int ob = 0; /* offset in buf */
150 unsigned int obo = 0; /* offset in bufo*/
151 unsigned int obl = 0; /* length of data in bufo */
152
153 if (areq->nbytes == 0)
154 return 0;
155
156 if (!areq->info) {
157 dev_err_ratelimited(ss->dev, "ERROR: Empty IV\n");
158 return -EINVAL;
159 }
160
161 if (!areq->src || !areq->dst) {
162 dev_err_ratelimited(ss->dev, "ERROR: Some SGs are NULL\n");
163 return -EINVAL;
164 }
165
166 /*
167 * if we have only SGs with size multiple of 4,
168 * we can use the SS optimized function
169 */
170 while (in_sg && no_chunk == 1) {
171 if ((in_sg->length % 4) != 0)
172 no_chunk = 0;
173 in_sg = sg_next(in_sg);
174 }
175 while (out_sg && no_chunk == 1) {
176 if ((out_sg->length % 4) != 0)
177 no_chunk = 0;
178 out_sg = sg_next(out_sg);
179 }
180
181 if (no_chunk == 1)
182 return sun4i_ss_opti_poll(areq);
183
184 spin_lock_bh(&ss->slock);
185
186 for (i = 0; i < op->keylen; i += 4)
187 writel(*(op->key + i / 4), ss->base + SS_KEY0 + i);
188
189 if (areq->info) {
190 for (i = 0; i < 4 && i < ivsize / 4; i++) {
191 v = *(u32 *)(areq->info + i * 4);
192 writel(v, ss->base + SS_IV0 + i * 4);
193 }
194 }
195 writel(mode, ss->base + SS_CTL);
196
197 sg_miter_start(&mi, areq->src, sg_nents(areq->src),
198 SG_MITER_FROM_SG | SG_MITER_ATOMIC);
199 sg_miter_start(&mo, areq->dst, sg_nents(areq->dst),
200 SG_MITER_TO_SG | SG_MITER_ATOMIC);
201 sg_miter_next(&mi);
202 sg_miter_next(&mo);
203 if (!mi.addr || !mo.addr) {
204 dev_err_ratelimited(ss->dev, "ERROR: sg_miter return null\n");
205 err = -EINVAL;
206 goto release_ss;
207 }
208 ileft = areq->nbytes;
209 oleft = areq->nbytes;
210 oi = 0;
211 oo = 0;
212
213 while (oleft > 0) {
214 if (ileft > 0) {
215 /*
216 * todo is the number of consecutive 4byte word that we
217 * can read from current SG
218 */
219 todo = min3(rx_cnt, ileft / 4, (mi.length - oi) / 4);
220 if (todo > 0 && ob == 0) {
221 writesl(ss->base + SS_RXFIFO, mi.addr + oi,
222 todo);
223 ileft -= todo * 4;
224 oi += todo * 4;
225 } else {
226 /*
227 * not enough consecutive bytes, so we need to
228 * linearize in buf. todo is in bytes
229 * After that copy, if we have a multiple of 4
230 * we need to be able to write all buf in one
231 * pass, so it is why we min() with rx_cnt
232 */
233 todo = min3(rx_cnt * 4 - ob, ileft,
234 mi.length - oi);
235 memcpy(buf + ob, mi.addr + oi, todo);
236 ileft -= todo;
237 oi += todo;
238 ob += todo;
239 if (ob % 4 == 0) {
240 writesl(ss->base + SS_RXFIFO, buf,
241 ob / 4);
242 ob = 0;
243 }
244 }
245 if (oi == mi.length) {
246 sg_miter_next(&mi);
247 oi = 0;
248 }
249 }
250
251 spaces = readl(ss->base + SS_FCSR);
252 rx_cnt = SS_RXFIFO_SPACES(spaces);
253 tx_cnt = SS_TXFIFO_SPACES(spaces);
254 dev_dbg(ss->dev, "%x %u/%u %u/%u cnt=%u %u/%u %u/%u cnt=%u %u %u\n",
255 mode,
256 oi, mi.length, ileft, areq->nbytes, rx_cnt,
257 oo, mo.length, oleft, areq->nbytes, tx_cnt,
258 todo, ob);
259
260 if (tx_cnt == 0)
261 continue;
262 /* todo in 4bytes word */
263 todo = min3(tx_cnt, oleft / 4, (mo.length - oo) / 4);
264 if (todo > 0) {
265 readsl(ss->base + SS_TXFIFO, mo.addr + oo, todo);
266 oleft -= todo * 4;
267 oo += todo * 4;
268 if (oo == mo.length) {
269 sg_miter_next(&mo);
270 oo = 0;
271 }
272 } else {
273 /*
274 * read obl bytes in bufo, we read at maximum for
275 * emptying the device
276 */
277 readsl(ss->base + SS_TXFIFO, bufo, tx_cnt);
278 obl = tx_cnt * 4;
279 obo = 0;
280 do {
281 /*
282 * how many bytes we can copy ?
283 * no more than remaining SG size
284 * no more than remaining buffer
285 * no need to test against oleft
286 */
287 todo = min(mo.length - oo, obl - obo);
288 memcpy(mo.addr + oo, bufo + obo, todo);
289 oleft -= todo;
290 obo += todo;
291 oo += todo;
292 if (oo == mo.length) {
293 sg_miter_next(&mo);
294 oo = 0;
295 }
296 } while (obo < obl);
297 /* bufo must be fully used here */
298 }
299 }
300 if (areq->info) {
301 for (i = 0; i < 4 && i < ivsize / 4; i++) {
302 v = readl(ss->base + SS_IV0 + i * 4);
303 *(u32 *)(areq->info + i * 4) = v;
304 }
305 }
306
307release_ss:
308 sg_miter_stop(&mi);
309 sg_miter_stop(&mo);
310 writel(0, ss->base + SS_CTL);
311 spin_unlock_bh(&ss->slock);
312
313 return err;
314}
315
316/* CBC AES */
317int sun4i_ss_cbc_aes_encrypt(struct ablkcipher_request *areq)
318{
319 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
320 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
321 struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
322
323 rctx->mode = SS_OP_AES | SS_CBC | SS_ENABLED | SS_ENCRYPTION |
324 op->keymode;
325 return sun4i_ss_cipher_poll(areq);
326}
327
328int sun4i_ss_cbc_aes_decrypt(struct ablkcipher_request *areq)
329{
330 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
331 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
332 struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
333
334 rctx->mode = SS_OP_AES | SS_CBC | SS_ENABLED | SS_DECRYPTION |
335 op->keymode;
336 return sun4i_ss_cipher_poll(areq);
337}
338
339/* ECB AES */
340int sun4i_ss_ecb_aes_encrypt(struct ablkcipher_request *areq)
341{
342 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
343 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
344 struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
345
346 rctx->mode = SS_OP_AES | SS_ECB | SS_ENABLED | SS_ENCRYPTION |
347 op->keymode;
348 return sun4i_ss_cipher_poll(areq);
349}
350
351int sun4i_ss_ecb_aes_decrypt(struct ablkcipher_request *areq)
352{
353 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
354 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
355 struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
356
357 rctx->mode = SS_OP_AES | SS_ECB | SS_ENABLED | SS_DECRYPTION |
358 op->keymode;
359 return sun4i_ss_cipher_poll(areq);
360}
361
362/* CBC DES */
363int sun4i_ss_cbc_des_encrypt(struct ablkcipher_request *areq)
364{
365 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
366 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
367 struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
368
369 rctx->mode = SS_OP_DES | SS_CBC | SS_ENABLED | SS_ENCRYPTION |
370 op->keymode;
371 return sun4i_ss_cipher_poll(areq);
372}
373
374int sun4i_ss_cbc_des_decrypt(struct ablkcipher_request *areq)
375{
376 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
377 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
378 struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
379
380 rctx->mode = SS_OP_DES | SS_CBC | SS_ENABLED | SS_DECRYPTION |
381 op->keymode;
382 return sun4i_ss_cipher_poll(areq);
383}
384
385/* ECB DES */
386int sun4i_ss_ecb_des_encrypt(struct ablkcipher_request *areq)
387{
388 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
389 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
390 struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
391
392 rctx->mode = SS_OP_DES | SS_ECB | SS_ENABLED | SS_ENCRYPTION |
393 op->keymode;
394 return sun4i_ss_cipher_poll(areq);
395}
396
397int sun4i_ss_ecb_des_decrypt(struct ablkcipher_request *areq)
398{
399 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
400 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
401 struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
402
403 rctx->mode = SS_OP_DES | SS_ECB | SS_ENABLED | SS_DECRYPTION |
404 op->keymode;
405 return sun4i_ss_cipher_poll(areq);
406}
407
408/* CBC 3DES */
409int sun4i_ss_cbc_des3_encrypt(struct ablkcipher_request *areq)
410{
411 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
412 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
413 struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
414
415 rctx->mode = SS_OP_3DES | SS_CBC | SS_ENABLED | SS_ENCRYPTION |
416 op->keymode;
417 return sun4i_ss_cipher_poll(areq);
418}
419
420int sun4i_ss_cbc_des3_decrypt(struct ablkcipher_request *areq)
421{
422 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
423 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
424 struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
425
426 rctx->mode = SS_OP_3DES | SS_CBC | SS_ENABLED | SS_DECRYPTION |
427 op->keymode;
428 return sun4i_ss_cipher_poll(areq);
429}
430
431/* ECB 3DES */
432int sun4i_ss_ecb_des3_encrypt(struct ablkcipher_request *areq)
433{
434 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
435 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
436 struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
437
438 rctx->mode = SS_OP_3DES | SS_ECB | SS_ENABLED | SS_ENCRYPTION |
439 op->keymode;
440 return sun4i_ss_cipher_poll(areq);
441}
442
443int sun4i_ss_ecb_des3_decrypt(struct ablkcipher_request *areq)
444{
445 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
446 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
447 struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
448
449 rctx->mode = SS_OP_3DES | SS_ECB | SS_ENABLED | SS_DECRYPTION |
450 op->keymode;
451 return sun4i_ss_cipher_poll(areq);
452}
453
454int sun4i_ss_cipher_init(struct crypto_tfm *tfm)
455{
456 struct sun4i_tfm_ctx *op = crypto_tfm_ctx(tfm);
457 struct crypto_alg *alg = tfm->__crt_alg;
458 struct sun4i_ss_alg_template *algt;
459
460 memset(op, 0, sizeof(struct sun4i_tfm_ctx));
461
462 algt = container_of(alg, struct sun4i_ss_alg_template, alg.crypto);
463 op->ss = algt->ss;
464
465 tfm->crt_ablkcipher.reqsize = sizeof(struct sun4i_cipher_req_ctx);
466
467 return 0;
468}
469
470/* check and set the AES key, prepare the mode to be used */
471int sun4i_ss_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
472 unsigned int keylen)
473{
474 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
475 struct sun4i_ss_ctx *ss = op->ss;
476
477 switch (keylen) {
478 case 128 / 8:
479 op->keymode = SS_AES_128BITS;
480 break;
481 case 192 / 8:
482 op->keymode = SS_AES_192BITS;
483 break;
484 case 256 / 8:
485 op->keymode = SS_AES_256BITS;
486 break;
487 default:
488 dev_err(ss->dev, "ERROR: Invalid keylen %u\n", keylen);
489 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
490 return -EINVAL;
491 }
492 op->keylen = keylen;
493 memcpy(op->key, key, keylen);
494 return 0;
495}
496
497/* check and set the DES key, prepare the mode to be used */
498int sun4i_ss_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
499 unsigned int keylen)
500{
501 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
502 struct sun4i_ss_ctx *ss = op->ss;
503 u32 flags;
504 u32 tmp[DES_EXPKEY_WORDS];
505 int ret;
506
507 if (unlikely(keylen != DES_KEY_SIZE)) {
508 dev_err(ss->dev, "Invalid keylen %u\n", keylen);
509 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
510 return -EINVAL;
511 }
512
513 flags = crypto_ablkcipher_get_flags(tfm);
514
515 ret = des_ekey(tmp, key);
516 if (unlikely(ret == 0) && (flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
517 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_WEAK_KEY);
518 dev_dbg(ss->dev, "Weak key %u\n", keylen);
519 return -EINVAL;
520 }
521
522 op->keylen = keylen;
523 memcpy(op->key, key, keylen);
524 return 0;
525}
526
527/* check and set the 3DES key, prepare the mode to be used */
528int sun4i_ss_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
529 unsigned int keylen)
530{
531 struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
532 struct sun4i_ss_ctx *ss = op->ss;
533
534 if (unlikely(keylen != 3 * DES_KEY_SIZE)) {
535 dev_err(ss->dev, "Invalid keylen %u\n", keylen);
536 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
537 return -EINVAL;
538 }
539 op->keylen = keylen;
540 memcpy(op->key, key, keylen);
541 return 0;
542}
diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-core.c b/drivers/crypto/sunxi-ss/sun4i-ss-core.c
new file mode 100644
index 000000000000..0b79b58c913b
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sun4i-ss-core.c
@@ -0,0 +1,403 @@
1/*
2 * sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
3 *
4 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
5 *
6 * Core file which registers crypto algorithms supported by the SS.
7 *
8 * You could find a link for the datasheet in Documentation/arm/sunxi/README
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15#include <linux/clk.h>
16#include <linux/crypto.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <crypto/scatterwalk.h>
22#include <linux/scatterlist.h>
23#include <linux/interrupt.h>
24#include <linux/delay.h>
25
26#include "sun4i-ss.h"
27
28static struct sun4i_ss_alg_template ss_algs[] = {
29{ .type = CRYPTO_ALG_TYPE_AHASH,
30 .mode = SS_OP_MD5,
31 .alg.hash = {
32 .init = sun4i_hash_init,
33 .update = sun4i_hash_update,
34 .final = sun4i_hash_final,
35 .finup = sun4i_hash_finup,
36 .digest = sun4i_hash_digest,
37 .export = sun4i_hash_export_md5,
38 .import = sun4i_hash_import_md5,
39 .halg = {
40 .digestsize = MD5_DIGEST_SIZE,
41 .base = {
42 .cra_name = "md5",
43 .cra_driver_name = "md5-sun4i-ss",
44 .cra_priority = 300,
45 .cra_alignmask = 3,
46 .cra_flags = CRYPTO_ALG_TYPE_AHASH,
47 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
48 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
49 .cra_module = THIS_MODULE,
50 .cra_type = &crypto_ahash_type,
51 .cra_init = sun4i_hash_crainit
52 }
53 }
54 }
55},
56{ .type = CRYPTO_ALG_TYPE_AHASH,
57 .mode = SS_OP_SHA1,
58 .alg.hash = {
59 .init = sun4i_hash_init,
60 .update = sun4i_hash_update,
61 .final = sun4i_hash_final,
62 .finup = sun4i_hash_finup,
63 .digest = sun4i_hash_digest,
64 .export = sun4i_hash_export_sha1,
65 .import = sun4i_hash_import_sha1,
66 .halg = {
67 .digestsize = SHA1_DIGEST_SIZE,
68 .base = {
69 .cra_name = "sha1",
70 .cra_driver_name = "sha1-sun4i-ss",
71 .cra_priority = 300,
72 .cra_alignmask = 3,
73 .cra_flags = CRYPTO_ALG_TYPE_AHASH,
74 .cra_blocksize = SHA1_BLOCK_SIZE,
75 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
76 .cra_module = THIS_MODULE,
77 .cra_type = &crypto_ahash_type,
78 .cra_init = sun4i_hash_crainit
79 }
80 }
81 }
82},
83{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
84 .alg.crypto = {
85 .cra_name = "cbc(aes)",
86 .cra_driver_name = "cbc-aes-sun4i-ss",
87 .cra_priority = 300,
88 .cra_blocksize = AES_BLOCK_SIZE,
89 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
90 .cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
91 .cra_module = THIS_MODULE,
92 .cra_alignmask = 3,
93 .cra_type = &crypto_ablkcipher_type,
94 .cra_init = sun4i_ss_cipher_init,
95 .cra_ablkcipher = {
96 .min_keysize = AES_MIN_KEY_SIZE,
97 .max_keysize = AES_MAX_KEY_SIZE,
98 .ivsize = AES_BLOCK_SIZE,
99 .setkey = sun4i_ss_aes_setkey,
100 .encrypt = sun4i_ss_cbc_aes_encrypt,
101 .decrypt = sun4i_ss_cbc_aes_decrypt,
102 }
103 }
104},
105{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
106 .alg.crypto = {
107 .cra_name = "ecb(aes)",
108 .cra_driver_name = "ecb-aes-sun4i-ss",
109 .cra_priority = 300,
110 .cra_blocksize = AES_BLOCK_SIZE,
111 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
112 .cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
113 .cra_module = THIS_MODULE,
114 .cra_alignmask = 3,
115 .cra_type = &crypto_ablkcipher_type,
116 .cra_init = sun4i_ss_cipher_init,
117 .cra_ablkcipher = {
118 .min_keysize = AES_MIN_KEY_SIZE,
119 .max_keysize = AES_MAX_KEY_SIZE,
120 .ivsize = AES_BLOCK_SIZE,
121 .setkey = sun4i_ss_aes_setkey,
122 .encrypt = sun4i_ss_ecb_aes_encrypt,
123 .decrypt = sun4i_ss_ecb_aes_decrypt,
124 }
125 }
126},
127{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
128 .alg.crypto = {
129 .cra_name = "cbc(des)",
130 .cra_driver_name = "cbc-des-sun4i-ss",
131 .cra_priority = 300,
132 .cra_blocksize = DES_BLOCK_SIZE,
133 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
134 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
135 .cra_module = THIS_MODULE,
136 .cra_alignmask = 3,
137 .cra_type = &crypto_ablkcipher_type,
138 .cra_init = sun4i_ss_cipher_init,
139 .cra_u.ablkcipher = {
140 .min_keysize = DES_KEY_SIZE,
141 .max_keysize = DES_KEY_SIZE,
142 .ivsize = DES_BLOCK_SIZE,
143 .setkey = sun4i_ss_des_setkey,
144 .encrypt = sun4i_ss_cbc_des_encrypt,
145 .decrypt = sun4i_ss_cbc_des_decrypt,
146 }
147 }
148},
149{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
150 .alg.crypto = {
151 .cra_name = "ecb(des)",
152 .cra_driver_name = "ecb-des-sun4i-ss",
153 .cra_priority = 300,
154 .cra_blocksize = DES_BLOCK_SIZE,
155 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
156 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
157 .cra_module = THIS_MODULE,
158 .cra_alignmask = 3,
159 .cra_type = &crypto_ablkcipher_type,
160 .cra_init = sun4i_ss_cipher_init,
161 .cra_u.ablkcipher = {
162 .min_keysize = DES_KEY_SIZE,
163 .max_keysize = DES_KEY_SIZE,
164 .setkey = sun4i_ss_des_setkey,
165 .encrypt = sun4i_ss_ecb_des_encrypt,
166 .decrypt = sun4i_ss_ecb_des_decrypt,
167 }
168 }
169},
170{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
171 .alg.crypto = {
172 .cra_name = "cbc(des3_ede)",
173 .cra_driver_name = "cbc-des3-sun4i-ss",
174 .cra_priority = 300,
175 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
176 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
177 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
178 .cra_module = THIS_MODULE,
179 .cra_alignmask = 3,
180 .cra_type = &crypto_ablkcipher_type,
181 .cra_init = sun4i_ss_cipher_init,
182 .cra_u.ablkcipher = {
183 .min_keysize = DES3_EDE_KEY_SIZE,
184 .max_keysize = DES3_EDE_KEY_SIZE,
185 .ivsize = DES3_EDE_BLOCK_SIZE,
186 .setkey = sun4i_ss_des3_setkey,
187 .encrypt = sun4i_ss_cbc_des3_encrypt,
188 .decrypt = sun4i_ss_cbc_des3_decrypt,
189 }
190 }
191},
192{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
193 .alg.crypto = {
194 .cra_name = "ecb(des3_ede)",
195 .cra_driver_name = "ecb-des3-sun4i-ss",
196 .cra_priority = 300,
197 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
198 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
199 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
200 .cra_module = THIS_MODULE,
201 .cra_alignmask = 3,
202 .cra_type = &crypto_ablkcipher_type,
203 .cra_init = sun4i_ss_cipher_init,
204 .cra_u.ablkcipher = {
205 .min_keysize = DES3_EDE_KEY_SIZE,
206 .max_keysize = DES3_EDE_KEY_SIZE,
207 .ivsize = DES3_EDE_BLOCK_SIZE,
208 .setkey = sun4i_ss_des3_setkey,
209 .encrypt = sun4i_ss_ecb_des3_encrypt,
210 .decrypt = sun4i_ss_ecb_des3_decrypt,
211 }
212 }
213},
214};
215
216static int sun4i_ss_probe(struct platform_device *pdev)
217{
218 struct resource *res;
219 u32 v;
220 int err, i;
221 unsigned long cr;
222 const unsigned long cr_ahb = 24 * 1000 * 1000;
223 const unsigned long cr_mod = 150 * 1000 * 1000;
224 struct sun4i_ss_ctx *ss;
225
226 if (!pdev->dev.of_node)
227 return -ENODEV;
228
229 ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL);
230 if (!ss)
231 return -ENOMEM;
232
233 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
234 ss->base = devm_ioremap_resource(&pdev->dev, res);
235 if (IS_ERR(ss->base)) {
236 dev_err(&pdev->dev, "Cannot request MMIO\n");
237 return PTR_ERR(ss->base);
238 }
239
240 ss->ssclk = devm_clk_get(&pdev->dev, "mod");
241 if (IS_ERR(ss->ssclk)) {
242 err = PTR_ERR(ss->ssclk);
243 dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err);
244 return err;
245 }
246 dev_dbg(&pdev->dev, "clock ss acquired\n");
247
248 ss->busclk = devm_clk_get(&pdev->dev, "ahb");
249 if (IS_ERR(ss->busclk)) {
250 err = PTR_ERR(ss->busclk);
251 dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err);
252 return err;
253 }
254 dev_dbg(&pdev->dev, "clock ahb_ss acquired\n");
255
256 /* Enable both clocks */
257 err = clk_prepare_enable(ss->busclk);
258 if (err != 0) {
259 dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
260 return err;
261 }
262 err = clk_prepare_enable(ss->ssclk);
263 if (err != 0) {
264 dev_err(&pdev->dev, "Cannot prepare_enable ssclk\n");
265 goto error_ssclk;
266 }
267
268 /*
269 * Check that clock have the correct rates given in the datasheet
270 * Try to set the clock to the maximum allowed
271 */
272 err = clk_set_rate(ss->ssclk, cr_mod);
273 if (err != 0) {
274 dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n");
275 goto error_clk;
276 }
277
278 /*
279 * The only impact on clocks below requirement are bad performance,
280 * so do not print "errors"
281 * warn on Overclocked clocks
282 */
283 cr = clk_get_rate(ss->busclk);
284 if (cr >= cr_ahb)
285 dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
286 cr, cr / 1000000, cr_ahb);
287 else
288 dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
289 cr, cr / 1000000, cr_ahb);
290
291 cr = clk_get_rate(ss->ssclk);
292 if (cr <= cr_mod)
293 if (cr < cr_mod)
294 dev_warn(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
295 cr, cr / 1000000, cr_mod);
296 else
297 dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
298 cr, cr / 1000000, cr_mod);
299 else
300 dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n",
301 cr, cr / 1000000, cr_mod);
302
303 /*
304 * Datasheet named it "Die Bonding ID"
305 * I expect to be a sort of Security System Revision number.
306 * Since the A80 seems to have an other version of SS
307 * this info could be useful
308 */
309 writel(SS_ENABLED, ss->base + SS_CTL);
310 v = readl(ss->base + SS_CTL);
311 v >>= 16;
312 v &= 0x07;
313 dev_info(&pdev->dev, "Die ID %d\n", v);
314 writel(0, ss->base + SS_CTL);
315
316 ss->dev = &pdev->dev;
317
318 spin_lock_init(&ss->slock);
319
320 for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
321 ss_algs[i].ss = ss;
322 switch (ss_algs[i].type) {
323 case CRYPTO_ALG_TYPE_ABLKCIPHER:
324 err = crypto_register_alg(&ss_algs[i].alg.crypto);
325 if (err != 0) {
326 dev_err(ss->dev, "Fail to register %s\n",
327 ss_algs[i].alg.crypto.cra_name);
328 goto error_alg;
329 }
330 break;
331 case CRYPTO_ALG_TYPE_AHASH:
332 err = crypto_register_ahash(&ss_algs[i].alg.hash);
333 if (err != 0) {
334 dev_err(ss->dev, "Fail to register %s\n",
335 ss_algs[i].alg.hash.halg.base.cra_name);
336 goto error_alg;
337 }
338 break;
339 }
340 }
341 platform_set_drvdata(pdev, ss);
342 return 0;
343error_alg:
344 i--;
345 for (; i >= 0; i--) {
346 switch (ss_algs[i].type) {
347 case CRYPTO_ALG_TYPE_ABLKCIPHER:
348 crypto_unregister_alg(&ss_algs[i].alg.crypto);
349 break;
350 case CRYPTO_ALG_TYPE_AHASH:
351 crypto_unregister_ahash(&ss_algs[i].alg.hash);
352 break;
353 }
354 }
355error_clk:
356 clk_disable_unprepare(ss->ssclk);
357error_ssclk:
358 clk_disable_unprepare(ss->busclk);
359 return err;
360}
361
362static int sun4i_ss_remove(struct platform_device *pdev)
363{
364 int i;
365 struct sun4i_ss_ctx *ss = platform_get_drvdata(pdev);
366
367 for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
368 switch (ss_algs[i].type) {
369 case CRYPTO_ALG_TYPE_ABLKCIPHER:
370 crypto_unregister_alg(&ss_algs[i].alg.crypto);
371 break;
372 case CRYPTO_ALG_TYPE_AHASH:
373 crypto_unregister_ahash(&ss_algs[i].alg.hash);
374 break;
375 }
376 }
377
378 writel(0, ss->base + SS_CTL);
379 clk_disable_unprepare(ss->busclk);
380 clk_disable_unprepare(ss->ssclk);
381 return 0;
382}
383
384static const struct of_device_id a20ss_crypto_of_match_table[] = {
385 { .compatible = "allwinner,sun4i-a10-crypto" },
386 {}
387};
388MODULE_DEVICE_TABLE(of, a20ss_crypto_of_match_table);
389
390static struct platform_driver sun4i_ss_driver = {
391 .probe = sun4i_ss_probe,
392 .remove = sun4i_ss_remove,
393 .driver = {
394 .name = "sun4i-ss",
395 .of_match_table = a20ss_crypto_of_match_table,
396 },
397};
398
399module_platform_driver(sun4i_ss_driver);
400
401MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator");
402MODULE_LICENSE("GPL");
403MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie@gmail.com>");
diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-hash.c b/drivers/crypto/sunxi-ss/sun4i-ss-hash.c
new file mode 100644
index 000000000000..ff8031498809
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sun4i-ss-hash.c
@@ -0,0 +1,492 @@
1/*
2 * sun4i-ss-hash.c - hardware cryptographic accelerator for Allwinner A20 SoC
3 *
4 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
5 *
6 * This file add support for MD5 and SHA1.
7 *
8 * You could find the datasheet in Documentation/arm/sunxi/README
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15#include "sun4i-ss.h"
16#include <linux/scatterlist.h>
17
18/* This is a totally arbitrary value */
19#define SS_TIMEOUT 100
20
21int sun4i_hash_crainit(struct crypto_tfm *tfm)
22{
23 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
24 sizeof(struct sun4i_req_ctx));
25 return 0;
26}
27
28/* sun4i_hash_init: initialize request context */
29int sun4i_hash_init(struct ahash_request *areq)
30{
31 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
32 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
33 struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg);
34 struct sun4i_ss_alg_template *algt;
35 struct sun4i_ss_ctx *ss;
36
37 memset(op, 0, sizeof(struct sun4i_req_ctx));
38
39 algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash);
40 ss = algt->ss;
41 op->ss = algt->ss;
42 op->mode = algt->mode;
43
44 return 0;
45}
46
47int sun4i_hash_export_md5(struct ahash_request *areq, void *out)
48{
49 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
50 struct md5_state *octx = out;
51 int i;
52
53 octx->byte_count = op->byte_count + op->len;
54
55 memcpy(octx->block, op->buf, op->len);
56
57 if (op->byte_count > 0) {
58 for (i = 0; i < 4; i++)
59 octx->hash[i] = op->hash[i];
60 } else {
61 octx->hash[0] = SHA1_H0;
62 octx->hash[1] = SHA1_H1;
63 octx->hash[2] = SHA1_H2;
64 octx->hash[3] = SHA1_H3;
65 }
66
67 return 0;
68}
69
70int sun4i_hash_import_md5(struct ahash_request *areq, const void *in)
71{
72 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
73 const struct md5_state *ictx = in;
74 int i;
75
76 sun4i_hash_init(areq);
77
78 op->byte_count = ictx->byte_count & ~0x3F;
79 op->len = ictx->byte_count & 0x3F;
80
81 memcpy(op->buf, ictx->block, op->len);
82
83 for (i = 0; i < 4; i++)
84 op->hash[i] = ictx->hash[i];
85
86 return 0;
87}
88
89int sun4i_hash_export_sha1(struct ahash_request *areq, void *out)
90{
91 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
92 struct sha1_state *octx = out;
93 int i;
94
95 octx->count = op->byte_count + op->len;
96
97 memcpy(octx->buffer, op->buf, op->len);
98
99 if (op->byte_count > 0) {
100 for (i = 0; i < 5; i++)
101 octx->state[i] = op->hash[i];
102 } else {
103 octx->state[0] = SHA1_H0;
104 octx->state[1] = SHA1_H1;
105 octx->state[2] = SHA1_H2;
106 octx->state[3] = SHA1_H3;
107 octx->state[4] = SHA1_H4;
108 }
109
110 return 0;
111}
112
113int sun4i_hash_import_sha1(struct ahash_request *areq, const void *in)
114{
115 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
116 const struct sha1_state *ictx = in;
117 int i;
118
119 sun4i_hash_init(areq);
120
121 op->byte_count = ictx->count & ~0x3F;
122 op->len = ictx->count & 0x3F;
123
124 memcpy(op->buf, ictx->buffer, op->len);
125
126 for (i = 0; i < 5; i++)
127 op->hash[i] = ictx->state[i];
128
129 return 0;
130}
131
132/*
133 * sun4i_hash_update: update hash engine
134 *
135 * Could be used for both SHA1 and MD5
136 * Write data by step of 32bits and put then in the SS.
137 *
138 * Since we cannot leave partial data and hash state in the engine,
139 * we need to get the hash state at the end of this function.
140 * We can get the hash state every 64 bytes
141 *
142 * So the first work is to get the number of bytes to write to SS modulo 64
143 * The extra bytes will go to a temporary buffer op->buf storing op->len bytes
144 *
145 * So at the begin of update()
146 * if op->len + areq->nbytes < 64
147 * => all data will be written to wait buffer (op->buf) and end=0
148 * if not, write all data from op->buf to the device and position end to
149 * complete to 64bytes
150 *
151 * example 1:
152 * update1 60o => op->len=60
153 * update2 60o => need one more word to have 64 bytes
154 * end=4
155 * so write all data from op->buf and one word of SGs
156 * write remaining data in op->buf
157 * final state op->len=56
158 */
159int sun4i_hash_update(struct ahash_request *areq)
160{
161 u32 v, ivmode = 0;
162 unsigned int i = 0;
163 /*
164 * i is the total bytes read from SGs, to be compared to areq->nbytes
165 * i is important because we cannot rely on SG length since the sum of
166 * SG->length could be greater than areq->nbytes
167 */
168
169 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
170 struct sun4i_ss_ctx *ss = op->ss;
171 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
172 unsigned int in_i = 0; /* advancement in the current SG */
173 unsigned int end;
174 /*
175 * end is the position when we need to stop writing to the device,
176 * to be compared to i
177 */
178 int in_r, err = 0;
179 unsigned int todo;
180 u32 spaces, rx_cnt = SS_RX_DEFAULT;
181 size_t copied = 0;
182 struct sg_mapping_iter mi;
183
184 dev_dbg(ss->dev, "%s %s bc=%llu len=%u mode=%x wl=%u h0=%0x",
185 __func__, crypto_tfm_alg_name(areq->base.tfm),
186 op->byte_count, areq->nbytes, op->mode,
187 op->len, op->hash[0]);
188
189 if (areq->nbytes == 0)
190 return 0;
191
192 /* protect against overflow */
193 if (areq->nbytes > UINT_MAX - op->len) {
194 dev_err(ss->dev, "Cannot process too large request\n");
195 return -EINVAL;
196 }
197
198 if (op->len + areq->nbytes < 64) {
199 /* linearize data to op->buf */
200 copied = sg_pcopy_to_buffer(areq->src, sg_nents(areq->src),
201 op->buf + op->len, areq->nbytes, 0);
202 op->len += copied;
203 return 0;
204 }
205
206 end = ((areq->nbytes + op->len) / 64) * 64 - op->len;
207
208 if (end > areq->nbytes || areq->nbytes - end > 63) {
209 dev_err(ss->dev, "ERROR: Bound error %u %u\n",
210 end, areq->nbytes);
211 return -EINVAL;
212 }
213
214 spin_lock_bh(&ss->slock);
215
216 /*
217 * if some data have been processed before,
218 * we need to restore the partial hash state
219 */
220 if (op->byte_count > 0) {
221 ivmode = SS_IV_ARBITRARY;
222 for (i = 0; i < 5; i++)
223 writel(op->hash[i], ss->base + SS_IV0 + i * 4);
224 }
225 /* Enable the device */
226 writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL);
227
228 i = 0;
229 sg_miter_start(&mi, areq->src, sg_nents(areq->src),
230 SG_MITER_FROM_SG | SG_MITER_ATOMIC);
231 sg_miter_next(&mi);
232 in_i = 0;
233
234 do {
235 /*
236 * we need to linearize in two case:
237 * - the buffer is already used
238 * - the SG does not have enough byte remaining ( < 4)
239 */
240 if (op->len > 0 || (mi.length - in_i) < 4) {
241 /*
242 * if we have entered here we have two reason to stop
243 * - the buffer is full
244 * - reach the end
245 */
246 while (op->len < 64 && i < end) {
247 /* how many bytes we can read from current SG */
248 in_r = min3(mi.length - in_i, end - i,
249 64 - op->len);
250 memcpy(op->buf + op->len, mi.addr + in_i, in_r);
251 op->len += in_r;
252 i += in_r;
253 in_i += in_r;
254 if (in_i == mi.length) {
255 sg_miter_next(&mi);
256 in_i = 0;
257 }
258 }
259 if (op->len > 3 && (op->len % 4) == 0) {
260 /* write buf to the device */
261 writesl(ss->base + SS_RXFIFO, op->buf,
262 op->len / 4);
263 op->byte_count += op->len;
264 op->len = 0;
265 }
266 }
267 if (mi.length - in_i > 3 && i < end) {
268 /* how many bytes we can read from current SG */
269 in_r = min3(mi.length - in_i, areq->nbytes - i,
270 ((mi.length - in_i) / 4) * 4);
271 /* how many bytes we can write in the device*/
272 todo = min3((u32)(end - i) / 4, rx_cnt, (u32)in_r / 4);
273 writesl(ss->base + SS_RXFIFO, mi.addr + in_i, todo);
274 op->byte_count += todo * 4;
275 i += todo * 4;
276 in_i += todo * 4;
277 rx_cnt -= todo;
278 if (rx_cnt == 0) {
279 spaces = readl(ss->base + SS_FCSR);
280 rx_cnt = SS_RXFIFO_SPACES(spaces);
281 }
282 if (in_i == mi.length) {
283 sg_miter_next(&mi);
284 in_i = 0;
285 }
286 }
287 } while (i < end);
288 /* final linear */
289 if ((areq->nbytes - i) < 64) {
290 while (i < areq->nbytes && in_i < mi.length && op->len < 64) {
291 /* how many bytes we can read from current SG */
292 in_r = min3(mi.length - in_i, areq->nbytes - i,
293 64 - op->len);
294 memcpy(op->buf + op->len, mi.addr + in_i, in_r);
295 op->len += in_r;
296 i += in_r;
297 in_i += in_r;
298 if (in_i == mi.length) {
299 sg_miter_next(&mi);
300 in_i = 0;
301 }
302 }
303 }
304
305 sg_miter_stop(&mi);
306
307 writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
308 i = 0;
309 do {
310 v = readl(ss->base + SS_CTL);
311 i++;
312 } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0);
313 if (i >= SS_TIMEOUT) {
314 dev_err_ratelimited(ss->dev,
315 "ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
316 i, SS_TIMEOUT, v, areq->nbytes);
317 err = -EIO;
318 goto release_ss;
319 }
320
321 /* get the partial hash only if something was written */
322 for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++)
323 op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
324
325release_ss:
326 writel(0, ss->base + SS_CTL);
327 spin_unlock_bh(&ss->slock);
328 return err;
329}
330
331/*
332 * sun4i_hash_final: finalize hashing operation
333 *
334 * If we have some remaining bytes, we write them.
335 * Then ask the SS for finalizing the hashing operation
336 *
337 * I do not check RX FIFO size in this function since the size is 32
338 * after each enabling and this function neither write more than 32 words.
339 */
340int sun4i_hash_final(struct ahash_request *areq)
341{
342 u32 v, ivmode = 0;
343 unsigned int i;
344 unsigned int j = 0;
345 int zeros, err = 0;
346 unsigned int index, padlen;
347 __be64 bits;
348 struct sun4i_req_ctx *op = ahash_request_ctx(areq);
349 struct sun4i_ss_ctx *ss = op->ss;
350 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
351 u32 bf[32];
352 u32 wb = 0;
353 unsigned int nwait, nbw = 0;
354
355 dev_dbg(ss->dev, "%s: byte=%llu len=%u mode=%x wl=%u h=%x",
356 __func__, op->byte_count, areq->nbytes, op->mode,
357 op->len, op->hash[0]);
358
359 spin_lock_bh(&ss->slock);
360
361 /*
362 * if we have already written something,
363 * restore the partial hash state
364 */
365 if (op->byte_count > 0) {
366 ivmode = SS_IV_ARBITRARY;
367 for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++)
368 writel(op->hash[i], ss->base + SS_IV0 + i * 4);
369 }
370 writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL);
371
372 /* write the remaining words of the wait buffer */
373 if (op->len > 0) {
374 nwait = op->len / 4;
375 if (nwait > 0) {
376 writesl(ss->base + SS_RXFIFO, op->buf, nwait);
377 op->byte_count += 4 * nwait;
378 }
379 nbw = op->len - 4 * nwait;
380 wb = *(u32 *)(op->buf + nwait * 4);
381 wb &= (0xFFFFFFFF >> (4 - nbw) * 8);
382 }
383
384 /* write the remaining bytes of the nbw buffer */
385 if (nbw > 0) {
386 wb |= ((1 << 7) << (nbw * 8));
387 bf[j++] = wb;
388 } else {
389 bf[j++] = 1 << 7;
390 }
391
392 /*
393 * number of space to pad to obtain 64o minus 8(size) minus 4 (final 1)
394 * I take the operations from other MD5/SHA1 implementations
395 */
396
397 /* we have already send 4 more byte of which nbw data */
398 if (op->mode == SS_OP_MD5) {
399 index = (op->byte_count + 4) & 0x3f;
400 op->byte_count += nbw;
401 if (index > 56)
402 zeros = (120 - index) / 4;
403 else
404 zeros = (56 - index) / 4;
405 } else {
406 op->byte_count += nbw;
407 index = op->byte_count & 0x3f;
408 padlen = (index < 56) ? (56 - index) : ((64 + 56) - index);
409 zeros = (padlen - 1) / 4;
410 }
411
412 memset(bf + j, 0, 4 * zeros);
413 j += zeros;
414
415 /* write the length of data */
416 if (op->mode == SS_OP_SHA1) {
417 bits = cpu_to_be64(op->byte_count << 3);
418 bf[j++] = bits & 0xffffffff;
419 bf[j++] = (bits >> 32) & 0xffffffff;
420 } else {
421 bf[j++] = (op->byte_count << 3) & 0xffffffff;
422 bf[j++] = (op->byte_count >> 29) & 0xffffffff;
423 }
424 writesl(ss->base + SS_RXFIFO, bf, j);
425
426 /* Tell the SS to stop the hashing */
427 writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
428
429 /*
430 * Wait for SS to finish the hash.
431 * The timeout could happen only in case of bad overcloking
432 * or driver bug.
433 */
434 i = 0;
435 do {
436 v = readl(ss->base + SS_CTL);
437 i++;
438 } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0);
439 if (i >= SS_TIMEOUT) {
440 dev_err_ratelimited(ss->dev,
441 "ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
442 i, SS_TIMEOUT, v, areq->nbytes);
443 err = -EIO;
444 goto release_ss;
445 }
446
447 /* Get the hash from the device */
448 if (op->mode == SS_OP_SHA1) {
449 for (i = 0; i < 5; i++) {
450 v = cpu_to_be32(readl(ss->base + SS_MD0 + i * 4));
451 memcpy(areq->result + i * 4, &v, 4);
452 }
453 } else {
454 for (i = 0; i < 4; i++) {
455 v = readl(ss->base + SS_MD0 + i * 4);
456 memcpy(areq->result + i * 4, &v, 4);
457 }
458 }
459
460release_ss:
461 writel(0, ss->base + SS_CTL);
462 spin_unlock_bh(&ss->slock);
463 return err;
464}
465
466/* sun4i_hash_finup: finalize hashing operation after an update */
467int sun4i_hash_finup(struct ahash_request *areq)
468{
469 int err;
470
471 err = sun4i_hash_update(areq);
472 if (err != 0)
473 return err;
474
475 return sun4i_hash_final(areq);
476}
477
478/* combo of init/update/final functions */
479int sun4i_hash_digest(struct ahash_request *areq)
480{
481 int err;
482
483 err = sun4i_hash_init(areq);
484 if (err != 0)
485 return err;
486
487 err = sun4i_hash_update(areq);
488 if (err != 0)
489 return err;
490
491 return sun4i_hash_final(areq);
492}
diff --git a/drivers/crypto/sunxi-ss/sun4i-ss.h b/drivers/crypto/sunxi-ss/sun4i-ss.h
new file mode 100644
index 000000000000..db18b2554e6f
--- /dev/null
+++ b/drivers/crypto/sunxi-ss/sun4i-ss.h
@@ -0,0 +1,199 @@
1/*
2 * sun4i-ss.h - hardware cryptographic accelerator for Allwinner A20 SoC
3 *
4 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
5 *
6 * Support AES cipher with 128,192,256 bits keysize.
7 * Support MD5 and SHA1 hash algorithms.
8 * Support DES and 3DES
9 *
10 * You could find the datasheet in Documentation/arm/sunxi/README
11 *
12 * Licensed under the GPL-2.
13 */
14
15#include <linux/clk.h>
16#include <linux/crypto.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <crypto/scatterwalk.h>
22#include <linux/scatterlist.h>
23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <crypto/md5.h>
26#include <crypto/sha.h>
27#include <crypto/hash.h>
28#include <crypto/internal/hash.h>
29#include <crypto/aes.h>
30#include <crypto/des.h>
31#include <crypto/internal/rng.h>
32
33#define SS_CTL 0x00
34#define SS_KEY0 0x04
35#define SS_KEY1 0x08
36#define SS_KEY2 0x0C
37#define SS_KEY3 0x10
38#define SS_KEY4 0x14
39#define SS_KEY5 0x18
40#define SS_KEY6 0x1C
41#define SS_KEY7 0x20
42
43#define SS_IV0 0x24
44#define SS_IV1 0x28
45#define SS_IV2 0x2C
46#define SS_IV3 0x30
47
48#define SS_FCSR 0x44
49
50#define SS_MD0 0x4C
51#define SS_MD1 0x50
52#define SS_MD2 0x54
53#define SS_MD3 0x58
54#define SS_MD4 0x5C
55
56#define SS_RXFIFO 0x200
57#define SS_TXFIFO 0x204
58
59/* SS_CTL configuration values */
60
61/* PRNG generator mode - bit 15 */
62#define SS_PRNG_ONESHOT (0 << 15)
63#define SS_PRNG_CONTINUE (1 << 15)
64
65/* IV mode for hash */
66#define SS_IV_ARBITRARY (1 << 14)
67
68/* SS operation mode - bits 12-13 */
69#define SS_ECB (0 << 12)
70#define SS_CBC (1 << 12)
71#define SS_CTS (3 << 12)
72
73/* Counter width for CNT mode - bits 10-11 */
74#define SS_CNT_16BITS (0 << 10)
75#define SS_CNT_32BITS (1 << 10)
76#define SS_CNT_64BITS (2 << 10)
77
78/* Key size for AES - bits 8-9 */
79#define SS_AES_128BITS (0 << 8)
80#define SS_AES_192BITS (1 << 8)
81#define SS_AES_256BITS (2 << 8)
82
83/* Operation direction - bit 7 */
84#define SS_ENCRYPTION (0 << 7)
85#define SS_DECRYPTION (1 << 7)
86
87/* SS Method - bits 4-6 */
88#define SS_OP_AES (0 << 4)
89#define SS_OP_DES (1 << 4)
90#define SS_OP_3DES (2 << 4)
91#define SS_OP_SHA1 (3 << 4)
92#define SS_OP_MD5 (4 << 4)
93#define SS_OP_PRNG (5 << 4)
94
95/* Data end bit - bit 2 */
96#define SS_DATA_END (1 << 2)
97
98/* PRNG start bit - bit 1 */
99#define SS_PRNG_START (1 << 1)
100
101/* SS Enable bit - bit 0 */
102#define SS_DISABLED (0 << 0)
103#define SS_ENABLED (1 << 0)
104
105/* SS_FCSR configuration values */
106/* RX FIFO status - bit 30 */
107#define SS_RXFIFO_FREE (1 << 30)
108
109/* RX FIFO empty spaces - bits 24-29 */
110#define SS_RXFIFO_SPACES(val) (((val) >> 24) & 0x3f)
111
112/* TX FIFO status - bit 22 */
113#define SS_TXFIFO_AVAILABLE (1 << 22)
114
115/* TX FIFO available spaces - bits 16-21 */
116#define SS_TXFIFO_SPACES(val) (((val) >> 16) & 0x3f)
117
118#define SS_RX_MAX 32
119#define SS_RX_DEFAULT SS_RX_MAX
120#define SS_TX_MAX 33
121
122#define SS_RXFIFO_EMP_INT_PENDING (1 << 10)
123#define SS_TXFIFO_AVA_INT_PENDING (1 << 8)
124#define SS_RXFIFO_EMP_INT_ENABLE (1 << 2)
125#define SS_TXFIFO_AVA_INT_ENABLE (1 << 0)
126
127struct sun4i_ss_ctx {
128 void __iomem *base;
129 int irq;
130 struct clk *busclk;
131 struct clk *ssclk;
132 struct device *dev;
133 struct resource *res;
134 spinlock_t slock; /* control the use of the device */
135};
136
137struct sun4i_ss_alg_template {
138 u32 type;
139 u32 mode;
140 union {
141 struct crypto_alg crypto;
142 struct ahash_alg hash;
143 } alg;
144 struct sun4i_ss_ctx *ss;
145};
146
147struct sun4i_tfm_ctx {
148 u32 key[AES_MAX_KEY_SIZE / 4];/* divided by sizeof(u32) */
149 u32 keylen;
150 u32 keymode;
151 struct sun4i_ss_ctx *ss;
152};
153
154struct sun4i_cipher_req_ctx {
155 u32 mode;
156};
157
158struct sun4i_req_ctx {
159 u32 mode;
160 u64 byte_count; /* number of bytes "uploaded" to the device */
161 u32 hash[5]; /* for storing SS_IVx register */
162 char buf[64];
163 unsigned int len;
164 struct sun4i_ss_ctx *ss;
165};
166
167int sun4i_hash_crainit(struct crypto_tfm *tfm);
168int sun4i_hash_init(struct ahash_request *areq);
169int sun4i_hash_update(struct ahash_request *areq);
170int sun4i_hash_final(struct ahash_request *areq);
171int sun4i_hash_finup(struct ahash_request *areq);
172int sun4i_hash_digest(struct ahash_request *areq);
173int sun4i_hash_export_md5(struct ahash_request *areq, void *out);
174int sun4i_hash_import_md5(struct ahash_request *areq, const void *in);
175int sun4i_hash_export_sha1(struct ahash_request *areq, void *out);
176int sun4i_hash_import_sha1(struct ahash_request *areq, const void *in);
177
178int sun4i_ss_cbc_aes_encrypt(struct ablkcipher_request *areq);
179int sun4i_ss_cbc_aes_decrypt(struct ablkcipher_request *areq);
180int sun4i_ss_ecb_aes_encrypt(struct ablkcipher_request *areq);
181int sun4i_ss_ecb_aes_decrypt(struct ablkcipher_request *areq);
182
183int sun4i_ss_cbc_des_encrypt(struct ablkcipher_request *areq);
184int sun4i_ss_cbc_des_decrypt(struct ablkcipher_request *areq);
185int sun4i_ss_ecb_des_encrypt(struct ablkcipher_request *areq);
186int sun4i_ss_ecb_des_decrypt(struct ablkcipher_request *areq);
187
188int sun4i_ss_cbc_des3_encrypt(struct ablkcipher_request *areq);
189int sun4i_ss_cbc_des3_decrypt(struct ablkcipher_request *areq);
190int sun4i_ss_ecb_des3_encrypt(struct ablkcipher_request *areq);
191int sun4i_ss_ecb_des3_decrypt(struct ablkcipher_request *areq);
192
193int sun4i_ss_cipher_init(struct crypto_tfm *tfm);
194int sun4i_ss_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
195 unsigned int keylen);
196int sun4i_ss_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
197 unsigned int keylen);
198int sun4i_ss_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
199 unsigned int keylen);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-27 12:03:43 -0400