diff options
author | Jarkko Nikula <jarkko.nikula@linux.intel.com> | 2015-10-28 09:13:39 -0400 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2015-10-29 22:18:05 -0400 |
commit | 624ea72ebddc1f61d32c9e6265f8d6f6dacd26d6 (patch) | |
tree | 64e4ba78b69bb94cba3ced0574249528a2d7e631 | |
parent | ceb941afa5c38dae8e273089266c412d362c7963 (diff) |
spi: pxa2xx: Use LPSS prefix for defines that are Intel LPSS specific
Rename a few defines that are specific to Intel LPSS SPI private
registers with LPSS prefix. It makes easier to distinguish them from
common defines.
Suggested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r-- | drivers/spi/spi-pxa2xx.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 0f6a6c89eab3..9060aee5a7b1 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c | |||
@@ -61,9 +61,9 @@ MODULE_ALIAS("platform:pxa2xx-spi"); | |||
61 | | QUARK_X1000_SSCR1_TFT \ | 61 | | QUARK_X1000_SSCR1_TFT \ |
62 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) | 62 | | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) |
63 | 63 | ||
64 | #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) | 64 | #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) |
65 | #define SPI_CS_CONTROL_SW_MODE BIT(0) | 65 | #define LPSS_CS_CONTROL_SW_MODE BIT(0) |
66 | #define SPI_CS_CONTROL_CS_HIGH BIT(1) | 66 | #define LPSS_CS_CONTROL_CS_HIGH BIT(1) |
67 | 67 | ||
68 | struct lpss_config { | 68 | struct lpss_config { |
69 | /* LPSS offset from drv_data->ioaddr */ | 69 | /* LPSS offset from drv_data->ioaddr */ |
@@ -250,8 +250,8 @@ static void lpss_ssp_setup(struct driver_data *drv_data) | |||
250 | 250 | ||
251 | /* Enable software chip select control */ | 251 | /* Enable software chip select control */ |
252 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); | 252 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); |
253 | value &= ~(SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH); | 253 | value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); |
254 | value |= SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH; | 254 | value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; |
255 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); | 255 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
256 | 256 | ||
257 | /* Enable multiblock DMA transfers */ | 257 | /* Enable multiblock DMA transfers */ |
@@ -261,7 +261,7 @@ static void lpss_ssp_setup(struct driver_data *drv_data) | |||
261 | if (config->reg_general >= 0) { | 261 | if (config->reg_general >= 0) { |
262 | value = __lpss_ssp_read_priv(drv_data, | 262 | value = __lpss_ssp_read_priv(drv_data, |
263 | config->reg_general); | 263 | config->reg_general); |
264 | value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE; | 264 | value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; |
265 | __lpss_ssp_write_priv(drv_data, | 265 | __lpss_ssp_write_priv(drv_data, |
266 | config->reg_general, value); | 266 | config->reg_general, value); |
267 | } | 267 | } |
@@ -277,9 +277,9 @@ static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable) | |||
277 | 277 | ||
278 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); | 278 | value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); |
279 | if (enable) | 279 | if (enable) |
280 | value &= ~SPI_CS_CONTROL_CS_HIGH; | 280 | value &= ~LPSS_CS_CONTROL_CS_HIGH; |
281 | else | 281 | else |
282 | value |= SPI_CS_CONTROL_CS_HIGH; | 282 | value |= LPSS_CS_CONTROL_CS_HIGH; |
283 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); | 283 | __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); |
284 | } | 284 | } |
285 | 285 | ||