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authorMahesh Kumar <mahesh1.kumar@intel.com>2018-04-08 23:41:05 -0400
committerMaarten Lankhorst <maarten.lankhorst@linux.intel.com>2018-04-09 07:37:28 -0400
commit62027b7736d038309e93e6d5d25a9a72390821cb (patch)
tree7d202b8212b18432aa76025371d90a7ee2434fa8
parent942aa2d0503d483562795d8f4c0957e13bd4b59d (diff)
drm/i915/skl+: pass skl_wm_level struct to wm compute func
This patch passes skl_wm_level structure itself to watermark computation function skl_compute_plane_wm function (instead of its internal parameters). It reduces number of arguments required to be passed. v2: Addressed review comments by Shashank Sharma v3: Adding reviewed by tag from Shashank Sharma v4: Added reviewed by from Juha-Pekka Heikkila v5: Rebased the series Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1523245273-30264-7-git-send-email-vidya.srinivas@intel.com
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c18
1 files changed, 7 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fb30efa22c24..06352c9e9ef6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4529,9 +4529,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
4529 uint16_t ddb_allocation, 4529 uint16_t ddb_allocation,
4530 int level, 4530 int level,
4531 const struct skl_wm_params *wp, 4531 const struct skl_wm_params *wp,
4532 uint16_t *out_blocks, /* out */ 4532 struct skl_wm_level *result /* out */)
4533 uint8_t *out_lines, /* out */
4534 bool *enabled /* out */)
4535{ 4533{
4536 const struct drm_plane_state *pstate = &intel_pstate->base; 4534 const struct drm_plane_state *pstate = &intel_pstate->base;
4537 uint32_t latency = dev_priv->wm.skl_latency[level]; 4535 uint32_t latency = dev_priv->wm.skl_latency[level];
@@ -4545,7 +4543,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
4545 4543
4546 if (latency == 0 || 4544 if (latency == 0 ||
4547 !intel_wm_plane_visible(cstate, intel_pstate)) { 4545 !intel_wm_plane_visible(cstate, intel_pstate)) {
4548 *enabled = false; 4546 result->plane_en = false;
4549 return 0; 4547 return 0;
4550 } 4548 }
4551 4549
@@ -4626,7 +4624,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
4626 if ((level > 0 && res_lines > 31) || 4624 if ((level > 0 && res_lines > 31) ||
4627 res_blocks >= ddb_allocation || 4625 res_blocks >= ddb_allocation ||
4628 min_disp_buf_needed >= ddb_allocation) { 4626 min_disp_buf_needed >= ddb_allocation) {
4629 *enabled = false; 4627 result->plane_en = false;
4630 4628
4631 /* 4629 /*
4632 * If there are no valid level 0 watermarks, then we can't 4630 * If there are no valid level 0 watermarks, then we can't
@@ -4646,9 +4644,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
4646 } 4644 }
4647 4645
4648 /* The number of lines are ignored for the level 0 watermark. */ 4646 /* The number of lines are ignored for the level 0 watermark. */
4649 *out_lines = level ? res_lines : 0; 4647 result->plane_res_b = res_blocks;
4650 *out_blocks = res_blocks; 4648 result->plane_res_l = res_lines;
4651 *enabled = true; 4649 result->plane_en = true;
4652 4650
4653 return 0; 4651 return 0;
4654} 4652}
@@ -4688,9 +4686,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
4688 ddb_blocks, 4686 ddb_blocks,
4689 level, 4687 level,
4690 wm_params, 4688 wm_params,
4691 &result->plane_res_b, 4689 result);
4692 &result->plane_res_l,
4693 &result->plane_en);
4694 if (ret) 4690 if (ret)
4695 return ret; 4691 return ret;
4696 } 4692 }