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authorMarek Szyprowski <m.szyprowski@samsung.com>2015-11-30 08:53:26 -0500
committerInki Dae <daeinki@gmail.com>2015-12-13 08:22:57 -0500
commit6178d3d1bbedd3fe08bb194272bc24f7f92282e7 (patch)
treeffede04af65276538e51b71f62d5dab9ab835d13
parentfd2d2fc2db28d3a2a18b7504e2d6d8b0753f90e8 (diff)
drm/exynos: add generic check for plane state
This patch adds generic check for plane state - display area dimensions, so drivers can always assume that they get valid plane state to set. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_drv.h3
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_plane.c31
-rw-r--r--drivers/gpu/drm/exynos/exynos_mixer.c3
3 files changed, 37 insertions, 0 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 6f8a296a3115..82bbd7f4b316 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -89,6 +89,9 @@ struct exynos_drm_plane {
89 struct drm_framebuffer *pending_fb; 89 struct drm_framebuffer *pending_fb;
90}; 90};
91 91
92#define EXYNOS_DRM_PLANE_CAP_DOUBLE (1 << 0)
93#define EXYNOS_DRM_PLANE_CAP_SCALE (1 << 1)
94
92/* 95/*
93 * Exynos DRM plane configuration structure. 96 * Exynos DRM plane configuration structure.
94 * 97 *
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index b620d7a76799..9eaa8627175f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -173,6 +173,36 @@ static struct drm_plane_funcs exynos_plane_funcs = {
173 .atomic_destroy_state = exynos_drm_plane_destroy_state, 173 .atomic_destroy_state = exynos_drm_plane_destroy_state,
174}; 174};
175 175
176static int
177exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config,
178 struct exynos_drm_plane_state *state)
179{
180 bool width_ok = false, height_ok = false;
181
182 if (config->capabilities & EXYNOS_DRM_PLANE_CAP_SCALE)
183 return 0;
184
185 if (state->src.w == state->crtc.w)
186 width_ok = true;
187
188 if (state->src.h == state->crtc.h)
189 height_ok = true;
190
191 if ((config->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) &&
192 state->h_ratio == (1 << 15))
193 width_ok = true;
194
195 if ((config->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) &&
196 state->v_ratio == (1 << 15))
197 height_ok = true;
198
199 if (width_ok & height_ok)
200 return 0;
201
202 DRM_DEBUG_KMS("scaling mode is not supported");
203 return -ENOTSUPP;
204}
205
176static int exynos_plane_atomic_check(struct drm_plane *plane, 206static int exynos_plane_atomic_check(struct drm_plane *plane,
177 struct drm_plane_state *state) 207 struct drm_plane_state *state)
178{ 208{
@@ -187,6 +217,7 @@ static int exynos_plane_atomic_check(struct drm_plane *plane,
187 /* translate state into exynos_state */ 217 /* translate state into exynos_state */
188 exynos_plane_mode_set(exynos_state); 218 exynos_plane_mode_set(exynos_state);
189 219
220 ret = exynos_drm_plane_check_size(exynos_plane->config, exynos_state);
190 return ret; 221 return ret;
191} 222}
192 223
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index a229f86d221a..4190285798ef 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -117,16 +117,19 @@ static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = {
117 .type = DRM_PLANE_TYPE_PRIMARY, 117 .type = DRM_PLANE_TYPE_PRIMARY,
118 .pixel_formats = mixer_formats, 118 .pixel_formats = mixer_formats,
119 .num_pixel_formats = ARRAY_SIZE(mixer_formats), 119 .num_pixel_formats = ARRAY_SIZE(mixer_formats),
120 .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE,
120 }, { 121 }, {
121 .zpos = 1, 122 .zpos = 1,
122 .type = DRM_PLANE_TYPE_CURSOR, 123 .type = DRM_PLANE_TYPE_CURSOR,
123 .pixel_formats = mixer_formats, 124 .pixel_formats = mixer_formats,
124 .num_pixel_formats = ARRAY_SIZE(mixer_formats), 125 .num_pixel_formats = ARRAY_SIZE(mixer_formats),
126 .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE,
125 }, { 127 }, {
126 .zpos = 2, 128 .zpos = 2,
127 .type = DRM_PLANE_TYPE_OVERLAY, 129 .type = DRM_PLANE_TYPE_OVERLAY,
128 .pixel_formats = vp_formats, 130 .pixel_formats = vp_formats,
129 .num_pixel_formats = ARRAY_SIZE(vp_formats), 131 .num_pixel_formats = ARRAY_SIZE(vp_formats),
132 .capabilities = EXYNOS_DRM_PLANE_CAP_SCALE,
130 }, 133 },
131}; 134};
132 135