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authorMaciej W. Rozycki <macro@linux-mips.org>2018-10-09 18:57:43 -0400
committerDavid S. Miller <davem@davemloft.net>2018-10-16 00:46:06 -0400
commit61414f5ec9834df8aa4f55c90de16b71a3d6ca8d (patch)
tree63fbcf2a6cbe3d285fca8b2e4aa41ef18220cd50
parentdf52eab23d703142c766ac00bdb8db19d71238d0 (diff)
FDDI: defza: Add support for DEC FDDIcontroller 700 TURBOchannel adapter
Add support for the DEC FDDIcontroller 700 (DEFZA), Digital Equipment Corporation's first-generation FDDI network interface adapter, made for TURBOchannel and based on a discrete version of what eventually became Motorola's widely used CAMEL chipset. The CAMEL chipset is present for example in the DEC FDDIcontroller TURBOchannel, EISA and PCI adapters (DEFTA/DEFEA/DEFPA) that we support with the `defxx' driver, however the host bus interface logic and the firmware API are different in the DEFZA and hence a separate driver is required. There isn't much to say about the driver except that it works, but there is one peculiarity to mention. The adapter implements two Tx/Rx queue pairs. Of these one pair is the usual network Tx/Rx queue pair, in this case used by the adapter to exchange frames with the ring, via the RMC (Ring Memory Controller) chip. The Tx queue is handled directly by the RMC chip and resides in onboard packet memory. The Rx queue is maintained via DMA in host memory by adapter's firmware copying received data stored by the RMC in onboard packet memory. The other pair is used to communicate SMT frames with adapter's firmware. Any SMT frame received from the RMC via the Rx queue must be queued back by the driver to the SMT Rx queue for the firmware to process. Similarly the firmware uses the SMT Tx queue to supply the driver with SMT frames that must be queued back to the Tx queue for the RMC to send to the ring. This solution was chosen because the designers ran out of PCB space and could not squeeze in more logic onto the board that would be required to handle this SMT frame traffic without the need to involve the driver, as with the later DEFTA/DEFEA/DEFPA adapters. Finally the driver does some Frame Control byte decoding, so to avoid magic numbers some macros are added to <linux/if_fddi.h>. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--Documentation/networking/00-INDEX2
-rw-r--r--Documentation/networking/defza.txt57
-rw-r--r--MAINTAINERS5
-rw-r--r--drivers/net/fddi/Kconfig11
-rw-r--r--drivers/net/fddi/Makefile1
-rw-r--r--drivers/net/fddi/defza.c1535
-rw-r--r--drivers/net/fddi/defza.h791
-rw-r--r--include/uapi/linux/if_fddi.h21
8 files changed, 2420 insertions, 3 deletions
diff --git a/Documentation/networking/00-INDEX b/Documentation/networking/00-INDEX
index f4f2b5d6c8d8..2d239770b95f 100644
--- a/Documentation/networking/00-INDEX
+++ b/Documentation/networking/00-INDEX
@@ -56,6 +56,8 @@ de4x5.txt
56 - the Digital EtherWORKS DE4?? and DE5?? PCI Ethernet driver 56 - the Digital EtherWORKS DE4?? and DE5?? PCI Ethernet driver
57decnet.txt 57decnet.txt
58 - info on using the DECnet networking layer in Linux. 58 - info on using the DECnet networking layer in Linux.
59defza.txt
60 - the DEC FDDIcontroller 700 (DEFZA-xx) TURBOchannel FDDI driver
59dl2k.txt 61dl2k.txt
60 - README for D-Link DL2000-based Gigabit Ethernet Adapters (dl2k.ko). 62 - README for D-Link DL2000-based Gigabit Ethernet Adapters (dl2k.ko).
61dm9000.txt 63dm9000.txt
diff --git a/Documentation/networking/defza.txt b/Documentation/networking/defza.txt
new file mode 100644
index 000000000000..663e4a906751
--- /dev/null
+++ b/Documentation/networking/defza.txt
@@ -0,0 +1,57 @@
1Notes on the DEC FDDIcontroller 700 (DEFZA-xx) driver v.1.1.4.
2
3
4DEC FDDIcontroller 700 is DEC's first-generation TURBOchannel FDDI
5network card, designed in 1990 specifically for the DECstation 5000
6model 200 workstation. The board is a single attachment station and
7it was manufactured in two variations, both of which are supported.
8
9First is the SAS MMF DEFZA-AA option, the original design implementing
10the standard MMF-PMD, however with a pair of ST connectors rather than
11the usual MIC connector. The other one is the SAS ThinWire/STP DEFZA-CA
12option, denoted 700-C, with the network medium selectable by a switch
13between the DEC proprietary ThinWire-PMD using a BNC connector and the
14standard STP-PMD using a DE-9F connector. This option can interface to
15a DECconcentrator 500 device and, in the case of the STP-PMD, also other
16FDDI equipment and was designed to make it easier to transition from
17existing IEEE 802.3 10BASE2 Ethernet and IEEE 802.5 Token Ring networks
18by providing means to reuse existing cabling.
19
20This driver handles any number of cards installed in a single system.
21They get fddi0, fddi1, etc. interface names assigned in the order of
22increasing TURBOchannel slot numbers.
23
24The board only supports DMA on the receive side. Transmission involves
25the use of PIO. As a result under a heavy transmission load there will
26be a significant impact on system performance.
27
28The board supports a 64-entry CAM for matching destination addresses.
29Two entries are preoccupied by the Directed Beacon and Ring Purger
30multicast addresses and the rest is used as a multicast filter. An
31all-multi mode is also supported for LLC frames and it is used if
32requested explicitly or if the CAM overflows. The promiscuous mode
33supports separate enables for LLC and SMT frames, but this driver
34doesn't support changing them individually.
35
36
37Known problems:
38
39None.
40
41
42To do:
43
445. MAC address change. The card does not support changing the Media
45 Access Controller's address registers but a similar effect can be
46 achieved by adding an alias to the CAM. There is no way to disable
47 matching against the original address though.
48
497. Queueing incoming/outgoing SMT frames in the driver if the SMT
50 receive/RMC transmit ring is full. (?)
51
528. Retrieving/reporting FDDI/SNMP stats.
53
54
55Both success and failure reports are welcome.
56
57Maciej W. Rozycki <macro@linux-mips.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index 6d5161def3f3..031127139f3b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4170,6 +4170,11 @@ S: Maintained
4170F: drivers/platform/x86/dell-smbios-wmi.c 4170F: drivers/platform/x86/dell-smbios-wmi.c
4171F: tools/wmi/dell-smbios-example.c 4171F: tools/wmi/dell-smbios-example.c
4172 4172
4173DEFZA FDDI NETWORK DRIVER
4174M: "Maciej W. Rozycki" <macro@linux-mips.org>
4175S: Maintained
4176F: drivers/net/fddi/defza.*
4177
4173DELL LAPTOP DRIVER 4178DELL LAPTOP DRIVER
4174M: Matthew Garrett <mjg59@srcf.ucam.org> 4179M: Matthew Garrett <mjg59@srcf.ucam.org>
4175M: Pali Rohár <pali.rohar@gmail.com> 4180M: Pali Rohár <pali.rohar@gmail.com>
diff --git a/drivers/net/fddi/Kconfig b/drivers/net/fddi/Kconfig
index 3a424c864f4d..d62e8c6205f7 100644
--- a/drivers/net/fddi/Kconfig
+++ b/drivers/net/fddi/Kconfig
@@ -15,6 +15,17 @@ config FDDI
15 15
16if FDDI 16if FDDI
17 17
18config DEFZA
19 tristate "DEC FDDIcontroller 700/700-C (DEFZA-xx) support"
20 depends on FDDI && TC
21 help
22 This is support for the DEC FDDIcontroller 700 (DEFZA-AA, fiber)
23 and 700-C (DEFZA-CA, copper) TURBOchannel network cards which
24 can connect you to a local FDDI network.
25
26 To compile this driver as a module, choose M here: the module
27 will be called defza. If unsure, say N.
28
18config DEFXX 29config DEFXX
19 tristate "Digital DEFTA/DEFEA/DEFPA adapter support" 30 tristate "Digital DEFTA/DEFEA/DEFPA adapter support"
20 depends on FDDI && (PCI || EISA || TC) 31 depends on FDDI && (PCI || EISA || TC)
diff --git a/drivers/net/fddi/Makefile b/drivers/net/fddi/Makefile
index 36da19c9a8aa..194b52cc20b0 100644
--- a/drivers/net/fddi/Makefile
+++ b/drivers/net/fddi/Makefile
@@ -3,4 +3,5 @@
3# 3#
4 4
5obj-$(CONFIG_DEFXX) += defxx.o 5obj-$(CONFIG_DEFXX) += defxx.o
6obj-$(CONFIG_DEFZA) += defza.o
6obj-$(CONFIG_SKFP) += skfp/ 7obj-$(CONFIG_SKFP) += skfp/
diff --git a/drivers/net/fddi/defza.c b/drivers/net/fddi/defza.c
new file mode 100644
index 000000000000..7d01b70f7ed8
--- /dev/null
+++ b/drivers/net/fddi/defza.c
@@ -0,0 +1,1535 @@
1// SPDX-License-Identifier: GPL-2.0
2/* FDDI network adapter driver for DEC FDDIcontroller 700/700-C devices.
3 *
4 * Copyright (c) 2018 Maciej W. Rozycki
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * References:
12 *
13 * Dave Sawyer & Phil Weeks & Frank Itkowsky,
14 * "DEC FDDIcontroller 700 Port Specification",
15 * Revision 1.1, Digital Equipment Corporation
16 */
17
18/* ------------------------------------------------------------------------- */
19/* FZA configurable parameters. */
20
21/* The number of transmit ring descriptors; either 0 for 512 or 1 for 1024. */
22#define FZA_RING_TX_MODE 0
23
24/* The number of receive ring descriptors; from 2 up to 256. */
25#define FZA_RING_RX_SIZE 256
26
27/* End of FZA configurable parameters. No need to change anything below. */
28/* ------------------------------------------------------------------------- */
29
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <linux/dma-mapping.h>
33#include <linux/init.h>
34#include <linux/interrupt.h>
35#include <linux/io.h>
36#include <linux/ioport.h>
37#include <linux/kernel.h>
38#include <linux/list.h>
39#include <linux/module.h>
40#include <linux/netdevice.h>
41#include <linux/fddidevice.h>
42#include <linux/sched.h>
43#include <linux/skbuff.h>
44#include <linux/spinlock.h>
45#include <linux/stat.h>
46#include <linux/tc.h>
47#include <linux/timer.h>
48#include <linux/types.h>
49#include <linux/wait.h>
50
51#include <asm/barrier.h>
52
53#include "defza.h"
54
55#define DRV_NAME "defza"
56#define DRV_VERSION "v.1.1.4"
57#define DRV_RELDATE "Oct 6 2018"
58
59static char version[] =
60 DRV_NAME ": " DRV_VERSION " " DRV_RELDATE " Maciej W. Rozycki\n";
61
62MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");
63MODULE_DESCRIPTION("DEC FDDIcontroller 700 (DEFZA-xx) driver");
64MODULE_LICENSE("GPL");
65
66static int loopback;
67module_param(loopback, int, 0644);
68
69/* Ring Purger Multicast */
70static u8 hw_addr_purger[8] = { 0x09, 0x00, 0x2b, 0x02, 0x01, 0x05 };
71/* Directed Beacon Multicast */
72static u8 hw_addr_beacon[8] = { 0x01, 0x80, 0xc2, 0x00, 0x01, 0x00 };
73
74/* Shorthands for MMIO accesses that we require to be strongly ordered
75 * WRT preceding MMIO accesses.
76 */
77#define readw_o readw_relaxed
78#define readl_o readl_relaxed
79
80#define writew_o writew_relaxed
81#define writel_o writel_relaxed
82
83/* Shorthands for MMIO accesses that we are happy with being weakly ordered
84 * WRT preceding MMIO accesses.
85 */
86#define readw_u readw_relaxed
87#define readl_u readl_relaxed
88#define readq_u readq_relaxed
89
90#define writew_u writew_relaxed
91#define writel_u writel_relaxed
92#define writeq_u writeq_relaxed
93
94static inline struct sk_buff *fza_alloc_skb_irq(struct net_device *dev,
95 unsigned int length)
96{
97 return __netdev_alloc_skb(dev, length, GFP_ATOMIC);
98}
99
100static inline struct sk_buff *fza_alloc_skb(struct net_device *dev,
101 unsigned int length)
102{
103 return __netdev_alloc_skb(dev, length, GFP_KERNEL);
104}
105
106static inline void fza_skb_align(struct sk_buff *skb, unsigned int v)
107{
108 unsigned long x, y;
109
110 x = (unsigned long)skb->data;
111 y = ALIGN(x, v);
112
113 skb_reserve(skb, y - x);
114}
115
116static inline void fza_reads(const void __iomem *from, void *to,
117 unsigned long size)
118{
119 if (sizeof(unsigned long) == 8) {
120 const u64 __iomem *src = from;
121 const u32 __iomem *src_trail;
122 u64 *dst = to;
123 u32 *dst_trail;
124
125 for (size = (size + 3) / 4; size > 1; size -= 2)
126 *dst++ = readq_u(src++);
127 if (size) {
128 src_trail = (u32 __iomem *)src;
129 dst_trail = (u32 *)dst;
130 *dst_trail = readl_u(src_trail);
131 }
132 } else {
133 const u32 __iomem *src = from;
134 u32 *dst = to;
135
136 for (size = (size + 3) / 4; size; size--)
137 *dst++ = readl_u(src++);
138 }
139}
140
141static inline void fza_writes(const void *from, void __iomem *to,
142 unsigned long size)
143{
144 if (sizeof(unsigned long) == 8) {
145 const u64 *src = from;
146 const u32 *src_trail;
147 u64 __iomem *dst = to;
148 u32 __iomem *dst_trail;
149
150 for (size = (size + 3) / 4; size > 1; size -= 2)
151 writeq_u(*src++, dst++);
152 if (size) {
153 src_trail = (u32 *)src;
154 dst_trail = (u32 __iomem *)dst;
155 writel_u(*src_trail, dst_trail);
156 }
157 } else {
158 const u32 *src = from;
159 u32 __iomem *dst = to;
160
161 for (size = (size + 3) / 4; size; size--)
162 writel_u(*src++, dst++);
163 }
164}
165
166static inline void fza_moves(const void __iomem *from, void __iomem *to,
167 unsigned long size)
168{
169 if (sizeof(unsigned long) == 8) {
170 const u64 __iomem *src = from;
171 const u32 __iomem *src_trail;
172 u64 __iomem *dst = to;
173 u32 __iomem *dst_trail;
174
175 for (size = (size + 3) / 4; size > 1; size -= 2)
176 writeq_u(readq_u(src++), dst++);
177 if (size) {
178 src_trail = (u32 __iomem *)src;
179 dst_trail = (u32 __iomem *)dst;
180 writel_u(readl_u(src_trail), dst_trail);
181 }
182 } else {
183 const u32 __iomem *src = from;
184 u32 __iomem *dst = to;
185
186 for (size = (size + 3) / 4; size; size--)
187 writel_u(readl_u(src++), dst++);
188 }
189}
190
191static inline void fza_zeros(void __iomem *to, unsigned long size)
192{
193 if (sizeof(unsigned long) == 8) {
194 u64 __iomem *dst = to;
195 u32 __iomem *dst_trail;
196
197 for (size = (size + 3) / 4; size > 1; size -= 2)
198 writeq_u(0, dst++);
199 if (size) {
200 dst_trail = (u32 __iomem *)dst;
201 writel_u(0, dst_trail);
202 }
203 } else {
204 u32 __iomem *dst = to;
205
206 for (size = (size + 3) / 4; size; size--)
207 writel_u(0, dst++);
208 }
209}
210
211static inline void fza_regs_dump(struct fza_private *fp)
212{
213 pr_debug("%s: iomem registers:\n", fp->name);
214 pr_debug(" reset: 0x%04x\n", readw_o(&fp->regs->reset));
215 pr_debug(" interrupt event: 0x%04x\n", readw_u(&fp->regs->int_event));
216 pr_debug(" status: 0x%04x\n", readw_u(&fp->regs->status));
217 pr_debug(" interrupt mask: 0x%04x\n", readw_u(&fp->regs->int_mask));
218 pr_debug(" control A: 0x%04x\n", readw_u(&fp->regs->control_a));
219 pr_debug(" control B: 0x%04x\n", readw_u(&fp->regs->control_b));
220}
221
222static inline void fza_do_reset(struct fza_private *fp)
223{
224 /* Reset the board. */
225 writew_o(FZA_RESET_INIT, &fp->regs->reset);
226 readw_o(&fp->regs->reset); /* Synchronize. */
227 readw_o(&fp->regs->reset); /* Read it back for a small delay. */
228 writew_o(FZA_RESET_CLR, &fp->regs->reset);
229
230 /* Enable all interrupt events we handle. */
231 writew_o(fp->int_mask, &fp->regs->int_mask);
232 readw_o(&fp->regs->int_mask); /* Synchronize. */
233}
234
235static inline void fza_do_shutdown(struct fza_private *fp)
236{
237 /* Disable the driver mode. */
238 writew_o(FZA_CONTROL_B_IDLE, &fp->regs->control_b);
239
240 /* And reset the board. */
241 writew_o(FZA_RESET_INIT, &fp->regs->reset);
242 readw_o(&fp->regs->reset); /* Synchronize. */
243 writew_o(FZA_RESET_CLR, &fp->regs->reset);
244 readw_o(&fp->regs->reset); /* Synchronize. */
245}
246
247static int fza_reset(struct fza_private *fp)
248{
249 unsigned long flags;
250 uint status, state;
251 long t;
252
253 pr_info("%s: resetting the board...\n", fp->name);
254
255 spin_lock_irqsave(&fp->lock, flags);
256 fp->state_chg_flag = 0;
257 fza_do_reset(fp);
258 spin_unlock_irqrestore(&fp->lock, flags);
259
260 /* DEC says RESET needs up to 30 seconds to complete. My DEFZA-AA
261 * rev. C03 happily finishes in 9.7 seconds. :-) But we need to
262 * be on the safe side...
263 */
264 t = wait_event_timeout(fp->state_chg_wait, fp->state_chg_flag,
265 45 * HZ);
266 status = readw_u(&fp->regs->status);
267 state = FZA_STATUS_GET_STATE(status);
268 if (fp->state_chg_flag == 0) {
269 pr_err("%s: RESET timed out!, state %x\n", fp->name, state);
270 return -EIO;
271 }
272 if (state != FZA_STATE_UNINITIALIZED) {
273 pr_err("%s: RESET failed!, state %x, failure ID %x\n",
274 fp->name, state, FZA_STATUS_GET_TEST(status));
275 return -EIO;
276 }
277 pr_info("%s: OK\n", fp->name);
278 pr_debug("%s: RESET: %lums elapsed\n", fp->name,
279 (45 * HZ - t) * 1000 / HZ);
280
281 return 0;
282}
283
284static struct fza_ring_cmd __iomem *fza_cmd_send(struct net_device *dev,
285 int command)
286{
287 struct fza_private *fp = netdev_priv(dev);
288 struct fza_ring_cmd __iomem *ring = fp->ring_cmd + fp->ring_cmd_index;
289 unsigned int old_mask, new_mask;
290 union fza_cmd_buf __iomem *buf;
291 struct netdev_hw_addr *ha;
292 int i;
293
294 old_mask = fp->int_mask;
295 new_mask = old_mask & ~FZA_MASK_STATE_CHG;
296 writew_u(new_mask, &fp->regs->int_mask);
297 readw_o(&fp->regs->int_mask); /* Synchronize. */
298 fp->int_mask = new_mask;
299
300 buf = fp->mmio + readl_u(&ring->buffer);
301
302 if ((readl_u(&ring->cmd_own) & FZA_RING_OWN_MASK) !=
303 FZA_RING_OWN_HOST) {
304 pr_warn("%s: command buffer full, command: %u!\n", fp->name,
305 command);
306 return NULL;
307 }
308
309 switch (command) {
310 case FZA_RING_CMD_INIT:
311 writel_u(FZA_RING_TX_MODE, &buf->init.tx_mode);
312 writel_u(FZA_RING_RX_SIZE, &buf->init.hst_rx_size);
313 fza_zeros(&buf->init.counters, sizeof(buf->init.counters));
314 break;
315
316 case FZA_RING_CMD_MODCAM:
317 i = 0;
318 fza_writes(&hw_addr_purger, &buf->cam.hw_addr[i++],
319 sizeof(*buf->cam.hw_addr));
320 fza_writes(&hw_addr_beacon, &buf->cam.hw_addr[i++],
321 sizeof(*buf->cam.hw_addr));
322 netdev_for_each_mc_addr(ha, dev) {
323 if (i >= FZA_CMD_CAM_SIZE)
324 break;
325 fza_writes(ha->addr, &buf->cam.hw_addr[i++],
326 sizeof(*buf->cam.hw_addr));
327 }
328 while (i < FZA_CMD_CAM_SIZE)
329 fza_zeros(&buf->cam.hw_addr[i++],
330 sizeof(*buf->cam.hw_addr));
331 break;
332
333 case FZA_RING_CMD_PARAM:
334 writel_u(loopback, &buf->param.loop_mode);
335 writel_u(fp->t_max, &buf->param.t_max);
336 writel_u(fp->t_req, &buf->param.t_req);
337 writel_u(fp->tvx, &buf->param.tvx);
338 writel_u(fp->lem_threshold, &buf->param.lem_threshold);
339 fza_writes(&fp->station_id, &buf->param.station_id,
340 sizeof(buf->param.station_id));
341 /* Convert to milliseconds due to buggy firmware. */
342 writel_u(fp->rtoken_timeout / 12500,
343 &buf->param.rtoken_timeout);
344 writel_u(fp->ring_purger, &buf->param.ring_purger);
345 break;
346
347 case FZA_RING_CMD_MODPROM:
348 if (dev->flags & IFF_PROMISC) {
349 writel_u(1, &buf->modprom.llc_prom);
350 writel_u(1, &buf->modprom.smt_prom);
351 } else {
352 writel_u(0, &buf->modprom.llc_prom);
353 writel_u(0, &buf->modprom.smt_prom);
354 }
355 if (dev->flags & IFF_ALLMULTI ||
356 netdev_mc_count(dev) > FZA_CMD_CAM_SIZE - 2)
357 writel_u(1, &buf->modprom.llc_multi);
358 else
359 writel_u(0, &buf->modprom.llc_multi);
360 writel_u(1, &buf->modprom.llc_bcast);
361 break;
362 }
363
364 /* Trigger the command. */
365 writel_u(FZA_RING_OWN_FZA | command, &ring->cmd_own);
366 writew_o(FZA_CONTROL_A_CMD_POLL, &fp->regs->control_a);
367
368 fp->ring_cmd_index = (fp->ring_cmd_index + 1) % FZA_RING_CMD_SIZE;
369
370 fp->int_mask = old_mask;
371 writew_u(fp->int_mask, &fp->regs->int_mask);
372
373 return ring;
374}
375
376static int fza_init_send(struct net_device *dev,
377 struct fza_cmd_init *__iomem *init)
378{
379 struct fza_private *fp = netdev_priv(dev);
380 struct fza_ring_cmd __iomem *ring;
381 unsigned long flags;
382 u32 stat;
383 long t;
384
385 spin_lock_irqsave(&fp->lock, flags);
386 fp->cmd_done_flag = 0;
387 ring = fza_cmd_send(dev, FZA_RING_CMD_INIT);
388 spin_unlock_irqrestore(&fp->lock, flags);
389 if (!ring)
390 /* This should never happen in the uninitialized state,
391 * so do not try to recover and just consider it fatal.
392 */
393 return -ENOBUFS;
394
395 /* INIT may take quite a long time (160ms for my C03). */
396 t = wait_event_timeout(fp->cmd_done_wait, fp->cmd_done_flag, 3 * HZ);
397 if (fp->cmd_done_flag == 0) {
398 pr_err("%s: INIT command timed out!, state %x\n", fp->name,
399 FZA_STATUS_GET_STATE(readw_u(&fp->regs->status)));
400 return -EIO;
401 }
402 stat = readl_u(&ring->stat);
403 if (stat != FZA_RING_STAT_SUCCESS) {
404 pr_err("%s: INIT command failed!, status %02x, state %x\n",
405 fp->name, stat,
406 FZA_STATUS_GET_STATE(readw_u(&fp->regs->status)));
407 return -EIO;
408 }
409 pr_debug("%s: INIT: %lums elapsed\n", fp->name,
410 (3 * HZ - t) * 1000 / HZ);
411
412 if (init)
413 *init = fp->mmio + readl_u(&ring->buffer);
414 return 0;
415}
416
417static void fza_rx_init(struct fza_private *fp)
418{
419 int i;
420
421 /* Fill the host receive descriptor ring. */
422 for (i = 0; i < FZA_RING_RX_SIZE; i++) {
423 writel_o(0, &fp->ring_hst_rx[i].rmc);
424 writel_o((fp->rx_dma[i] + 0x1000) >> 9,
425 &fp->ring_hst_rx[i].buffer1);
426 writel_o(fp->rx_dma[i] >> 9 | FZA_RING_OWN_FZA,
427 &fp->ring_hst_rx[i].buf0_own);
428 }
429}
430
431static void fza_set_rx_mode(struct net_device *dev)
432{
433 fza_cmd_send(dev, FZA_RING_CMD_MODCAM);
434 fza_cmd_send(dev, FZA_RING_CMD_MODPROM);
435}
436
437union fza_buffer_txp {
438 struct fza_buffer_tx *data_ptr;
439 struct fza_buffer_tx __iomem *mmio_ptr;
440};
441
442static int fza_do_xmit(union fza_buffer_txp ub, int len,
443 struct net_device *dev, int smt)
444{
445 struct fza_private *fp = netdev_priv(dev);
446 struct fza_buffer_tx __iomem *rmc_tx_ptr;
447 int i, first, frag_len, left_len;
448 u32 own, rmc;
449
450 if (((((fp->ring_rmc_txd_index - 1 + fp->ring_rmc_tx_size) -
451 fp->ring_rmc_tx_index) % fp->ring_rmc_tx_size) *
452 FZA_TX_BUFFER_SIZE) < len)
453 return 1;
454
455 first = fp->ring_rmc_tx_index;
456
457 left_len = len;
458 frag_len = FZA_TX_BUFFER_SIZE;
459 /* First descriptor is relinquished last. */
460 own = FZA_RING_TX_OWN_HOST;
461 /* First descriptor carries frame length; we don't use cut-through. */
462 rmc = FZA_RING_TX_SOP | FZA_RING_TX_VBC | len;
463 do {
464 i = fp->ring_rmc_tx_index;
465 rmc_tx_ptr = &fp->buffer_tx[i];
466
467 if (left_len < FZA_TX_BUFFER_SIZE)
468 frag_len = left_len;
469 left_len -= frag_len;
470
471 /* Length must be a multiple of 4 as only word writes are
472 * permitted!
473 */
474 frag_len = (frag_len + 3) & ~3;
475 if (smt)
476 fza_moves(ub.mmio_ptr, rmc_tx_ptr, frag_len);
477 else
478 fza_writes(ub.data_ptr, rmc_tx_ptr, frag_len);
479
480 if (left_len == 0)
481 rmc |= FZA_RING_TX_EOP; /* Mark last frag. */
482
483 writel_o(rmc, &fp->ring_rmc_tx[i].rmc);
484 writel_o(own, &fp->ring_rmc_tx[i].own);
485
486 ub.data_ptr++;
487 fp->ring_rmc_tx_index = (fp->ring_rmc_tx_index + 1) %
488 fp->ring_rmc_tx_size;
489
490 /* Settings for intermediate frags. */
491 own = FZA_RING_TX_OWN_RMC;
492 rmc = 0;
493 } while (left_len > 0);
494
495 if (((((fp->ring_rmc_txd_index - 1 + fp->ring_rmc_tx_size) -
496 fp->ring_rmc_tx_index) % fp->ring_rmc_tx_size) *
497 FZA_TX_BUFFER_SIZE) < dev->mtu + dev->hard_header_len) {
498 netif_stop_queue(dev);
499 pr_debug("%s: queue stopped\n", fp->name);
500 }
501
502 writel_o(FZA_RING_TX_OWN_RMC, &fp->ring_rmc_tx[first].own);
503
504 /* Go, go, go! */
505 writew_o(FZA_CONTROL_A_TX_POLL, &fp->regs->control_a);
506
507 return 0;
508}
509
510static int fza_do_recv_smt(struct fza_buffer_tx *data_ptr, int len,
511 u32 rmc, struct net_device *dev)
512{
513 struct fza_private *fp = netdev_priv(dev);
514 struct fza_buffer_tx __iomem *smt_rx_ptr;
515 u32 own;
516 int i;
517
518 i = fp->ring_smt_rx_index;
519 own = readl_o(&fp->ring_smt_rx[i].own);
520 if ((own & FZA_RING_OWN_MASK) == FZA_RING_OWN_FZA)
521 return 1;
522
523 smt_rx_ptr = fp->mmio + readl_u(&fp->ring_smt_rx[i].buffer);
524
525 /* Length must be a multiple of 4 as only word writes are permitted! */
526 fza_writes(data_ptr, smt_rx_ptr, (len + 3) & ~3);
527
528 writel_o(rmc, &fp->ring_smt_rx[i].rmc);
529 writel_o(FZA_RING_OWN_FZA, &fp->ring_smt_rx[i].own);
530
531 fp->ring_smt_rx_index =
532 (fp->ring_smt_rx_index + 1) % fp->ring_smt_rx_size;
533
534 /* Grab it! */
535 writew_o(FZA_CONTROL_A_SMT_RX_POLL, &fp->regs->control_a);
536
537 return 0;
538}
539
540static void fza_tx(struct net_device *dev)
541{
542 struct fza_private *fp = netdev_priv(dev);
543 u32 own, rmc;
544 int i;
545
546 while (1) {
547 i = fp->ring_rmc_txd_index;
548 if (i == fp->ring_rmc_tx_index)
549 break;
550 own = readl_o(&fp->ring_rmc_tx[i].own);
551 if ((own & FZA_RING_OWN_MASK) == FZA_RING_TX_OWN_RMC)
552 break;
553
554 rmc = readl_u(&fp->ring_rmc_tx[i].rmc);
555 /* Only process the first descriptor. */
556 if ((rmc & FZA_RING_TX_SOP) != 0) {
557 if ((rmc & FZA_RING_TX_DCC_MASK) ==
558 FZA_RING_TX_DCC_SUCCESS) {
559 int pkt_len = (rmc & FZA_RING_PBC_MASK) - 3;
560 /* Omit PRH. */
561
562 fp->stats.tx_packets++;
563 fp->stats.tx_bytes += pkt_len;
564 } else {
565 fp->stats.tx_errors++;
566 switch (rmc & FZA_RING_TX_DCC_MASK) {
567 case FZA_RING_TX_DCC_DTP_SOP:
568 case FZA_RING_TX_DCC_DTP:
569 case FZA_RING_TX_DCC_ABORT:
570 fp->stats.tx_aborted_errors++;
571 break;
572 case FZA_RING_TX_DCC_UNDRRUN:
573 fp->stats.tx_fifo_errors++;
574 break;
575 case FZA_RING_TX_DCC_PARITY:
576 default:
577 break;
578 }
579 }
580 }
581
582 fp->ring_rmc_txd_index = (fp->ring_rmc_txd_index + 1) %
583 fp->ring_rmc_tx_size;
584 }
585
586 if (((((fp->ring_rmc_txd_index - 1 + fp->ring_rmc_tx_size) -
587 fp->ring_rmc_tx_index) % fp->ring_rmc_tx_size) *
588 FZA_TX_BUFFER_SIZE) >= dev->mtu + dev->hard_header_len) {
589 if (fp->queue_active) {
590 netif_wake_queue(dev);
591 pr_debug("%s: queue woken\n", fp->name);
592 }
593 }
594}
595
596static inline int fza_rx_err(struct fza_private *fp,
597 const u32 rmc, const u8 fc)
598{
599 int len, min_len, max_len;
600
601 len = rmc & FZA_RING_PBC_MASK;
602
603 if (unlikely((rmc & FZA_RING_RX_BAD) != 0)) {
604 fp->stats.rx_errors++;
605
606 /* Check special status codes. */
607 if ((rmc & (FZA_RING_RX_CRC | FZA_RING_RX_RRR_MASK |
608 FZA_RING_RX_DA_MASK | FZA_RING_RX_SA_MASK)) ==
609 (FZA_RING_RX_CRC | FZA_RING_RX_RRR_DADDR |
610 FZA_RING_RX_DA_CAM | FZA_RING_RX_SA_ALIAS)) {
611 if (len >= 8190)
612 fp->stats.rx_length_errors++;
613 return 1;
614 }
615 if ((rmc & (FZA_RING_RX_CRC | FZA_RING_RX_RRR_MASK |
616 FZA_RING_RX_DA_MASK | FZA_RING_RX_SA_MASK)) ==
617 (FZA_RING_RX_CRC | FZA_RING_RX_RRR_DADDR |
618 FZA_RING_RX_DA_CAM | FZA_RING_RX_SA_CAM)) {
619 /* Halt the interface to trigger a reset. */
620 writew_o(FZA_CONTROL_A_HALT, &fp->regs->control_a);
621 readw_o(&fp->regs->control_a); /* Synchronize. */
622 return 1;
623 }
624
625 /* Check the MAC status. */
626 switch (rmc & FZA_RING_RX_RRR_MASK) {
627 case FZA_RING_RX_RRR_OK:
628 if ((rmc & FZA_RING_RX_CRC) != 0)
629 fp->stats.rx_crc_errors++;
630 else if ((rmc & FZA_RING_RX_FSC_MASK) == 0 ||
631 (rmc & FZA_RING_RX_FSB_ERR) != 0)
632 fp->stats.rx_frame_errors++;
633 return 1;
634 case FZA_RING_RX_RRR_SADDR:
635 case FZA_RING_RX_RRR_DADDR:
636 case FZA_RING_RX_RRR_ABORT:
637 /* Halt the interface to trigger a reset. */
638 writew_o(FZA_CONTROL_A_HALT, &fp->regs->control_a);
639 readw_o(&fp->regs->control_a); /* Synchronize. */
640 return 1;
641 case FZA_RING_RX_RRR_LENGTH:
642 fp->stats.rx_frame_errors++;
643 return 1;
644 default:
645 return 1;
646 }
647 }
648
649 /* Packet received successfully; validate the length. */
650 switch (fc & FDDI_FC_K_FORMAT_MASK) {
651 case FDDI_FC_K_FORMAT_MANAGEMENT:
652 if ((fc & FDDI_FC_K_CLASS_MASK) == FDDI_FC_K_CLASS_ASYNC)
653 min_len = 37;
654 else
655 min_len = 17;
656 break;
657 case FDDI_FC_K_FORMAT_LLC:
658 min_len = 20;
659 break;
660 default:
661 min_len = 17;
662 break;
663 }
664 max_len = 4495;
665 if (len < min_len || len > max_len) {
666 fp->stats.rx_errors++;
667 fp->stats.rx_length_errors++;
668 return 1;
669 }
670
671 return 0;
672}
673
674static void fza_rx(struct net_device *dev)
675{
676 struct fza_private *fp = netdev_priv(dev);
677 struct sk_buff *skb, *newskb;
678 struct fza_fddihdr *frame;
679 dma_addr_t dma, newdma;
680 u32 own, rmc, buf;
681 int i, len;
682 u8 fc;
683
684 while (1) {
685 i = fp->ring_hst_rx_index;
686 own = readl_o(&fp->ring_hst_rx[i].buf0_own);
687 if ((own & FZA_RING_OWN_MASK) == FZA_RING_OWN_FZA)
688 break;
689
690 rmc = readl_u(&fp->ring_hst_rx[i].rmc);
691 skb = fp->rx_skbuff[i];
692 dma = fp->rx_dma[i];
693
694 /* The RMC doesn't count the preamble and the starting
695 * delimiter. We fix it up here for a total of 3 octets.
696 */
697 dma_rmb();
698 len = (rmc & FZA_RING_PBC_MASK) + 3;
699 frame = (struct fza_fddihdr *)skb->data;
700
701 /* We need to get at real FC. */
702 dma_sync_single_for_cpu(fp->bdev,
703 dma +
704 ((u8 *)&frame->hdr.fc - (u8 *)frame),
705 sizeof(frame->hdr.fc),
706 DMA_FROM_DEVICE);
707 fc = frame->hdr.fc;
708
709 if (fza_rx_err(fp, rmc, fc))
710 goto err_rx;
711
712 /* We have to 512-byte-align RX buffers... */
713 newskb = fza_alloc_skb_irq(dev, FZA_RX_BUFFER_SIZE + 511);
714 if (newskb) {
715 fza_skb_align(newskb, 512);
716 newdma = dma_map_single(fp->bdev, newskb->data,
717 FZA_RX_BUFFER_SIZE,
718 DMA_FROM_DEVICE);
719 if (dma_mapping_error(fp->bdev, newdma)) {
720 dev_kfree_skb_irq(newskb);
721 newskb = NULL;
722 }
723 }
724 if (newskb) {
725 int pkt_len = len - 7; /* Omit P, SD and FCS. */
726 int is_multi;
727 int rx_stat;
728
729 dma_unmap_single(fp->bdev, dma, FZA_RX_BUFFER_SIZE,
730 DMA_FROM_DEVICE);
731
732 /* Queue SMT frames to the SMT receive ring. */
733 if ((fc & (FDDI_FC_K_CLASS_MASK |
734 FDDI_FC_K_FORMAT_MASK)) ==
735 (FDDI_FC_K_CLASS_ASYNC |
736 FDDI_FC_K_FORMAT_MANAGEMENT) &&
737 (rmc & FZA_RING_RX_DA_MASK) !=
738 FZA_RING_RX_DA_PROM) {
739 if (fza_do_recv_smt((struct fza_buffer_tx *)
740 skb->data, len, rmc,
741 dev)) {
742 writel_o(FZA_CONTROL_A_SMT_RX_OVFL,
743 &fp->regs->control_a);
744 }
745 }
746
747 is_multi = ((frame->hdr.daddr[0] & 0x01) != 0);
748
749 skb_reserve(skb, 3); /* Skip over P and SD. */
750 skb_put(skb, pkt_len); /* And cut off FCS. */
751 skb->protocol = fddi_type_trans(skb, dev);
752
753 rx_stat = netif_rx(skb);
754 if (rx_stat != NET_RX_DROP) {
755 fp->stats.rx_packets++;
756 fp->stats.rx_bytes += pkt_len;
757 if (is_multi)
758 fp->stats.multicast++;
759 } else {
760 fp->stats.rx_dropped++;
761 }
762
763 skb = newskb;
764 dma = newdma;
765 fp->rx_skbuff[i] = skb;
766 fp->rx_dma[i] = dma;
767 } else {
768 fp->stats.rx_dropped++;
769 pr_notice("%s: memory squeeze, dropping packet\n",
770 fp->name);
771 }
772
773err_rx:
774 writel_o(0, &fp->ring_hst_rx[i].rmc);
775 buf = (dma + 0x1000) >> 9;
776 writel_o(buf, &fp->ring_hst_rx[i].buffer1);
777 buf = dma >> 9 | FZA_RING_OWN_FZA;
778 writel_o(buf, &fp->ring_hst_rx[i].buf0_own);
779 fp->ring_hst_rx_index =
780 (fp->ring_hst_rx_index + 1) % fp->ring_hst_rx_size;
781 }
782}
783
784static void fza_tx_smt(struct net_device *dev)
785{
786 struct fza_private *fp = netdev_priv(dev);
787 struct fza_buffer_tx __iomem *smt_tx_ptr, *skb_data_ptr;
788 int i, len;
789 u32 own;
790
791 while (1) {
792 i = fp->ring_smt_tx_index;
793 own = readl_o(&fp->ring_smt_tx[i].own);
794 if ((own & FZA_RING_OWN_MASK) == FZA_RING_OWN_FZA)
795 break;
796
797 smt_tx_ptr = fp->mmio + readl_u(&fp->ring_smt_tx[i].buffer);
798 len = readl_u(&fp->ring_smt_tx[i].rmc) & FZA_RING_PBC_MASK;
799
800 /* Queue the frame to the RMC transmit ring. */
801 if (!netif_queue_stopped(dev))
802 fza_do_xmit((union fza_buffer_txp)
803 { .mmio_ptr = smt_tx_ptr },
804 len, dev, 1);
805
806 writel_o(FZA_RING_OWN_FZA, &fp->ring_smt_tx[i].own);
807 fp->ring_smt_tx_index =
808 (fp->ring_smt_tx_index + 1) % fp->ring_smt_tx_size;
809 }
810}
811
812static void fza_uns(struct net_device *dev)
813{
814 struct fza_private *fp = netdev_priv(dev);
815 u32 own;
816 int i;
817
818 while (1) {
819 i = fp->ring_uns_index;
820 own = readl_o(&fp->ring_uns[i].own);
821 if ((own & FZA_RING_OWN_MASK) == FZA_RING_OWN_FZA)
822 break;
823
824 if (readl_u(&fp->ring_uns[i].id) == FZA_RING_UNS_RX_OVER) {
825 fp->stats.rx_errors++;
826 fp->stats.rx_over_errors++;
827 }
828
829 writel_o(FZA_RING_OWN_FZA, &fp->ring_uns[i].own);
830 fp->ring_uns_index =
831 (fp->ring_uns_index + 1) % FZA_RING_UNS_SIZE;
832 }
833}
834
835static void fza_tx_flush(struct net_device *dev)
836{
837 struct fza_private *fp = netdev_priv(dev);
838 u32 own;
839 int i;
840
841 /* Clean up the SMT TX ring. */
842 i = fp->ring_smt_tx_index;
843 do {
844 writel_o(FZA_RING_OWN_FZA, &fp->ring_smt_tx[i].own);
845 fp->ring_smt_tx_index =
846 (fp->ring_smt_tx_index + 1) % fp->ring_smt_tx_size;
847
848 } while (i != fp->ring_smt_tx_index);
849
850 /* Clean up the RMC TX ring. */
851 i = fp->ring_rmc_tx_index;
852 do {
853 own = readl_o(&fp->ring_rmc_tx[i].own);
854 if ((own & FZA_RING_OWN_MASK) == FZA_RING_TX_OWN_RMC) {
855 u32 rmc = readl_u(&fp->ring_rmc_tx[i].rmc);
856
857 writel_u(rmc | FZA_RING_TX_DTP,
858 &fp->ring_rmc_tx[i].rmc);
859 }
860 fp->ring_rmc_tx_index =
861 (fp->ring_rmc_tx_index + 1) % fp->ring_rmc_tx_size;
862
863 } while (i != fp->ring_rmc_tx_index);
864
865 /* Done. */
866 writew_o(FZA_CONTROL_A_FLUSH_DONE, &fp->regs->control_a);
867}
868
869static irqreturn_t fza_interrupt(int irq, void *dev_id)
870{
871 struct net_device *dev = dev_id;
872 struct fza_private *fp = netdev_priv(dev);
873 uint int_event;
874
875 /* Get interrupt events. */
876 int_event = readw_o(&fp->regs->int_event) & fp->int_mask;
877 if (int_event == 0)
878 return IRQ_NONE;
879
880 /* Clear the events. */
881 writew_u(int_event, &fp->regs->int_event);
882
883 /* Now handle the events. The order matters. */
884
885 /* Command finished interrupt. */
886 if ((int_event & FZA_EVENT_CMD_DONE) != 0) {
887 fp->irq_count_cmd_done++;
888
889 spin_lock(&fp->lock);
890 fp->cmd_done_flag = 1;
891 wake_up(&fp->cmd_done_wait);
892 spin_unlock(&fp->lock);
893 }
894
895 /* Transmit finished interrupt. */
896 if ((int_event & FZA_EVENT_TX_DONE) != 0) {
897 fp->irq_count_tx_done++;
898 fza_tx(dev);
899 }
900
901 /* Host receive interrupt. */
902 if ((int_event & FZA_EVENT_RX_POLL) != 0) {
903 fp->irq_count_rx_poll++;
904 fza_rx(dev);
905 }
906
907 /* SMT transmit interrupt. */
908 if ((int_event & FZA_EVENT_SMT_TX_POLL) != 0) {
909 fp->irq_count_smt_tx_poll++;
910 fza_tx_smt(dev);
911 }
912
913 /* Transmit ring flush request. */
914 if ((int_event & FZA_EVENT_FLUSH_TX) != 0) {
915 fp->irq_count_flush_tx++;
916 fza_tx_flush(dev);
917 }
918
919 /* Link status change interrupt. */
920 if ((int_event & FZA_EVENT_LINK_ST_CHG) != 0) {
921 uint status;
922
923 fp->irq_count_link_st_chg++;
924 status = readw_u(&fp->regs->status);
925 if (FZA_STATUS_GET_LINK(status) == FZA_LINK_ON) {
926 netif_carrier_on(dev);
927 pr_info("%s: link available\n", fp->name);
928 } else {
929 netif_carrier_off(dev);
930 pr_info("%s: link unavailable\n", fp->name);
931 }
932 }
933
934 /* Unsolicited event interrupt. */
935 if ((int_event & FZA_EVENT_UNS_POLL) != 0) {
936 fp->irq_count_uns_poll++;
937 fza_uns(dev);
938 }
939
940 /* State change interrupt. */
941 if ((int_event & FZA_EVENT_STATE_CHG) != 0) {
942 uint status, state;
943
944 fp->irq_count_state_chg++;
945
946 status = readw_u(&fp->regs->status);
947 state = FZA_STATUS_GET_STATE(status);
948 pr_debug("%s: state change: %x\n", fp->name, state);
949 switch (state) {
950 case FZA_STATE_RESET:
951 break;
952
953 case FZA_STATE_UNINITIALIZED:
954 netif_carrier_off(dev);
955 del_timer_sync(&fp->reset_timer);
956 fp->ring_cmd_index = 0;
957 fp->ring_uns_index = 0;
958 fp->ring_rmc_tx_index = 0;
959 fp->ring_rmc_txd_index = 0;
960 fp->ring_hst_rx_index = 0;
961 fp->ring_smt_tx_index = 0;
962 fp->ring_smt_rx_index = 0;
963 if (fp->state > state) {
964 pr_info("%s: OK\n", fp->name);
965 fza_cmd_send(dev, FZA_RING_CMD_INIT);
966 }
967 break;
968
969 case FZA_STATE_INITIALIZED:
970 if (fp->state > state) {
971 fza_set_rx_mode(dev);
972 fza_cmd_send(dev, FZA_RING_CMD_PARAM);
973 }
974 break;
975
976 case FZA_STATE_RUNNING:
977 case FZA_STATE_MAINTENANCE:
978 fp->state = state;
979 fza_rx_init(fp);
980 fp->queue_active = 1;
981 netif_wake_queue(dev);
982 pr_debug("%s: queue woken\n", fp->name);
983 break;
984
985 case FZA_STATE_HALTED:
986 fp->queue_active = 0;
987 netif_stop_queue(dev);
988 pr_debug("%s: queue stopped\n", fp->name);
989 del_timer_sync(&fp->reset_timer);
990 pr_warn("%s: halted, reason: %x\n", fp->name,
991 FZA_STATUS_GET_HALT(status));
992 fza_regs_dump(fp);
993 pr_info("%s: resetting the board...\n", fp->name);
994 fza_do_reset(fp);
995 fp->timer_state = 0;
996 fp->reset_timer.expires = jiffies + 45 * HZ;
997 add_timer(&fp->reset_timer);
998 break;
999
1000 default:
1001 pr_warn("%s: undefined state: %x\n", fp->name, state);
1002 break;
1003 }
1004
1005 spin_lock(&fp->lock);
1006 fp->state_chg_flag = 1;
1007 wake_up(&fp->state_chg_wait);
1008 spin_unlock(&fp->lock);
1009 }
1010
1011 return IRQ_HANDLED;
1012}
1013
1014static void fza_reset_timer(struct timer_list *t)
1015{
1016 struct fza_private *fp = from_timer(fp, t, reset_timer);
1017
1018 if (!fp->timer_state) {
1019 pr_err("%s: RESET timed out!\n", fp->name);
1020 pr_info("%s: trying harder...\n", fp->name);
1021
1022 /* Assert the board reset. */
1023 writew_o(FZA_RESET_INIT, &fp->regs->reset);
1024 readw_o(&fp->regs->reset); /* Synchronize. */
1025
1026 fp->timer_state = 1;
1027 fp->reset_timer.expires = jiffies + HZ;
1028 } else {
1029 /* Clear the board reset. */
1030 writew_u(FZA_RESET_CLR, &fp->regs->reset);
1031
1032 /* Enable all interrupt events we handle. */
1033 writew_o(fp->int_mask, &fp->regs->int_mask);
1034 readw_o(&fp->regs->int_mask); /* Synchronize. */
1035
1036 fp->timer_state = 0;
1037 fp->reset_timer.expires = jiffies + 45 * HZ;
1038 }
1039 add_timer(&fp->reset_timer);
1040}
1041
1042static int fza_set_mac_address(struct net_device *dev, void *addr)
1043{
1044 return -EOPNOTSUPP;
1045}
1046
1047static netdev_tx_t fza_start_xmit(struct sk_buff *skb, struct net_device *dev)
1048{
1049 struct fza_private *fp = netdev_priv(dev);
1050 unsigned int old_mask, new_mask;
1051 int ret;
1052 u8 fc;
1053
1054 skb_push(skb, 3); /* Make room for PRH. */
1055
1056 /* Decode FC to set PRH. */
1057 fc = skb->data[3];
1058 skb->data[0] = 0;
1059 skb->data[1] = 0;
1060 skb->data[2] = FZA_PRH2_NORMAL;
1061 if ((fc & FDDI_FC_K_CLASS_MASK) == FDDI_FC_K_CLASS_SYNC)
1062 skb->data[0] |= FZA_PRH0_FRAME_SYNC;
1063 switch (fc & FDDI_FC_K_FORMAT_MASK) {
1064 case FDDI_FC_K_FORMAT_MANAGEMENT:
1065 if ((fc & FDDI_FC_K_CONTROL_MASK) == 0) {
1066 /* Token. */
1067 skb->data[0] |= FZA_PRH0_TKN_TYPE_IMM;
1068 skb->data[1] |= FZA_PRH1_TKN_SEND_NONE;
1069 } else {
1070 /* SMT or MAC. */
1071 skb->data[0] |= FZA_PRH0_TKN_TYPE_UNR;
1072 skb->data[1] |= FZA_PRH1_TKN_SEND_UNR;
1073 }
1074 skb->data[1] |= FZA_PRH1_CRC_NORMAL;
1075 break;
1076 case FDDI_FC_K_FORMAT_LLC:
1077 case FDDI_FC_K_FORMAT_FUTURE:
1078 skb->data[0] |= FZA_PRH0_TKN_TYPE_UNR;
1079 skb->data[1] |= FZA_PRH1_CRC_NORMAL | FZA_PRH1_TKN_SEND_UNR;
1080 break;
1081 case FDDI_FC_K_FORMAT_IMPLEMENTOR:
1082 skb->data[0] |= FZA_PRH0_TKN_TYPE_UNR;
1083 skb->data[1] |= FZA_PRH1_TKN_SEND_ORIG;
1084 break;
1085 }
1086
1087 /* SMT transmit interrupts may sneak frames into the RMC
1088 * transmit ring. We disable them while queueing a frame
1089 * to maintain consistency.
1090 */
1091 old_mask = fp->int_mask;
1092 new_mask = old_mask & ~FZA_MASK_SMT_TX_POLL;
1093 writew_u(new_mask, &fp->regs->int_mask);
1094 readw_o(&fp->regs->int_mask); /* Synchronize. */
1095 fp->int_mask = new_mask;
1096 ret = fza_do_xmit((union fza_buffer_txp)
1097 { .data_ptr = (struct fza_buffer_tx *)skb->data },
1098 skb->len, dev, 0);
1099 fp->int_mask = old_mask;
1100 writew_u(fp->int_mask, &fp->regs->int_mask);
1101
1102 if (ret) {
1103 /* Probably an SMT packet filled the remaining space,
1104 * so just stop the queue, but don't report it as an error.
1105 */
1106 netif_stop_queue(dev);
1107 pr_debug("%s: queue stopped\n", fp->name);
1108 fp->stats.tx_dropped++;
1109 }
1110
1111 dev_kfree_skb(skb);
1112
1113 return ret;
1114}
1115
1116static int fza_open(struct net_device *dev)
1117{
1118 struct fza_private *fp = netdev_priv(dev);
1119 struct fza_ring_cmd __iomem *ring;
1120 struct sk_buff *skb;
1121 unsigned long flags;
1122 dma_addr_t dma;
1123 int ret, i;
1124 u32 stat;
1125 long t;
1126
1127 for (i = 0; i < FZA_RING_RX_SIZE; i++) {
1128 /* We have to 512-byte-align RX buffers... */
1129 skb = fza_alloc_skb(dev, FZA_RX_BUFFER_SIZE + 511);
1130 if (skb) {
1131 fza_skb_align(skb, 512);
1132 dma = dma_map_single(fp->bdev, skb->data,
1133 FZA_RX_BUFFER_SIZE,
1134 DMA_FROM_DEVICE);
1135 if (dma_mapping_error(fp->bdev, dma)) {
1136 dev_kfree_skb(skb);
1137 skb = NULL;
1138 }
1139 }
1140 if (!skb) {
1141 for (--i; i >= 0; i--) {
1142 dma_unmap_single(fp->bdev, fp->rx_dma[i],
1143 FZA_RX_BUFFER_SIZE,
1144 DMA_FROM_DEVICE);
1145 dev_kfree_skb(fp->rx_skbuff[i]);
1146 fp->rx_dma[i] = 0;
1147 fp->rx_skbuff[i] = NULL;
1148 }
1149 return -ENOMEM;
1150 }
1151 fp->rx_skbuff[i] = skb;
1152 fp->rx_dma[i] = dma;
1153 }
1154
1155 ret = fza_init_send(dev, NULL);
1156 if (ret != 0)
1157 return ret;
1158
1159 /* Purger and Beacon multicasts need to be supplied before PARAM. */
1160 fza_set_rx_mode(dev);
1161
1162 spin_lock_irqsave(&fp->lock, flags);
1163 fp->cmd_done_flag = 0;
1164 ring = fza_cmd_send(dev, FZA_RING_CMD_PARAM);
1165 spin_unlock_irqrestore(&fp->lock, flags);
1166 if (!ring)
1167 return -ENOBUFS;
1168
1169 t = wait_event_timeout(fp->cmd_done_wait, fp->cmd_done_flag, 3 * HZ);
1170 if (fp->cmd_done_flag == 0) {
1171 pr_err("%s: PARAM command timed out!, state %x\n", fp->name,
1172 FZA_STATUS_GET_STATE(readw_u(&fp->regs->status)));
1173 return -EIO;
1174 }
1175 stat = readl_u(&ring->stat);
1176 if (stat != FZA_RING_STAT_SUCCESS) {
1177 pr_err("%s: PARAM command failed!, status %02x, state %x\n",
1178 fp->name, stat,
1179 FZA_STATUS_GET_STATE(readw_u(&fp->regs->status)));
1180 return -EIO;
1181 }
1182 pr_debug("%s: PARAM: %lums elapsed\n", fp->name,
1183 (3 * HZ - t) * 1000 / HZ);
1184
1185 return 0;
1186}
1187
1188static int fza_close(struct net_device *dev)
1189{
1190 struct fza_private *fp = netdev_priv(dev);
1191 unsigned long flags;
1192 uint state;
1193 long t;
1194 int i;
1195
1196 netif_stop_queue(dev);
1197 pr_debug("%s: queue stopped\n", fp->name);
1198
1199 del_timer_sync(&fp->reset_timer);
1200 spin_lock_irqsave(&fp->lock, flags);
1201 fp->state = FZA_STATE_UNINITIALIZED;
1202 fp->state_chg_flag = 0;
1203 /* Shut the interface down. */
1204 writew_o(FZA_CONTROL_A_SHUT, &fp->regs->control_a);
1205 readw_o(&fp->regs->control_a); /* Synchronize. */
1206 spin_unlock_irqrestore(&fp->lock, flags);
1207
1208 /* DEC says SHUT needs up to 10 seconds to complete. */
1209 t = wait_event_timeout(fp->state_chg_wait, fp->state_chg_flag,
1210 15 * HZ);
1211 state = FZA_STATUS_GET_STATE(readw_o(&fp->regs->status));
1212 if (fp->state_chg_flag == 0) {
1213 pr_err("%s: SHUT timed out!, state %x\n", fp->name, state);
1214 return -EIO;
1215 }
1216 if (state != FZA_STATE_UNINITIALIZED) {
1217 pr_err("%s: SHUT failed!, state %x\n", fp->name, state);
1218 return -EIO;
1219 }
1220 pr_debug("%s: SHUT: %lums elapsed\n", fp->name,
1221 (15 * HZ - t) * 1000 / HZ);
1222
1223 for (i = 0; i < FZA_RING_RX_SIZE; i++)
1224 if (fp->rx_skbuff[i]) {
1225 dma_unmap_single(fp->bdev, fp->rx_dma[i],
1226 FZA_RX_BUFFER_SIZE, DMA_FROM_DEVICE);
1227 dev_kfree_skb(fp->rx_skbuff[i]);
1228 fp->rx_dma[i] = 0;
1229 fp->rx_skbuff[i] = NULL;
1230 }
1231
1232 return 0;
1233}
1234
1235static struct net_device_stats *fza_get_stats(struct net_device *dev)
1236{
1237 struct fza_private *fp = netdev_priv(dev);
1238
1239 return &fp->stats;
1240}
1241
1242static int fza_probe(struct device *bdev)
1243{
1244 static const struct net_device_ops netdev_ops = {
1245 .ndo_open = fza_open,
1246 .ndo_stop = fza_close,
1247 .ndo_start_xmit = fza_start_xmit,
1248 .ndo_set_rx_mode = fza_set_rx_mode,
1249 .ndo_set_mac_address = fza_set_mac_address,
1250 .ndo_get_stats = fza_get_stats,
1251 };
1252 static int version_printed;
1253 char rom_rev[4], fw_rev[4], rmc_rev[4];
1254 struct tc_dev *tdev = to_tc_dev(bdev);
1255 struct fza_cmd_init __iomem *init;
1256 resource_size_t start, len;
1257 struct net_device *dev;
1258 struct fza_private *fp;
1259 uint smt_ver, pmd_type;
1260 void __iomem *mmio;
1261 uint hw_addr[2];
1262 int ret, i;
1263
1264 if (!version_printed) {
1265 pr_info("%s", version);
1266 version_printed = 1;
1267 }
1268
1269 dev = alloc_fddidev(sizeof(*fp));
1270 if (!dev)
1271 return -ENOMEM;
1272 SET_NETDEV_DEV(dev, bdev);
1273
1274 fp = netdev_priv(dev);
1275 dev_set_drvdata(bdev, dev);
1276
1277 fp->bdev = bdev;
1278 fp->name = dev_name(bdev);
1279
1280 /* Request the I/O MEM resource. */
1281 start = tdev->resource.start;
1282 len = tdev->resource.end - start + 1;
1283 if (!request_mem_region(start, len, dev_name(bdev))) {
1284 pr_err("%s: cannot reserve MMIO region\n", fp->name);
1285 ret = -EBUSY;
1286 goto err_out_kfree;
1287 }
1288
1289 /* MMIO mapping setup. */
1290 mmio = ioremap_nocache(start, len);
1291 if (!mmio) {
1292 pr_err("%s: cannot map MMIO\n", fp->name);
1293 ret = -ENOMEM;
1294 goto err_out_resource;
1295 }
1296
1297 /* Initialize the new device structure. */
1298 switch (loopback) {
1299 case FZA_LOOP_NORMAL:
1300 case FZA_LOOP_INTERN:
1301 case FZA_LOOP_EXTERN:
1302 break;
1303 default:
1304 loopback = FZA_LOOP_NORMAL;
1305 }
1306
1307 fp->mmio = mmio;
1308 dev->irq = tdev->interrupt;
1309
1310 pr_info("%s: DEC FDDIcontroller 700 or 700-C at 0x%08llx, irq %d\n",
1311 fp->name, (long long)tdev->resource.start, dev->irq);
1312 pr_debug("%s: mapped at: 0x%p\n", fp->name, mmio);
1313
1314 fp->regs = mmio + FZA_REG_BASE;
1315 fp->ring_cmd = mmio + FZA_RING_CMD;
1316 fp->ring_uns = mmio + FZA_RING_UNS;
1317
1318 init_waitqueue_head(&fp->state_chg_wait);
1319 init_waitqueue_head(&fp->cmd_done_wait);
1320 spin_lock_init(&fp->lock);
1321 fp->int_mask = FZA_MASK_NORMAL;
1322
1323 timer_setup(&fp->reset_timer, fza_reset_timer, 0);
1324
1325 /* Sanitize the board. */
1326 fza_regs_dump(fp);
1327 fza_do_shutdown(fp);
1328
1329 ret = request_irq(dev->irq, fza_interrupt, IRQF_SHARED, fp->name, dev);
1330 if (ret != 0) {
1331 pr_err("%s: unable to get IRQ %d!\n", fp->name, dev->irq);
1332 goto err_out_map;
1333 }
1334
1335 /* Enable the driver mode. */
1336 writew_o(FZA_CONTROL_B_DRIVER, &fp->regs->control_b);
1337
1338 /* For some reason transmit done interrupts can trigger during
1339 * reset. This avoids a division error in the handler.
1340 */
1341 fp->ring_rmc_tx_size = FZA_RING_TX_SIZE;
1342
1343 ret = fza_reset(fp);
1344 if (ret != 0)
1345 goto err_out_irq;
1346
1347 ret = fza_init_send(dev, &init);
1348 if (ret != 0)
1349 goto err_out_irq;
1350
1351 fza_reads(&init->hw_addr, &hw_addr, sizeof(hw_addr));
1352 memcpy(dev->dev_addr, &hw_addr, FDDI_K_ALEN);
1353
1354 fza_reads(&init->rom_rev, &rom_rev, sizeof(rom_rev));
1355 fza_reads(&init->fw_rev, &fw_rev, sizeof(fw_rev));
1356 fza_reads(&init->rmc_rev, &rmc_rev, sizeof(rmc_rev));
1357 for (i = 3; i >= 0 && rom_rev[i] == ' '; i--)
1358 rom_rev[i] = 0;
1359 for (i = 3; i >= 0 && fw_rev[i] == ' '; i--)
1360 fw_rev[i] = 0;
1361 for (i = 3; i >= 0 && rmc_rev[i] == ' '; i--)
1362 rmc_rev[i] = 0;
1363
1364 fp->ring_rmc_tx = mmio + readl_u(&init->rmc_tx);
1365 fp->ring_rmc_tx_size = readl_u(&init->rmc_tx_size);
1366 fp->ring_hst_rx = mmio + readl_u(&init->hst_rx);
1367 fp->ring_hst_rx_size = readl_u(&init->hst_rx_size);
1368 fp->ring_smt_tx = mmio + readl_u(&init->smt_tx);
1369 fp->ring_smt_tx_size = readl_u(&init->smt_tx_size);
1370 fp->ring_smt_rx = mmio + readl_u(&init->smt_rx);
1371 fp->ring_smt_rx_size = readl_u(&init->smt_rx_size);
1372
1373 fp->buffer_tx = mmio + FZA_TX_BUFFER_ADDR(readl_u(&init->rmc_tx));
1374
1375 fp->t_max = readl_u(&init->def_t_max);
1376 fp->t_req = readl_u(&init->def_t_req);
1377 fp->tvx = readl_u(&init->def_tvx);
1378 fp->lem_threshold = readl_u(&init->lem_threshold);
1379 fza_reads(&init->def_station_id, &fp->station_id,
1380 sizeof(fp->station_id));
1381 fp->rtoken_timeout = readl_u(&init->rtoken_timeout);
1382 fp->ring_purger = readl_u(&init->ring_purger);
1383
1384 smt_ver = readl_u(&init->smt_ver);
1385 pmd_type = readl_u(&init->pmd_type);
1386
1387 pr_debug("%s: INIT parameters:\n", fp->name);
1388 pr_debug(" tx_mode: %u\n", readl_u(&init->tx_mode));
1389 pr_debug(" hst_rx_size: %u\n", readl_u(&init->hst_rx_size));
1390 pr_debug(" rmc_rev: %.4s\n", rmc_rev);
1391 pr_debug(" rom_rev: %.4s\n", rom_rev);
1392 pr_debug(" fw_rev: %.4s\n", fw_rev);
1393 pr_debug(" mop_type: %u\n", readl_u(&init->mop_type));
1394 pr_debug(" hst_rx: 0x%08x\n", readl_u(&init->hst_rx));
1395 pr_debug(" rmc_tx: 0x%08x\n", readl_u(&init->rmc_tx));
1396 pr_debug(" rmc_tx_size: %u\n", readl_u(&init->rmc_tx_size));
1397 pr_debug(" smt_tx: 0x%08x\n", readl_u(&init->smt_tx));
1398 pr_debug(" smt_tx_size: %u\n", readl_u(&init->smt_tx_size));
1399 pr_debug(" smt_rx: 0x%08x\n", readl_u(&init->smt_rx));
1400 pr_debug(" smt_rx_size: %u\n", readl_u(&init->smt_rx_size));
1401 /* TC systems are always LE, so don't bother swapping. */
1402 pr_debug(" hw_addr: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
1403 (readl_u(&init->hw_addr[0]) >> 0) & 0xff,
1404 (readl_u(&init->hw_addr[0]) >> 8) & 0xff,
1405 (readl_u(&init->hw_addr[0]) >> 16) & 0xff,
1406 (readl_u(&init->hw_addr[0]) >> 24) & 0xff,
1407 (readl_u(&init->hw_addr[1]) >> 0) & 0xff,
1408 (readl_u(&init->hw_addr[1]) >> 8) & 0xff,
1409 (readl_u(&init->hw_addr[1]) >> 16) & 0xff,
1410 (readl_u(&init->hw_addr[1]) >> 24) & 0xff);
1411 pr_debug(" def_t_req: %u\n", readl_u(&init->def_t_req));
1412 pr_debug(" def_tvx: %u\n", readl_u(&init->def_tvx));
1413 pr_debug(" def_t_max: %u\n", readl_u(&init->def_t_max));
1414 pr_debug(" lem_threshold: %u\n", readl_u(&init->lem_threshold));
1415 /* Don't bother swapping, see above. */
1416 pr_debug(" def_station_id: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
1417 (readl_u(&init->def_station_id[0]) >> 0) & 0xff,
1418 (readl_u(&init->def_station_id[0]) >> 8) & 0xff,
1419 (readl_u(&init->def_station_id[0]) >> 16) & 0xff,
1420 (readl_u(&init->def_station_id[0]) >> 24) & 0xff,
1421 (readl_u(&init->def_station_id[1]) >> 0) & 0xff,
1422 (readl_u(&init->def_station_id[1]) >> 8) & 0xff,
1423 (readl_u(&init->def_station_id[1]) >> 16) & 0xff,
1424 (readl_u(&init->def_station_id[1]) >> 24) & 0xff);
1425 pr_debug(" pmd_type_alt: %u\n", readl_u(&init->pmd_type_alt));
1426 pr_debug(" smt_ver: %u\n", readl_u(&init->smt_ver));
1427 pr_debug(" rtoken_timeout: %u\n", readl_u(&init->rtoken_timeout));
1428 pr_debug(" ring_purger: %u\n", readl_u(&init->ring_purger));
1429 pr_debug(" smt_ver_max: %u\n", readl_u(&init->smt_ver_max));
1430 pr_debug(" smt_ver_min: %u\n", readl_u(&init->smt_ver_min));
1431 pr_debug(" pmd_type: %u\n", readl_u(&init->pmd_type));
1432
1433 pr_info("%s: model %s, address %pMF\n",
1434 fp->name,
1435 pmd_type == FZA_PMD_TYPE_TW ?
1436 "700-C (DEFZA-CA), ThinWire PMD selected" :
1437 pmd_type == FZA_PMD_TYPE_STP ?
1438 "700-C (DEFZA-CA), STP PMD selected" :
1439 "700 (DEFZA-AA), MMF PMD",
1440 dev->dev_addr);
1441 pr_info("%s: ROM rev. %.4s, firmware rev. %.4s, RMC rev. %.4s, "
1442 "SMT ver. %u\n", fp->name, rom_rev, fw_rev, rmc_rev, smt_ver);
1443
1444 /* Now that we fetched initial parameters just shut the interface
1445 * until opened.
1446 */
1447 ret = fza_close(dev);
1448 if (ret != 0)
1449 goto err_out_irq;
1450
1451 /* The FZA-specific entries in the device structure. */
1452 dev->netdev_ops = &netdev_ops;
1453
1454 ret = register_netdev(dev);
1455 if (ret != 0)
1456 goto err_out_irq;
1457
1458 pr_info("%s: registered as %s\n", fp->name, dev->name);
1459 fp->name = (const char *)dev->name;
1460
1461 get_device(bdev);
1462 return 0;
1463
1464err_out_irq:
1465 del_timer_sync(&fp->reset_timer);
1466 fza_do_shutdown(fp);
1467 free_irq(dev->irq, dev);
1468
1469err_out_map:
1470 iounmap(mmio);
1471
1472err_out_resource:
1473 release_mem_region(start, len);
1474
1475err_out_kfree:
1476 free_netdev(dev);
1477
1478 pr_err("%s: initialization failure, aborting!\n", fp->name);
1479 return ret;
1480}
1481
1482static int fza_remove(struct device *bdev)
1483{
1484 struct net_device *dev = dev_get_drvdata(bdev);
1485 struct fza_private *fp = netdev_priv(dev);
1486 struct tc_dev *tdev = to_tc_dev(bdev);
1487 resource_size_t start, len;
1488
1489 put_device(bdev);
1490
1491 unregister_netdev(dev);
1492
1493 del_timer_sync(&fp->reset_timer);
1494 fza_do_shutdown(fp);
1495 free_irq(dev->irq, dev);
1496
1497 iounmap(fp->mmio);
1498
1499 start = tdev->resource.start;
1500 len = tdev->resource.end - start + 1;
1501 release_mem_region(start, len);
1502
1503 free_netdev(dev);
1504
1505 return 0;
1506}
1507
1508static struct tc_device_id const fza_tc_table[] = {
1509 { "DEC ", "PMAF-AA " },
1510 { }
1511};
1512MODULE_DEVICE_TABLE(tc, fza_tc_table);
1513
1514static struct tc_driver fza_driver = {
1515 .id_table = fza_tc_table,
1516 .driver = {
1517 .name = "defza",
1518 .bus = &tc_bus_type,
1519 .probe = fza_probe,
1520 .remove = fza_remove,
1521 },
1522};
1523
1524static int fza_init(void)
1525{
1526 return tc_register_driver(&fza_driver);
1527}
1528
1529static void fza_exit(void)
1530{
1531 tc_unregister_driver(&fza_driver);
1532}
1533
1534module_init(fza_init);
1535module_exit(fza_exit);
diff --git a/drivers/net/fddi/defza.h b/drivers/net/fddi/defza.h
new file mode 100644
index 000000000000..b06acf32738e
--- /dev/null
+++ b/drivers/net/fddi/defza.h
@@ -0,0 +1,791 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/* FDDI network adapter driver for DEC FDDIcontroller 700/700-C devices.
3 *
4 * Copyright (c) 2018 Maciej W. Rozycki
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * References:
12 *
13 * Dave Sawyer & Phil Weeks & Frank Itkowsky,
14 * "DEC FDDIcontroller 700 Port Specification",
15 * Revision 1.1, Digital Equipment Corporation
16 */
17
18#include <linux/compiler.h>
19#include <linux/if_fddi.h>
20#include <linux/spinlock.h>
21#include <linux/timer.h>
22#include <linux/types.h>
23
24/* IOmem register offsets. */
25#define FZA_REG_BASE 0x100000 /* register base address */
26#define FZA_REG_RESET 0x100200 /* reset, r/w */
27#define FZA_REG_INT_EVENT 0x100400 /* interrupt event, r/w1c */
28#define FZA_REG_STATUS 0x100402 /* status, r/o */
29#define FZA_REG_INT_MASK 0x100404 /* interrupt mask, r/w */
30#define FZA_REG_CONTROL_A 0x100500 /* control A, r/w1s */
31#define FZA_REG_CONTROL_B 0x100502 /* control B, r/w */
32
33/* Reset register constants. Bits 1:0 are r/w, others are fixed at 0. */
34#define FZA_RESET_DLU 0x0002 /* OR with INIT to blast flash memory */
35#define FZA_RESET_INIT 0x0001 /* switch into the reset state */
36#define FZA_RESET_CLR 0x0000 /* run self-test and return to work */
37
38/* Interrupt event register constants. All bits are r/w1c. */
39#define FZA_EVENT_DLU_DONE 0x0800 /* flash memory write complete */
40#define FZA_EVENT_FLUSH_TX 0x0400 /* transmit ring flush request */
41#define FZA_EVENT_PM_PARITY_ERR 0x0200 /* onboard packet memory parity err */
42#define FZA_EVENT_HB_PARITY_ERR 0x0100 /* host bus parity error */
43#define FZA_EVENT_NXM_ERR 0x0080 /* non-existent memory access error;
44 * also raised for unaligned and
45 * unsupported partial-word accesses
46 */
47#define FZA_EVENT_LINK_ST_CHG 0x0040 /* link status change */
48#define FZA_EVENT_STATE_CHG 0x0020 /* adapter state change */
49#define FZA_EVENT_UNS_POLL 0x0010 /* unsolicited event service request */
50#define FZA_EVENT_CMD_DONE 0x0008 /* command done ack */
51#define FZA_EVENT_SMT_TX_POLL 0x0004 /* SMT frame transmit request */
52#define FZA_EVENT_RX_POLL 0x0002 /* receive request (packet avail.) */
53#define FZA_EVENT_TX_DONE 0x0001 /* RMC transmit done ack */
54
55/* Status register constants. All bits are r/o. */
56#define FZA_STATUS_DLU_SHIFT 0xc /* down line upgrade status bits */
57#define FZA_STATUS_DLU_MASK 0x03
58#define FZA_STATUS_LINK_SHIFT 0xb /* link status bits */
59#define FZA_STATUS_LINK_MASK 0x01
60#define FZA_STATUS_STATE_SHIFT 0x8 /* adapter state bits */
61#define FZA_STATUS_STATE_MASK 0x07
62#define FZA_STATUS_HALT_SHIFT 0x0 /* halt reason bits */
63#define FZA_STATUS_HALT_MASK 0xff
64#define FZA_STATUS_TEST_SHIFT 0x0 /* test failure bits */
65#define FZA_STATUS_TEST_MASK 0xff
66
67#define FZA_STATUS_GET_DLU(x) (((x) >> FZA_STATUS_DLU_SHIFT) & \
68 FZA_STATUS_DLU_MASK)
69#define FZA_STATUS_GET_LINK(x) (((x) >> FZA_STATUS_LINK_SHIFT) & \
70 FZA_STATUS_LINK_MASK)
71#define FZA_STATUS_GET_STATE(x) (((x) >> FZA_STATUS_STATE_SHIFT) & \
72 FZA_STATUS_STATE_MASK)
73#define FZA_STATUS_GET_HALT(x) (((x) >> FZA_STATUS_HALT_SHIFT) & \
74 FZA_STATUS_HALT_MASK)
75#define FZA_STATUS_GET_TEST(x) (((x) >> FZA_STATUS_TEST_SHIFT) & \
76 FZA_STATUS_TEST_MASK)
77
78#define FZA_DLU_FAILURE 0x0 /* DLU catastrophic error; brain dead */
79#define FZA_DLU_ERROR 0x1 /* DLU error; old firmware intact */
80#define FZA_DLU_SUCCESS 0x2 /* DLU OK; new firmware loaded */
81
82#define FZA_LINK_OFF 0x0 /* link unavailable */
83#define FZA_LINK_ON 0x1 /* link available */
84
85#define FZA_STATE_RESET 0x0 /* resetting */
86#define FZA_STATE_UNINITIALIZED 0x1 /* after a reset */
87#define FZA_STATE_INITIALIZED 0x2 /* initialized */
88#define FZA_STATE_RUNNING 0x3 /* running (link active) */
89#define FZA_STATE_MAINTENANCE 0x4 /* running (link looped back) */
90#define FZA_STATE_HALTED 0x5 /* halted (error condition) */
91
92#define FZA_HALT_UNKNOWN 0x00 /* unknown reason */
93#define FZA_HALT_HOST 0x01 /* host-directed HALT */
94#define FZA_HALT_HB_PARITY 0x02 /* host bus parity error */
95#define FZA_HALT_NXM 0x03 /* adapter non-existent memory ref. */
96#define FZA_HALT_SW 0x04 /* adapter software fault */
97#define FZA_HALT_HW 0x05 /* adapter hardware fault */
98#define FZA_HALT_PC_TRACE 0x06 /* PC Trace path test */
99#define FZA_HALT_DLSW 0x07 /* data link software fault */
100#define FZA_HALT_DLHW 0x08 /* data link hardware fault */
101
102#define FZA_TEST_FATAL 0x00 /* self-test catastrophic failure */
103#define FZA_TEST_68K 0x01 /* 68000 CPU */
104#define FZA_TEST_SRAM_BWADDR 0x02 /* SRAM byte/word address */
105#define FZA_TEST_SRAM_DBUS 0x03 /* SRAM data bus */
106#define FZA_TEST_SRAM_STUCK1 0x04 /* SRAM stuck-at range 1 */
107#define FZA_TEST_SRAM_STUCK2 0x05 /* SRAM stuck-at range 2 */
108#define FZA_TEST_SRAM_COUPL1 0x06 /* SRAM coupling range 1 */
109#define FZA_TEST_SRAM_COUPL2 0x07 /* SRAM coupling */
110#define FZA_TEST_FLASH_CRC 0x08 /* Flash CRC */
111#define FZA_TEST_ROM 0x09 /* option ROM */
112#define FZA_TEST_PHY_CSR 0x0a /* PHY CSR */
113#define FZA_TEST_MAC_BIST 0x0b /* MAC BiST */
114#define FZA_TEST_MAC_CSR 0x0c /* MAC CSR */
115#define FZA_TEST_MAC_ADDR_UNIQ 0x0d /* MAC unique address */
116#define FZA_TEST_ELM_BIST 0x0e /* ELM BiST */
117#define FZA_TEST_ELM_CSR 0x0f /* ELM CSR */
118#define FZA_TEST_ELM_ADDR_UNIQ 0x10 /* ELM unique address */
119#define FZA_TEST_CAM 0x11 /* CAM */
120#define FZA_TEST_NIROM 0x12 /* NI ROM checksum */
121#define FZA_TEST_SC_LOOP 0x13 /* SC loopback packet */
122#define FZA_TEST_LM_LOOP 0x14 /* LM loopback packet */
123#define FZA_TEST_EB_LOOP 0x15 /* EB loopback packet */
124#define FZA_TEST_SC_LOOP_BYPS 0x16 /* SC bypass loopback packet */
125#define FZA_TEST_LM_LOOP_LOCAL 0x17 /* LM local loopback packet */
126#define FZA_TEST_EB_LOOP_LOCAL 0x18 /* EB local loopback packet */
127#define FZA_TEST_CDC_LOOP 0x19 /* CDC loopback packet */
128#define FZA_TEST_FIBER_LOOP 0x1A /* FIBER loopback packet */
129#define FZA_TEST_CAM_MATCH_LOOP 0x1B /* CAM match packet loopback */
130#define FZA_TEST_68K_IRQ_STUCK 0x1C /* 68000 interrupt line stuck-at */
131#define FZA_TEST_IRQ_PRESENT 0x1D /* interrupt present register */
132#define FZA_TEST_RMC_BIST 0x1E /* RMC BiST */
133#define FZA_TEST_RMC_CSR 0x1F /* RMC CSR */
134#define FZA_TEST_RMC_ADDR_UNIQ 0x20 /* RMC unique address */
135#define FZA_TEST_PM_DPATH 0x21 /* packet memory data path */
136#define FZA_TEST_PM_ADDR 0x22 /* packet memory address */
137#define FZA_TEST_RES_23 0x23 /* reserved */
138#define FZA_TEST_PM_DESC 0x24 /* packet memory descriptor */
139#define FZA_TEST_PM_OWN 0x25 /* packet memory own bit */
140#define FZA_TEST_PM_PARITY 0x26 /* packet memory parity */
141#define FZA_TEST_PM_BSWAP 0x27 /* packet memory byte swap */
142#define FZA_TEST_PM_WSWAP 0x28 /* packet memory word swap */
143#define FZA_TEST_PM_REF 0x29 /* packet memory refresh */
144#define FZA_TEST_PM_CSR 0x2A /* PM CSR */
145#define FZA_TEST_PORT_STATUS 0x2B /* port status register */
146#define FZA_TEST_HOST_IRQMASK 0x2C /* host interrupt mask */
147#define FZA_TEST_TIMER_IRQ1 0x2D /* RTOS timer */
148#define FZA_TEST_FORCE_IRQ1 0x2E /* force RTOS IRQ1 */
149#define FZA_TEST_TIMER_IRQ5 0x2F /* IRQ5 backoff timer */
150#define FZA_TEST_FORCE_IRQ5 0x30 /* force IRQ5 */
151#define FZA_TEST_RES_31 0x31 /* reserved */
152#define FZA_TEST_IC_PRIO 0x32 /* interrupt controller priority */
153#define FZA_TEST_PM_FULL 0x33 /* full packet memory */
154#define FZA_TEST_PMI_DMA 0x34 /* PMI DMA */
155
156/* Interrupt mask register constants. All bits are r/w. */
157#define FZA_MASK_RESERVED 0xf000 /* unused */
158#define FZA_MASK_DLU_DONE 0x0800 /* flash memory write complete */
159#define FZA_MASK_FLUSH_TX 0x0400 /* transmit ring flush request */
160#define FZA_MASK_PM_PARITY_ERR 0x0200 /* onboard packet memory parity error
161 */
162#define FZA_MASK_HB_PARITY_ERR 0x0100 /* host bus parity error */
163#define FZA_MASK_NXM_ERR 0x0080 /* adapter non-existent memory
164 * reference
165 */
166#define FZA_MASK_LINK_ST_CHG 0x0040 /* link status change */
167#define FZA_MASK_STATE_CHG 0x0020 /* adapter state change */
168#define FZA_MASK_UNS_POLL 0x0010 /* unsolicited event service request */
169#define FZA_MASK_CMD_DONE 0x0008 /* command ring entry processed */
170#define FZA_MASK_SMT_TX_POLL 0x0004 /* SMT frame transmit request */
171#define FZA_MASK_RCV_POLL 0x0002 /* receive request (packet available)
172 */
173#define FZA_MASK_TX_DONE 0x0001 /* RMC transmit done acknowledge */
174
175/* Which interrupts to receive: 0/1 is mask/unmask. */
176#define FZA_MASK_NONE 0x0000
177#define FZA_MASK_NORMAL \
178 ((~(FZA_MASK_RESERVED | FZA_MASK_DLU_DONE | \
179 FZA_MASK_PM_PARITY_ERR | FZA_MASK_HB_PARITY_ERR | \
180 FZA_MASK_NXM_ERR)) & 0xffff)
181
182/* Control A register constants. */
183#define FZA_CONTROL_A_HB_PARITY_ERR 0x8000 /* host bus parity error */
184#define FZA_CONTROL_A_NXM_ERR 0x4000 /* adapter non-existent memory
185 * reference
186 */
187#define FZA_CONTROL_A_SMT_RX_OVFL 0x0040 /* SMT receive overflow */
188#define FZA_CONTROL_A_FLUSH_DONE 0x0020 /* flush tx request complete */
189#define FZA_CONTROL_A_SHUT 0x0010 /* turn the interface off */
190#define FZA_CONTROL_A_HALT 0x0008 /* halt the controller */
191#define FZA_CONTROL_A_CMD_POLL 0x0004 /* command ring poll */
192#define FZA_CONTROL_A_SMT_RX_POLL 0x0002 /* SMT receive ring poll */
193#define FZA_CONTROL_A_TX_POLL 0x0001 /* transmit poll */
194
195/* Control B register constants. All bits are r/w.
196 *
197 * Possible values:
198 * 0x0000 after booting into REX,
199 * 0x0003 after issuing `boot #/mop'.
200 */
201#define FZA_CONTROL_B_CONSOLE 0x0002 /* OR with DRIVER for console
202 * (TC firmware) mode
203 */
204#define FZA_CONTROL_B_DRIVER 0x0001 /* driver mode */
205#define FZA_CONTROL_B_IDLE 0x0000 /* no driver installed */
206
207#define FZA_RESET_PAD \
208 (FZA_REG_RESET - FZA_REG_BASE)
209#define FZA_INT_EVENT_PAD \
210 (FZA_REG_INT_EVENT - FZA_REG_RESET - sizeof(u16))
211#define FZA_CONTROL_A_PAD \
212 (FZA_REG_CONTROL_A - FZA_REG_INT_MASK - sizeof(u16))
213
214/* Layout of registers. */
215struct fza_regs {
216 u8 pad0[FZA_RESET_PAD];
217 u16 reset; /* reset register */
218 u8 pad1[FZA_INT_EVENT_PAD];
219 u16 int_event; /* interrupt event register */
220 u16 status; /* status register */
221 u16 int_mask; /* interrupt mask register */
222 u8 pad2[FZA_CONTROL_A_PAD];
223 u16 control_a; /* control A register */
224 u16 control_b; /* control B register */
225};
226
227/* Command descriptor ring entry. */
228struct fza_ring_cmd {
229 u32 cmd_own; /* bit 31: ownership, bits [30:0]: command */
230 u32 stat; /* command status */
231 u32 buffer; /* address of the buffer in the FZA space */
232 u32 pad0;
233};
234
235#define FZA_RING_CMD 0x200400 /* command ring address */
236#define FZA_RING_CMD_SIZE 0x40 /* command descriptor ring
237 * size
238/* Command constants. */
239#define FZA_RING_CMD_MASK 0x7fffffff
240#define FZA_RING_CMD_NOP 0x00000000 /* nop */
241#define FZA_RING_CMD_INIT 0x00000001 /* initialize */
242#define FZA_RING_CMD_MODCAM 0x00000002 /* modify CAM */
243#define FZA_RING_CMD_PARAM 0x00000003 /* set system parameters */
244#define FZA_RING_CMD_MODPROM 0x00000004 /* modify promiscuous mode */
245#define FZA_RING_CMD_SETCHAR 0x00000005 /* set link characteristics */
246#define FZA_RING_CMD_RDCNTR 0x00000006 /* read counters */
247#define FZA_RING_CMD_STATUS 0x00000007 /* get link status */
248#define FZA_RING_CMD_RDCAM 0x00000008 /* read CAM */
249
250/* Command status constants. */
251#define FZA_RING_STAT_SUCCESS 0x00000000
252
253/* Unsolicited event descriptor ring entry. */
254struct fza_ring_uns {
255 u32 own; /* bit 31: ownership, bits [30:0]: reserved */
256 u32 id; /* event ID */
257 u32 buffer; /* address of the buffer in the FZA space */
258 u32 pad0; /* reserved */
259};
260
261#define FZA_RING_UNS 0x200800 /* unsolicited ring address */
262#define FZA_RING_UNS_SIZE 0x40 /* unsolicited descriptor ring
263 * size
264 */
265/* Unsolicited event constants. */
266#define FZA_RING_UNS_UND 0x00000000 /* undefined event ID */
267#define FZA_RING_UNS_INIT_IN 0x00000001 /* ring init initiated */
268#define FZA_RING_UNS_INIT_RX 0x00000002 /* ring init received */
269#define FZA_RING_UNS_BEAC_IN 0x00000003 /* ring beaconing initiated */
270#define FZA_RING_UNS_DUP_ADDR 0x00000004 /* duplicate address detected */
271#define FZA_RING_UNS_DUP_TOK 0x00000005 /* duplicate token detected */
272#define FZA_RING_UNS_PURG_ERR 0x00000006 /* ring purger error */
273#define FZA_RING_UNS_STRIP_ERR 0x00000007 /* bridge strip error */
274#define FZA_RING_UNS_OP_OSC 0x00000008 /* ring op oscillation */
275#define FZA_RING_UNS_BEAC_RX 0x00000009 /* directed beacon received */
276#define FZA_RING_UNS_PCT_IN 0x0000000a /* PC trace initiated */
277#define FZA_RING_UNS_PCT_RX 0x0000000b /* PC trace received */
278#define FZA_RING_UNS_TX_UNDER 0x0000000c /* transmit underrun */
279#define FZA_RING_UNS_TX_FAIL 0x0000000d /* transmit failure */
280#define FZA_RING_UNS_RX_OVER 0x0000000e /* receive overrun */
281
282/* RMC (Ring Memory Control) transmit descriptor ring entry. */
283struct fza_ring_rmc_tx {
284 u32 rmc; /* RMC information */
285 u32 avl; /* available for host (unused by RMC) */
286 u32 own; /* bit 31: ownership, bits [30:0]: reserved */
287 u32 pad0; /* reserved */
288};
289
290#define FZA_TX_BUFFER_ADDR(x) (0x200000 | (((x) & 0xffff) << 5))
291#define FZA_TX_BUFFER_SIZE 512
292struct fza_buffer_tx {
293 u32 data[FZA_TX_BUFFER_SIZE / sizeof(u32)];
294};
295
296/* Transmit ring RMC constants. */
297#define FZA_RING_TX_SOP 0x80000000 /* start of packet */
298#define FZA_RING_TX_EOP 0x40000000 /* end of packet */
299#define FZA_RING_TX_DTP 0x20000000 /* discard this packet */
300#define FZA_RING_TX_VBC 0x10000000 /* valid buffer byte count */
301#define FZA_RING_TX_DCC_MASK 0x0f000000 /* DMA completion code */
302#define FZA_RING_TX_DCC_SUCCESS 0x01000000 /* transmit succeeded */
303#define FZA_RING_TX_DCC_DTP_SOP 0x02000000 /* DTP set at SOP */
304#define FZA_RING_TX_DCC_DTP 0x04000000 /* DTP set within packet */
305#define FZA_RING_TX_DCC_ABORT 0x05000000 /* MAC-requested abort */
306#define FZA_RING_TX_DCC_PARITY 0x06000000 /* xmit data parity error */
307#define FZA_RING_TX_DCC_UNDRRUN 0x07000000 /* transmit underrun */
308#define FZA_RING_TX_XPO_MASK 0x003fe000 /* transmit packet offset */
309
310/* Host receive descriptor ring entry. */
311struct fza_ring_hst_rx {
312 u32 buf0_own; /* bit 31: ownership, bits [30:23]: unused,
313 * bits [22:0]: right-shifted address of the
314 * buffer in system memory (low buffer)
315 */
316 u32 buffer1; /* bits [31:23]: unused,
317 * bits [22:0]: right-shifted address of the
318 * buffer in system memory (high buffer)
319 */
320 u32 rmc; /* RMC information */
321 u32 pad0;
322};
323
324#define FZA_RX_BUFFER_SIZE (4096 + 512) /* buffer length */
325
326/* Receive ring RMC constants. */
327#define FZA_RING_RX_SOP 0x80000000 /* start of packet */
328#define FZA_RING_RX_EOP 0x40000000 /* end of packet */
329#define FZA_RING_RX_FSC_MASK 0x38000000 /* # of frame status bits */
330#define FZA_RING_RX_FSB_MASK 0x07c00000 /* frame status bits */
331#define FZA_RING_RX_FSB_ERR 0x04000000 /* error detected */
332#define FZA_RING_RX_FSB_ADDR 0x02000000 /* address recognized */
333#define FZA_RING_RX_FSB_COP 0x01000000 /* frame copied */
334#define FZA_RING_RX_FSB_F0 0x00800000 /* first additional flag */
335#define FZA_RING_RX_FSB_F1 0x00400000 /* second additional flag */
336#define FZA_RING_RX_BAD 0x00200000 /* bad packet */
337#define FZA_RING_RX_CRC 0x00100000 /* CRC error */
338#define FZA_RING_RX_RRR_MASK 0x000e0000 /* MAC receive status bits */
339#define FZA_RING_RX_RRR_OK 0x00000000 /* receive OK */
340#define FZA_RING_RX_RRR_SADDR 0x00020000 /* source address matched */
341#define FZA_RING_RX_RRR_DADDR 0x00040000 /* dest address not matched */
342#define FZA_RING_RX_RRR_ABORT 0x00060000 /* RMC abort */
343#define FZA_RING_RX_RRR_LENGTH 0x00080000 /* invalid length */
344#define FZA_RING_RX_RRR_FRAG 0x000a0000 /* fragment */
345#define FZA_RING_RX_RRR_FORMAT 0x000c0000 /* format error */
346#define FZA_RING_RX_RRR_RESET 0x000e0000 /* MAC reset */
347#define FZA_RING_RX_DA_MASK 0x00018000 /* daddr match status bits */
348#define FZA_RING_RX_DA_NONE 0x00000000 /* no match */
349#define FZA_RING_RX_DA_PROM 0x00008000 /* promiscuous match */
350#define FZA_RING_RX_DA_CAM 0x00010000 /* CAM entry match */
351#define FZA_RING_RX_DA_LOCAL 0x00018000 /* link addr or LLC bcast */
352#define FZA_RING_RX_SA_MASK 0x00006000 /* saddr match status bits */
353#define FZA_RING_RX_SA_NONE 0x00000000 /* no match */
354#define FZA_RING_RX_SA_ALIAS 0x00002000 /* alias address match */
355#define FZA_RING_RX_SA_CAM 0x00004000 /* CAM entry match */
356#define FZA_RING_RX_SA_LOCAL 0x00006000 /* link address match */
357
358/* SMT (Station Management) transmit/receive descriptor ring entry. */
359struct fza_ring_smt {
360 u32 own; /* bit 31: ownership, bits [30:0]: unused */
361 u32 rmc; /* RMC information */
362 u32 buffer; /* address of the buffer */
363 u32 pad0; /* reserved */
364};
365
366/* Ownership constants.
367 *
368 * Only an owner is permitted to process a given ring entry.
369 * RMC transmit ring meanings are reversed.
370 */
371#define FZA_RING_OWN_MASK 0x80000000
372#define FZA_RING_OWN_FZA 0x00000000 /* permit FZA, forbid host */
373#define FZA_RING_OWN_HOST 0x80000000 /* permit host, forbid FZA */
374#define FZA_RING_TX_OWN_RMC 0x80000000 /* permit RMC, forbid host */
375#define FZA_RING_TX_OWN_HOST 0x00000000 /* permit host, forbid RMC */
376
377/* RMC constants. */
378#define FZA_RING_PBC_MASK 0x00001fff /* frame length */
379
380/* Layout of counter buffers. */
381
382struct fza_counter {
383 u32 msw;
384 u32 lsw;
385};
386
387struct fza_counters {
388 struct fza_counter sys_buf; /* system buffer unavailable */
389 struct fza_counter tx_under; /* transmit underruns */
390 struct fza_counter tx_fail; /* transmit failures */
391 struct fza_counter rx_over; /* receive data overruns */
392 struct fza_counter frame_cnt; /* frame count */
393 struct fza_counter error_cnt; /* error count */
394 struct fza_counter lost_cnt; /* lost count */
395 struct fza_counter rinit_in; /* ring initialization initiated */
396 struct fza_counter rinit_rx; /* ring initialization received */
397 struct fza_counter beac_in; /* ring beacon initiated */
398 struct fza_counter dup_addr; /* duplicate address test failures */
399 struct fza_counter dup_tok; /* duplicate token detected */
400 struct fza_counter purg_err; /* ring purge errors */
401 struct fza_counter strip_err; /* bridge strip errors */
402 struct fza_counter pct_in; /* traces initiated */
403 struct fza_counter pct_rx; /* traces received */
404 struct fza_counter lem_rej; /* LEM rejects */
405 struct fza_counter tne_rej; /* TNE expiry rejects */
406 struct fza_counter lem_event; /* LEM events */
407 struct fza_counter lct_rej; /* LCT rejects */
408 struct fza_counter conn_cmpl; /* connections completed */
409 struct fza_counter el_buf; /* elasticity buffer errors */
410};
411
412/* Layout of command buffers. */
413
414/* INIT command buffer.
415 *
416 * Values of default link parameters given are as obtained from a
417 * DEFZA-AA rev. C03 board. The board counts time in units of 80ns.
418 */
419struct fza_cmd_init {
420 u32 tx_mode; /* transmit mode */
421 u32 hst_rx_size; /* host receive ring entries */
422
423 struct fza_counters counters; /* counters */
424
425 u8 rmc_rev[4]; /* RMC revision */
426 u8 rom_rev[4]; /* ROM revision */
427 u8 fw_rev[4]; /* firmware revision */
428
429 u32 mop_type; /* MOP device type */
430
431 u32 hst_rx; /* base of host rx descriptor ring */
432 u32 rmc_tx; /* base of RMC tx descriptor ring */
433 u32 rmc_tx_size; /* size of RMC tx descriptor ring */
434 u32 smt_tx; /* base of SMT tx descriptor ring */
435 u32 smt_tx_size; /* size of SMT tx descriptor ring */
436 u32 smt_rx; /* base of SMT rx descriptor ring */
437 u32 smt_rx_size; /* size of SMT rx descriptor ring */
438
439 u32 hw_addr[2]; /* link address */
440
441 u32 def_t_req; /* default Requested TTRT (T_REQ) --
442 * C03: 100000 [80ns]
443 */
444 u32 def_tvx; /* default Valid Transmission Time
445 * (TVX) -- C03: 32768 [80ns]
446 */
447 u32 def_t_max; /* default Maximum TTRT (T_MAX) --
448 * C03: 2162688 [80ns]
449 */
450 u32 lem_threshold; /* default LEM threshold -- C03: 8 */
451 u32 def_station_id[2]; /* default station ID */
452
453 u32 pmd_type_alt; /* alternative PMD type code */
454
455 u32 smt_ver; /* SMT version */
456
457 u32 rtoken_timeout; /* default restricted token timeout
458 * -- C03: 12500000 [80ns]
459 */
460 u32 ring_purger; /* default ring purger enable --
461 * C03: 1
462 */
463
464 u32 smt_ver_max; /* max SMT version ID */
465 u32 smt_ver_min; /* min SMT version ID */
466 u32 pmd_type; /* PMD type code */
467};
468
469/* INIT command PMD type codes. */
470#define FZA_PMD_TYPE_MMF 0 /* Multimode fiber */
471#define FZA_PMD_TYPE_TW 101 /* ThinWire */
472#define FZA_PMD_TYPE_STP 102 /* STP */
473
474/* MODCAM/RDCAM command buffer. */
475#define FZA_CMD_CAM_SIZE 64 /* CAM address entry count */
476struct fza_cmd_cam {
477 u32 hw_addr[FZA_CMD_CAM_SIZE][2]; /* CAM address entries */
478};
479
480/* PARAM command buffer.
481 *
482 * Permitted ranges given are as defined by the spec and obtained from a
483 * DEFZA-AA rev. C03 board, respectively. The rtoken_timeout field is
484 * erroneously interpreted in units of ms.
485 */
486struct fza_cmd_param {
487 u32 loop_mode; /* loopback mode */
488 u32 t_max; /* Maximum TTRT (T_MAX)
489 * def: ??? [80ns]
490 * C03: [t_req+1,4294967295] [80ns]
491 */
492 u32 t_req; /* Requested TTRT (T_REQ)
493 * def: [50000,2097151] [80ns]
494 * C03: [50001,t_max-1] [80ns]
495 */
496 u32 tvx; /* Valid Transmission Time (TVX)
497 * def: [29375,65280] [80ns]
498 * C03: [29376,65279] [80ns]
499 */
500 u32 lem_threshold; /* LEM threshold */
501 u32 station_id[2]; /* station ID */
502 u32 rtoken_timeout; /* restricted token timeout
503 * def: [0,125000000] [80ns]
504 * C03: [0,9999] [ms]
505 */
506 u32 ring_purger; /* ring purger enable: 0|1 */
507};
508
509/* Loopback modes for the PARAM command. */
510#define FZA_LOOP_NORMAL 0
511#define FZA_LOOP_INTERN 1
512#define FZA_LOOP_EXTERN 2
513
514/* MODPROM command buffer. */
515struct fza_cmd_modprom {
516 u32 llc_prom; /* LLC promiscuous enable */
517 u32 smt_prom; /* SMT promiscuous enable */
518 u32 llc_multi; /* LLC multicast promiscuous enable */
519 u32 llc_bcast; /* LLC broadcast promiscuous enable */
520};
521
522/* SETCHAR command buffer.
523 *
524 * Permitted ranges are as for the PARAM command.
525 */
526struct fza_cmd_setchar {
527 u32 t_max; /* Maximum TTRT (T_MAX) */
528 u32 t_req; /* Requested TTRT (T_REQ) */
529 u32 tvx; /* Valid Transmission Time (TVX) */
530 u32 lem_threshold; /* LEM threshold */
531 u32 rtoken_timeout; /* restricted token timeout */
532 u32 ring_purger; /* ring purger enable */
533};
534
535/* RDCNTR command buffer. */
536struct fza_cmd_rdcntr {
537 struct fza_counters counters; /* counters */
538};
539
540/* STATUS command buffer. */
541struct fza_cmd_status {
542 u32 led_state; /* LED state */
543 u32 rmt_state; /* ring management state */
544 u32 link_state; /* link state */
545 u32 dup_addr; /* duplicate address flag */
546 u32 ring_purger; /* ring purger state */
547 u32 t_neg; /* negotiated TTRT [80ns] */
548 u32 una[2]; /* upstream neighbour address */
549 u32 una_timeout; /* UNA timed out */
550 u32 strip_mode; /* frame strip mode */
551 u32 yield_mode; /* claim token yield mode */
552 u32 phy_state; /* PHY state */
553 u32 neigh_phy; /* neighbour PHY type */
554 u32 reject; /* reject reason */
555 u32 phy_lee; /* PHY link error estimate [-log10] */
556 u32 una_old[2]; /* old upstream neighbour address */
557 u32 rmt_mac; /* remote MAC indicated */
558 u32 ring_err; /* ring error reason */
559 u32 beac_rx[2]; /* sender of last directed beacon */
560 u32 un_dup_addr; /* upstream neighbr dup address flag */
561 u32 dna[2]; /* downstream neighbour address */
562 u32 dna_old[2]; /* old downstream neighbour address */
563};
564
565/* Common command buffer. */
566union fza_cmd_buf {
567 struct fza_cmd_init init;
568 struct fza_cmd_cam cam;
569 struct fza_cmd_param param;
570 struct fza_cmd_modprom modprom;
571 struct fza_cmd_setchar setchar;
572 struct fza_cmd_rdcntr rdcntr;
573 struct fza_cmd_status status;
574};
575
576/* MAC (Media Access Controller) chip packet request header constants. */
577
578/* Packet request header byte #0. */
579#define FZA_PRH0_FMT_TYPE_MASK 0xc0 /* type of packet, always zero */
580#define FZA_PRH0_TOK_TYPE_MASK 0x30 /* type of token required
581 * to send this frame
582 */
583#define FZA_PRH0_TKN_TYPE_ANY 0x30 /* use either token type */
584#define FZA_PRH0_TKN_TYPE_UNR 0x20 /* use an unrestricted token */
585#define FZA_PRH0_TKN_TYPE_RST 0x10 /* use a restricted token */
586#define FZA_PRH0_TKN_TYPE_IMM 0x00 /* send immediately, no token required
587 */
588#define FZA_PRH0_FRAME_MASK 0x08 /* type of frame to send */
589#define FZA_PRH0_FRAME_SYNC 0x08 /* send a synchronous frame */
590#define FZA_PRH0_FRAME_ASYNC 0x00 /* send an asynchronous frame */
591#define FZA_PRH0_MODE_MASK 0x04 /* send mode */
592#define FZA_PRH0_MODE_IMMED 0x04 /* an immediate mode, send regardless
593 * of the ring operational state
594 */
595#define FZA_PRH0_MODE_NORMAL 0x00 /* a normal mode, send only if ring
596 * operational
597 */
598#define FZA_PRH0_SF_MASK 0x02 /* send frame first */
599#define FZA_PRH0_SF_FIRST 0x02 /* send this frame first
600 * with this token capture
601 */
602#define FZA_PRH0_SF_NORMAL 0x00 /* treat this frame normally */
603#define FZA_PRH0_BCN_MASK 0x01 /* beacon frame */
604#define FZA_PRH0_BCN_BEACON 0x01 /* send the frame only
605 * if in the beacon state
606 */
607#define FZA_PRH0_BCN_DATA 0x01 /* send the frame only
608 * if in the data state
609 */
610/* Packet request header byte #1. */
611 /* bit 7 always zero */
612#define FZA_PRH1_SL_MASK 0x40 /* send frame last */
613#define FZA_PRH1_SL_LAST 0x40 /* send this frame last, releasing
614 * the token afterwards
615 */
616#define FZA_PRH1_SL_NORMAL 0x00 /* treat this frame normally */
617#define FZA_PRH1_CRC_MASK 0x20 /* CRC append */
618#define FZA_PRH1_CRC_NORMAL 0x20 /* calculate the CRC and append it
619 * as the FCS field to the frame
620 */
621#define FZA_PRH1_CRC_SKIP 0x00 /* leave the frame as is */
622#define FZA_PRH1_TKN_SEND_MASK 0x18 /* type of token to send after the
623 * frame if this is the last frame
624 */
625#define FZA_PRH1_TKN_SEND_ORIG 0x18 /* send a token of the same type as the
626 * originally captured one
627 */
628#define FZA_PRH1_TKN_SEND_RST 0x10 /* send a restricted token */
629#define FZA_PRH1_TKN_SEND_UNR 0x08 /* send an unrestricted token */
630#define FZA_PRH1_TKN_SEND_NONE 0x00 /* send no token */
631#define FZA_PRH1_EXTRA_FS_MASK 0x07 /* send extra frame status indicators
632 */
633#define FZA_PRH1_EXTRA_FS_ST 0x07 /* TR RR ST II */
634#define FZA_PRH1_EXTRA_FS_SS 0x06 /* TR RR SS II */
635#define FZA_PRH1_EXTRA_FS_SR 0x05 /* TR RR SR II */
636#define FZA_PRH1_EXTRA_FS_NONE1 0x04 /* TR RR II II */
637#define FZA_PRH1_EXTRA_FS_RT 0x03 /* TR RR RT II */
638#define FZA_PRH1_EXTRA_FS_RS 0x02 /* TR RR RS II */
639#define FZA_PRH1_EXTRA_FS_RR 0x01 /* TR RR RR II */
640#define FZA_PRH1_EXTRA_FS_NONE 0x00 /* TR RR II II */
641/* Packet request header byte #2. */
642#define FZA_PRH2_NORMAL 0x00 /* always zero */
643
644/* PRH used for LLC frames. */
645#define FZA_PRH0_LLC (FZA_PRH0_TKN_TYPE_UNR)
646#define FZA_PRH1_LLC (FZA_PRH1_CRC_NORMAL | FZA_PRH1_TKN_SEND_UNR)
647#define FZA_PRH2_LLC (FZA_PRH2_NORMAL)
648
649/* PRH used for SMT frames. */
650#define FZA_PRH0_SMT (FZA_PRH0_TKN_TYPE_UNR)
651#define FZA_PRH1_SMT (FZA_PRH1_CRC_NORMAL | FZA_PRH1_TKN_SEND_UNR)
652#define FZA_PRH2_SMT (FZA_PRH2_NORMAL)
653
654#if ((FZA_RING_RX_SIZE) < 2) || ((FZA_RING_RX_SIZE) > 256)
655# error FZA_RING_RX_SIZE has to be from 2 up to 256
656#endif
657#if ((FZA_RING_TX_MODE) != 0) && ((FZA_RING_TX_MODE) != 1)
658# error FZA_RING_TX_MODE has to be either 0 or 1
659#endif
660
661#define FZA_RING_TX_SIZE (512 << (FZA_RING_TX_MODE))
662
663struct fza_private {
664 struct device *bdev; /* pointer to the bus device */
665 const char *name; /* printable device name */
666 void __iomem *mmio; /* MMIO ioremap cookie */
667 struct fza_regs __iomem *regs; /* pointer to FZA registers */
668
669 struct sk_buff *rx_skbuff[FZA_RING_RX_SIZE];
670 /* all skbs assigned to the host
671 * receive descriptors
672 */
673 dma_addr_t rx_dma[FZA_RING_RX_SIZE];
674 /* their corresponding DMA addresses */
675
676 struct fza_ring_cmd __iomem *ring_cmd;
677 /* pointer to the command descriptor
678 * ring
679 */
680 int ring_cmd_index; /* index to the command descriptor ring
681 * for the next command
682 */
683 struct fza_ring_uns __iomem *ring_uns;
684 /* pointer to the unsolicited
685 * descriptor ring
686 */
687 int ring_uns_index; /* index to the unsolicited descriptor
688 * ring for the next event
689 */
690
691 struct fza_ring_rmc_tx __iomem *ring_rmc_tx;
692 /* pointer to the RMC transmit
693 * descriptor ring (obtained from the
694 * INIT command)
695 */
696 int ring_rmc_tx_size; /* number of entries in the RMC
697 * transmit descriptor ring (obtained
698 * from the INIT command)
699 */
700 int ring_rmc_tx_index; /* index to the RMC transmit descriptor
701 * ring for the next transmission
702 */
703 int ring_rmc_txd_index; /* index to the RMC transmit descriptor
704 * ring for the next transmit done
705 * acknowledge
706 */
707
708 struct fza_ring_hst_rx __iomem *ring_hst_rx;
709 /* pointer to the host receive
710 * descriptor ring (obtained from the
711 * INIT command)
712 */
713 int ring_hst_rx_size; /* number of entries in the host
714 * receive descriptor ring (set by the
715 * INIT command)
716 */
717 int ring_hst_rx_index; /* index to the host receive descriptor
718 * ring for the next transmission
719 */
720
721 struct fza_ring_smt __iomem *ring_smt_tx;
722 /* pointer to the SMT transmit
723 * descriptor ring (obtained from the
724 * INIT command)
725 */
726 int ring_smt_tx_size; /* number of entries in the SMT
727 * transmit descriptor ring (obtained
728 * from the INIT command)
729 */
730 int ring_smt_tx_index; /* index to the SMT transmit descriptor
731 * ring for the next transmission
732 */
733
734 struct fza_ring_smt __iomem *ring_smt_rx;
735 /* pointer to the SMT transmit
736 * descriptor ring (obtained from the
737 * INIT command)
738 */
739 int ring_smt_rx_size; /* number of entries in the SMT
740 * receive descriptor ring (obtained
741 * from the INIT command)
742 */
743 int ring_smt_rx_index; /* index to the SMT receive descriptor
744 * ring for the next transmission
745 */
746
747 struct fza_buffer_tx __iomem *buffer_tx;
748 /* pointer to the RMC transmit buffers
749 */
750
751 uint state; /* adapter expected state */
752
753 spinlock_t lock; /* for device & private data access */
754 uint int_mask; /* interrupt source selector */
755
756 int cmd_done_flag; /* command completion trigger */
757 wait_queue_head_t cmd_done_wait;
758
759 int state_chg_flag; /* state change trigger */
760 wait_queue_head_t state_chg_wait;
761
762 struct timer_list reset_timer; /* RESET time-out trigger */
763 int timer_state; /* RESET trigger state */
764
765 int queue_active; /* whether to enable queueing */
766
767 struct net_device_stats stats;
768
769 uint irq_count_flush_tx; /* transmit flush irqs */
770 uint irq_count_uns_poll; /* unsolicited event irqs */
771 uint irq_count_smt_tx_poll; /* SMT transmit irqs */
772 uint irq_count_rx_poll; /* host receive irqs */
773 uint irq_count_tx_done; /* transmit done irqs */
774 uint irq_count_cmd_done; /* command done irqs */
775 uint irq_count_state_chg; /* state change irqs */
776 uint irq_count_link_st_chg; /* link status change irqs */
777
778 uint t_max; /* T_MAX */
779 uint t_req; /* T_REQ */
780 uint tvx; /* TVX */
781 uint lem_threshold; /* LEM threshold */
782 uint station_id[2]; /* station ID */
783 uint rtoken_timeout; /* restricted token timeout */
784 uint ring_purger; /* ring purger enable flag */
785};
786
787struct fza_fddihdr {
788 u8 pa[2]; /* preamble */
789 u8 sd; /* starting delimiter */
790 struct fddihdr hdr;
791} __packed;
diff --git a/include/uapi/linux/if_fddi.h b/include/uapi/linux/if_fddi.h
index 75eed8b62823..7239aa9c0766 100644
--- a/include/uapi/linux/if_fddi.h
+++ b/include/uapi/linux/if_fddi.h
@@ -6,9 +6,10 @@
6 * 6 *
7 * Global definitions for the ANSI FDDI interface. 7 * Global definitions for the ANSI FDDI interface.
8 * 8 *
9 * Version: @(#)if_fddi.h 1.0.2 Sep 29 2004 9 * Version: @(#)if_fddi.h 1.0.3 Oct 6 2018
10 * 10 *
11 * Author: Lawrence V. Stefani, <stefani@lkg.dec.com> 11 * Author: Lawrence V. Stefani, <stefani@yahoo.com>
12 * Maintainer: Maciej W. Rozycki, <macro@linux-mips.org>
12 * 13 *
13 * if_fddi.h is based on previous if_ether.h and if_tr.h work by 14 * if_fddi.h is based on previous if_ether.h and if_tr.h work by
14 * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG> 15 * Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
@@ -45,7 +46,21 @@
45#define FDDI_K_OUI_LEN 3 /* Octets in OUI in 802.2 SNAP 46#define FDDI_K_OUI_LEN 3 /* Octets in OUI in 802.2 SNAP
46 header */ 47 header */
47 48
48/* Define FDDI Frame Control (FC) Byte values */ 49/* Define FDDI Frame Control (FC) Byte masks */
50#define FDDI_FC_K_CLASS_MASK 0x80 /* class bit */
51#define FDDI_FC_K_CLASS_SYNC 0x80
52#define FDDI_FC_K_CLASS_ASYNC 0x00
53#define FDDI_FC_K_ALEN_MASK 0x40 /* address length bit */
54#define FDDI_FC_K_ALEN_48 0x40
55#define FDDI_FC_K_ALEN_16 0x00
56#define FDDI_FC_K_FORMAT_MASK 0x30 /* format bits */
57#define FDDI_FC_K_FORMAT_FUTURE 0x30
58#define FDDI_FC_K_FORMAT_IMPLEMENTOR 0x20
59#define FDDI_FC_K_FORMAT_LLC 0x10
60#define FDDI_FC_K_FORMAT_MANAGEMENT 0x00
61#define FDDI_FC_K_CONTROL_MASK 0x0f /* control bits */
62
63/* Define FDDI Frame Control (FC) Byte specific values */
49#define FDDI_FC_K_VOID 0x00 64#define FDDI_FC_K_VOID 0x00
50#define FDDI_FC_K_NON_RESTRICTED_TOKEN 0x80 65#define FDDI_FC_K_NON_RESTRICTED_TOKEN 0x80
51#define FDDI_FC_K_RESTRICTED_TOKEN 0xC0 66#define FDDI_FC_K_RESTRICTED_TOKEN 0xC0
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-17 18:58:47 -0400