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authorJerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>2018-03-05 14:59:57 -0500
committerAlex Deucher <alexander.deucher@amd.com>2018-05-09 16:15:31 -0400
commit60a5205fb5f3da3907b8b53561571a790e7b1e70 (patch)
tree09b60cecaf06e4929e89906fcf47053d385e131d
parentc5191133405ac317d20d23c8510416e18842031d (diff)
drm/amd: Add BIOS smu_info v3_3 required struct def.
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/include/atomfirmware.h170
1 files changed, 168 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 0f5ad54d3fd3..de177ce8ca80 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -501,6 +501,32 @@ enum atom_cooling_solution_id{
501 LIQUID_COOLING = 0x01 501 LIQUID_COOLING = 0x01
502}; 502};
503 503
504struct atom_firmware_info_v3_2 {
505 struct atom_common_table_header table_header;
506 uint32_t firmware_revision;
507 uint32_t bootup_sclk_in10khz;
508 uint32_t bootup_mclk_in10khz;
509 uint32_t firmware_capability; // enum atombios_firmware_capability
510 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
511 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
512 uint16_t bootup_vddc_mv;
513 uint16_t bootup_vddci_mv;
514 uint16_t bootup_mvddc_mv;
515 uint16_t bootup_vddgfx_mv;
516 uint8_t mem_module_id;
517 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
518 uint8_t reserved1[2];
519 uint32_t mc_baseaddr_high;
520 uint32_t mc_baseaddr_low;
521 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
522 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
523 uint8_t board_i2c_feature_slave_addr;
524 uint8_t reserved3;
525 uint16_t bootup_mvddq_mv;
526 uint16_t bootup_mvpp_mv;
527 uint32_t zfbstartaddrin16mb;
528 uint32_t reserved2[3];
529};
504 530
505/* 531/*
506 *************************************************************************** 532 ***************************************************************************
@@ -1169,7 +1195,29 @@ struct atom_gfx_info_v2_2
1169 uint32_t rlc_gpu_timer_refclk; 1195 uint32_t rlc_gpu_timer_refclk;
1170}; 1196};
1171 1197
1172 1198struct atom_gfx_info_v2_3 {
1199 struct atom_common_table_header table_header;
1200 uint8_t gfxip_min_ver;
1201 uint8_t gfxip_max_ver;
1202 uint8_t max_shader_engines;
1203 uint8_t max_tile_pipes;
1204 uint8_t max_cu_per_sh;
1205 uint8_t max_sh_per_se;
1206 uint8_t max_backends_per_se;
1207 uint8_t max_texture_channel_caches;
1208 uint32_t regaddr_cp_dma_src_addr;
1209 uint32_t regaddr_cp_dma_src_addr_hi;
1210 uint32_t regaddr_cp_dma_dst_addr;
1211 uint32_t regaddr_cp_dma_dst_addr_hi;
1212 uint32_t regaddr_cp_dma_command;
1213 uint32_t regaddr_cp_status;
1214 uint32_t regaddr_rlc_gpu_clock_32;
1215 uint32_t rlc_gpu_timer_refclk;
1216 uint8_t active_cu_per_sh;
1217 uint8_t active_rb_per_se;
1218 uint16_t gcgoldenoffset;
1219 uint32_t rm21_sram_vmin_value;
1220};
1173 1221
1174/* 1222/*
1175 *************************************************************************** 1223 ***************************************************************************
@@ -1198,6 +1246,76 @@ struct atom_smu_info_v3_1
1198 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1246 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1199}; 1247};
1200 1248
1249struct atom_smu_info_v3_2 {
1250 struct atom_common_table_header table_header;
1251 uint8_t smuip_min_ver;
1252 uint8_t smuip_max_ver;
1253 uint8_t smu_rsd1;
1254 uint8_t gpuclk_ss_mode;
1255 uint16_t sclk_ss_percentage;
1256 uint16_t sclk_ss_rate_10hz;
1257 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1258 uint16_t gpuclk_ss_rate_10hz;
1259 uint32_t core_refclk_10khz;
1260 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1261 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1262 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1263 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1264 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1265 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1266 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1267 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1268 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1269 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1270 uint16_t smugoldenoffset;
1271 uint32_t gpupll_vco_freq_10khz;
1272 uint32_t bootup_smnclk_10khz;
1273 uint32_t bootup_socclk_10khz;
1274 uint32_t bootup_mp0clk_10khz;
1275 uint32_t bootup_mp1clk_10khz;
1276 uint32_t bootup_lclk_10khz;
1277 uint32_t bootup_dcefclk_10khz;
1278 uint32_t ctf_threshold_override_value;
1279 uint32_t reserved[5];
1280};
1281
1282struct atom_smu_info_v3_3 {
1283 struct atom_common_table_header table_header;
1284 uint8_t smuip_min_ver;
1285 uint8_t smuip_max_ver;
1286 uint8_t smu_rsd1;
1287 uint8_t gpuclk_ss_mode;
1288 uint16_t sclk_ss_percentage;
1289 uint16_t sclk_ss_rate_10hz;
1290 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1291 uint16_t gpuclk_ss_rate_10hz;
1292 uint32_t core_refclk_10khz;
1293 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1294 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1295 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1296 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1297 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1298 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1299 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1300 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1301 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1302 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1303 uint16_t smugoldenoffset;
1304 uint32_t gpupll_vco_freq_10khz;
1305 uint32_t bootup_smnclk_10khz;
1306 uint32_t bootup_socclk_10khz;
1307 uint32_t bootup_mp0clk_10khz;
1308 uint32_t bootup_mp1clk_10khz;
1309 uint32_t bootup_lclk_10khz;
1310 uint32_t bootup_dcefclk_10khz;
1311 uint32_t ctf_threshold_override_value;
1312 uint32_t syspll3_0_vco_freq_10khz;
1313 uint32_t syspll3_1_vco_freq_10khz;
1314 uint32_t bootup_fclk_10khz;
1315 uint32_t bootup_waflclk_10khz;
1316 uint32_t reserved[3];
1317};
1318
1201/* 1319/*
1202 *************************************************************************** 1320 ***************************************************************************
1203 Data Table smc_dpm_info structure 1321 Data Table smc_dpm_info structure
@@ -1283,7 +1401,6 @@ struct atom_smc_dpm_info_v4_1
1283 uint32_t boardreserved[10]; 1401 uint32_t boardreserved[10];
1284}; 1402};
1285 1403
1286
1287/* 1404/*
1288 *************************************************************************** 1405 ***************************************************************************
1289 Data Table asic_profiling_info structure 1406 Data Table asic_profiling_info structure
@@ -1864,6 +1981,55 @@ enum atom_smu9_syspll0_clock_id
1864 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 1981 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
1865}; 1982};
1866 1983
1984enum atom_smu11_syspll_id {
1985 SMU11_SYSPLL0_ID = 0,
1986 SMU11_SYSPLL1_0_ID = 1,
1987 SMU11_SYSPLL1_1_ID = 2,
1988 SMU11_SYSPLL1_2_ID = 3,
1989 SMU11_SYSPLL2_ID = 4,
1990 SMU11_SYSPLL3_0_ID = 5,
1991 SMU11_SYSPLL3_1_ID = 6,
1992};
1993
1994
1995enum atom_smu11_syspll0_clock_id {
1996 SMU11_SYSPLL0_SOCCLK_ID = 0, // SOCCLK
1997 SMU11_SYSPLL0_MP0CLK_ID = 1, // MP0CLK
1998 SMU11_SYSPLL0_DCLK_ID = 2, // DCLK
1999 SMU11_SYSPLL0_VCLK_ID = 3, // VCLK
2000 SMU11_SYSPLL0_ECLK_ID = 4, // ECLK
2001 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
2002};
2003
2004
2005enum atom_smu11_syspll1_0_clock_id {
2006 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
2007};
2008
2009enum atom_smu11_syspll1_1_clock_id {
2010 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
2011};
2012
2013enum atom_smu11_syspll1_2_clock_id {
2014 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
2015};
2016
2017enum atom_smu11_syspll2_clock_id {
2018 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
2019};
2020
2021enum atom_smu11_syspll3_0_clock_id {
2022 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
2023 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
2024 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
2025};
2026
2027enum atom_smu11_syspll3_1_clock_id {
2028 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
2029 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
2030 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
2031};
2032
1867struct atom_get_smu_clock_info_output_parameters_v3_1 2033struct atom_get_smu_clock_info_output_parameters_v3_1
1868{ 2034{
1869 union { 2035 union {
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