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authorOlof Johansson <olof@lixom.net>2016-07-07 01:11:20 -0400
committerOlof Johansson <olof@lixom.net>2016-07-07 01:11:20 -0400
commit5fd70b1b17d47519b908ae6a4960dfdcf0a069ca (patch)
treede7a2cd101c3dfc29eea421c20e62ba639a4686d
parent46e6b3aa65c86bf204deb5ff590e186639009427 (diff)
parent8fd763c75c3ab8e72e5d7f0d4c53531e6ff76197 (diff)
Merge tag 'renesas-dt2-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Second Round of Renesas ARM Based SoC DT Updates for v4.8 * Use APMU on R-Car Gen2 and provide SMP for r8a7793 SoC * Update console parameters to uniformly use chosen/stdout-path, serial0, not provide kernel unnecessary command line parameters * Add DU pins to silk board * Add support for blanche/r8a7792 * Name pfc subnodes after device name * tag 'renesas-dt2-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (41 commits) ARM: dts: r8a7792: add SMP support ARM: dts: r8a7793: Add APMU node and second CPU core ARM: dts: r8a7791: Add APMU node ARM: dts: r8a7790: Add APMU nodes devicetree: bindings: Renesas APMU and SMP Enable method ARM: dts: kzm9g: Update console parameters ARM: dts: kzm9d: Update console parameters ARM: dts: marzen: Add serial port config to chosen/stdout-path ARM: dts: genmai: Update console parameters ARM: dts: armadillo800eva: Update console parameters ARM: dts: r8a7792: add JPU support ARM: dts: r8a7792: add JPU clocks ARM: dts: silk: add DU pins ARM: dts: blanche: add Ethernet support ARM: dts: blanche: initial device tree ARM: dts: blanche: document Blanche board ARM: dts: r8a7792: add IRQC support ARM: dts: r8a7792: add [H]SCIF support ARM: dts: r8a7792: add SYS-DMAC support ARM: dts: r8a7792: initial SoC device tree ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/cpus.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/shmobile.txt2
-rw-r--r--Documentation/devicetree/bindings/power/renesas,apmu.txt31
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/emev2-kzm9d.dts8
-rw-r--r--arch/arm/boot/dts/r7s72100-genmai.dts4
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm.dts4
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva.dts8
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw.dts2
-rw-r--r--arch/arm/boot/dts/r8a7779-marzen.dts6
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts10
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi13
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts8
-rw-r--r--arch/arm/boot/dts/r8a7791-porter.dts4
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi7
-rw-r--r--arch/arm/boot/dts/r8a7792-blanche.dts66
-rw-r--r--arch/arm/boot/dts/r8a7792.dtsi378
-rw-r--r--arch/arm/boot/dts/r8a7793-gose.dts6
-rw-r--r--arch/arm/boot/dts/r8a7793.dtsi15
-rw-r--r--arch/arm/boot/dts/r8a7794-alt.dts4
-rw-r--r--arch/arm/boot/dts/r8a7794-silk.dts16
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g.dts8
-rw-r--r--include/dt-bindings/clock/r8a7792-clock.h103
-rw-r--r--include/dt-bindings/power/r8a7792-sysc.h26
24 files changed, 695 insertions, 36 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index ff76088f3b84..e6782d50cbcd 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -206,6 +206,7 @@ nodes to be present and contain the properties described below.
206 "qcom,gcc-msm8660" 206 "qcom,gcc-msm8660"
207 "qcom,kpss-acc-v1" 207 "qcom,kpss-acc-v1"
208 "qcom,kpss-acc-v2" 208 "qcom,kpss-acc-v2"
209 "renesas,apmu"
209 "rockchip,rk3036-smp" 210 "rockchip,rk3036-smp"
210 "rockchip,rk3066-smp" 211 "rockchip,rk3066-smp"
211 "ste,dbx500-smp" 212 "ste,dbx500-smp"
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 9cf67e48f222..6adb9d549fce 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -39,6 +39,8 @@ Boards:
39 compatible = "renesas,ape6evm", "renesas,r8a73a4" 39 compatible = "renesas,ape6evm", "renesas,r8a73a4"
40 - Atmark Techno Armadillo-800 EVA 40 - Atmark Techno Armadillo-800 EVA
41 compatible = "renesas,armadillo800eva" 41 compatible = "renesas,armadillo800eva"
42 - Blanche (RTP0RC7792SEB00010S)
43 compatible = "renesas,blanche", "renesas,r8a7792"
42 - BOCK-W 44 - BOCK-W
43 compatible = "renesas,bockw", "renesas,r8a7778" 45 compatible = "renesas,bockw", "renesas,r8a7778"
44 - Genmai (RTK772100BC00000BR) 46 - Genmai (RTK772100BC00000BR)
diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt
new file mode 100644
index 000000000000..84404c9edff7
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/renesas,apmu.txt
@@ -0,0 +1,31 @@
1DT bindings for the Renesas Advanced Power Management Unit
2
3Renesas R-Car line of SoCs utilize one or more APMU hardware units
4for CPU core power domain control including SMP boot and CPU Hotplug.
5
6Required properties:
7
8- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
9 Examples with soctypes are:
10 - "renesas,r8a7790-apmu" (R-Car H2)
11 - "renesas,r8a7791-apmu" (R-Car M2-W)
12 - "renesas,r8a7792-apmu" (R-Car V2H)
13 - "renesas,r8a7793-apmu" (R-Car M2-N)
14 - "renesas,r8a7794-apmu" (R-Car E2)
15
16- reg: Base address and length of the I/O registers used by the APMU.
17
18- cpus: This node contains a list of CPU cores, which should match the order
19 of CPU cores used by the WUPCR and PSTR registers in the Advanced Power
20 Management Unit section of the device's datasheet.
21
22
23Example:
24
25This shows the r8a7791 APMU that can control CPU0 and CPU1.
26
27 apmu@e6152000 {
28 compatible = "renesas,r8a7791-apmu", "renesas,apmu";
29 reg = <0 0xe6152000 0 0x188>;
30 cpus = <&cpu0 &cpu1>;
31 };
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e8ce0cb859ee..f65a24b861e5 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -653,6 +653,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
653 r8a7790-lager.dtb \ 653 r8a7790-lager.dtb \
654 r8a7791-koelsch.dtb \ 654 r8a7791-koelsch.dtb \
655 r8a7791-porter.dtb \ 655 r8a7791-porter.dtb \
656 r8a7792-blanche.dtb \
656 r8a7793-gose.dtb \ 657 r8a7793-gose.dtb \
657 r8a7794-alt.dtb \ 658 r8a7794-alt.dtb \
658 r8a7794-silk.dtb \ 659 r8a7794-silk.dtb \
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index 9eb86f8f32c5..60d0a732833a 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -23,9 +23,13 @@
23 reg = <0x40000000 0x8000000>; 23 reg = <0x40000000 0x8000000>;
24 }; 24 };
25 25
26 aliases {
27 serial1 = &uart1;
28 };
29
26 chosen { 30 chosen {
27 bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp"; 31 bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp";
28 stdout-path = &uart1; 32 stdout-path = "serial1:115200n8";
29 }; 33 };
30 34
31 gpio_keys { 35 gpio_keys {
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 05ba9953b4d8..118a8e2b86bd 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -17,12 +17,12 @@
17 compatible = "renesas,genmai", "renesas,r7s72100"; 17 compatible = "renesas,genmai", "renesas,r7s72100";
18 18
19 aliases { 19 aliases {
20 serial2 = &scif2; 20 serial0 = &scif2;
21 }; 21 };
22 22
23 chosen { 23 chosen {
24 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; 24 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
25 stdout-path = &scif2; 25 stdout-path = "serial0:115200n8";
26 }; 26 };
27 27
28 memory@8000000 { 28 memory@8000000 {
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index 740e5d23f7c7..ec7c86e06538 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -188,12 +188,12 @@
188}; 188};
189 189
190&pfc { 190&pfc {
191 scifa0_pins: serial0 { 191 scifa0_pins: scifa0 {
192 groups = "scifa0_data"; 192 groups = "scifa0_data";
193 function = "scifa0"; 193 function = "scifa0";
194 }; 194 };
195 195
196 mmc0_pins: mmc { 196 mmc0_pins: mmc0 {
197 groups = "mmc0_data8", "mmc0_ctrl"; 197 groups = "mmc0_data8", "mmc0_ctrl";
198 function = "mmc0"; 198 function = "mmc0";
199 }; 199 };
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index 162049516685..7885075428bb 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -20,12 +20,12 @@
20 compatible = "renesas,armadillo800eva", "renesas,r8a7740"; 20 compatible = "renesas,armadillo800eva", "renesas,r8a7740";
21 21
22 aliases { 22 aliases {
23 serial1 = &scifa1; 23 serial0 = &scifa1;
24 }; 24 };
25 25
26 chosen { 26 chosen {
27 bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; 27 bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=dhcp rw";
28 stdout-path = &scifa1; 28 stdout-path = "serial0:115200n8";
29 }; 29 };
30 30
31 memory@40000000 { 31 memory@40000000 {
@@ -232,7 +232,7 @@
232 function = "gether"; 232 function = "gether";
233 }; 233 };
234 234
235 scifa1_pins: serial1 { 235 scifa1_pins: scifa1 {
236 groups = "scifa1_data"; 236 groups = "scifa1_data";
237 function = "scifa1"; 237 function = "scifa1";
238 }; 238 };
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index 0a0bd3b6bb40..211d239d9041 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -129,7 +129,7 @@
129 pinctrl-0 = <&scif_clk_pins>; 129 pinctrl-0 = <&scif_clk_pins>;
130 pinctrl-names = "default"; 130 pinctrl-names = "default";
131 131
132 scif0_pins: serial0 { 132 scif0_pins: scif0 {
133 groups = "scif0_data_a", "scif0_ctrl"; 133 groups = "scif0_data_a", "scif0_ctrl";
134 function = "scif0"; 134 function = "scif0";
135 }; 135 };
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index cec79a6347c0..541678df90a9 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -25,7 +25,7 @@
25 25
26 chosen { 26 chosen {
27 bootargs = "ignore_loglevel root=/dev/nfs ip=on"; 27 bootargs = "ignore_loglevel root=/dev/nfs ip=on";
28 stdout-path = &scif2; 28 stdout-path = "serial0:115200n8";
29 }; 29 };
30 30
31 memory@60000000 { 31 memory@60000000 {
@@ -195,12 +195,12 @@
195 }; 195 };
196 }; 196 };
197 197
198 scif2_pins: serial2 { 198 scif2_pins: scif2 {
199 groups = "scif2_data_c"; 199 groups = "scif2_data_c";
200 function = "scif2"; 200 function = "scif2";
201 }; 201 };
202 202
203 scif4_pins: serial4 { 203 scif4_pins: scif4 {
204 groups = "scif4_data"; 204 groups = "scif4_data";
205 function = "scif4"; 205 function = "scif4";
206 }; 206 };
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 9d20ace33b01..52b56fcaddf2 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -317,7 +317,7 @@
317 function = "du"; 317 function = "du";
318 }; 318 };
319 319
320 scif0_pins: serial0 { 320 scif0_pins: scif0 {
321 groups = "scif0_data"; 321 groups = "scif0_data";
322 function = "scif0"; 322 function = "scif0";
323 }; 323 };
@@ -337,7 +337,7 @@
337 function = "intc"; 337 function = "intc";
338 }; 338 };
339 339
340 scifa1_pins: serial1 { 340 scifa1_pins: scifa1 {
341 groups = "scifa1_data"; 341 groups = "scifa1_data";
342 function = "scifa1"; 342 function = "scifa1";
343 }; 343 };
@@ -371,12 +371,12 @@
371 function = "mmc1"; 371 function = "mmc1";
372 }; 372 };
373 373
374 qspi_pins: spi0 { 374 qspi_pins: qspi {
375 groups = "qspi_ctrl", "qspi_data4"; 375 groups = "qspi_ctrl", "qspi_data4";
376 function = "qspi"; 376 function = "qspi";
377 }; 377 };
378 378
379 msiof1_pins: spi2 { 379 msiof1_pins: msiof1 {
380 groups = "msiof1_clk", "msiof1_sync", "msiof1_rx", 380 groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
381 "msiof1_tx"; 381 "msiof1_tx";
382 function = "msiof1"; 382 function = "msiof1";
@@ -427,7 +427,7 @@
427 function = "usb2"; 427 function = "usb2";
428 }; 428 };
429 429
430 vin1_pins: vin { 430 vin1_pins: vin1 {
431 groups = "vin1_data8", "vin1_clk"; 431 groups = "vin1_data8", "vin1_clk";
432 function = "vin1"; 432 function = "vin1";
433 }; 433 };
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 9997e7dfabe2..d18558f21102 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -44,6 +44,7 @@
44 cpus { 44 cpus {
45 #address-cells = <1>; 45 #address-cells = <1>;
46 #size-cells = <0>; 46 #size-cells = <0>;
47 enable-method = "renesas,apmu";
47 48
48 cpu0: cpu@0 { 49 cpu0: cpu@0 {
49 device_type = "cpu"; 50 device_type = "cpu";
@@ -164,6 +165,18 @@
164 }; 165 };
165 }; 166 };
166 167
168 apmu@e6151000 {
169 compatible = "renesas,r8a7790-apmu", "renesas,apmu";
170 reg = <0 0xe6151000 0 0x188>;
171 cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
172 };
173
174 apmu@e6152000 {
175 compatible = "renesas,r8a7790-apmu", "renesas,apmu";
176 reg = <0 0xe6152000 0 0x188>;
177 cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
178 };
179
167 gic: interrupt-controller@f1001000 { 180 gic: interrupt-controller@f1001000 {
168 compatible = "arm,gic-400"; 181 compatible = "arm,gic-400";
169 #interrupt-cells = <3>; 182 #interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 20fbc8c36a78..f8a7d090fd01 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -332,12 +332,12 @@
332 function = "du"; 332 function = "du";
333 }; 333 };
334 334
335 scif0_pins: serial0 { 335 scif0_pins: scif0 {
336 groups = "scif0_data_d"; 336 groups = "scif0_data_d";
337 function = "scif0"; 337 function = "scif0";
338 }; 338 };
339 339
340 scif1_pins: serial1 { 340 scif1_pins: scif1 {
341 groups = "scif1_data_d"; 341 groups = "scif1_data_d";
342 function = "scif1"; 342 function = "scif1";
343 }; 343 };
@@ -372,12 +372,12 @@
372 function = "sdhi2"; 372 function = "sdhi2";
373 }; 373 };
374 374
375 qspi_pins: spi0 { 375 qspi_pins: qspi {
376 groups = "qspi_ctrl", "qspi_data4"; 376 groups = "qspi_ctrl", "qspi_data4";
377 function = "qspi"; 377 function = "qspi";
378 }; 378 };
379 379
380 msiof0_pins: spi1 { 380 msiof0_pins: msiof0 {
381 groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", 381 groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
382 "msiof0_tx"; 382 "msiof0_tx";
383 function = "msiof0"; 383 function = "msiof0";
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index e9151e946da8..6761d11d3f9e 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -142,7 +142,7 @@
142}; 142};
143 143
144&pfc { 144&pfc {
145 scif0_pins: serial0 { 145 scif0_pins: scif0 {
146 groups = "scif0_data_d"; 146 groups = "scif0_data_d";
147 function = "scif0"; 147 function = "scif0";
148 }; 148 };
@@ -167,7 +167,7 @@
167 function = "sdhi2"; 167 function = "sdhi2";
168 }; 168 };
169 169
170 qspi_pins: spi0 { 170 qspi_pins: qspi {
171 groups = "qspi_ctrl", "qspi_data4"; 171 groups = "qspi_ctrl", "qspi_data4";
172 function = "qspi"; 172 function = "qspi";
173 }; 173 };
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 1985bd0dc32c..8f0086bbd96b 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -43,6 +43,7 @@
43 cpus { 43 cpus {
44 #address-cells = <1>; 44 #address-cells = <1>;
45 #size-cells = <0>; 45 #size-cells = <0>;
46 enable-method = "renesas,apmu";
46 47
47 cpu0: cpu@0 { 48 cpu0: cpu@0 {
48 device_type = "cpu"; 49 device_type = "cpu";
@@ -101,6 +102,12 @@
101 }; 102 };
102 }; 103 };
103 104
105 apmu@e6152000 {
106 compatible = "renesas,r8a7791-apmu", "renesas,apmu";
107 reg = <0 0xe6152000 0 0x188>;
108 cpus = <&cpu0 &cpu1>;
109 };
110
104 gic: interrupt-controller@f1001000 { 111 gic: interrupt-controller@f1001000 {
105 compatible = "arm,gic-400"; 112 compatible = "arm,gic-400";
106 #interrupt-cells = <3>; 113 #interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts
new file mode 100644
index 000000000000..e7b40f0e7da6
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -0,0 +1,66 @@
1/*
2 * Device Tree Source for the Blanche board
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2016 Cogent Embedded, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/dts-v1/;
13#include "r8a7792.dtsi"
14
15/ {
16 model = "Blanche";
17 compatible = "renesas,blanche", "renesas,r8a7792";
18
19 aliases {
20 serial0 = &scif0;
21 serial1 = &scif3;
22 };
23
24 chosen {
25 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
26 stdout-path = "serial0:115200n8";
27 };
28
29 memory@40000000 {
30 device_type = "memory";
31 reg = <0 0x40000000 0 0x40000000>;
32 };
33
34 d3_3v: regulator-3v3 {
35 compatible = "regulator-fixed";
36 regulator-name = "D3.3V";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 regulator-boot-on;
40 regulator-always-on;
41 };
42
43 ethernet@18000000 {
44 compatible = "smsc,lan89218", "smsc,lan9115";
45 reg = <0 0x18000000 0 0x100>;
46 phy-mode = "mii";
47 interrupt-parent = <&irqc>;
48 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
49 smsc,irq-push-pull;
50 reg-io-width = <4>;
51 vddvario-supply = <&d3_3v>;
52 vdd33a-supply = <&d3_3v>;
53 };
54};
55
56&extal_clk {
57 clock-frequency = <20000000>;
58};
59
60&scif0 {
61 status = "okay";
62};
63
64&scif3 {
65 status = "okay";
66};
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
new file mode 100644
index 000000000000..75256ef4a04d
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -0,0 +1,378 @@
1/*
2 * Device Tree Source for the r8a7792 SoC
3 *
4 * Copyright (C) 2016 Cogent Embedded Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/clock/r8a7792-clock.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/power/r8a7792-sysc.h>
15
16/ {
17 compatible = "renesas,r8a7792";
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "renesas,apmu";
25
26 cpu0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a15";
29 reg = <0>;
30 clock-frequency = <1000000000>;
31 clocks = <&cpg_clocks R8A7792_CLK_Z>;
32 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
33 next-level-cache = <&L2_CA15>;
34 };
35
36 cpu1: cpu@1 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a15";
39 reg = <1>;
40 clock-frequency = <1000000000>;
41 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
42 next-level-cache = <&L2_CA15>;
43 };
44
45 L2_CA15: cache-controller@0 {
46 compatible = "cache";
47 reg = <0>;
48 cache-unified;
49 cache-level = <2>;
50 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
51 };
52 };
53
54 soc {
55 compatible = "simple-bus";
56 interrupt-parent = <&gic>;
57
58 #address-cells = <2>;
59 #size-cells = <2>;
60 ranges;
61
62 apmu@e6152000 {
63 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
64 reg = <0 0xe6152000 0 0x188>;
65 cpus = <&cpu0 &cpu1>;
66 };
67
68 gic: interrupt-controller@f1001000 {
69 compatible = "arm,gic-400";
70 #interrupt-cells = <3>;
71 interrupt-controller;
72 reg = <0 0xf1001000 0 0x1000>,
73 <0 0xf1002000 0 0x1000>,
74 <0 0xf1004000 0 0x2000>,
75 <0 0xf1006000 0 0x2000>;
76 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
77 IRQ_TYPE_LEVEL_HIGH)>;
78 };
79
80 irqc: interrupt-controller@e61c0000 {
81 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
82 #interrupt-cells = <2>;
83 interrupt-controller;
84 reg = <0 0xe61c0000 0 0x200>;
85 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
90 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
91 };
92
93 timer {
94 compatible = "arm,armv7-timer";
95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
96 IRQ_TYPE_LEVEL_LOW)>,
97 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
98 IRQ_TYPE_LEVEL_LOW)>,
99 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
100 IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
102 IRQ_TYPE_LEVEL_LOW)>;
103 };
104
105 sysc: system-controller@e6180000 {
106 compatible = "renesas,r8a7792-sysc";
107 reg = <0 0xe6180000 0 0x0200>;
108 #power-domain-cells = <1>;
109 };
110
111 dmac0: dma-controller@e6700000 {
112 compatible = "renesas,dmac-r8a7792",
113 "renesas,rcar-dmac";
114 reg = <0 0xe6700000 0 0x20000>;
115 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
116 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
117 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
118 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
119 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
120 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
121 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
122 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
123 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
124 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
125 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
126 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
127 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
128 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
129 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
130 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
131 interrupt-names = "error",
132 "ch0", "ch1", "ch2", "ch3",
133 "ch4", "ch5", "ch6", "ch7",
134 "ch8", "ch9", "ch10", "ch11",
135 "ch12", "ch13", "ch14";
136 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
137 clock-names = "fck";
138 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
139 #dma-cells = <1>;
140 dma-channels = <15>;
141 };
142
143 dmac1: dma-controller@e6720000 {
144 compatible = "renesas,dmac-r8a7792",
145 "renesas,rcar-dmac";
146 reg = <0 0xe6720000 0 0x20000>;
147 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
148 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
149 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
150 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
151 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
152 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
153 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
154 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
155 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
156 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
157 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
158 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
159 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
160 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
161 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
162 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
163 interrupt-names = "error",
164 "ch0", "ch1", "ch2", "ch3",
165 "ch4", "ch5", "ch6", "ch7",
166 "ch8", "ch9", "ch10", "ch11",
167 "ch12", "ch13", "ch14";
168 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
169 clock-names = "fck";
170 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
171 #dma-cells = <1>;
172 dma-channels = <15>;
173 };
174
175 scif0: serial@e6e60000 {
176 compatible = "renesas,scif-r8a7792",
177 "renesas,rcar-gen2-scif", "renesas,scif";
178 reg = <0 0xe6e60000 0 64>;
179 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
181 <&scif_clk>;
182 clock-names = "fck", "brg_int", "scif_clk";
183 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
184 <&dmac1 0x29>, <&dmac1 0x2a>;
185 dma-names = "tx", "rx", "tx", "rx";
186 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
187 status = "disabled";
188 };
189
190 scif1: serial@e6e68000 {
191 compatible = "renesas,scif-r8a7792",
192 "renesas,rcar-gen2-scif", "renesas,scif";
193 reg = <0 0xe6e68000 0 64>;
194 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
196 <&scif_clk>;
197 clock-names = "fck", "brg_int", "scif_clk";
198 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
199 <&dmac1 0x2d>, <&dmac1 0x2e>;
200 dma-names = "tx", "rx", "tx", "rx";
201 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
202 status = "disabled";
203 };
204
205 scif2: serial@e6e58000 {
206 compatible = "renesas,scif-r8a7792",
207 "renesas,rcar-gen2-scif", "renesas,scif";
208 reg = <0 0xe6e58000 0 64>;
209 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
211 <&scif_clk>;
212 clock-names = "fck", "brg_int", "scif_clk";
213 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
214 <&dmac1 0x2b>, <&dmac1 0x2c>;
215 dma-names = "tx", "rx", "tx", "rx";
216 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
217 status = "disabled";
218 };
219
220 scif3: serial@e6ea8000 {
221 compatible = "renesas,scif-r8a7792",
222 "renesas,rcar-gen2-scif", "renesas,scif";
223 reg = <0 0xe6ea8000 0 64>;
224 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
226 <&scif_clk>;
227 clock-names = "fck", "brg_int", "scif_clk";
228 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
229 <&dmac1 0x2f>, <&dmac1 0x30>;
230 dma-names = "tx", "rx", "tx", "rx";
231 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
232 status = "disabled";
233 };
234
235 hscif0: serial@e62c0000 {
236 compatible = "renesas,hscif-r8a7792",
237 "renesas,rcar-gen2-hscif", "renesas,hscif";
238 reg = <0 0xe62c0000 0 96>;
239 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
241 <&scif_clk>;
242 clock-names = "fck", "brg_int", "scif_clk";
243 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
244 <&dmac1 0x39>, <&dmac1 0x3a>;
245 dma-names = "tx", "rx", "tx", "rx";
246 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
247 status = "disabled";
248 };
249
250 hscif1: serial@e62c8000 {
251 compatible = "renesas,hscif-r8a7792",
252 "renesas,rcar-gen2-hscif", "renesas,hscif";
253 reg = <0 0xe62c8000 0 96>;
254 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
256 <&scif_clk>;
257 clock-names = "fck", "brg_int", "scif_clk";
258 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
259 <&dmac1 0x4d>, <&dmac1 0x4e>;
260 dma-names = "tx", "rx", "tx", "rx";
261 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
262 status = "disabled";
263 };
264
265 jpu: jpeg-codec@fe980000 {
266 compatible = "renesas,jpu-r8a7792",
267 "renesas,rcar-gen2-jpu";
268 reg = <0 0xfe980000 0 0x10300>;
269 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&mstp1_clks R8A7792_CLK_JPU>;
271 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
272 };
273
274 /* Special CPG clocks */
275 cpg_clocks: cpg_clocks@e6150000 {
276 compatible = "renesas,r8a7792-cpg-clocks",
277 "renesas,rcar-gen2-cpg-clocks";
278 reg = <0 0xe6150000 0 0x1000>;
279 clocks = <&extal_clk>;
280 #clock-cells = <1>;
281 clock-output-names = "main", "pll0", "pll1", "pll3",
282 "lb", "qspi", "z", "adsp";
283 #power-domain-cells = <0>;
284 };
285
286 /* Fixed factor clocks */
287 zs_clk: zs {
288 compatible = "fixed-factor-clock";
289 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
290 #clock-cells = <0>;
291 clock-div = <6>;
292 clock-mult = <1>;
293 };
294 p_clk: p {
295 compatible = "fixed-factor-clock";
296 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
297 #clock-cells = <0>;
298 clock-div = <24>;
299 clock-mult = <1>;
300 };
301 cp_clk: cp {
302 compatible = "fixed-factor-clock";
303 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
304 #clock-cells = <0>;
305 clock-div = <48>;
306 clock-mult = <1>;
307 };
308 m2_clk: m2 {
309 compatible = "fixed-factor-clock";
310 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
311 #clock-cells = <0>;
312 clock-div = <8>;
313 clock-mult = <1>;
314 };
315
316 /* Gate clocks */
317 mstp1_clks: mstp1_clks@e6150134 {
318 compatible = "renesas,r8a7792-mstp-clocks",
319 "renesas,cpg-mstp-clocks";
320 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
321 clocks = <&m2_clk>;
322 #clock-cells = <1>;
323 clock-indices = <R8A7792_CLK_JPU>;
324 clock-output-names = "jpu";
325 };
326 mstp2_clks: mstp2_clks@e6150138 {
327 compatible = "renesas,r8a7792-mstp-clocks",
328 "renesas,cpg-mstp-clocks";
329 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
330 clocks = <&zs_clk>, <&zs_clk>;
331 #clock-cells = <1>;
332 clock-indices = <
333 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
334 >;
335 clock-output-names = "sys-dmac1", "sys-dmac0";
336 };
337 mstp4_clks: mstp4_clks@e6150140 {
338 compatible = "renesas,r8a7792-mstp-clocks",
339 "renesas,cpg-mstp-clocks";
340 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
341 clocks = <&cp_clk>;
342 #clock-cells = <1>;
343 clock-indices = <R8A7792_CLK_IRQC>;
344 clock-output-names = "irqc";
345 };
346 mstp7_clks: mstp7_clks@e615014c {
347 compatible = "renesas,r8a7792-mstp-clocks",
348 "renesas,cpg-mstp-clocks";
349 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
350 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
351 <&p_clk>, <&p_clk>;
352 #clock-cells = <1>;
353 clock-indices = <
354 R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
355 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
356 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
357 >;
358 clock-output-names = "hscif1", "hscif0", "scif3",
359 "scif2", "scif1", "scif0";
360 };
361 };
362
363 /* External root clock */
364 extal_clk: extal {
365 compatible = "fixed-clock";
366 #clock-cells = <0>;
367 /* This value must be overridden by the board. */
368 clock-frequency = <0>;
369 };
370
371 /* External SCIF clock */
372 scif_clk: scif {
373 compatible = "fixed-clock";
374 #clock-cells = <0>;
375 /* This value must be overridden by the board. */
376 clock-frequency = <0>;
377 };
378};
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index f748360ee857..90af18600124 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -320,12 +320,12 @@
320 function = "du"; 320 function = "du";
321 }; 321 };
322 322
323 scif0_pins: serial0 { 323 scif0_pins: scif0 {
324 groups = "scif0_data_d"; 324 groups = "scif0_data_d";
325 function = "scif0"; 325 function = "scif0";
326 }; 326 };
327 327
328 scif1_pins: serial1 { 328 scif1_pins: scif1 {
329 groups = "scif1_data_d"; 329 groups = "scif1_data_d";
330 function = "scif1"; 330 function = "scif1";
331 }; 331 };
@@ -360,7 +360,7 @@
360 renesas,function = "sdhi2"; 360 renesas,function = "sdhi2";
361 }; 361 };
362 362
363 qspi_pins: spi0 { 363 qspi_pins: qspi {
364 groups = "qspi_ctrl", "qspi_data4"; 364 groups = "qspi_ctrl", "qspi_data4";
365 function = "qspi"; 365 function = "qspi";
366 }; 366 };
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 9b55c1c6ee31..8d02aacf2892 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -35,6 +35,7 @@
35 cpus { 35 cpus {
36 #address-cells = <1>; 36 #address-cells = <1>;
37 #size-cells = <0>; 37 #size-cells = <0>;
38 enable-method = "renesas,apmu";
38 39
39 cpu0: cpu@0 { 40 cpu0: cpu@0 {
40 device_type = "cpu"; 41 device_type = "cpu";
@@ -56,6 +57,14 @@
56 next-level-cache = <&L2_CA15>; 57 next-level-cache = <&L2_CA15>;
57 }; 58 };
58 59
60 cpu1: cpu@1 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a15";
63 reg = <1>;
64 clock-frequency = <1500000000>;
65 power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
66 };
67
59 L2_CA15: cache-controller@0 { 68 L2_CA15: cache-controller@0 {
60 compatible = "cache"; 69 compatible = "cache";
61 reg = <0>; 70 reg = <0>;
@@ -65,6 +74,12 @@
65 }; 74 };
66 }; 75 };
67 76
77 apmu@e6152000 {
78 compatible = "renesas,r8a7793-apmu", "renesas,apmu";
79 reg = <0 0xe6152000 0 0x188>;
80 cpus = <&cpu0 &cpu1>;
81 };
82
68 thermal-zones { 83 thermal-zones {
69 cpu_thermal: cpu-thermal { 84 cpu_thermal: cpu-thermal {
70 polling-delay-passive = <0>; 85 polling-delay-passive = <0>;
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 383ad791f1db..1ad37d431a2a 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -111,7 +111,7 @@
111 function = "du"; 111 function = "du";
112 }; 112 };
113 113
114 scif2_pins: serial2 { 114 scif2_pins: scif2 {
115 groups = "scif2_data"; 115 groups = "scif2_data";
116 function = "scif2"; 116 function = "scif2";
117 }; 117 };
@@ -147,7 +147,7 @@
147}; 147};
148 148
149&pfc { 149&pfc {
150 qspi_pins: spi0 { 150 qspi_pins: qspi {
151 groups = "qspi_ctrl", "qspi_data4"; 151 groups = "qspi_ctrl", "qspi_data4";
152 function = "qspi"; 152 function = "qspi";
153 }; 153 };
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index b8c7a63c5ec4..cf24f45fff22 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -129,7 +129,7 @@
129 pinctrl-0 = <&scif_clk_pins>; 129 pinctrl-0 = <&scif_clk_pins>;
130 pinctrl-names = "default"; 130 pinctrl-names = "default";
131 131
132 scif2_pins: serial2 { 132 scif2_pins: scif2 {
133 groups = "scif2_data"; 133 groups = "scif2_data";
134 function = "scif2"; 134 function = "scif2";
135 }; 135 };
@@ -164,7 +164,7 @@
164 function = "sdhi1"; 164 function = "sdhi1";
165 }; 165 };
166 166
167 qspi_pins: spi0 { 167 qspi_pins: qspi {
168 groups = "qspi_ctrl", "qspi_data4"; 168 groups = "qspi_ctrl", "qspi_data4";
169 function = "qspi"; 169 function = "qspi";
170 }; 170 };
@@ -183,6 +183,16 @@
183 groups = "usb1"; 183 groups = "usb1";
184 function = "usb1"; 184 function = "usb1";
185 }; 185 };
186
187 du0_pins: du0 {
188 groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out";
189 function = "du0";
190 };
191
192 du1_pins: du1 {
193 groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
194 function = "du1";
195 };
186}; 196};
187 197
188&scif2 { 198&scif2 {
@@ -360,6 +370,8 @@
360}; 370};
361 371
362&du { 372&du {
373 pinctrl-0 = <&du0_pins &du1_pins>;
374 pinctrl-names = "default";
363 status = "okay"; 375 status = "okay";
364 376
365 clocks = <&mstp7_clks R8A7794_CLK_DU0>, 377 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
index 36567cbf2e1c..3d65f1f6d78b 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -22,7 +22,7 @@
22 compatible = "renesas,kzm9g", "renesas,sh73a0"; 22 compatible = "renesas,kzm9g", "renesas,sh73a0";
23 23
24 aliases { 24 aliases {
25 serial4 = &scifa4; 25 serial0 = &scifa4;
26 }; 26 };
27 27
28 cpus { 28 cpus {
@@ -39,8 +39,8 @@
39 }; 39 };
40 40
41 chosen { 41 chosen {
42 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw"; 42 bootargs = "root=/dev/nfs ip=dhcp ignore_loglevel rw";
43 stdout-path = &scifa4; 43 stdout-path = "serial0:115200n8";
44 }; 44 };
45 45
46 memory@40000000 { 46 memory@40000000 {
@@ -352,7 +352,7 @@
352 }; 352 };
353 }; 353 };
354 354
355 scifa4_pins: serial4 { 355 scifa4_pins: scifa4 {
356 groups = "scifa4_data", "scifa4_ctrl"; 356 groups = "scifa4_data", "scifa4_ctrl";
357 function = "scifa4"; 357 function = "scifa4";
358 }; 358 };
diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h
new file mode 100644
index 000000000000..89a5155913f6
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7792-clock.h
@@ -0,0 +1,103 @@
1/*
2 * Copyright (C) 2016 Cogent Embedded, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
11#define __DT_BINDINGS_CLOCK_R8A7792_H__
12
13/* CPG */
14#define R8A7792_CLK_MAIN 0
15#define R8A7792_CLK_PLL0 1
16#define R8A7792_CLK_PLL1 2
17#define R8A7792_CLK_PLL3 3
18#define R8A7792_CLK_LB 4
19#define R8A7792_CLK_QSPI 5
20#define R8A7792_CLK_Z 6
21#define R8A7792_CLK_ADSP 7
22
23/* MSTP0 */
24#define R8A7792_CLK_MSIOF0 0
25
26/* MSTP1 */
27#define R8A7792_CLK_JPU 6
28#define R8A7792_CLK_TMU1 11
29#define R8A7792_CLK_TMU3 21
30#define R8A7792_CLK_TMU2 22
31#define R8A7792_CLK_CMT0 24
32#define R8A7792_CLK_TMU0 25
33#define R8A7792_CLK_VSP1DU1 27
34#define R8A7792_CLK_VSP1DU0 28
35#define R8A7792_CLK_VSP1_SY 31
36
37/* MSTP2 */
38#define R8A7792_CLK_MSIOF1 8
39#define R8A7792_CLK_SYS_DMAC1 18
40#define R8A7792_CLK_SYS_DMAC0 19
41
42/* MSTP3 */
43#define R8A7792_CLK_TPU0 4
44#define R8A7792_CLK_SDHI0 14
45#define R8A7792_CLK_CMT1 29
46
47/* MSTP4 */
48#define R8A7792_CLK_IRQC 7
49
50/* MSTP5 */
51#define R8A7792_CLK_AUDIO_DMAC0 2
52#define R8A7792_CLK_THERMAL 22
53#define R8A7792_CLK_PWM 23
54
55/* MSTP7 */
56#define R8A7792_CLK_HSCIF1 16
57#define R8A7792_CLK_HSCIF0 17
58#define R8A7792_CLK_SCIF3 18
59#define R8A7792_CLK_SCIF2 19
60#define R8A7792_CLK_SCIF1 20
61#define R8A7792_CLK_SCIF0 21
62#define R8A7792_CLK_DU1 23
63#define R8A7792_CLK_DU0 24
64
65/* MSTP8 */
66#define R8A7792_CLK_VIN5 4
67#define R8A7792_CLK_VIN4 5
68#define R8A7792_CLK_VIN3 8
69#define R8A7792_CLK_VIN2 9
70#define R8A7792_CLK_VIN1 10
71#define R8A7792_CLK_VIN0 11
72#define R8A7792_CLK_ETHERAVB 12
73
74/* MSTP9 */
75#define R8A7792_CLK_GPIO7 4
76#define R8A7792_CLK_GPIO6 5
77#define R8A7792_CLK_GPIO5 7
78#define R8A7792_CLK_GPIO4 8
79#define R8A7792_CLK_GPIO3 9
80#define R8A7792_CLK_GPIO2 10
81#define R8A7792_CLK_GPIO1 11
82#define R8A7792_CLK_GPIO0 12
83#define R8A7792_CLK_GPIO11 13
84#define R8A7792_CLK_GPIO10 14
85#define R8A7792_CLK_CAN1 15
86#define R8A7792_CLK_CAN0 16
87#define R8A7792_CLK_QSPI_MOD 17
88#define R8A7792_CLK_GPIO9 19
89#define R8A7792_CLK_GPIO8 21
90#define R8A7792_CLK_I2C5 25
91#define R8A7792_CLK_IICDVFS 26
92#define R8A7792_CLK_I2C4 27
93#define R8A7792_CLK_I2C3 28
94#define R8A7792_CLK_I2C2 29
95#define R8A7792_CLK_I2C1 30
96#define R8A7792_CLK_I2C0 31
97
98/* MSTP10 */
99#define R8A7792_CLK_SSI_ALL 5
100#define R8A7792_CLK_SSI4 11
101#define R8A7792_CLK_SSI3 12
102
103#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */
diff --git a/include/dt-bindings/power/r8a7792-sysc.h b/include/dt-bindings/power/r8a7792-sysc.h
new file mode 100644
index 000000000000..74f4a78e29aa
--- /dev/null
+++ b/include/dt-bindings/power/r8a7792-sysc.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright (C) 2016 Cogent Embedded Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 */
8#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__
9#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__
10
11/*
12 * These power domain indices match the numbers of the interrupt bits
13 * representing the power areas in the various Interrupt Registers
14 * (e.g. SYSCISR, Interrupt Status Register)
15 */
16
17#define R8A7792_PD_CA15_CPU0 0
18#define R8A7792_PD_CA15_CPU1 1
19#define R8A7792_PD_CA15_SCU 12
20#define R8A7792_PD_SGX 20
21#define R8A7792_PD_IMP 24
22
23/* Always-on power area */
24#define R8A7792_PD_ALWAYS_ON 32
25
26#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-16 03:16:28 -0400