diff options
author | Rex Zhu <Rex.Zhu@amd.com> | 2016-06-03 07:12:42 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2016-06-09 10:49:16 -0400 |
commit | 5f96ddb4607382528ef2eb23b49ce1856fdb316d (patch) | |
tree | 7a15653df2cbe305d7d282246d1f4fdde5ffa09b | |
parent | d2e312183b62cde0c44af35664f3b104b247dd9c (diff) |
drm/amd/powerplay: delete useless code as pptable changed in vbios.
The vbios table changed so this code is useless now.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c index 16fed487973b..d27e8c40602a 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | |||
@@ -2847,27 +2847,6 @@ static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) | |||
2847 | } | 2847 | } |
2848 | } | 2848 | } |
2849 | 2849 | ||
2850 | /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */ | ||
2851 | for (i = 0; i < allowed_vdd_sclk_table->count; i++) { | ||
2852 | data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddc; | ||
2853 | /* tonga_hwmgr->dpm_table.VddcTable.dpm_levels[i].param1 = stdVoltageTable->entries[i].Leakage; */ | ||
2854 | /* param1 is for corresponding std voltage */ | ||
2855 | data->dpm_table.vddc_table.dpm_levels[i].enabled = 1; | ||
2856 | } | ||
2857 | data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count; | ||
2858 | |||
2859 | if (NULL != allowed_vdd_mclk_table) { | ||
2860 | /* Initialize Vddci DPM table based on allow Mclk values */ | ||
2861 | for (i = 0; i < allowed_vdd_mclk_table->count; i++) { | ||
2862 | data->dpm_table.vdd_ci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddci; | ||
2863 | data->dpm_table.vdd_ci_table.dpm_levels[i].enabled = 1; | ||
2864 | data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].mvdd; | ||
2865 | data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1; | ||
2866 | } | ||
2867 | data->dpm_table.vdd_ci_table.count = allowed_vdd_mclk_table->count; | ||
2868 | data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count; | ||
2869 | } | ||
2870 | |||
2871 | /* setup PCIE gen speed levels*/ | 2850 | /* setup PCIE gen speed levels*/ |
2872 | tonga_setup_default_pcie_tables(hwmgr); | 2851 | tonga_setup_default_pcie_tables(hwmgr); |
2873 | 2852 | ||